STE2002DIE2_技术文档

STE2002

81 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER

■ 104 x 128 bits Display Data RAM

■ Low Power Consumption, suitable for battery

operated systems

■ Programmable MUX rate

■ Logic Supply Voltage range from 1.7 to 3.6V

■ Programmable Frame Rate

■ X,Y Programmable Carriage Return

■ Dual Partial Display Mode

■ High Voltage Generator Supply Voltage range

from 1.75 to 4.2V

■ Display Supply Voltage range from 4.5 to 11V

■ Backward Compatibility with STE2001

■ Row by Row Scrolling

■ Automatic data RAM Blanking procedure

■ Selectable Input Interface:

2

DESCRIPTION

• I C Bus Fast and Hs-mode (read and write)

• Parallel Interface (read and write)

• Serial Interface (read and write)

The STE2002 is a low power CMOS LCD controller

driver. Designed to drive a 81 rows by 128 columns

graphic display, provides all necessary functions in a

single chip, including on-chip LCD supply and bias

voltages generators, resulting in a minimum of exter-

nals components and in a very low power consump-

tion. The STE2002 features three standard interfaces

■ Fully Integrated Oscillator requires no external

components

■ CMOS Compatible Inputs

■ Fully Integrated Configurable LCD bias voltage

2

generator with:

• Selectable multiplication factor (up to 6X)

(Serial, Parallel & I C) for ease of interfacing with the

host

mcontroller.

• Effective sensing for High Precision Output

• Eight selectable temperature compensation

coefficients

Type

Ordering Number

STE2002DIE1

STE2002DIE2

Bumped Wafers

Bumped Dice on Waffle Pack

■ Designed for chip-on-glass (COG) applications

Figure 1. Block Diagram

ICON

CO to C127

R0 to R80

OSC_IN

TIMING

GENERATOR

COLUMN

DRIVERS

ROW

DRIVERS

OSC

OSC_OUT

CLOCK

BIAS VOLTAGE

GENERATOR

VLCDIN

DATA

SHIFT

LATCHES

REGISTER

VLCDSENSE

VLCDOUT

HIGH VOLTAGE

GENERATOR

104 x 128

RAM

SCROLL

LOGIC

RES

RESET

TEST_1_14

VSSAUX

TEST

VDD1,2

V_SS

ICON_MODE

EXT

DISPLAY

CONTROL

LOGIC

DATA

REGISTER

INSTRUCTION

REGISTER

BSY_FLG

SEL1,2

SOUT

SA1

2

I

CBUS

PARALLEL

SERIAL

SAO

SCL

SDA_IN SDA_OUT DB0 to DB7 E

PD/C SCE SDIN SCLK SD/C

R/W

September 2002

1/51

STE2002

PIN DESCRIPTION

N°

Pad

Type

Function

R0 to R80

129-169

282-322

O

LCD Row Driver Output

ICON

C0 to C127

VSS

323

O

ICON Row Driver

1-128

LCD Column Driver Output

Ground pads.

236-255

188-199

200-211

261-270

273-282

271-272

GND

VDD1

Supply IC Positive Power Supply

VDD2

Supply Internal Generator Supply Voltages.

VLCDIN

VLCDOUT

Supply LCD Supply Voltages for the Column and Row Output Drivers.

Supply Voltage Multiplier Output

VLCDSENSE

Supply Voltage Multiplier Regulation Input. V

Sensing for Output Voltage Fine

LCDOUT

Tuning

V

SSAUX

180, 231,

218

O

Ground Reference for Selection Pins Configuration

SEL1,2

EXT

184,185

183

I

Interface Mode Selection

Extended Instruction Set Selection

EXT PAD CONFIG

VSS or VSSAUX

INSTRUCTION SET SELECTED

BASIC

VDD1

EXTENDED

ICON_MO

DE

186

I

ICON ROW Management

ICON MODE PAD CONFIG

VSS or VSSAUX

VDD1

ICON MODE STATUS

DISABLED

ENABLED

2

SDA_IN

SDA_OUT

SCL

234

232

235

182

181

I

O

I

I C Bus Data In

2

I C Bus Data Out

2

I C bus Clock

2

SA0

I

I C Slave Address BIT 0

2

SA1

I

I C Slave Address BIT 1

OSCIN

OSCOUT

RES

187

260

I

External Oscillator Input

O

Internal/External Oscillator Out

Reset Input. Active Low.

230

I

DB0 to DB7

R/W

220-227

219

I/O

Parallel Interface 8 Bit Data Bus

I

Parallel Interface Read & Write Control Line

Parallel Interface Data Latch Signal.

Parallel Interface Data/Command Selector

Serial Interface Data Input

E

229

PD/C

228

SDIN

214

2/51

STE2002

PIN DESCRIPTION (continued)

N°

SCLK

SCE

Pad

217

216

215

213

212

Type

Function

I

Serial Interface Clock

Serial Interface ENABLE. When Low the Incoming Data are Clocked In.

Serial Interface Data/Command Selector

Serial Out

SD/C

I

SOUT

BSYFLG

O

Active Procedure Flag. Notice if There is an ongoing Internal Operation or an

active reset. Active Low.

T1 to T14

170-179,

256-259

I/O

Test Pads. - A 50kohm pull-down resistor is added on input pis.

Test Num.

Pin Configuration

TEST_1

TEST_2

TEST_3

TEST_4

OPEN

TEST_5

TEST_6

TEST_7

TEST_8

TEST_9

TEST_10

VSS / VSSAUX

TEST_11

TEST_12

TEST_13

TEST_14

3/51

STE2002

Figure 2. Chip Mechanical Drawing

MARK_1

COL

0

ROW 35

ROW 39.

STE2002

VLCDOUT

VLCDSENSE

VLCDIN

VLCDOUT

VLCDSENSE

VLCDIN

MARK_3

OSCOUT

TEST_14

TEST_13

TEST_12

TEST_11

VSS

SCL

SDAIN

SDAOUT

VSSAUX

COL 63

COL 64

RES

(0,0)

E

PD/C

D0

Y

D1

D2

D3

D4

D5

D6

X

D7

R/W

VSSAUX

SCLK

SCE

SD/C

SDIN

SDOUT

BSY_FLG

MARK_4

VDD2

VDD1

VDD2

VDD1

OSCIN

ICON_MODE

SEL1

SEL2

EXT_SET

SA0

SA1

VSSAUX

TEST_10

TEST_9

TEST_8

TEST_7

TEST_6

TEST_5

TEST_4

TEST_3

TEST_2

TEST_1

ROW 80/ICON

ROW 79

COL 127

ROW 76

MARK_2

4/51

STE2002

Figure 3. Improved ALTH & PLESKO Driving Method

V_LCD

V₂

V₃

∆V₁(t)

∆V₂(t)

ROW 0

R0 (t)

V₄

V₅

V_SS

V_LCD

V₂

V₃

ROW 1

R1 (t)

V₄

V₅

V_SS

V_LCD

V₂

V₃

COL 0

C0 (t)

V₄

V₅

V_SS

V_LCD

V₂

V₃

COL 1

C1 (t)

V₄

V₅

V_SS

V_LCD- V_SS

V₃- V_SS

V_LCD- V₂

V₄- V₅

0V

V_state1(t)

0V

V₃- V_SS

V_SS- V₅

V₄- V_LCD

V_LCD- V_SS

V₃- V_SS

V_SS- V_LCD

V_LCD- V₂

0V

V₄- V₅

0V

V_state2(t)

V₃- V_SS

V_SS- V₅

V₄- V_LCD

V_SS- V_LCD

.......

0

..... 64

1

2

3

4

5

6

7

8

9

..... 64

0

1

2

3

4

5

6

7

8

9

FRAME n

FRAME n + 1

D00IN1154

∆V₁(t) = C1(t) - R0(t)

∆V₂(t) = C1(t) - R1(t)

5/51

STE2002

CIRCUIT DESCRIPTION

Supplies Voltages and Grounds

V

is supply voltages to the internal voltage generator (see below). If the internal voltage generator is

DD2

not used, this should be connected to V

pad. V

supplies the rest of the IC. V

supply voltage

DD1

could be different form V

.

DD2

Internal Supply Voltage Generator

The IC has a fully integrated (no external capacitors required) charge pump for the Liquid Crystal Display

supply voltage generation. The multiplying factor can be programmed to be: Auto, X6, X5, X4, X3, X2, us-

ing the ’set CP Multiplication’ Command. If Auto is set, the multiplying factor is automatically selected to

have the lowest current consumption in every condition. This make possible to have an input voltage that

changes over time and a constant V

voltage. The output voltage (V

) is tightly controlled through

LCDOUT

LCD

the V

pad. For this voltage, eight different temperature coefficients (TC, rate of change with tem-

LCDSENSE

perature) can be programmed using the bits TC1 and TC0 and T2,T1 & T0. This will ensure no contrast

degradation over the LCD operating range. Using the internal charge pump, the V and V pads

LCDIN

LCDOUT

must be connected together. An external supply could be connected to V

to supply the LCD without

LCDIN

using the internal generator. In such event the V

and V

must be connected to GND and

LDCOUT

LCDSENSE

the internal voltage generator must be programmed to zero (PRS = [0;0], Vop = 0 - Reset condition).

Oscillator

A fully integrated oscillator (requires no external components) is present to provide the clock for the Dis-

play System. When used the OSC pad must be connected to V

pad. An external oscillator could be

DD1

used and fed into the OSC pin. An oscillator out is provided on the OSCOUT Pad to cascade two or more

drivers

Bias Levels

To properly drive the LCD, six (Including VLCD and VSS) different voltage (Bias) levels are generated.

The ratios among these levels and VLCD, should be selected according to the MUX ratio (m). They are

established to be (Fig. 4):

n + 3

, ------------ V

n + 4

n + 2

,------------ V

n + 4

2

1

V

,------------ V

n + 4

,------------ V

n + 4

,V

LCD SS

LCD

Figure 4. Bias level Generator

V_LCD

R

n + 3

·V_LCD

n + 4

n + 2

·V_LCD

n + 4

nR

R

2

·V_LCD

n + 4

1

·V_LCD

n + 4

R

V_SS

D00IN1150

thus providing an 1/(n+4) ratio, with n calculated from:

n= m – 3

For m = 81, n = 6 and an 1/10 ratio is set.

For m = 65, n =5 and an 1/9 ratio is set.

6/51

STE2002

The STE2002 provides three bits (BS0, BS1, BS2) for programming the desired Bias Ratio as shown below:

BS2

0

BS1

0

BS0

0

n

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

1

0

1

The following table Bias Level for m = 65 and m = 81 are provided:

Symbol

V1

m = 65 (1/9)

m = 81 (1/10)

V

LCD

V2

8/9*V

7/9*V

9/10*V

8/10*V

2/10*V

1/10*V

LCD

V3

V4

2/9*V V

LCD

V5

1/9 *V

LCD

V6

V

SS

LCD Voltage Generation

The LCD Voltage at reference temperature (To = 27°C) can be set using the VOP register content according to

the following formula:

V

LCD

(T=To) = V

o = (Ai+V · B)

(i=0,1,2)

LCD

OP

with the following values:

Symbol

Ao

Value

2.95

Unit

V

Note

PRS = [0;0]

PRS = [0;1]

PRS = [1;0]

A1

6.83

V

A2

10.71

0.0303

27

V

B

V

To

°C

Note that the three PRS values produce three adjacent ranges for VLCD. If the V register and PRS bits are

OP

set to zero the internal voltage generator is switched off.

The proper value for the VLCD is a function of the Liquid Crystal Threshold Voltage (Vth) and of the Multiplexing

Rate. A general expression for this is:

1 +

m

V

= ----------------------------------- V

LCD

th

1

2

1 – --------

m

For MUX Rate m = 65 the ideal V

than:

is:

LCD

V

= 6.85 · V

LCD(to)

th

(6.85 V – A )

th

i

V

= ----------------------------------------

op

0.03

7/51

STE2002

Temperature Coefficient

As the viscosity, and therefore the contrast, of the LCD are subject to change with temperature, there's the need

to vary the LCD Voltage with temperature. The STE2002 provides the possibility to change the VLCD in a linear

fashion against temperature with eight different Temperature Coefficient selectable through the T2, T1 and T0

bits. Only four of them are available with basic instruction set (TC1 & TC0 Bits).

NAME

TC1

TC0

Value

Unit

-3

TC0

0

1/ °C

-0.0· 10

TC2

TC3

TC6

0

1

0

1

1/°C

-0.7 · 10

-3

-1.05· 10

-2.1 · 10

NAME

TC2

TC1

TC0

Value

Unit

-3

TC0

TC1

TC2

TC3

TC4

TC5

TC6

TC7

0

1

0

1

1/ °C

-0.0· 10

-3

0

1

0

1

1/°C

-0.35 · 10

-3

-0.7 · 10

-1.05· 10

-3

-1.4 · 10

-3

-1.75· 10

-3

-2.1 · 10

-3

-2.3· 10

Figure 5.

LCD

V

B

2

A

1

A

0

A + B

0

A

00h 01h 02h 03h 04h 05h …. 7Ch 7Dh 7Eh 7Fh 00h 01h 02h 03h 04h 05h …. 7Ch 7Dh 7Eh 7Fh 00h 01h 02h 03h 04h 05h …. 7Ch 7Dh 7Eh 7Fh

O

V

PRS = [0;0]

PRS = [0;1]

PRS = [1;0]

Finally, the V

voltage at a given (T) temperature can be calculated as:

LCD

V (T) = V o · [1 + (T-To) · TC]

LCD LCD

8/51

STE2002

Display Data RAM

The STE2002, provides an 104X128 bits Static RAM to store Display data. This is organized into 13

(Bank0 to Bank12) banks with 128 Bytes. One of these banks (128 bits wide) can be used for Icons. RAM

access is accomplished in either one of the Bus Interfaces provided (see below). Allowed addresses are

X0 to X127 (Horizontal) and Y0 to Y12 (Vertical).

When writing to RAM, four addressing mode are provided:

• Normal Horizontal (MX=0 and V=0), having the column with address X= 0 located on the left of the mem-

ory map. The X pointer is increased after each byte written. After the last column address (X=X-Car-

riage), Y address pointer is set to jump to the following bank and X restarts from X=0. (Fig. 6)

• Normal Vertical (MX=0 and V=1), having the column with address X= 0 located on the left of the memory

map. The Y pointer is increased after each byte written. After the last Y bank address (Y=Y-Carriage),

X address pointer is set to jump to next column and Y restarts from Y=0 (Fig. 7).

• Mirrored Horizontal (MX=1 and V=0), having the column with address X= 0 located on the right of the

memory map. The X pointer is increased after each byte written. After the last column address (X=X-

Carriage), Y address pointer is set to jump to the next bank and X restarts from X=0 (fig. 8).

• Mirrored Vertical (MX=1 and V=1), having the column with address X= 0 located on the right of the mem-

ory map. The Y pointer is increased after each byte written. After the last Y bank address (Y=Y-Car-

riage), the X pointer is set to jump to next column and Y restarts from Y=0 (fig. 9).

After the last allowed address (X;Y)=(X-Carriage; Y-Carriage), the address pointers always jump to the

cell with address (X;Y) = (0;0) (Fi. 10, 11, 12 & 13).

Data bytes in the memory could have the MSB either on top (D0 = 0, Fig.14) or on the bottom (D0=1, Fig.

15).

The STE2002 provides also means to alter the normal output addressing. A mirroring of the Display along

the X axis is enabled setting to a logic one MY bit.This function doesn't affect the content of the memory

RAM. It is only related to the visualization process.

When ICON MODE=1 the Icon Row is not mirrored with MY and is not scrolled. When ICON Mode=0 the

Icon Row is like the other graphic lines and is mirrored and scrolled.

Four are the multiplex ratio available when the partial display mode is disabled (MUX 33, MUX 49, MUX

65 and MUX 81).

Only a subset of writable rows are output on Row drivers.

When Y-Carriage<MUX/8, if Mux 65 is selected only the first 65 memory rows are visualized, if Mux 49 is

selected only the first 49 memory rows are visualized, if Mux 33 is selected only the first 33 memory rows

are visualized. All unused Row and Column drivers must be left floating.

When Y-Carriage<MUX/8, the icon Bank is located to BANK 10 in MUX 81 Mode, to BANK8 in MUX 65

Mode, to BANK 6 in MUX 49 Mode and to BANK 4 in MUX 33 Mode.

When Y-Carriage>MUX/8 lines only 33, 49, 65 or 81 lines are visualized but it is possible to select which

lines of DDRAM are connected on the output drivers. The DDRAM rows to visualized can be selected in

the 0-Y-Carriage*8 range using the scrolling function.

When Y-Carriage>MUX lines, the icon row is moved in DDRAM to the first row of the Y-CARRIAGE Re-

turn BANK even if it is always connected on the same output Driver.

When MY=0, the icon Row is output on R80 in mux 81 mode, on R72 in MUX 65, on R64 in MUX49 and

on R56 in MUX 33.

When MY=1, and ICON MODE=1, the icon Row is output on R80 in mux 81 mode, on R72 in MUX 65, on

R64 in MUX49 and on R56 in MUX 33.

When MY=1, and ICON MODE=0, the icon Row is output on R0 whatever is the MUX Rate.

When ICON MODE =1, the Memory ICON Row content is output on ICON Pad.

If Not Used ICON Pad must be left floating.

9/51

STE2002

1

Figure 6. Automatic data RAM writing sequence with V=0 and Data RAM Normal Format (MX=0)

0

1

2

3

124 125 126 127

BANK

0

1

2

3

4

5

6

7

8

9

BANK 10

BANK 11

BANK 12

1

Figure 7. Automatic data RAM writing sequence with V=1 and Data RAM Normal Format (MX=0)

0

1

2

3

124 125 126 127

BANK

0

1

2

3

4

5

6

7

8

9

BANK 10

BANK 11

BANK 12

1

Figure 8. Automatic data RAM writing sequence with V=0 and Data RAM Mirrored Format (MX=1)

127 126 125 124

3

2

1

0

BANK

0

1

2

3

4

5

6

7

8

9

BANK 10

BANK 11

BANK 12

1

Figure 9. Automatic data RAM writing sequence with V=1 and Data RAM Mirrored Format (MX=1)

127 126 125 124

3

2

1

0

BANK

0

1

2

3

4

5

6

7

8

9

BANK 10

BANK 11

BANK 12

1. X Carriage=127; Y-Carriage = 12

10/51

STE2002

Figure 10. Automatic data RAM writing sequence with X-Y Carriage Return (V=0; MX=0)

X CARR

0

1

2

3

124 125 126 127

BANK

0

1

2

Y CARR

BANK 11

BANK 12

Figure 11. Automatic data RAM writing sequence with X-Y Carriage Return (V=1; MX=0)

X CARR

0

1

2

3

124 125 126 127

BANK

0

1

2

Y CARR

BANK 11

BANK 12

Figure 12. Automatic data RAM writing sequence with X-Y Carriage Return (V=0; MX=1)

X CARR

127 126 125 124

3

2

1

0

BANK

0

1

2

Y CARR

BANK 11

BANK 12

Figure 13. Automatic data RAM writing sequence with X-Y Carriage Return (V=1; MX=1)

X CARR

127 126 125 124

3

2

1

0

BANK

0

1

2

Y CARR

BANK 11

BANK 12

11/51

STE2002

Figure 14. Data RAM Byte organization with D0 = 0

MSB

0

1

2

3

124 125 126 127

BANK

0

1

2

3

4

5

6

7

8

9

LSB

BANK 10

BANK 11

BANK 12

Figure 15. Data RAM Byte organization with D0 = 1

LSB

0

1

2

3

124 125 126 127

BANK

0

1

2

3

4

5

6

7

8

9

MSB

BANK 10

BANK 11

BANK 12

Figure 16. Memory Rows vs. Row drivers mapping with MY=0, MUX81, ICON MODE=0,1

ROW DRIVER

ICON MODE=1

ROW DRIVER

ICON MODE=0

PHYSICAL MEMORY ROW

0

1

2

3

124 125 126 127

ROW 0

R 0

R 1

R 2

R 3

R 0

R 1

R 2

R 3

ROW 1

ROW 2

ROW 3

Y-CARRIAGE

R 79

R 80

R 79

R 80

ROW 79

ROW 80

ICON ROW

ICON

Figure 17. Memory Rows vs. Row drivers mapping with MY=0, MUX 81, SCROLL POINTER = +3, ICON MODE=1

ROW DRIVER

PHYSICAL MEMORY ROW

ICON MODE=1

0

1

2

3

124 125 126 127

ROW 0

ROW 1

R 0

R 1

R 2

R 3

ROW 2

ROW 3

Y-CARRIAGE

R 76

R 77

R 78

R 79

R 80

ROW 79

ROW 80

ICON ROW

ICON

12/51

STE2002

Figure 18. Memory Rows vs. Row drivers mapping with MY=0, MUX 81, SCROLL POINTER=+3, ICON MODE=0

ROW DRIVER

ICON MODE=0

PHYSICAL MEMORY ROW

0

1

2

3

124 125 126 127

ROW 0

R 0

R 1

R 2

R 3

ROW 1

ROW 2

ROW 3

Y-CARRIAGE

R 76

R 77

R 78

R 79

R 80

ROW 79

ROW 80

ROW 161

ICON ROW

ICON

Figure 19. Memory Rows vs. Row drivers mapping with MUX 65 Y-CARRIAGE<=8 SCROLL POINTER=0, ICON MODE=1

PHYSICAL MEMORY ROW

ROW DRIVER

0

1

2

3

124 125 126 127

ROW 0

ROW 1

R 0

R 30

R 31

ROW 31

ROW 32

N.C.

R 40

Y-CARRIAGE

ICON ROW

R 71

R 72

ROW 63

ROW 64

R 79

R 80

ROW 96

ICON

Figure 20. Memory Rows vs. Row drivers mapping with MUX65, Y-CARRIAGE>8, SCROLL POINTER=0, ICON MODE=1

PHYSICAL MEMORY ROW

ROW DRIVER

0

1

2

3

124 125 126 127

ROW 0

R 0

ROW 31

ROW 32

R 31

R 32

N.C.

R 40

ROW 63

R 71

R 72

ICON ROW

ROW 75

ROW 76

Y-CARRIAGE

N.C.

R 79

R 80

ROW 96

ICON

13/51

STE2002

Figure 21. Memory Rows vs. Row drivers mapping with MUX65, Y-CARRIAGE>8, SCROLL POINTER=3, ICON MODE=1,

PHYSICAL MEMORY ROW

ROW DRIVER

0

1

2

3

124 125 126 127

ROW 0

R 0

ROW 1

ROW 2

R 30

R 31

ROW 33

ROW 34

N.C.

R 40

R 71

R 72

ROW 66

ICON ROW

ROW 75

ROW 76

Y-CARRIAGE

N.C.

R 79

R 80

ROW 96

ICON

Figure 22. Memory Rows vs. Row drivers mapping with MY=1, MUX81, ICON MODE 0,1 SCROLL POINTER=0

ROW DRIVER

ICON MODE=1

ROW DRIVER

ICON MODE=0

PHYSICAL MEMORY ROW

0

1

2

3

124 125 126 127

ROW 0

R 79

R 78

R 80

R 79

ROW 1

ROW 2

ROW 3

Y-CARRIAGE

R 2

R 1

R 3

R 2

R 1

R 0

ROW 79

ROW 80

R 0

ICON ROW

R 80

ICON

Figure 23. Memory Rows vs. Row drivers mapping with MY=1, MUX81, SCROLL OFFSET= +3, ICON MODE =0

ROW DRIVER

PHYSICAL MEMORY ROW

ICON MODE=0

0

1

2

3

124 125 126 127

ROW 0

R 80

R 78

R 79

R 77

R 76

ROW 1

ROW 2

ROW 3

Y-CARRIAGE

ROW 79

ROW 80

R 1

R 0

ICON ROW

ICON

14/51

STE2002

Figure 24. Memory Rows vs. Row drivers mapping with MY=1, MUX81, SCROLL OFFSET= +3, ICON MODE =1

ROW DRIVER

ICON MODE=1

SCROLL OFFSET +3

PHYSICAL MEMORY ROW

0

1

2

3

124 125 126 127

ROW 0

R 79

R 78

R 77

ROW 1

ROW 2

R 76

ROW 3

Y-CARRIAGE

R 1

R 0

ROW 79

ROW 80

R 80

ICON ROW

ICON

Figure 25. Row Drivers vs. LCD Panel Interconnection in MUX81 Mode

ICON

81x128

MUX 81 Mode

COLUMN DRIVERS

R40

R41

R42

R43

R44

R45

R46

R47

R48

R49

R50

R51

R52

R53

R54

R55

R56

R57

R58

R59

R60

R61

R62

R63

R64

R65

R66

R67

R68

R69

R70

R71

R72

R73

R74

R75

ICON

R

0

1

2

3

4

5

6

7

8

9

ROW DRIVERS

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22

R23

R24

R25

R26

R27

R28

R29

R30

R31

R32

R33

R34

STE2002

LR0012

15/51

STE2002

Figure 26. Row Drivers vs. LCD Panel Interconnection in MUX65 Mode

ICON

65x128

MUX 65 Mode

COLUMN DRIVERS

R40

R41

R42

R43

R44

R45

R46

R47

R48

R49

R50

R51

R52

R53

R54

R55

R56

R57

R58

R59

R60

R61

R62

R63

R64

R65

R66

R67

R68

R69

R70

R71

R72

R73

R74

R75

ICON

R

0

1

2

3

4

5

6

7

8

9

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22

R23

R24

R25

R26

R27

R28

R29

R30

R31

R32

R33

R34

ROW DRIVERS

STE2002

LR0014

Figure 27. Row Drivers vs. LCD Panel Interconnection in MUX49 Mode

ICON

49x128

MUX 49 Mode

COLUMN DRIVERS

R40

R41

R42

R43

R44

R45

R46

R47

R48

R49

R50

R51

R52

R53

R54

R55

R56

R57

R58

R59

R60

R61

R62

R63

R64

R65

R66

R67

R68

R69

R70

R71

R72

R73

R74

R75

ICON

R

0

1

2

3

4

5

6

7

8

9

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22

R23

R24

R25

R26

R27

R28

R29

R30

R31

R32

R33

R34

ROW DRIVERS

STE2002

LR0013

16/51

STE2002

Figure 28. Row Drivers vs. LCD Panel Interconnection in MUX33 Mode

ICON

33x128

MUX 33Mode

COLUMN DRIVERS

R40

R41

R42

R43

R44

R45

R46

R47

R48

R49

R50

R51

R52

R53

R54

R55

R56

R57

R58

R59

R60

R61

R62

R63

R64

R65

R66

R67

R68

R69

R70

R71

R72

R73

R74

R75

ICON

R

0

1

2

3

4

5

6

7

8

9

ROW DRIVERS

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22

R23

R24

R25

R26

R27

R28

R29

R30

R31

R32

R33

R34

STE2002

LR0106

Instruction Set

Two different instructions formats are provided:

- With D/C set to LOW

commands are sent to the Control circuitry.

- With D/C set to HIGH

the Data RAM is addressed.

Two different instruction set are embedded: the STE2001-like instruction set and the extended instruction

set. To select the STE2001-like instruction set the EXT pad has to be connected to a logic LOW (connect

to VSS). To select the extended instruction the EXT pad has to be connected to a logic HIGH (connect to

VDD1).

The instructions have the syntax summarized in Table 1 (basic-set) and Table 2 (extended set)

Reset (RES)

At power-on, all internal registers are configured with the default value. The RAM content is not defined.

A Reset pulse on RES pad (active low) re-initialize the internal registers content (see Tables 3,4,5,&6).

Applying a reset pulse, every on-going communication with the host controller is interrupted. After the

power-on, the Software Reset instruction can be used to re-load the reset configuration into the internal

registers

The Default configurations is: .

- Horizontal addressing (V = 0)

- Bias system (BS[2: 0] = 0)

- Multiplexing Ratio (M[1:0]=0)

- Frame Rate (FR[1:0]=”75Hz”)

- Power Down (PD = 1)

- Normal instruction set (H[1:0] = 0)

- Normal display (MX = MY = 0)

- Display blank (E = D = 0)

- Address counter X[6: 0] = 0 and Y[4: 0] = 0

- Temperature coefficient (TC[1: 0] = 0)

- Dual Partial Display Disabled (PE=0)

- V =0

OP

A MEMORY BLANK instruction can be executed to clear the RAM content.

17/51

STE2002

Power Down (PD = 1)

When at Power Down, all LCD outputs are kept at V (display off). Bias generator and V

generator

LCD

SS

are OFF (V

output is discharged to V , and then is possible to disconnect V

). The internal

LCDOUT

SS

LCDOUT

Oscillator is in off state. An external clock can be provided. The RAM contents is not cleared.

Memory Blanking Procedure

This instruction allows to fill the memory with "blank" patterns, in order to delete patterns randomly gener-

ated in memory when starting up the device. This instruction substitutes (128X13) single "write" instruc-

tions. It is possible to program "Memory Blanking Procedure" only under the following conditions:

- PD bit

= 0

The end of the procedure will be notified on the BSY_FLG pad going HIGH (while LOW the procedure is

running). Any instruction programmed with BSY_FLG LOW will be ignored that is, no instruction can be

programmed for a period equivalent to 128X13 internal write cycles (128X13X1/fclock). The start of Mem-

ory blanking procedure will be between one and two fclock cycles from the last active edge (E rising edge

2

for the parallel interface, last SCLK rising edge for the Serial interface, last SCL rising edge for the I C

interface).

Checker Board Procedure

This instruction allows to fill the memory with "checker-board" pattern. It is mainly intended to developers, who

can now simply obtain complex module test configuration by means of a single instruction. It is possible to pro-

gram "Checker Board Procedure" only under the following conditions:

- PD bit

= 0

The end of the procedure will be notified on the BSY_FLG pad going HIGH, while LOW the procedure is running.

Any instruction programmed with BSY_FLG LOW will be ignored, that is, no instruction can be programmed for

a period equivalent to 128X13 internal write cycles (128X13X1/fclock). The start of Memory blanking procedure

will be between one and two fclock cycles from the last active edge (E rising edge for the parallel interface, last

2

SCLK rising edge for the Serial interface, last SCL rising edge for the I C interface).

Scrolling function

The STE2002 can scroll the graphics display in units of raster-rows. The scrolling function is achieved

changing the correspondence between the rows of the logical memory map and the output row drivers.

The scroll function doesn't affect the data ram content. It is only related to the visualization process. The

information output on the drivers is related to the row reading sequence (the 1st row read is output on R0,

the 2nd on R1 and so on). Scrolling means reading the matrix starting from a row that is sequentially in-

creased or decreased. After every scrolling command the offset between the memory address and the

memory scanning pointer is increased or decreased by one. The offset range changes in accordance with

MUX Rate. After 80th/81th scrolling commands in MUX 81 mode, or after the 64th/65th scrolling com-

mands in mux 65 mode, or after 48nd/49rd scrolling command in MUX 49 mode, or after 32nd/33rd scroll-

ing command in MUX 33 mode, the offset between the memory address and the memory scanning pointer

is again zero (Cyclic Scrolling).

A Reset Scrolling Pointer instruction can be executed to force to zero the offset between the memory ad-

dress and the memory scanning pointer

The Icon Row is not scrolled if ICON MODE =1. If ICON MODE=0 the last row is like a general purpose

row and it is scrolled as other rows.

If the DIR Bit is set to a logic zero the offset register is increased by one and the raster is scrolled from top

down. If the DIR Bit is set to a logic one the offset register is decreased by one and the raster is scrolled

from bottom-up.

18/51

STE2002

OFFSET

RANGE

ICON Row Driver with

MY=0

MUX RATE

ICON MODE

DESCRIPTION

MUX 33

MUX 49

MUX 65

MUX 81

1

0

1

0

1

0

1

0

0-31

0-32

0-47

0-48

0-63

0-64

0-79

0-80

ICON ROW NOT SCROOLED

33 LINE GRAPHIC MATRIX

ICON ROW NOT SCROOLED

49 LINE GRAPHIC MATRIX

ICON ROW NOT SCROOLED

65 LINE GRAPHIC MATRIX

ICON ROW NOT SCROOLED

81 LINE GRAPHIC MATRIX

R56

R64

R72

R80

Dual Partial Display

If the PE Bit is set to a logic one the dual partial display mode is enabled.

Eight partial display modes are available. The offset of the two partial display zones is row by row programma-

ble. The Icon row is accessed last in each partial display frame.

Two sets of register for the HV-generator parameters are provided (PRS[1:0], Vop[6:0], BS[2:0], CP[2:0].).

This allows switching from normal mode to partial display mode applying one instruction. The HV generator is

automatically re configured using the parameters related to the enabled mode. The parameters of the two sets

of registers with the same function are located in the same position of the instruction set. The registers related

to the normal mode are accessible when normal mode (PE=0) is selected, the others are accessible when the

partial display mode is enabled (PE=1). To Setup PRS[1:0], Vop[6:0], BS[2:0], CP[2:0] values the instruction

flow proposed in Fig.46 must be followed. To setup Partial Display Sectors Start Address and Partial Dis-

play Mode no particular instruction flow has to be followed.

.

PD2 PD1 PD0

SECTION 1

SECTION2

8 + Icon Row

0 + Icon Row

8 + Icon Row

16 + Icon Row

0 + Icon Row

16 + Icon Row

8 + Icon Row

16 + Icon Row

RESET STATE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

8

0

000

16

8

16

19/51

STE2002

Bus Interfaces

To provide the widest flexibility and ease of use the STE2002 features three different methods for interfacing

the host Controller. To select the desired interface the SEL1 and SEL2 pads need to be connected to a logic

LOW (connect to GND) or a logic HIGH (connect to VDD). All the I/O pins of the unused interfaces must be

connected to GND.

All interfaces are working while the STE2002 is in Power Down

.

SEL2

SEL1

Interface

Note

2

0

Read and Write; Fast and

High Speed Mode

I C

0

1

0

1

Serial

Read and Write

Not Used

Parallel

2

I C Interface

2

The I C interface is a fully complying I C bus specification, selectable to work in both Fast (400kHz Clock) and

High Speed Mode (3.4MHz).

This bus is intended for communication between different Ics. It consists of two lines: one bi-directional for data

signals (SDA) and one for clock signals (SCL). Both the SDA and SCL lines must be connected to a positive

supply voltage via an active or passive pull-up.

The following protocol has been defined:

- Data transfer may be initiated only when the bus is not busy.

- During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line

while the clock line is high will be interpreted as control signals.

Accordingly, the following bus conditions have been defined:

BUS not busy: Both data and clock lines remain High.

Start Data Transfer: A change in the state of the data line, from High to Low, while the clock is High, define the

START condition.

Stop Data Transfer: A Change in the state of the data line, from low to High, while the clock signal is High,

defines the STOP condition.

Data Valid: The state of the data line represents valid data when after a start condition, the data line is stable

for the duration of the High period of the clock signal. The data on the line may be changed during the Low period

of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data

bytes transferred between the start and the stop conditions is not limited. The information is transmitted byte-

wide and each receiver acknowledges with the ninth bit.

By definition, a device that gives out a message is called "transmitter", the receiving device that gets the signals

is called "receiver". The device that controls the message is called "master". The devices that are controlled by

the master are called "slaves"

Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level

put on the bus by the receiver, whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also, a

master receiver must generate an acknowledge after the reception of each byte that has been clocked out of

the slave transmitter. The device that acknowledges has to pull down the SDA_IN line during the acknowledge

clock pulse. Of course, setup and hold time must be taken into account. A master receiver must signal an end-

of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of

the slave. In this case, the transmitter must leave the data line High to enable the master to generate the STOP

20/51

STE2002

condition.

Connecting SDA_IN and SDA_OUT together the SDA line become the standard data line. Having the ac-

knowledge output (SDAOUT) separated from the serial data line is advantageous in Chip-On-Glass

(COG) applications. In COG applications where the track resistance from the SDAOUT pad to the system

SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the Indium Tin

Oxide (ITO) track resistance. It is possible that during the acknowledge cycle the STE2002 will not be able

to create a valid logic 0 level. By splitting the SDA input from the output the device could be used in a mode

that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is nec-

essary to minimize the track resistance from the SDACK pad to the system SDA line to guarantee a valid

LOW level.

2

To be compliant with the I C-bus Hs-mode specification the STE2002 is able to detect the special sequence

"S00001xxx". After this sequence no acknowledge pulse is generated.

Since no internal modification are applied to work in Hs-mode, the device is able to work in Hs-mode without

detecting the master code.

Figure 29. Bit transfer and START,STOP conditions definition

DATA LINE

STABLE

DATA VALID

CLOCK

DATA

START

CHANGE OF

STOP

CONDITION

DATA ALLOWED

CONDITION

D00IN1151

2

Figure 30. Acknowledgment on the I C-bus

CLOCK PULSE FOR

ACKNOWLEDGEMENT

START

SCLK FROM

MASTER

1

2

8

9

DATA OUTPUT

BY TRANSMITTER

MSB

LSB

DATA OUTPUT

BY RECEIVER

D00IN1152

Communication Protocol

2

The STE2002 is an I C slave. The access to the device is bi-directional since data write and status read are allowed.

Four are the device addresses available for the device. All have in common the first 5 bits (01111). The two least sig-

nificant bit of the slave address are set by connecting the SA0 and SA1 inputs to a logic 0 or to a logic 1.

To start the communication between the bus master and the slave LCD driver, the master must initiate a START con-

dition. Following this, the master sends an 8-bit byte, shown in Fig. 30, on the SDA bus line (Most significant bit first).

This consists of the 7-bit Device select Code, and the 1-bit Read/Write Designator (R/W).

2

All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I C-bus transfer.

Writing Mode.

If the R/W bit is set to logic 0 the STE2002 is set to be a receiver. After the slaves acknowledge one or more

command word follows to define the status of the device.

A command word is composed by two bytes. The first is a control byte which defines the Co and D/C values,

21/51

STE2002

the second is a data byte (fig 31). The Co bit is the command MSB and defines if after this command will follow

one data byte and an other command word or if will follow a stream of data (Co = 1 Command word, Co = 0

Stream of data). The D/C bit defines whether the data byte is a command or RAM data (D/C = 1 RAM Data, D/

C = 0 Command).

If Co =1 and D/C = 0 the incoming data byte is decoded as a command, and if Co =1 and D/C =1, the following

data byte will be stored in the data RAM at the location specified by the data pointer.

Every byte of a command word must be acknowledged by all addressed units.

After the last control byte, if D/C is set to a logic 1 the incoming data bytes are stored inside the STE2002 Display

RAM starting at the address specified by the data pointer. The data pointer is automatically updated after every

byte written and in the end points to the last RAM location written.

Every byte must be acknowledged by all addressed units.

Reading Mode.

If the R/W bit is set to logic 1 the chip will output data immediately after the slave address. If the D/C bit sent

during the last write access, is set to a logic 0, the byte read is the status byte.

Figure 31. Communication Protocol

WRITE MODE

STE2002 ACK

S S

STE2002 ACK

S 0 1 1 1 1 A A 0 A 1 DC Control Byte

1 0

A

DATA Byte

A 0 DC Control Byte

A

DATA Byte A P

R/W Co

Co

LAST

N> 0 BYTE

SLAVE ADDRESS

COMMAND WORD

CONTROL BYTE

MSB........LSB

READ MODE

STE2002 ACK

MASTER ACK

P

S S

S 0 1 1 1 1 A A 1 A

1 0

S S R

0 1 1 1 1 A A /

1 0 W

C D

o C

0 0 0 0 0 0 A

R/W

STE2002

CONTROL BYTE

SLAVE ADDRESS

SERIAL INTERFACE

The STE2002 serial Interface is a bidirectional link between the display driver and the application supervisor.

It consists of five lines: two for data signals (SDIN, SOUT), one for clock signals (SCLK), one for the peripheral

enable (SCE) and one for mode selection (SD/C).

The serial interface is active only if the SCE line is set to a logic 0. When SCE line is high the serial peripheral

power consumption is zero. While SCE pin is high the serial interface is kept in reset.

The STE2002 is always a slave on the bus and receive the communication clock on the SCLK pin from the mas-

ter.

Information are exchanged byte-wide. During data transfer, the data line is sampled on the positive SCLK edge.

SD/C line status indicates whether the byte is a command (SD/C =0) or RAM data (SD/C =1);it is read on the

eighth SCLK clock pulse during every byte transfer.

22/51

STE2002

If SCE stays low after the last bit of a command/data byte, the serial interface expects the MSB of the next byte

at the next SCLK positive edge.

A reset pulse on RES pin interrupts the transmission. No data is written into the data RAM and all the internal

registers are cleared.

If SCE is low after the positive edge of RES, the serial interface is ready to receive data.

2

Throughout SOUT can be read only the driver I C slave address. The Command sequence that allows to read

2

I C slave address is reported in Fig. 34 & 35. SOUT is in High impedance in steady state and during data write.

It is possible to short circuit DOUT and SDIN and read I2C address without any additional lines.

Figure 32. Serial bus protocol - one byte transmission

SCE

D/C

SCLK

SDIN

MSB

LSB

D00IN1159

Figure 33. Serial bus protocol - several byte transmission

SCE

D/C

SCLK

SDIN

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DB7

DB6

DB5

D00IN1160

Figure 34. Serial bus protocol - several byte transmission

SCE

D/C

SCLK

Don't

Care

Don't

Care

Don't

Care

Don't

Care

Don't

Care

Don't

Care

Don't

Care

Don't

Care

SDIN

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DB7

DB6

DB5

D00IN1160

High-Z

SOUT

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Command Write

I2C Address Read

23/51

STE2002

Figure 35. Reading Sequence

READING SEQUENCE

Write a "00000000" Instruction

SOUT Buffer becomes active (Low Impedence)

Source 8 pulses on SCLK and

1

Read the I2C Address or Status Byte On SOUT

SOUT Buffer Configured in High Impedence

END OF READING SEQUENCE

note: 1) these data are not read by the display Diver

2) SDIN and SOUT can be short circuited if the processor can configure

serial output buffers in high impedence during data read

.

LR0078

Parallel Interface

The STE2002 parallel Interface is a bidirectional link between the display driver and the application supervisor.

It consists of eleven lines: eight data lines (from DB7 to DB0) and three control lines. The control lines are: en-

able (E) for data latch, PD/C for mode selection and R/W for reading or writing.

The data lines and the control line values are internally latched on E rising edge (fig. 50).

When the parallel interface is selected, if R/W line is set to “one”, D0-D7 lines are configured as output drivers

2

(low impedence) and it is possible to read the driver I C address (Fig. 51)

24/51

STE2002

Table 1. STE2001-like instruction Set

Instruction

D/C

R/W

Description

B7 B6 B5 B4 B3

B2 B1 B0

H=0 or H=1

2

0

Read I C Address

(with Serial Interface only)

Function Set

0

1

MX MY PD

V

H[0] Power Down Management; Entry

Mode;

2

Read Status Byte

0

1

0

PD

A1

A2

D

E

MX MY DO

D2 D1 D0

(I C interface only)

Writes data to RAM

Write Data

H=0

D7 D6 D5 D4 D3

Memory Blank

Scroll

0

1

0

1

0

1

Starts Memory Blank Procedure

DIR Scrolls by one Row UP or DOWN

V

Range Setting

PRS

[0]

V

LDC

programming range selection

LCD

Display Control

Set CP Factor

0

1

0

D

0

E

Select Display Configuration

S2

S1

S0

Charge Pump Multiplication

factor

Set RAM Y

Set RAM X

H=1

0

1

0

Y3

X3

Y2

X2

Y1

X1

Y0 Set Horizontal (Y) RAM Address

X6

X5

X4

X0

Set Vertical (X) RAM Address

Checker Board

Multiplex Select

TC Select

0

1

0

1

0

X

0

1

X

0

1

0

X

0

1

0

1

Starts Checker Board Procedure

Selects MUX factor

MUX

TC1 TC0 Set Temperature Coefficient for V

LDC

Output Address

Bias Ratios

Reserved

DO A1

A2

No function

Set desired Bias Ratios

Not to be used

BS2 BS1 BS0

X

Set V

OP6 OP5 OP4 OP3 OP2 OP1 OP0

V

OP

register Write instruction

OP

25/51

STE2002

Table 2. Extended Instruction Set

Instruction

D/C R/W

Description

B7 B6 B5

B4 B3 B2 B1 B0

H Independent Instructions

2

NOP

0

Read I C Address

(with Serial Interface only)

Function Set

0

1

0

MX MY PD H[1] H[0]

Power Down Management; Entry

Mode; Extended Instruction Set

2

Read Status Byte

Write Data

0

1

0

PD

D

E

MX MY DO

D4 D3 D2 D1 D0

H=[0;0] RAM Commands

(I C interface only)

D7 D6 D5

Writes data to RAM

Memory Blank

Scroll

0

1

Starts Memory Blank Procedure

Scrolls by one Row UP or DOWN

0

DIR

V

Range Setting

0

1

PRS PRS

V

LDC

programming range selection

LCD

[1]

[0]

Display Control

Set CP Factor

Set RAM Y

0

1

0

1

0

D

0

E

Select Display Configuration

S2

Y2

X2

S1

Y1

X1

S0

Y0

X0

Charge Pump Multiplication factor

Set Horizontal (Y) RAM Address

Set Vertical (X) RAM Address

1

0

Y3

X3

Set RAM X

X6

X5

X4

H=[0;1]

Checker Board

0

1

0

1

0

X

0

1

X

0

1

0

X

0

1

Starts Checker Board Procedure

Vertical Addressing Mode

V

TC Select

Data Format

Bias Ratios

1

TC1 TC0 Set Temperature Coefficient for V

LDC

DO

0

MSB Position

Set desired Bias Ratios

Reserved

BS2 BS1 BS0

X

Set V

OP6 OP5 OP4 OP3 OP2 OP1 OP0

V

OP

register Write instruction

OP

H=[1;0]

0

1

0

1

0

1

0

1

0

1

Software RESET

Partial Enable

PE

FR1 FR0

M[1] M[0]

Frame rate Control

Mux Ratio

Partial Mode

PD2 PD1 PD0

Partial Display Config

st

PD PD PD PD PD PDY

Y5 Y4 Y2 Y1

1

Sector Start Address

Y3

0

nd

0

1

PD PD PD PD PD PD PD

2

Sector Start Address

Y6

Y5

Y4

Y3

Y2

Y1

Y0

H=[1;1]

0

1

0

1

0

1

0

1

X

0

1

X

Scrolling Pointer Reset

Not Used

1

X

Not Used

T2

X

T1

X

T0 Set Temperature Coefficient for V

LDC

X

Not Used

YC-3 YC-2 YC-1 YC-0

Y-CARRIAGE RETURN

X CARRIAGE RETURN

XC-6 XC-5 XC-4 XC-3 XC-2 XC-1 XC-0

26/51

STE2002

Table 3. Explanations of Table 2 symbols

RESET

STATE

BIT

0

1

DIR

PD

Scroll by one down

Device fully working

Horizontal addressing

Normal X axis addressing

Image is displayed not vertically mirrored

MSB on TOP

Scroll by one up

Device in power down

Vertical addressing

1

0

V

MX

MY

DO

PE

X axis address is mirrored.

Image is displayed vertically mirrored

MSB on BOTTOM

Partial Display disabled

Select page 0

Partial Display enabled

Select page 1

H[0]

MUX

MUX 65

MUX 33

Table 4. PAGE NUMBER

H[1]

H[0]

DESCRIPTION

RESET STATE

0

1

0

1

0

1

Page 0

Page 1

Page 2

Page 3

Page 0

Table 5. DISPLAY MODE

D

0

1

E

0

1

0

1

DESCRIPTION

RESET STATE

display blank

all display segments on

normal mode

D=0

E=0

inverse video mode

Table 6. FRAME RATE CONTROL

FR[1]

FR[0]

DESCRIPTION

65Hz

RESET STATE

0

1

0

1

0

1

70Hz

75Hz

80Hz

Table 7. VLCD RANGE SELECTION

PRS[1]

PRS[0]

DESCRIPTION

2.94

RESET STATE

0

1

0

1

0

1

6.78

10.62

Not Used

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Table 8. MULTIPLEXING RATIO

M[1]

M[0]

DESCRIPTION

RESET STATE

0

1

0

1

0

1

49

65

01

81

Not Used

Table 9. TEMPERATURE COEFFICIENT

T2

0

T1

0

T0

0

DESCRIPTION

RESET STATE

VLCD temperature Coefficient 0

VLCD temperature Coefficient 1

VLCD temperature Coefficient 2

VLCD temperature Coefficient 3

VLCD temperature Coefficient 4

VLCD temperature Coefficient 5

VLCD temperature Coefficient 6

VLCD temperature Coefficient 7

0

1

0

1

0

1

000

1

0

1

0

1

0

1

Table 10.

TC1

0

TC0

DESCRIPTION

RESET STATE

0

1

0

1

VLCD temperature Coefficient 0

VLCD temperature Coefficient 2

VLCD temperature Coefficient 3

VLCD temperature Coefficient 6

0

00

1

Table 11. CHARGE PUMP MULTIPLICATION FACTOR

CP2

CP1

CP0

DESCRIPTION

RESET STATE

0

Multiplication Factor X2

Multiplication Factor X3

0

1

0

1

Multiplication Factor X4

Multiplication Factor X5

Multiplication Factor X6

NOT USED

000

1

0

1

0

1

0

1

NOT USED

AUTOMATIC

Table 12. BIAS RATIO

BS2

0

BS1

0

BS0

0

DESCRIPTION

RESET STATE

Bias Ratio equal to 7

Bias Ratio equal to 6

Bias Ratio equal to 5

Bias Ratio equal to 4

Bias Ratio equal to 3

Bias Ratio equal to 2

Bias Ratio equal to 1

Bias Ratio equal to 0

0

1

0

1

0

1

000

1

0

1

0

1

0

1

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Table 13. Y CARRIAGE RETURN REGISTER

Y-C[3] Y-C[2] Y-C[1] Y-C[0]

DESCRIPTION

RESET STATE

0

.

0

1

.

0

1

0

.

0

1

0

1

0

1

.

Y-CARRIAGE =1

Y-CARRIAGE =2

Y-CARRIAGE =3

Y-CARRIAGE =4

Y-CARRIAGE =5

1000

1

0

1

0

1

0

Y-CARRIAGE =10

Y-CARRIAGE =11

Y-CARRIAGE =12

Table 14. PARTIAL DISPLAY CONFIGURATION

PD2

0

PD1

0

PD0

0

SECTION 1

SECTION2

8 + Icon Row

0 + Icon Row

8 + Icon Row

16 + Icon Row

0 + Icon Row

16 + Icon Row

8 + Icon Row

16 + Icon Row

RESET STATE

0

8

0

1

0

1

0

8

0

1

0

000

1

0

16

8

1

0

1

0

16

1

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Figure 36. Host Processor Interconnection with I2C Interface

SCL

SDAIN

SDAOUT

µP

STE2002

VSSAUX

RES

E

PD/C

D0

D1

D2

D3

D4

D5

D6

D7

R/W

VSSAUX

SCLK

SCE

SD/C

SDIN

SDOUT

BSY_FLG

VDD2

VDD1

OSCIN

VDD1 / GND / VSSAUX

ICON_MODE

SEL1

SEL2

GND / VSSAUX

VDD1

EXT_SET

SA0

VDD1 / GND / VSSAUX

SA1

VSSAUX

TEST_10

TEST_9

TEST_8

TEST_7

TEST_6

TEST_5

TEST_4

TEST_3

TEST_2

TEST_1

Figure 37. Host Processor Interconnection with Serial Interface

SCL

SDAIN

SDAOUT

µP

STE2002

VSSAUX

RES

E

PD/C

D0

D1

D2

D3

D4

D5

D6

D7

R/W

VSSAUX

SCLK

SCE

SD/C

SDIN

SDOUT

BSY_FLG

VDD2

VDD1

OSCIN

VDD1 / GND / VSSAUX

ICON_MODE

SEL1

VDD1

GND / VSSAUX

VDD1

SEL2

EXT_SET

VDD1 / GND / VSSAUX

SA0

SA1

VSSAUX

TEST_10

TEST_9

TEST_8

TEST_7

TEST_6

TEST_5

TEST_4

TEST_3

TEST_2

TEST_1

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Figure 38. Host Processor Interconnection with Parallel Interface

SCL

SDAIN

SDAOUT

µP

STE2002

VSSAUX

RES

E

PD/C

D0

D1

D2

D3

D4

D5

D6

D7

R/W

VSSAUX

SCLK

SCE

SD/C

SDIN

SDOUT

BSY_FLG

VDD2

VDD1

OSCIN

ICON_MODE

SEL1

VDD1 / GND / VSSAUX

GND / VSSAUX

VDD1

SEL2

EXT_SET

VDD1

VDD1 / GND / VSSAUX

SA0

SA1

VSSAUX

TEST_10

TEST_9

TEST_8

TEST_7

TEST_6

TEST_5

TEST_4

TEST_3

TEST_2

TEST_1

Figure 39. Application Schematic Using an External LCD Voltage Generator

I/O

VDD2

V_DD

40

128

41

VDD1

100nF

V_SS

81x 128

DISPLAY

VSS2

VSS1

1µF

VLCDSENSE

VLCDOUT

VLCDIN

V_LCD

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Figure 40. Application Schematic using the Internal LCD Voltage Generator and two separate supplies

I/O

V_DD2

VDD2

VDD1

40

128

41

V_DD1

100nF

V_SS

100nF

81x 128

DISPLAY

VSS2

VSS1

1µF

VLCDSENSE

VLCDOUT

VLCDIN

Figure 41. Application Schematic using the Internal LCD Voltage Generator and a single supply

I/O

V_DD

VDD2

VDD1

40

128

41

100nF

V_SS

81 x 128

DISPLAY

VSS2

VSS1

1µF

VLCDSENSE

VLCDOUT

VLCDIN

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Figure 42. Power-Up sequence

T

vdd

Tw(res) TLogic (res)

VDD2

VDD1

RES

SCE

SCLK

SDIN

SD/C

PD/C

E

R/W

D0 - D7

HOST

D0 - D7

DRIVER

Hi-Z

SCL

SDAIN

SOUT

SDA OUT

OSCIN

(HOST)

OSC OUT

(DRIVER)

BSY FLG

RESET POWER ON

BOOSTER

OFF

TABLE

INTERNAL

RESET

LR0116

LOADED

33/51

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Figure 43. Power-OFF Sequence

T

w(res)

VDD2

VDD1

RES

SCLK

SDIN

SD/C

PD/C

E

SCE

SCl

SDAIN

R/W

D0 - D7

HOST

D0 - D7

DRIVER

Hi-Z

SOUT

SDA OUT

OSCIN

(HOST)

OSC OUT

(DRIVER)

BSY FLG

RESET

TABLE

LOADED

LR0117

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Figure 44. Initialization with built-in Booster

SETUP NORMAL DISPLAY MODE CONFIGURATION

SET Driver in Power Down(PD=1)

SET Driver in Normal Display Mode (PE=0)

SET PRS[1:0], Vop[6:0], BS[2:0], CP[2:0], FR[1:0],

TC, M[1:0] for Normal Display Operation

Switch "ON" Booster and Display Control Logic

(PD=0)

END OF NORMAL DISPLAY MODE CONFIG.

Figure 45. Dual Partial Display Enabling Instruction Flow

ENABLE DUAL PARTIAL DISPLAY

SET 1st Sector Start Address

SET 2nd Sector Start Address

OPTIONAL1

SET PE=1

END OF ENABLING DUAL PARTIAL DISPLAY

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Figure 46. Dual Partial Display Mode configuration or Duty Change

SETUP PARTIAL DISPLAY CONFIGURATION

SET Driver in Power Down(PD=1)

SET Driver in Partial Display Mode (PE=1)

SET PRS[1:0], Vop[6:0], BS[2:0], CP[2:0]

for Partial Display Operation

SET Partial Display Configuration (PD[2:0])

SET 1st Sector Start Address

OPTIONAL

SET 2nd Sector Start Address

SET Driver in Normal Mode (PE=0)

END OF PARTIAL DISPLAY CONFIG.

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Figure 47. DATA RAM to display Mapping

DISPLAY DATA RAM

bank

0

GLASS

TOP VIEW

bank

1

DISPLAY DATA RAM = "1"

DISPLAY DATA RAM = "0"

bank

2

LCD

bank

3

bank

7

bank

8

ICOR ROW

D00IN1155

Table 15. Test Pin Configuration

Test Numb.

Pin Configuration

TEST_1

TEST_2

TEST_3

TEST_4

OPEN

TEST_5

TEST_6

TEST_7

TEST_8

TEST_9

TEST_10

GND

TEST_11

TEST_12

TEST_13

TEST_14

37/51

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ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

V

Supply Voltage Range

LCD Supply Voltage Range

Supply Current

- 0.5 to + 5

- 0.5 to + 7

- 0.5 to + 12

- 50 to +50

DD1

DD2

LCD

V

I

mA

V

SS

V

Input Voltage (all input pads)

DC Input Current

-0.5 to V

+ 0.5

i

DD2

I

in

- 10 to + 10

mA

mW

°C

I

DC Output Current

- 10 to + 10

300

out

P

Total Power Dissipation (T = 85°C)

tot

j

P

Power Dissipation per Output

Operating Junction Temperature

Storage Temperature

30

o

T

-40 to + 85

- 65 to 150

j

T

stg

°C

ELECTRICAL CHARACTERISTICS

DC OPERATION

(V

DD1

= 1.7 to 3.6 V; V

= 1.75 to 4.2V; V

= 0V; V

= 4.5 to 11 V; T

=-40 to 85°C; unless otherwise specified)

DD2

ss1,2

LCD

amb

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Supply Voltages

V

Supply Voltage

note 9

1.7

3.6

4.2

V

DD1

DD2

V

LCD Voltage Internally

generated

1.75

V

LCD Supply Voltage

Supply Current

LCD Voltage Supplied externally

Internally generated; note 1

4.5

15

11

30

V

LCDIN

V

LCDOUT

I(V

)

V

= 2.8V; V = 7.6V;

LCD

20

µA

DD1

f

= 0;T

= 25°C; note 3.

sclk

amb

V

= 2.8V; V

= 7.6V;

120

150

µA

DD1

LCD

f

= 1Mhz;T

= 25°C; note 3,

sclk

amb

8. OSC_IN=GND; parallel port

I(V

)

Voltage Generator Supply

Current

with V = 0 and PRS = [0:0]

1

µA

DD2

OP

with external V

LCD

V

= 2.8V;V

=7.6V; f = 0;

10

25

35

DD2

LCD

sclk

T

amb

= 25°C; no display load; 4x

charge pump; note 2,3,6,

I(V

)

Total Supply Current

V

= 2.8V; V = 7.6V;

65

µA

DD1,2

DD1, DD2

LCD

4x charge pump; f

= 0;T

=

sclk

amb

25°C; no display load; note 2,3,6

Power down Mode with internal

or External VLCD. Note 4

3

5

µA

)

External LCD Supply Voltage

Current

V

=2.8V; V =7.6V;no

LCD

5

10

15

LDCIN

DD

display load; f

25°C; note 3.

= 0; T

=

sclk

amb

Logic Outputs

V

High logic Level Output Voltage IOH=-500µA

Low logic Level Output Voltage IOL=500µA

0.8V

V

DD1

V

0H

OL

DD1

V

0.2V

DD1

SS

38/51

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ELECTRICAL CHARACTERISTICS (continued)

DC OPERATION

(V

DD1

= 1.7 to 3.6 V; V

= 1.75 to 4.2V; V

= 0V; V

= 4.5 to 11 V; T =-40 to 85°C; unless otherwise specified)

amb

DD2

ss1,2

LCD

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Logic Inputs

V

Logic LOW voltage level

Logic HIGH Voltage Level

Input Current

V

0.3V

DD1

V

IL

IH

in

SS

V

0.7V

V

DD2

DD1

I

V

in

= V

or V

DD1

-1

1

µA

SS1

Logic Inputs/Outputs

V

Logic LOW voltage level

Logic HIGH Voltage Level

V

0.3V

DD1

V

IL

SS

V

0.7V

V

DD1

IH

DD1

+0.5V

Column and Row Driver

R

ROW Output Resistance

Column Output resistance

Column Bias voltage accuracy

Row Bias voltage accuracy

V

= 10V;

3K

5K

kohm

mV

row

LCD

R

10K

+50

col

V

No load

-50

V

row

-50

mV

LCD Supply Voltage

V

LCD

LCD Supply Voltage accuracy;

Internally generated

V

T

amb

= 2.8V; V

=25°C;

= 10V; fsclk=0;

LCD

-1.5

1.5

%

DD

no display load; note 2, 3, 6 & 7;

VOP = 61h, PRS = 2hex

-3

TC0

TC1

TC2

TC3

TC4

TC5

TC6

TC7

Temperature coefficient

1/°C

-0.0·10

-3

-0.35·10

-3

-0.7·10

-3

-1.05·10

-3

-1.4 ·10

-3

-1.75·10

-3

-2.1·10

-2.3·10

-3

Notes: 1. The maximum possible V

2. Internal clock

voltage that can be generated is dependent on voltage, temperature and (display) load.

LCD

3. When f

= 0 there is no interface clock.

sclk

4. Power-down mode. During power-down all static currents are switched-off.

5. f external V , the display load current is not transmitted to I

LCD

DD

6. Tolerance depends on the temperature; (typically zero at T

ature range limit.

= 27°C), maximum tolerance values are measured at the temper-

amb

7. For TC0 to TC7

8. Data Byte Writing Mode

9.V

≤ V

DD1

DD2

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ELECTRICAL CHARACTERISTICS

AC OPERATION

(V

DD1

= 1.7 to 3.6V; V

= 1.75 to 4.2V; V

= 0V; V

= 4.5 to 11V; T

=-40 to 85°C; unless otherwise specified)

DD2

ss1,2

LCD

amb

Symbol

INTERNAL OSCILLATOR

Parameter

Test Condition

Min.

Typ.

Max.

Unit

F

Internal Oscillator frequency

V

= 2.8V;

64

20

72

80

kHz

OSC

DD

Tamb = -20 to +70 °C

F

External Oscillator frequency

Frame frequency

100

kHz

Hz

µs

EXT

F

T

fosc or fext = 72 kHz; note 1

75

FRAME

w(RES)

RES LOW pulse width

Reset Pulse Rejection

Internal Logic Reset Time

5

1

5

µs

T

µs

LOGIC

(RES)

T

V

vs. V Delay

DD2

0

µs

VDD

DD1

Figure 48. RESET timing diagram

Tlogic(res)

Tw(res)

VDD2

VDD1

RES

INPUTS

I/O

(HOST)

I/O

(DRIVER)

Hi-Z

INTERFACE

OUTPUT

OSCIN

(HOST)

OSC OUT

(DRIVER)

BSY FLG

RESET

TABLE

LOADED

LR0118

40/51

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ELECTRICAL CHARACTERISTICS

AC OPERATION

(V

DD1

= 1.7 to 3.6V; V

= 1.75 to 4.2V; V

= 0V; V

= 4.5 to 11V; T =-40 to 85°C; unless otherwise specified)

amb

DD2

ss1,2

LCD

Symbol

Parameter

I C BUS INTERFACE (See note 4)

SCL Clock Frequency

Test Condition

Min.

Typ.

Max.

Unit

2

F

Fast Mode

DC

400

3.4

kHz

SCL

High Speed Mode; Cb=100pF

(max);VDD1=2

MHz

High Speed Mode; Cb=400pF

(max); VDD1=2

DC

1.7

MHz

Fast Mode; VDD1=1.7V

Note 2, 3, Cb=100pF

400

KHz

ns

T

Set-up time (repeated) START

condition

160

SU;STA

HD;STA

Hold time (repeated) START

condition

Note 2, 3, Cb=100pF

ns

T

LOW period of the SCLH clock

160

60

ns

LOW

T

HIGH period of the SCLH clock Note 2, 3, Cb=100pF

HIGH

T

Data set-up time

Data hold time

Note 2, 3, Cb=100pF

Note 2, 3; Cb=100pF

10

SU;DAT

HD;DAT

40

10

T

r;CL

Rise time of SCLH signal

Note 2, 3; Cb=100pF

ns

T

Rise time of SCLH signal after a Note 2, 3, Cb=100pF

repeated START condition and

rCL1

after an acknowledge bit

T

Fall time of SCLH signal

Rise time of SDAH signal

Fall time of SDAH signal

Rise time of SDAH signal

Fall time of SDAH signal

Note 2, 3, Cb=100pF

Note 2, 3, 4, Cb=100pF

Note 2, 3, 4, Cb=400pF

10

ns

pF

fCL

rDA

fDA

rDA

fDA

T

10

80

20

160

T

Set-up time for STOP condition Note 2, 3, Cb=100pF

160

100

SU;STO

C

Capacitive load for SDAH and

SCLH

400

b

C

Capacitive load for SDAH + SDA

line and SCLH + SCL line

pF

b

2

Figure 49. I C-bus timings

Sr

Sr P

t

rDA

fDA

SDAH

SCLH

t

HD;DAT

t

HD;STA

t

SU;DAT

t

SU;STA

t

fCL

t

rCL1

rCL

rCL1

(1)

t

LOW HIGH

HIGH LOW

D00IN1153

= MCS current source pull-up

= Rp resistor pull-up

41/51

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ELECTRICAL CHARACTERISTICS (continued)

AC OPERATION

(V

DD1

= 1.7 to 3.6V; V

= 1.75 to 4.2V; V

= 0V; V

= 4.5 to 11V; T

=-40 to 85°C; unless otherwise specified)

DD2

ss1,2

LCD

amb

Symbol

PARALLEL INTERFACE

Parameter

Test Condition

Min.

Typ.

Max.

Unit

T

Enable Cycle Time

Enable Pulse width

Address Set-up Time

Address Hold Time

Data Set-Up Time

Data Hold Time

V

= 1.7V; Write; note 2, 6

DD1

150

60

30

40

30

ns

CY(EN)

T

W(EN)

T

SU(A)

T

H(A)

T

SU(D)

T

H(D)

SU(D)

HU(D)

T

Data Set-Up Time in read Mode

Data Hold Time In Read mode

100

Figure 50. Parallel interface Write timing

PD/C

t

W(en)

SU(A)

t

h(A)

E

t

SU(D) HO(D)

t

CY(en)

DB0-DB7

R/W

WRITE

Figure 51. Parallel interface Read timing

PD/C

Don't Care

t

W(en)

SU(A)

t

h(A)

E

t

HOR(D)

t

SUR(D)

t

CY(en)

DB0-DB7

R/W

READ

42/51

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ELECTRICAL CHARACTERISTICS (continued)

AC OPERATION

(V

DD1

= 1.7 to 3.6V; V

= 1.75 to 4.2V; V

= 0V; V

= 4.5 to 11V; T =-40 to 85°C; unless otherwise specified)

amb

DD2

ss1,2

LCD

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

SERIAL INTERFACE

T

Clock Cycle SCLK

V

DD1

= 1.7V; Write; note 2, 6

150

60

30

50

30

40

30

40

ns

CYC

T

SCLK pulse width HIGH

SCLK Pulse width LOW

SCE setup time

PWH1

T

PWL1

T

S2

SCE hold time

H2

T

PWH2

SCE minimum high time

SD/C setup time

T

S3

H3

S4

H4

S5

H5

H6

SD/C hold time

SDIN setup time

SDIN hold time

SOUT Access Time

100

SOUT Disable Time vs. SCLK

SOUT Disable Time vs. SCE

Figure 52. Serial interface Timing

t

PWH2

S2

H2

CS

t

S3

H3

D/C

t

CYC

t

WH1

PWL1

t

S2

SCLK

SDIN

SOUT

t

H4

S4

t

H6

t

H5

S5

LR0001

f_osc

Notes: 1. F_frame= ---------

960

2. All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to V and V with

IL

IH

an input voltage swing of V to V

SS

DD

3. Cb is the capacitive load for each bus line.

4. For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated

5. C

is the filtering Capacitor on VLCDOUT

VLCD

6. T

and T (30%-70%) = 10 ns

rise

fall

43/51

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Table 16. Pad Coordinates

Table 16. Pad Coordinates (continued)

NAME

C0

PAD

1

X (µm)

-3275.0

-3225.0

-3175.0

-3125.0

-3075.0

-3025.0

-2975.0

-2925.0

-2875.0

-2825.0

-2775.0

-2725.0

-2675.0

-2625.0

-2575.0

-2525.0

-2475.0

-2425.0

-2375.0

-2325.0

-2275.0

-2225.0

-2175.0

-2125.0

-2075.0

-2025.0

-1975.0

-1925.0

-1875.0

-1825.0

-1775.0

Y(µm)

-946.5

-946.11

-946.5

NAME

C31

C32

C33

C34

C35

C36

C37

C38

C39

C40

C41

C42

C43

C44

C45

C46

C47

C48

C49

C50

C51

C52

C53

C54

C55

C56

C57

C58

C59

C60

C61

PAD

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

X (µm)

-1725.0

-1675.0

-1625.0

-1575.0

-1525.0

-1475.0

-1425.0

-1375.0

-1325.0

-1275.0

-1225.0

-1175.0

-1125.0

-1075.0

-1025.0

-975.0

-925.0

-875.0

-825.0

-775.0

-725.0

-675.0

-625.0

-575.0

-525.0

-475.0

-425.0

-375.0

-325.0

-275.0

-225.0

Y(µm)

-946.5

C1

2

C2

3

C3

4

C4

5

C5

6

C6

7

C7

8

C8

9

C9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

C30

44/51

STE2002

Table 16. Pad Coordinates (continued)

NAME

C62

C63

C64

C65

C66

C67

C68

C69

C70

C71

C72

C73

C74

C75

C76

C77

C78

C79

C80

C81

C82

C83

C84

C85

C86

C87

C88

C89

C90

C91

C92

PAD

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

X (µm)

-175.0

Y(µm)

-946.5

NAME

C93

PAD

94

X (µm)

+1575.0

+1625.0

+1675.0

+1725.0

+1775.0

+1825.0

+1875.0

+1925.0

+1975.0

+2025.0

+2075.0

+2125.0

+2175.0

+2225.0

+2275.0

+2325.0

+2375.0

+2425.0

+2475.0

+2525.0

+2575.0

+2625.0

+2675.0

+2725.0

+2775.0

+2825.0

+2875.0

+2925.0

+2975.0

+3025.0

+3075.0

Y(µm)

-946.5

-125.0

C94

95

+125.0

+175.0

+225.0

+275.0

+325.0

+375.0

+425.0

+475.0

+525.0

+575.0

+625.0

+675.0

+725.0

+775.0

+825.0

+875.0

+925.0

+975.0

+1025.0

+1075.0

+1125.0

+1175.0

+1225.0

+1275.0

+1325.0

+1375.0

+1425.0

+1475.0

+1525.0

C95

96

C96

97

C97

98

C98

99

C99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

C100

C101

C102

C103

C104

C105

C106

C107

C108

C109

C110

C111

C112

C113

C114

C115

C116

C117

C118

C119

C120

C121

C122

C123

45/51

STE2002

Table 16. Pad Coordinates (continued)

NAME

C124

C125

C126

C127

R40

R41

R42

R43

R44

R45

R46

R47

R48

R49

R50

R51

R52

R53

R54

R55

R56

R57

R58

R59

R60

R61

R62

R63

R64

R65

R66

PAD

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

X (µm)

+3125.0

+3175.0

+3225.0

+3275.0

+3571.5

Y(µm)

-946.5

-875.0

-825.0

-775.0

-725.0

-675.0

-625.0

-575.0

-525.0

-475.0

-425.0

-375.0

-325.0

-275.0

-225.0

-175.0

-125.0

-75.0

NAME

R67

PAD

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

X (µm)

+3571.5

+3275.0

+3225.0

+3175.0

+3125.0

+3075.0

+2825.0

+2775.0

+2725.0

+2675.0

+2625.0

+2575.0

+2525.0

+2475.0

+2425.0

+2375.0

+2225.0

+2175.0

+2125.0

+2075.0

+2025.0

+1975.0

+1925.0

Y(µm)

+475.0

+525.0

+575.0

+625.0

+675.0

+725.0

+775.0

+825.0

+875.0

+946.5

R68

R69

R70

R71

R72

R73

R74

R75

R76

R77

R78

R79

R80/ICON

TEST_1

TEST_2

TEST_3

TEST_4

TEST_5

TEST_6

TEST_7

TEST_8

TEST_9

TEST_10

VSSAUX

SA1

-25.0

+25.0

+75.0

+125.0

+175.0

+225.0

+275.0

+325.0

+375.0

+425.0

SA0

EXT

SEL2

SEL1

ICON_MODE

46/51

STE2002

Table 16. Pad Coordinates (continued)

NAME

OSC_IN

VDD1_1

VDD1_2

VDD1_3

VDD1_4

VDD1_5

VDD1_6

VDD1_7

VDD1_8

VDD1_9

VDD1_10

VDD1_11

VDD1_12

VDD2_1

VDD2_2

VDD2_3

VDD2_4

VDD2_5

VDD2_6

VDD2_7

VDD2_8

VDD2_9

VDD2_10

VDD2_11

VDD2_12

BUSY_FLAG

SDOUT

SDIN

PAD

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

X (µm)

+1875.0

+1825.0

+1775.0

+1725.0

+1675.0

+1625.0

+1575.0

+1525.0

+1475.0

+1425.0

+1375.0

+1325.0

+1275.0

+1125.0

+975.0

Y(µm)

+946.5

+839.5

+946.5

+839.5

+946.5

+839.5

+946.5

+839.5

+946.5

+839.5

+946.5

+839.5

+946.5

+839.5

+946.5

+839.5

+946.5

+839.5

+946.5

+839.5

+946.5

+839.5

+946.5

+839.5

+946.5

NAME

VSSAUX

R/W

PAD

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

X (µm)

+625.0

+575.0

+525.0

+475.0

+425.0

+375.0

+325.0

+275.0

+225.0

+175.0

+125.0

+75.0

Y(µm)

+946.5

+839.5

+946.5

+839.5

+946.5

+839.5

+946.5

+839.5

+946.5

+839.5

+946.5

+839.5

+946.5

D7

D6

D5

D4

D3

D2

D1

D0

PD/C

E

RES

-75.0

VSSAUX

SDA_OUT

SDA_IN

SCL

-225.0

-275.0

-325.0

-375.0

-425.0

-975.0

-1025.0

-1075.0

-1125.0

-1175.0

-1225.0

-1275.0

VSS_1

VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12

VSS_13

+925.0

SD/C

+875.0

SCE

+825.0

SCLK

+775.0

47/51

STE2002

Table 16. Pad Coordinates (continued)

NAME

VSS_14

PAD

249

250

251

252

253

254

255

256

257

258

259

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

X (µm)

-1275.0

-1325.0

-1375.0

-1425.0

-1475.0

-1525.0

-1575.0

-1625.0

-2175.0

-2325.0

-2375.0

-2425.0

-2475.0

-2525.0

-2575.0

-2625.0

-2675.0

-2725.0

-2775.0

Y(µm)

+839.5

+946.5

+839.5

+946.5

+839.5

+946.5

+839.5

+946.5

+839.5

+946.5

+839.5

+946.5

+839.5

+946.5

+839.5

+946.5

+839.5

+946.5

+839.5

+946.5

+839.5

+946.5

+839.5

+946.5

+839.5

+946.5

NAME

VLCDOUT_8

VLCDOUT_9

VLCDOUT_10

R39

PAD

280

281

282

283

284

285

286

287

288

289

290

291

292

293

294

295

296

297

298

299

300

301

302

303

304

305

306

307

308

309

310

X (µm)

-2775.0

-2825.0

-3075.0

-3125.0

-3175.0

-3225.0

-3275.0

-3571.5

Y(µm)

+839.5

+946.5

+839.5

+946.5

+875.0

+825.0

+775.0

+725.0

+675.0

+625.0

+575.0

+525.0

+475.0

+425.0

+375.0

+325.0

+275.0

+225.0

+175.0

+125.0

+75.0

VSS_15

VSS_16

VSS_17

VSS_18

R38

VSS_19

R37

VSS_20

R36

TEST_11

R35

TEST_12

R34

TEST_13

R33

TEST_14

R32

OSC_OUT

VLCDIN_1

VLCDIN_2

VLCDIN_3

VLCDIN_4

VLCDIN_5

VLCDIN_6

VLCDIN_7

VLCDIN_8

VLCDIN_9

VLCDIN_10

VLCDSENSE_1

VLCDSENSE_2

VLCDOUT_1

VLCDOUT_2

VLCDOUT_3

VLCDOUT_4

VLCDOUT_5

VLCDOUT_6

VLCDOUT_7

R31

R30

R29

R28

R27

R26

R25

R24

R23

R22

R21

R20

R19

R18

R17

+25.0

R16

-25.0

R15

-75.0

R14

-125.0

-175.0

-225.0

R13

R12

48/51

STE2002

Table 16. Pad Coordinates (continued)

Figure 54. Alignment marks dimensions

NAME

R11

R10

R9

PAD

311

312

313

314

315

316

317

318

319

320

321

322

323

X (µm)

-3571.5

Y(µm)

-275.0

-325.0

-375.0

-425.0

-475.0

-525.0

-575.0

-625.0

-675.0

-725.0

-775.0

-825.0

-875.0

39 µm

94 µm

R8

R7

R6

R5

Table 17. Bumps

R4

Bump

Number

Dimensions

R3

Bumps on Single

Row Size

1-187

30

µ

m X 98

µ

m X 17.5

R2

212-235

256-260

283-323

R1

R0

Bumps on Two

Rows Size

188-211

236-255

261-282

30µ

m X 87

µm X 17.5

ICON

Pad Size

1-323

43µm X 107µm

Figure 53. Alignment marks coordinates

Pad Pitch

50µm

X

Y

MARKS

mark1

mark2

mark3

mark4

Spacing

between Bumps

20µm

-3574.5

+3574.5

-2250

-949.5

+949.5

Table 18. Die Mechanical Dimensions

Die Size

2.07mm x 7.32mm

+1200

Wafers Thickness

500µm

49/51

STE2002

Figure 55. DIE ORIENTATION IN TRAY

DIE IDENTIFICATION

Mark 3

Mark 1

Mark 4

Mark 2

STE2002

Figure 56. TRAY INFORMATION

A

Array Size = 13 x5 (65) Units

50/51

STE2002

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use.No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

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51/51


型号：	STE2002DIE2
厂家：	ST
描述：	81 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER 81 X 128单芯片LCD控制器/驱动显示驱动器驱动程序和接口接口集成电路控制器 CD
文件：	总51页 (文件大小：494K)
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STE2002DIE2 [STMICROELECTRONICS]

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