STN2NE10L_07 [STMICROELECTRONICS]

N-channel 100V - 0.33з -2A - SOT-223; N沟道100V - 0.33Ω -2A - SOT- 223
STN2NE10L_07
型号: STN2NE10L_07
厂家: ST    ST
描述:

N-channel 100V - 0.33з -2A - SOT-223
N沟道100V - 0.33Ω -2A - SOT- 223

文件: 总12页 (文件大小:236K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
STN2NE10L  
N-channel 100V - 0.33-2A - SOT-223  
STripFET™ Power MOSFET  
General features  
VDSS  
Type  
RDS(on)  
ID  
(@Tjmax)  
2
STN2NE10L  
100V  
<0.4Ω  
1.8A  
3
2
1
Exceptional dv/dt capability  
Avalanche rugged technology  
100% avalanche tested  
Low threshold drive  
SOT-223  
Description  
This Power MOSFET is the latest development of  
STMicroelectronics unique "Single Feature  
Size™" strip-based process. The resulting  
transistor shows extremely high packing density  
for low on-resistance, rugged avalanche  
characteristics and less critical alignment steps  
therefore a remarkable manufacturing  
reproducibility.  
Internal schematic diagram  
Applications  
Switching application  
Order codes  
Part number  
Marking  
Package  
Packaging  
STN2NE10L  
N2NE10L  
SOT-223  
Tape & reel  
February 2007  
Rev 5  
1/12  
www.st.com  
12  
Contents  
STN2NE10L  
Contents  
1
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
2.1  
Electrical characteristics (curves)  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
3
4
5
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
2/12  
STN2NE10L  
Electrical ratings  
1
Electrical ratings  
Table 1.  
Symbol  
Absolute maximum ratings  
Parameter  
Value  
Unit  
VDS  
VGS  
ID  
Drain-source voltage (VGS = 0)  
Gate-source voltage  
100  
20  
V
V
Drain current (continuous) at TC = 25°C  
Drain current (continuous) at TC=100°C  
Drain current (pulsed)  
1.8  
1.3  
7.2  
2.5  
0.02  
6
A
ID  
A
(1)  
IDM  
A
PTOT  
Total dissipation at TC = 25°C  
Derating factor  
W
W/°C  
V/ns  
dv/dt (2)  
Peak diode recovery voltage slope  
TJ  
Operating junction temperature  
Storage temperature  
150  
°C  
Tstg  
-65 to 150  
1. Pulse width limited by safe operating area  
2. ISD 7.2 A, di/dt 200As, VDD V(BR)DSS, TJ TJMAX  
Table 2.  
Rthj-pcb  
Thermal data  
Thermal resistance junction-PC Board max  
50  
60  
°C/W  
°C/W  
Rthj-amb Thermal resistance junction-ambient max  
Maximum lead temperature for soldering  
purpose  
Tl  
260  
°C  
Table 3.  
Avalanche characteristics  
Parameter  
Symbol  
Value  
Unit  
Avalanche current, repetitive or not-repetitive  
(pulse width limited by Tj Max)  
IAR  
1.8  
20  
A
Single pulse avalanche energy  
EAS  
mJ  
(starting Tj=25°C, Id=Iar, Vdd=25V)  
3/12  
Electrical characteristics  
STN2NE10L  
2
Electrical characteristics  
(T  
=25°C unless otherwise specified)  
CASE  
Table 4.  
Symbol  
On/off states  
Parameter  
Test conditions  
Min.  
Typ.  
Max.  
Unit  
Drain-source breakdown  
voltage  
ID = 250 µA, VGS= 0  
V(BR)DSS  
100  
V
V
DS = Max rating,  
1
µA  
µA  
Zero gate voltage drain  
current (VGS = 0)  
IDSS  
VDS = Max rating @125°C  
10  
Gate body leakage current  
(VDS = 0)  
VGS = 20V  
IGSS  
100  
3
nA  
V
VDS= VGS, ID = 250µA  
VGS(th) Gate threshold voltage  
1
1.7  
VGS= 10V, ID= 1A  
VGS= 5V, ID= 1A  
0.33  
0.38  
0.4  
Static drain-source on  
resistance  
RDS(on)  
0.45  
Table 5.  
Symbol  
Dynamic  
Parameter  
Test conditions  
Min. Typ. Max. Unit  
VDS>ID(on) x RDS(on)max,  
ID=1A  
(1)  
gfs  
Forward transconductance  
1
3
S
Input capacitance  
Output capacitance  
Ciss  
Coss  
Crss  
345  
45  
pF  
pF  
pF  
VDS =25V, f=1 MHz, VGS=0  
Reverse transfer  
capacitance  
20  
Qg  
Qgs  
Qgd  
Total gate charge  
Gate-source charge  
Gate-drain charge  
VDD=80V, ID = 7A  
VGS =5V  
10  
5
14  
nC  
nC  
nC  
(see Figure 13)  
4
1. Pulsed: pulse duration=300µs, duty cycle 1.5%  
Table 6.  
Symbol  
Switching times  
Parameter  
Test conditions  
Min. Typ. Max. Unit  
VDD=50 V, ID=3.5A,  
RG=4.7, VGS=5V  
(see Figure 14)  
td(on)  
tr  
Turn-on delay time  
rise time  
7
ns  
ns  
17  
VDD=50 V, ID=3.5A,  
td(off)  
tf  
Turn-off-delay time  
fall time  
22  
8
ns  
ns  
RG=4.7, VGS=5V  
(see Figure 14)  
tr(Voff)  
Off-voltage Rise Time  
Fall Time  
VDD=80 V, ID=7A,  
RG=4.7, VGS=5V  
(see Figure 14)  
8
9
ns  
ns  
ns  
tf  
Cross-over Time  
19  
tc  
4/12  
STN2NE10L  
Electrical characteristics  
Min. Typ. Max Unit  
Table 7.  
Symbol  
Source drain diode  
Parameter  
Test conditions  
ISD  
Source-drain current  
2
8
A
A
(1)  
ISDM  
Source-drain current (pulsed)  
(2)  
ISD=2A, VGS=0  
Forward on voltage  
1.5  
V
VSD  
trr  
ISD=7 A,  
Reverse recovery time  
Reverse recovery charge  
Reverse recovery current  
75  
190  
5
ns  
nC  
A
Qrr  
di/dt = 100A/µs,  
VDD=30 V, Tj=150°C  
IRRM  
1. Pulse width limited by safe operating area.  
2. Pulsed: pulse duration=300µs, duty cycle 1.5%  
5/12  
Electrical characteristics  
STN2NE10L  
2.1  
Electrical characteristics (curves)  
Figure 1. Safe operating area  
Figure 2. Thermal impedance  
Figure 3.  
Output characteristics  
Figure 4.  
Transfer characteristics  
Figure 5. Transconductance  
Figure 6. Static drain-source on resistance  
6/12  
STN2NE10L  
Electrical characteristics  
Figure 7. Gate charge vs. gate-source voltage Figure 8. Capacitance variations  
Figure 9. Normalized gate threshold voltage Figure 10. Normalized on resistance vs.  
vs. temperature  
temperature  
Figure 11. Source-drain diode forward  
characteristics  
7/12  
Test circuit  
STN2NE10L  
3
Test circuit  
Figure 12. Switching times test circuit for  
resistive load  
Figure 13. Gate charge test circuit  
Figure 14. Test circuit for inductive load  
switching and diode recovery times  
Figure 15. Unclamped Inductive load test  
circuit  
Figure 16. Unclamped inductive waveform  
Figure 17. Switching time waveform  
8/12  
STN2NE10L  
Package mechanical data  
4
Package mechanical data  
In order to meet environmental requirements, ST offers these devices in ECOPACK®  
packages. These packages have a Lead-free second level interconnect. The category of  
second level interconnect is marked on the package and on the inner box label, in  
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering  
conditions are also marked on the inner box label. ECOPACK is an ST trademark.  
ECOPACK specifications are available at: www.st.com  
9/12  
Package mechanical data  
STN2NE10L  
SOT-223 MECHANICAL DATA  
mm  
mils  
TYP.  
90.6  
181.1  
15.7  
25.6  
63  
DIM.  
MIN.  
2.27  
4.57  
0.2  
TYP.  
2.3  
MAX.  
2.33  
4.63  
0.6  
MIN.  
89.4  
179.9  
7.9  
MAX.  
91.7  
a
b
4.6  
182.3  
23.6  
c
0.4  
d
0.63  
1.5  
0.65  
1.6  
0.67  
1.7  
24.8  
59.1  
26.4  
e1  
e4  
f
66.9  
0.32  
3.1  
12.6  
2.9  
0.67  
6.7  
3
114.2  
26.4  
118.1  
27.6  
122.1  
28.7  
g
0.7  
7
0.73  
7.3  
l1  
l2  
L
263.8  
137.8  
248  
275.6  
137.8  
255.9  
287.4  
145.7  
263.8  
3.5  
3.5  
6.5  
3.7  
6.3  
6.7  
L
l2  
d
a
e4  
c
b
f
C
C
B
E
g
P008B  
10/12  
STN2NE10L  
Revision history  
5
Revision history  
Table 8.  
Date  
Revision history  
Revision  
Changes  
19-Oct-2005  
05-March-2006  
19-Sep-2006  
01-Feb-2007  
2
3
4
5
Preliminary datasheet  
Modified value on Table 4  
New template, no content change  
Typo mistake on Table 1.  
11/12  
STN2NE10L  
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12/12  

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