STV6888 [STMICROELECTRONICS]
LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR; 低成本I2C可控弯曲处理器的MultiSync显示器
| 型号： | STV6888 |
| 厂家： | 
ST |
| 描述： | LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR |
| 文件： | 总46页 (文件大小：723K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STV6888
LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR
FOR MULTISYNC MONITOR
FEATURES
Dynamic correction section
■ Output with vertical dynamic correction
waveform for dynamic corrections like focus,
brightness uniformity, ...
General
■ ADVANCED I2C BUS CONTROLLED
DEFLECTION PROCESSOR DEDICATED
FOR HIGH-END CRT MONITORS
■ Fixed on screen by means of tracking system
■ SINGLE SUPPLY VOLTAGE 12V
■ VERY LOW JITTER
■ DC/DC CONVERTER CONTROLLER
■ ADVANCED EW DRIVE
DC/DC controller section
■ Step-up and step-down conversion modes
■ External sawtooth configuration
■ Bus-controlled output voltage
■ ADVANCED ASYMMETRY CORRECTIONS
■ Synchronization on hor. frequency with phase
selection
■ AUTOMATIC MULTISTANDARD
SYNCHRONIZATION
■ Selectable polarity of drive signal
■ VERTICAL DYNAMIC CORRECTION
DESCRIPTION
WAVEFORM OUTPUT
The STV6888 is a monolithic integrated circuit as-
sembled in a 32-pin shrink dual-in-line plastic
package. This IC controls all the functions related
to horizontal and vertical deflection in multimode
or multi-frequency computer display monitors.
■ X-RAY PROTECTION AND SOFT-START &
STOP ON HORIZONTAL AND DC/DC DRIVE
OUTPUTS
■ I2C BUS STATUS REGISTER
Horizontal section
■ 100 kHz maximum frequency
The internal sync processor, combined with the
powerful geometry correction block, makes the
STV6888 suitable for very high performance mon-
itors, using few external components.
■ Corrections of geometric asymmetry:
Pin cushion asymmetry, Parallelogram
■ Tracking of asymmetry corrections with vertical
Combined with other ST components dedicated
for CRT monitors (microcontroller, video preampli-
fier, video amplifier, OSD controller) the STV6888
allows fully I2C bus-controlled computer display
monitors to be built with a reduced number of ex-
ternal components
size and position
■ Fully integrated internal horizontal moiré
cancellation and moiré cancellation output
Vertical section
■ 200 Hz maximum frequency
■ Vertical ramp for DC-coupled output stage with
adjustments of: C-correction, S-correction for
super-flat CRT, Vertical size, Vertical position
ORDERING INFORMATION
Ordering code
package
Shrink 32
■ Vertical moiré cancellation through vertical
ramp waveform
STV6888
■ Compensation of vertical breathing with EHT
variation
EW section
.
■ Symmetrical geometry corrections: Pin cushion,
Keystone, Top/Bottom corners separately
■ Horizontal size adjustment
■ Tracking of EW waveform with Vertical size and
position and adaptation to frequency
■ Compensation of horizontal breathing through
EW waveform
Version 4.1
August 2003
1/47
1
Table of Contents
1 - GLOSSARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 - PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 - BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 - PIN FUNCTION REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 - QUICK REFERENCE DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6 - ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7 - ELECTRICAL PARAMETERS AND OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . 10
7.1 -THERMAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7.2 -SUPPLY AND REFERENCE VOLTAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7.3 -SYNCHRONIZATION INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7.4 -HORIZONTAL SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.5 -VERTICAL SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.6 -EW DRIVE SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.7 -DYNAMIC CORRECTION OUTPUT SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.8 -DC/DC CONTROLLER SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.9 -MISCELLANEOUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8 - TYPICAL OUTPUT WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2
9 - I C BUS CONTROL REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10 - OPERATING DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10.1 -SUPPLY AND CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10.1.1 -Power supply and voltage references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10.1.2 -I2C Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10.2 -SYNC. PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10.2.1 -Synchronization signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10.2.2 -Sync. presence detection flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.2.3 -MCU controlled sync. selection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.2.4 -Automatic sync. selection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.3 -HORIZONTAL SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.3.1 -General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.3.2 -PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.3.3 -Voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10.3.4 -PLL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10.3.5 -Dynamic PLL2 phase control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10.3.6 -Output Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10.3.7 -Soft-start and soft-stop on H-drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10.3.8 -Horizontal moiré cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2/47
10.4 -VERTICAL SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.4.1 -General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.4.2 -Vertical moiré . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10.5 -EW DRIVE SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.6 -DYNAMIC CORRECTION OUTPUT SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.6.1 -Vertical dynamic correction output VDyCor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.7 -DC/DC CONTROLLER SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.8 -MISCELLANEOUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.8.1 -Safety functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.8.2 -Soft start and soft stop functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.8.3 -X-ray protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.8.4 -Composite output HLckVBk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
11 - INTERNAL SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12 - PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3/47
STV6888
1 - GLOSSARY
AC
Alternate Current
ACK
AGC
COMP
CRT
DC
ACKnowledge bit of I2C-bus transfer
Automatic Gain Control
COMParator
Cathode Ray Tube
Direct Current
EHT
EW
Extra High Voltage
East-West
H/W
HOT
I2C
HardWare
Horizontal Output Transistor
Inter-Integrated Circuit
Inter-Integrated Circuit
Micro-Controller Unit
Negated AND (logic operation)
Negative-Positive-Negative
OSCillator
IIC
MCU
NAND
NPN
OSC
PLL
PNP
REF
RS, R-S
S/W
TTL
Phase-Locked Loop
Positive-Negative-Positive
REFerence
Reset-Set
SoftWare
Transistor Transistor Logic
Voltage-Controlled Oscillator
VCO
4/47
STV6888
2 - PIN CONFIGURATION
H/HVSyn
VSyn
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDyCor
SDA
1
2
HLckVBk
HOscF
HPLL2C
CO
3
SCL
Vcc
4
BOut
5
GND
6
HGND
RO
7
HOut
XRay
8
HPLL1F
HPosF
HMoiré
HFly
EWOut
VOut
9
10
11
12
13
14
15
16
VCap
VGND
VAGCCap
VOscF
VEHTIn
HEHTIn
RefOut
BComp
BRegIn
BISense
5/47
HFly
HGND
HPosF
HPLL1F
R0 C0 HOscF
HPLL2C
7
10
9
8
6
4
12
5
H-drive
buffer
H-sync
detection
26
25
HOut
XRay
Horizontal
VCO
Phase/frequency
comparator
1
H/HVSyn
HLckVBk
Phase comparator
Phase shifter
H duty controller
Pin cushion asymm.
Parallelogram
Polarity
handling
Horizontal position
Safety
processor
Lock detection
Hor. duty cycle
PLL1
V-blank
H-lock
3
28
16
15
14
BOut
Int./Ext. H-moiré
B+
H-moiré amplitude
Control voltage level
PLL2
BISense
BRegIn
BComp
DC/DC
converter
controller
B+ ref.
31
30
I2C Bus
interface
SDA
SCL
I2C Bus registers
2
:
Functions controlled via I C Bus
29
13
Vcc
Supply
supervision
11
V-dynamic
correction
(focus, bright.)
HMoiré
Geometry
tracking
V-sync
extraction
& detection
Reference
generation
RefOut
VDyCor amplitude
Internal
ref.
EW generator
V-ramp control
H size
27
GND
Tracking EHT
Vertical size
Vertical position
Vertical moiré
Pin cushion
Keystone
Top corners
Bottom corners
Vertical oscillator
V-sync detection
Input selection
Polarity handling
24
EWOut
with AGC
S-correction
C-correction
STV6888
2
21
19
20
22
32
23
18
17
VGND
VOscF
VSyn
VDyCor
VOut
VEHTIn
HEHTIn
VCap
VAGCCap
STV6888
4 - PIN FUNCTION REFERENCE
Pin
1
Name
H/HVSyn
VSyn
Function
TTL compatible Horizontal / Horizontal and Vertical Sync. input
TTL compatible Vertical Sync. input
2
3
HLckVBk
HOscF
HPLL2C
CO
Horizontal PLL1 Lock detection and Vertical early Blanking composite output
High Horizontal Oscillator sawtooth threshold level Filter input
Horizontal PLL2 loop Capacitive filter input
Horizontal Oscillator Capacitor input
4
5
6
7
HGND
RO
Horizontal section GrouND
8
Horizontal Oscillator Resistor input
9
HPLL1F
HPosF
HMoiré
HFly
Horizontal PLL1 loop Filter input
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Horizontal Position Filter and soft-start time constant capacitor input
Horizontal Moiré output
Horizontal Flyback input
RefOut
BComp
BRegIn
BISense
HEHTIn
VEHTIn
VOscF
VAGCCap
VGND
VCap
Reference voltage Output
B+ DC/DC error amplifier (Comparator) output
Regulation feedback Input of the B+ DC/DC converter controller
B+ DC/DC converter current (I) Sense input
Input for compensation of Horizontal amplitude versus EHT variation
Input for compensation of Vertical amplitude versus EHT variation
Vertical Oscillator sawtooth low threshold Filter (capacitor to be connected to VGND)
Input for storage Capacitor for Automatic Gain Control loop in Vertical oscillator
Vertical section GrouND
Vertical sawtooth generator Capacitor
Vertical deflection drive Output for a DC-coupled output stage
E/W Output
VOut
EWOut
XRay
X-Ray protection input
HOut
Horizontal drive Output
GND
Main GrouND
BOut
B+ DC/DC converter controller Output
Supply voltage
Vcc
2
SCL
I C bus Serial CLock Input
2
SDA
I C bus Serial DAta input/output
VDyCor
Vertical Dynamic Correction output
7/47
STV6888
5 - QUICK REFERENCE DATA
Characteristic
Value
Unit
General
Package
SDIP 32
12
Supply voltage
V
Supply current
65
mA
Application category
Mid-range
2
Means of control/Maximum clock frequency
EW drive
I C bus/400
kHz
Yes
Yes
No
DC/DC converter controller
Adjustable DC level output
Horizontal section
Frequency range
15 to 100
4.28
kHz
Autosync frequency ratio (can be enlarged in application)
Positive/Negative polarity of horizontal sync signal/Automatic adaptation
Duty cycle range of the drive signal
Position adjustment range with respect to H period
Soft start/Soft stop feature
Yes/Yes/Yes
30 to 65
±10
%
%
Yes/Yes
Yes/Yes
Yes
Hardware/Software PLL lock indication
Parallelogram
Pin cushion asymmetry correction (also called Side pin balance)
Top/Bottom/Common corner asymmetry correction
Tracking of asymmetry corrections with vertical size & position
Horizontal moiré cancellation (int./ext.) for Combined/Separated architecture
Vertical section
Yes
No/No/No
Yes
Yes/Yes
Frequency range
35 to 200
50 to 180
Yes/Yes/Yes
Yes/Yes/Yes
Yes/Yes
Yes
Hz
Hz
Autosync frequency range (150nF at VCap and 470nF at VAGCCap)
Positive/Negative polarity of vertical sync signa/Automatic adaptationl
S-correction/C-correction/Super-flat tube characteristic
Vertical size/Vertical position adjustment
Vertical moiré cancellation (internal)
Vertical breathing compensation
Yes
EW section
Pin cushion correction
Yes
Yes
Keystone correction
Top/Bottom/Common corner correction
Horizontal size adjustment
Yes/Yes/No
Yes
Tracking of EW waveform with Frequency/Vertical size & position
Breathing compensation on EW waveform
Dynamic correction section (dyn. focus, dyn. brightness,...)
Vertical dynamic correction output
Horizontal dynamic correction output
Composite HV dynamic correction output
Tracking of vertical waveform with V. size & position
DC/DC controller section
Yes/Yes
Yes
Yes
No
No
Yes
Step-up/Step-down conversion mode
Internal/External sawtooth configuration
Bus-controlled output voltage
Yes/Yes
No/Yes
Yes
Soft start/Soft stop feature
Yes/Yes
Yes/Yes
Positive(N-MOS)/Negative(P-MOS) polarity of BOut signal
8/47
STV6888
6 - ABSOLUTE MAXIMUM RATINGS
All voltages are given with respect to ground.
Currents flowing from the device (sourced) are signed negative. Currents flowing to the device are signed
positive.
Value
Symbol
Parameter
Unit
Min
Max
V
Supply voltage (pin Vcc)
-0.4
13.5
V
CC
PinsHEHTIn, VEHTIn, XRay, HOut, BOut
PinsH/HVSyn, VSyn, SCL, SDA
PinsHLckVBk, CO, RO, HPLL1F, HPosF, HMoiré, BRegIn, BI-
Sense, VAGCCap, VCap, VDyCor, HOscF, VOscF
Pin HPLL2C
-0.4
-0.4
-0.4
V
5.5
V
V
V
CC
V
RefO
V
(pin)
-0.4
-0.4
V
/2
V
V
RefO
Pin HFly
V
RefO
ESD susceptibility
(human body model: discharge of 100pF through 1.5kΩ)
V
ESD
-2000
-40
2000
150
V
T
Storage temperature
Junction temperature
°C
°C
stg
T
150
j
9/47
STV6888
7 - ELECTRICAL PARAMETERS AND OPERATING CONDITIONS
The medium (middle) value of an I2C Bus control
or adjustment register composed of bits D0,
D1,...,Dn is the one having Dn at "1" and all other
bits at "0". The minimum value is the one with all
bits at 0, maximum value is the one with all at "1".
Currents flowing from the device (sourced) are
signed negative. Currents flowing to the device are
signed positive.
TH is the period of horizontal deflection.
7.1 - THERMAL DATA
Value
Unit
Symbol
Parameter
Min.
Typ.
Max.
T
Operating ambient temperature
Junction-ambience thermal resistance
0
70
°C
amb
R
65
°C/W
th(j-a)
7.2 - SUPPLY AND REFERENCE VOLTAGES
T
amb = 25°C
Value
Symbol
Parameter
Test Conditions
Units
Min.
Typ.
12
Max.
V
Supply voltage at Vcc pin
10.8
13.2
V
CC
I
Supply current to Vcc pin
V
V
= 12V
65
mA
V
CC
CC
CC
V
Reference output voltage at RefOut pin
Current sourced by RefOut output
= 12V, I
= -2mA
7.65
-5
7.9
8.2
0
RefO
RefO
RefO
I
mA
7.3 - SYNCHRONIZATION INPUTS
Vcc = 12V, Tamb = 25°C
Value
Typ.
Symbol
Parameter
Test Conditions
Units
Min.
0
Max.
0.8
5
V
LOW level voltage on H/HVSyn
HIGH level voltage on H/HVSyn
LOW level voltage on VSyn
V
V
LoH/HVSyn
V
2.2
0
HiH/HVSyn
V
0.8
5
V
LoVSyn
V
HIGH level voltage on VSyn
2.2
100
0.5
V
HiVSyn
R
Internal pull-down on H/HVSyn, VSyn
H sync. pulse duration on H/HVSyn pin
Proportion of H sync pulse to H period
V sync. pulse duration
175
0.3
250
kΩ
µs
PdSyn
PulseHSyn
t
t
t
/T
Pin H/HVSyn
0.2
750
0.15
PulseHSyn
H
V
t
Pins H/HVSyn, VSyn
Pins H/HVSyn, VSyn
0.5
µs
PulseVSyn
/T
Proportion of V sync pulse to V period
PulseVSyn
Proportion of sync pulse length to H peri- Pin H/HVSyn,
od for extraction as V sync pulse
t
/T
0.21
0.75
extrV
H
cap. on pin CO = 820pF
t
Polarity detection time (after change)
Pin H/HVSyn
ms
HPolDet
10/47
STV6888
7.4 - HORIZONTAL SECTION
Vcc = 12V, Tamb = 25°C
Value
Typ.
Symbol
Parameter
Test Conditions
Units
Min.
Max.
PLL1
I
Current load on RO pin
1.5
mA
pF
RO
C
Capacitance on CO pin
390
CO
HO
f
Frequency of hor. oscillator
Free-running frequency of hor. oscill.
100
29.9
122
kHz
kHz
kHz
(1)
f
R
=5.23kΩ, C =820pF 27
28.5
-150
HO(0)
RO
CO
(4)
f
Hor. PLL1 capture frequency
f
= 28.5kHz
29
HOCapt
HO(0)
∆f
(3)
HO(0)
Temperature drift of free-running freq.
ppm/°C
----------------------------
∆T
f
HO(0)
∆f /∆V
Average horizontal oscillator sensitivity
H. oscill. control voltage on pin HPLL1F
f
= 28.5kHz
=8V
19.6
5.0
kHz/V
V
HO
HO
HO(0)
V
V
1.4
6.0
HO
RefO
RefO
Threshold on H. oscill. control voltage on
HPLL1F pin for tracking of EW with freq.
V
V
=8V
V
HOThrfr
HPOS (Sad01):
1111111xb
1000000xb
2.8
3.4
4.0
V
V
V
V
Control voltage on HPosF pin
HPosF
0000000xb
(6)
V
Bottom of hor. oscillator sawtooth
1.6
6.4
V
V
HOThrLo
(6)
V
Top of hor. oscillator sawtooth
HOThrHi
PLL2
(2)
R
Input impedance on HFly input
Current into HFly input
V
>V
ThrHFly
300
0.6
500
700
5
Ω
mA
V
In(HFly)
(HFly)
I
At top of H flyback pulse
InHFly
V
Voltage threshold on HFly input
0.7
4.0
ThrHFly
No PLL2 phase modula-
tion
(6)
V
H flyback lock middle point
V
S(0)
(5)
V
Low clamping voltage on HPLL2C pin
1.6
4.0
V
V
BotHPLL2C
(5)
V
High clamping voltage on HPLL2C pin
TopHPLL2C
Min. advance of H-drive OFF before
middle of H flyback
t
(min)/T
Null asym. correction
Null asym. correction
0
%
%
(7)
ph
H
Max. advance of H-drive OFF before
t
(max)/T
44
(8)
ph
H
middle of H flyback
H-drive output on pin HOut
I
Current into HOut output
Output driven LOW
30
mA
HOut
HDUTY (Sad00):
x1111111b
x0000000b
27
65
85
%
%
%
t
/T
Duty cycle of H-drive signal
Hoff
H
Soft-start/Soft-stop value
Picture geometry corrections through PLL1 & PLL2
HPOS (Sad01):
1111111xb
0000000xb
H-flyback (center) static phase vs. sync
signal (via PLL1), see Figure 7
t
/T
+11
-11
%
%
Hph
H
11/47
STV6888
Value
Typ.
Symbol
Parameter
Test Conditions
Units
Min.
Max.
PCAC (Sad11h) full span
(9)
Contribution of pin cushion asymmetry
correction to phase of H-drive vs. static
phase (via PLL2), measured in corners
VPOS at medium
VSIZE at minimum
VSIZE at medium
VSIZE at maximum
t
/T
H
PCAC
±1.0
±1.8
±2.8
%
%
%
PARAL (Sad12h) full span
(9)
VPOS at medium
VSIZE at minimum
VSIZE at medium
VSIZE at maximum
VPOS at max. or min.
VSIZE at minimum
Contribution of parallelogram correction
to phase of H-drive vs. static phase (via
PLL2), measured in corners
±1.75
±2.2
±2.8
%
%
%
t
/T
H
ParalC
±1.75
%
Note 1: Frequency at no sync signal condition. For correct operation, the frequency of the sync signal applied must
always be higher than the free-running frequency. The application must consider the spread of values of real
electrical components in R and C positions so as to always meet this condition. The formula to calculate
RO
CO
the free-running frequency is
f
=0.12125/(R
C
)
HO(0)
RO CO
Note 2: Base of NPN transistor with emitter to ground is internally connected on pin HFly through a series resistance of
about 500Ω and a resistance to ground of about 20kΩ.
Note 3: Evaluated and figured out during the device qualification phase. Informative. Not tested on every single unit.
Note 4: This capture range can be enlarged by external circuitry.
Note 5: The voltage on HPLL2C pin corresponds to immediate phase of leading edge of H-drive signal on HOut pin with
respect to internal horizontal oscillator sawtooth. It must be between the two clamping levels given. Voltage
equal to one of the clamping values indicates a marginal operation of PLL2 or non-locked state.
Note 6: Internal threshold. See Figure 10.
Note 7: The t (min)/T parameter is fixed by the application. For correct operation of asymmetry corrections through
ph
H
dynamic phase modulation, this minimum must be increased by maximum of the total dynamic phase required
in the direction leading to bending of corners to the left. Marginal situation is indicated by reach of V
TopHPLL2C
high clamping level by waveform on pin HPLL2C. Also refer to Note 5 and Figure 10.
Note 8: The t (max)/T parameter is fixed by the application. For correct operation of asymmetry corrections through
ph
H
dynamic phase modulation, this maximum must be reduced by maximum of the total dynamic phase required in
the direction leading to bending of corners to the right. Marginal situation is indicated by reach of V
BotHPLL2C
low clamping level by waveform on pin HPLL2C. Also refer to Note 5 and Figure 10 .
Note 9: All other dynamic phase corrections of picture asymmetry set to their neutral (medium) positions.
7.5 - VERTICAL SECTION
VCC = 12V, Tamb = 25°C
Value
Symbol
Parameter
Test Conditions
Units
Min.
Typ.
Max.
AGC-controlled vertical oscillator sawtooth; V
= 8V
RefO
Ext. load resistance on
VAGCCap pin
R
∆V
/V (R=∞) ≤1%
65
MΩ
(10)
L(VAGCCap)
amp amp
Sawtooth bottom voltage on
VCap pin
(11)
V
No load on VOscF pin
2
V
(11)
VOB
AGC loop stabilized
V sync present
No V sync
Sawtooth top voltage on VCap
pin
V
5
4.9
V
V
VOT
12/47
STV6888
Value
Symbol
Parameter
Test Conditions
Units
Min.
Typ.
80
Max.
t
Sawtooth Discharge time
Free-running frequency
AGC loop capture frequency
C
C
C
=150nF
=150nF
=150nF
µs
Hz
Hz
VODis
VCap
VCap
VCap
f
100
VO(0)
f
50
185
VOCapt
∆V
VOdev
(12)
(12)
(13)
--------------------------------
Sawtooth non-linearity
AGC loop stabilized,
0.5
%
V
(16)
VOamp
AGC loop stabilized,
∆V
VOS – cor
(15)
--------------------------------
S-correction range
-5
+5
%
%
t
t
=1/4 T
=3/4 T
VR
VR
VR
VR
V
VOamp
(14)
AGC loop stabilized,
(15)
t
=1/2 T
VR
VR
∆V
VOC – cor
CCOR(Sad0A):
x0000000b
x1000000b
x1111111b
--------------------------------
C-correction range
-3
0
+3
%
%
%
V
VOamp
∆V
Frequency drift of sawtooth
amplitude
AGC loop stabilized
ppm/
Hz
VOamp
----------------------------------------
200
(17)(18)
f
(min)≤f ≤f (max)
V
∆f
VO
VOCapt VO VOCapt
VOamp
Vertical output drive signal (on pin VOut);V
= 8V
RefO
VPOS (Sad08):
x0000000b
x1000000b
x1111111b
3.2
3.5
3.8
3.3
2.5
V
V
V
V
Middle point on VOut sawtooth
mid(VOut)
3.65
3.5
VSIZE (Sad07):
x0000000b
x1000000b
x1111111b
2
Amplitude of VOut sawtooth
(peak-to-peak voltage)
2.25
3.0
3.75
V
V
V
V
amp
V
Level on VOut pin at V-drive "off" I Cbit VOutEn at 0
Current delivered by VOut output
3.8
V
offVOut
I
-5
1
5
mA
VOut
Control input voltage range on-
VEHTIn pin
V
V
V
RefO
VEHT
∆V
ς
ς
>
0
2.5
%/V
%/V
amp
VEHT VRefO
-----------------------------------------
∆V
Breathing compensation
(min)≤ς
≤
VEHT VRefO
V
VEHT
amp
VEHT
Note 10: Value of acceptable cumulated parasitic load resistance due to humidity, AGC storage capacitor leakage, etc.,
for less than 1% of V change.
amp
Note 11: The threshold for V
is generated internally and routed to VOscF pin. Any DC current on this pin will
VOB
influence the value of V
.
VOB
Note 12: Maximum of deviation from an ideally linear sawtooth ramp at null SCOR (Sad09 at x0000000b) and null CCOR
(Sad0A at x1000000b). The same rate applies to V-drive signal on VOut pin.
Note 13: Maximum SCOR (Sad09 at x1111111b), null CCOR (Sad0A at x1000000b).
Note 14: Null SCOR (Sad09 at x0000000b).
Note 15: "t " is time from the beginning of vertical ramp of V-drive signal on VOut pin. "T " is duration of this ramp, see
VR
VR
chapterTYPICAL OUTPUT WAVEFORMS and Figure 13.
Note 16: V
=
-
VOamp VVOT VVOB
Note 17: The same rate applies to V-drive signal on VOut pin.
Note 18: Informative, not tested on each unit.
13/47
STV6888
7.6 - EW DRIVE SECTION
VCC = 12V, Tamb = 25°C
Value
Typ.
Symbol
Parameter
Test Conditions
Units
Min.
Max.
V
Output voltage on EWOut pin
1.8
6.5
V
EW
Current sourced by EWOut out-
put
I
-1.5
1
0
mA
EWOut
Control voltage range on HEH-
TIn pin
V
V
VRefO
HEHT
(19)(22)(23)(30)
(15)
t
=1/2 T
VR
VR
DC component of the EW-drive
signal on EWOut pin
HSIZE (Sad10h):
0000000xb
1000000xb
V
EW-DC
2
3.25
4.5
V
V
V
1111111xb
(19)(20)(21)(22)
(15)
∆V
Breathing compensation on
t
ς
ς
=1/2 T
EW – DC
VR
VR
----------------------------
V
>
0
V/V
V/V
∆V
EW-DC
HEHT VRefO
HEHT
(min)≤ς
≤
-0.125
HEHT
HEHT VRefO
Temperature drift of DC compo-
nent of the EW-drive signal on
EWOut pin
(15)
∆V
t
=1/2 T
EW – DC
-------------------------------------
VR
VR
100
ppm/°C
(18)(19)(21)(23)(30)
V
∆T
Notes
EW – DC
(19)(20)(21)(23)(24)(25)(26)(30)
VSIZE at maximum
PCC (Sad0C):
x0000000b
x1000000b
x1111111b
0
0.7
1.5
V
V
V
Pin cushion correction compo-
nent of the EW-drive signal on
EWOut pin
V
EW-PCC
Tracking with VSIZE :
PCC at x1000000b
VSIZE (Sad07):
x0000000b
0.25
0.5
V
V
x1000000b
(19)(20)(21)(24)(27)(29)(30)
Tracking of PCC component of PCC at x1111111b
the EW-drive signal with vertical VPOS (Sad08):
V
[t = 0]
EW – PCC vr
---------------------------------------------------------
V
[t = T
]
VR
position adjustment
x0000000b
0.52
1.92
EW – PCC vr
x1111111b
(20)(21)(22)(23)(24)(27)(28)(30)
Keystone correction component
of the EW-drive signal on EWOut
pin
KEYST (Sad0D):
x0000000b
x1111111b
V
EW-Key
0.4
-0.4
V
V
(19)(21)(22)(23)(24)(25)(27)(30)
Top corner correction compo-
nent of the EW-drive signal on
EWOut pin
TCC (Sad0E):
x0000000b
x1000000b
x1111111b
(19)(20)(22)(23)(24)(26)(27)(30)
V
-1.25
0
+1.25
V
V
V
EW-TCor
EW-BCor
Bottom corner correction compo- BCC (Sad0F):
nent of the EW-drive signal on
EWOut pin
V
x0000000b
x1000000b
x1111111b
-1.25
0
+1.25
V
V
V
14/47
STV6888
Value
Typ.
Symbol
Parameter
Test Conditions
Units
Min.
Max.
∆V
ς
ς
>
0
20
%/V
%/V
EW
HO VHOThrfr
----------------------------------------------------------
Tracking of EW-drive signal with
horizontal frequency
(min)≤ς
≤
(32)
HO
HO VHOThrfr
V
EW[f
]
∆V
max
HO
(25)(26)
∆V
EW – AC
Breathing compensation on
----------------------------------------------------
∆V
ς
ς
>
0
1.75
%/V
%/V
(31)
HEHT VRefO
V
V
EW-AC
EW – AC
HEHT
(min)≤ς
≤
HEHT
HEHT VRefO
Note 19: KEYST at medium (neutral) value.
Note 20: TCC at medium (neutral) value.
Note 21: BCC at medium (neutral) value.
Note 22: PCC at minimum value.
Note 23: VPOS at medium (neutral) value.
Note 24: HSIZE at minimum value.
Note 25: Defined as difference of (voltage at t =0) minus (voltage at t =1/2 T ).
VR
VR
VR
Note 26: Defined as difference of (voltage at t =T ) minus (voltage at t =1/2 T ).
VR VR
VR
VR
Note 27: VSIZE at maximum value.
Note 28: Difference (voltage at t =0) minus (voltage at t =T ).
VR
VR
VR
Note 29: Ratio "A/B"of parabola component voltage at t =0 versus parabola component voltage at t =T .
VR
VR
VR
Note 30: ς
>
, ς
>
HEHT VRefO VEHT VRefO
Note 31: V
is sum of all components other than V
(contribution of PCC, keystone correction and corner
EW-AC
EW-DC
corrections).
Note 32: More precisely tracking with voltage on HPLL1F pin which itself depends on frequency at a rate given by
external components on PLL1 pins. V [fmax] is the value at condition V >V
.
EW
HO
HOThrfr
7.7 - DYNAMIC CORRECTION OUTPUT SECTION
VCC = 12V, Tamb = 25°C
Value
Typ.
Symbol
Parameter
Test Conditions
Units
Min.
Max.
Vertical Dynamic Correction output VDyCor
I
Current delivered by VDyCor output
-1.5
0
mA
V
VDyCor
DC component of the drive signal
on VDyCor output
V
R
=10kΩ
4
VD-DC
L(VDyCor)
(23)
VSIZE at medium
VDC-AMP (Sad15h):
x0000000b
0
0.5
1
V
V
V
Amplitude of V-parabola on VDyCor x1000000b
IVVD-V
I
(34)
output
x1111111b
VDC-AMP at maximum
VSIZE (Sad07):
x0000000b
0.6
1.6
V
V
x1111111b
VDC-AMP at maximum
Tracking of V-parabola on VDyCor VPOS (Sad08):
V
[t = 0]
VD – V vr
-------------------------------------------------
[t = T
(33)
V
]
VR
output with vertical position
x0000000b
x1111111b
0.52
1.92
VD – V vr
15/47
STV6888
Note 33: Ratio "A/B"of vertical parabola component voltage at t =0 versus vertical parabola component voltage at
VR
t
=T
.
VR VR
2
2
Note 34: Unsigned value. Polarity selection by VDyCorPol I C Bus bit. Refer to section I C Bus control register map.
7.8 - DC/DC CONTROLLER SECTION
VCC = 12V, Tamb = 25°C
Value
Symbol
Parameter
Test Conditions
Units
Min.
Typ. Max.
Ext. resistance applied between
BComp output and BRegIn input
R
5
kΩ
dB
B+FB
Open loop gain of error amplifier
on BRegIn input
(18)
A
Low frequency
100
6
OLG
Unity gain bandwidth of error am-
plifier on BRegIn input
(18)
f
MHz
µA
UGBW
Bias current delivered by regula-
tion input BRegIn
I
-0.2
RI
Output current capability of BComp out- HBOutEn = "Enable"
-0.5
2.0
0.5
mA
mA
I
(35)
BComp
put.
HBOutEn = "Disable"
BISense
A
Voltage gain on
input
3
BISense
BISense
Threshold voltage on
input cor-
V
TBD
2.1
-1
V
ThrBIsCurr
responding to current limitation
BISense
I
Input current sourced by
input
µA
BISense
(38)
t
Conduction time of the power transistor
T - t
H inh
BOn
Output current capability of BOut
output
I
0
10
mA
BOut
Saturation voltage of the internal output
transistor on BOut
V
I
=10mA
BOut
0.25
V
BOSat
V
=8V
RefO
BREF (Sad03):
x0000000b
x1000000b
x1111111b
Regulation reference for BRegIn
voltage
V
3.8
4.9
6.0
V
V
V
(36)
BReg
Delay of BOut “Off-to-On” edge after
t
/ T
middle of flyback pulse, as part of T
BOutPh = "0"
16
%
BTrigDel
H
H
(37)
Note 35: A current sink is provided by the BComp output while BOut is disabled:
Note 36: Internal reference related to V
. The same values to be found on pin BRegIn, while regulation loop is
RefO
stabilized.
Note 37: Only applies to configuration specified in "Test conditions" column, i.e. synchronization of BOut “Off-to-On”
edge with horizontal flyback signal. Refer to chapter "DC/DC controller" for more details.
Note 38: t is about 300ns regardless of the H frequency
inh
16/47
STV6888
7.9 - MISCELLANEOUS
VCC = 12V, Tamb = 25°C
Value
Typ.
Symbol
Parameter
Test Conditions
Units
Min.
Max.
Vertical blanking and horizontal lock indication composite output HLckVBk
(39)
I
Sink current to HLckVBk pin
100
µA
SinkLckBk
V.blank
No
Yes
No
H.lock
Yes
Yes
No
0.1
1.1
5
V
V
V
V
V
Output voltage on HLckVBk output
OLckBk
Yes
No
6
Horizontal moiré canceller
HMoiMode=0 (internal)
HMOIRE (Sad02):
x0000000b
∆T
H(H – moire)
-------------------------------------- Modulation of T by H-moiré function
H
0
0.04
%
%
T
H
x1111111b
HMoiMode=1 (external)
Rext=10kΩ
V
H-moiré pulse amplitude on HMoiré pin HMOIRE (Sad02):
HMoiré
x0000000b
x1111111b
0.1
2.1
V
V
Vertical moiré canceller
VMOIRE (Sad0Bh):
x0000000b
x1111111b
Amplitude of modulation of V-drive sig-
nal on VOut pin by vertical moiré.
V
0
3
mV
mV
V-moiré
Protection functions
Input threshold on
XRay
(40)
V
input
7.65
7.9
8.2
V
ThrXRay
Delay time between XRay detection
event and protection action
t
2T
H
XRayDelay
V
value for start of operation at V
CC
CC
V
8.5
6.5
V
V
(41)
CCEn
ramp-up
V
value for stop of operation at V
CC
CC
V
(41)
CCDis
ramp-down
(18)(42)
Control voltages on HPosF pin for Soft start/stop operation
Threshold for start/stop of H-drive sig-
nal
V
1
V
V
HOn
BOn
Threshold for start/stop of B-drive sig-
nal
V
1.7
2.4
Threshold for full operational duty cycle
of H-drive and B-drive signals
V
HBNorm f
Normal operation
Voltage onHPosF pin as function of ad- HPOS (Sad01)
V
HPos
justment of HPOS register
0000000xb
1111111xb
4.0
2.8
V
V
Note 39: Current sunk by the pin if the external voltage is higher than one the circuit tries to force.
Note 40: The threshold is equal to actual V
.
RefO
Note 41: In the regions of V where the device's operation is disabled, the H-drive, V-drive and B+-drive signals on
CC
2
HOut, VOut and BOut pins, resp., are inhibited, the I C Bus does not accept any data and the XRayAlarm flag
is reset. Also see Figure 15
Note 42: See Figure 10
17/47
STV6888
8 - TYPICAL OUTPUT WAVEFORMS
Note (43)
Function
Sad
Pin
Byte
Waveform
Effect on Screen
V
V
amp(min)
amp(max)
x0000000
V
mid(VOut)
mid(VOut)
Vertical Size
07
VOut
x1111111
x0000000
x1000000
x1111111
V
3.5V
3.5V
V
mid(VOut)
Vertical
Position
08
VOut
V
mid(VOut)
V
mid(VOut)
3.5V
x0000000:
Null
V
VOamp
V
VOS-cor
S-correction
09
VOut
V
V
x1111111:
Max.
VOamp
0
¼
T
¾
T
T
T
VR
VR
VR
t
t
VR
VR
VOamp
V
x0000000
VOC-cor
0
½T
VR
VR
x1000000 :
Null
V
VOamp
C-correction
0A
VOut
V
VOamp
V
x1111111
VOC-cor
0
½
T
T
VR
VR
t
VR
18/47
STV6888
Function
Sad
Pin
Byte
Waveform
Effect on Screen
V
amp
x0000000:
Null
(n-1)T
nT
(n+1)T
V
V
V
t
Vertical moiré
amplitude
0B
VOut
V
V-moiré
V
amp
x1111111:
Max.
(n-1)T
nT
(n+1)T
V
V
V
t
V
V
EW-DC(min)
0
0000000x
1111111x
½
½
T
T
VR
VR
t
t
VR
Horizontal size 10h
EWOut
EWOut
EWOut
EW-DC(max)
0
T
T
VR
V
VR
VR
V
EW-DC
EW-key
x0000000
x1111111
x0000000
Keystone
0D
correction
V
EW-key
V
EW-DC
V
EW-PCC(min)
0
½
T
T
VR
VR
t
t
VR
VR
Pin cushion
0C
correction
V
EW-PCC(max)
x1111111
0
½
T
T
VR
VR
V
EW-TCor(max)
x1111111
x0000000
x1111111
x0000000
0
½
T
T
T
Top corner
0E
VR
VR
VR
t
t
VR
VR
EWOut
correction
V
EW-TCor(min)
0
½T
VR
V
EW-TBot(max)
0
½
T
T
T
Bottom corner
0F
VR
VR
VR
t
t
VR
VR
EWOut
correction
V
EW-TBot(min)
0
½T
VR
19/47
STV6888
Function
Sad
Pin
Byte
Waveform
Effect on Screen
static phase
t
ParalC(min)
x0000000
0
½
½
T
T
T
VR
VR
VR
t
t
VR
VR
Parallelogram
correction
12h
t
ParalC(max)
static phase
x1111111
x0000000
x1111111
0
T
VR
t
t
PCAC(max)
static
H-phase
0
½
T
T
VR
VR
t
Pin cushion
asymmetry
correction
VR
11h
PCAC(max)
static
H-phase
0
½
T
T
VR
VR
t
VR
VDyCorP
V
VD-V(max)
V
VR
V
VD-DC
01111111
0
½
T
T
T
VR
VR
t
VR
Vertical
dynamic
correction
amplitude
V
VD-V(max)
VD-DC
15h
VDyCor
Application dependent
x0000000
11111111
0
½
T
VR
t
VR
VDyCorP
V
VD-V(max)
V
VD-DC
0
½
T
T
VR
VR
t
VR
Note 43: For any H and V correction component of the waveforms onEWOut and VOut pins and for internal waveform for
corrections of H asymmetry, displayed in the table, weight of the other relevant components is nullified
(minimum for parabola, S-correction, medium for keystone, all corner corrections, C-correction, parallelogram,
parabola asymmetry correction, written in corresponding registers).
20/47
STV6888
9 - I2C BUS CONTROL REGISTER MAP
The device slave address is 8C in write mode and 8D in read mode.
Bold weight denotes default value at Power-On-Reset.
I2C Bus data in the adjustment register is buffered and internally applied with discharge of the vertical os-
cillator (44)
In order to ensure compatibility with future devices, all “Reserved” bits should be set to 0.
.
Sad
D7
D6
D5
D4
D3
D2
D1
D0
WRITE MODE (SLAVE ADDRESS = 8C)
HDutySyncV
HDUTY (Horizontal duty cycle)
00
01
02
1: Synchro.
0: Asynchro.
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
HPOS (Horizontal position)
Reserved
1
0
0
0
HMoiré
1: Separated
0: Combined
HMOIRE (Horizontal moiré amplitude)
0
0
0
0
0
BREF (B+reference)
B+SyncV
0: Asynchro.
03
04
05
06
0
0
0
Reserved
Reserved
Reserved
Reserved
BOutPol
0: Type N
Reserved
BOutPh
VSIZE (Vertical size)
07
0: H-flyback
1: H-drive
1
0
0
0
0
0
0
VPOS (Vertical position)
EWTrHFr
0: No tracking
08
09
0A
0B
0C
0D
0E
0F
10
11
1
1
1
0
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SCOR (S-correction)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
CCOR (C-correction)
0
0
VMOIRE (Vertical moiré amplitude)
0
0
0
PCC (Pin cushion correction)
0
0
0
KEYST (Keystone correction)
0
0
0
0
0
TCC (Top corner correction)
0
0
BCC (Bottom corner correction)
0
0
0
0
HSIZE (Horizontal size)
Reserved
1
0
0
PCAC (Pin cushion asymmetry correction)
Reserved
0
0
0
0
0
21/47
STV6888
Sad
D7
D6
D5
D4
D3
D2
D1
D0
PARAL (Parallelogram correction)
12
Reserved
1
0
0
0
0
0
0
13
14
Reserved
Reserved
VDC-AMP (Vertical dynamic correction amplitude)
VDyCorPol
15
16
17
0: ” "
1
0
0
0
0
0
0
XRayReset
0: No effect
1: Reset
VSyncAuto VSyncSel
SDetReset HMoiMode PLL1Pump PLL1InhEn
HLockEn
1: On
1: On
0:Comp
1:Sep
0: No effect 0: Internal
1: Fast
1: On
1: Reset
1: External 0: Slow
TV
TH
0: Off
TVM
0: Off
THM
0: Off
BOHEdge
0: Falling
HBOutEn
0: Disable
VOutEn
0: Disable
BlankMode
1: Perm.
(46)
(46)
(46)
(46)
0: Off
READ MODE (SLAVE ADDRESS = 8D)
XX
Polarity detection
Sync detection
HVDet
HLock
VLock
XRayAlarm
1: On
0: Locked
0: Locked
HVPol
VPol
VExtrDet
VDet
(45)
1: Not locked 1: Not lock. 0: Off
1: Negative 1: Negative 0: Not det. 0: Not det. 0: Not det.
Note 44: With exception of HDUTY and BREF adjustments data that can take effect instantaneously if switches
HDutySyncV and B+SyncV are at 0 respectively.
Note 45: In Read Mode, the device always outputs data of the status register, regardless of sub address previously
selected.
Note 46: The TV, TH, TVM and THM bits are for testing purposes and must be kept at 0 by application.
Description of I2C Bus switches and flags
Write-to bits
Sad06/D7 - BOutPol
Polarity of B+ drive signal on BOut pin
0: adapted to N type of power MOS - high
level to make it conductive
Sad00/D7 - HDutySyncV
1: adapted to P type of power MOS - low level
to make it conductive
Synchronization of internal application of Hori-
zontal Duty cycle data, buffered in I2C Bus latch,
with internal discharge of Vertical oscillator
Sad07/D7 - BOutPh
Phase of start of B+ drive signal on BOut pin
0: Asynchronous mode, new data applied
with ACK bit of I2C Bus transfer on this sub
address
0: Just after horizontal flyback pulse
1: With one of edges of line drive signal on
HOut pin, selected by BOHEdge bit
1: Synchronous mode
Sad02/D7 - HMoiré
Sad08/D7 - EWTrHFr
Horizontal Moiré characteristics
Tracking of all corrections contained in wave-
form on pin EWOut with Horizontal Frequency
0: Not active
0: Adapted to an architecture with EHT gener-
ated in deflection section
1: Adapted to an architecture with separated
deflection and EHT sections
1: Active
Sad15/D7 - VDyCorPol
Polarity of Vertical Dynamic Correction wave-
form (parabola)
Sad03/D7 - B+SyncV
Same as HDutySyncV, applicable for B+ refer-
ence data
0: Concave (minimum in the middle of the pa-
rabola)
1: Convex (maximum in the middle of the pa-
rabola)
22/47
STV6888
Sad16/D0 - HLockEn
Enable of output of Horizontal PLL1 Lock/unlock
status signal on pin HLckVBk
nism. If both are present, the one coming first is
kept.
0: Disabled, selection done according to bit
VSyncSel
1: Enabled, the bit VSyncSel has no effect
0: Disabled, vertical blanking only on the pin
HLckVBk
1: Enabled
Sad16/D7 - XRayReset
Sad16/D1 - PLL1InhEn
Reset to 0 of XRay flag of status register effect-
ed with ACK bit of I2C Bus data transfer into reg-
ister containing the XRayReset bit. Also see de-
scription of the flag.
Enable of Inhibition of horizontal PLL1 during
extracted vertical synchronization pulse
0: Disabled, PLL1 is never inhibited
1: Enabled
0: No effect
1: Reset with automatic return of the bit to 0
Sad16/D2 - PLL1Pump
Horizontal PLL1 charge Pump current
0: Slow PLL1, low current
Sad17/D0 - BlankMode
Blanking operation Mode
0: Blanking pulse starting with detection of
vertical synchronization pulse and ending
with end of vertical oscillator discharge
(start of vertical sawtooth ramp on the VOut
pin)
1: Permanent blanking - high blanking level in
composite signal on pin HLckVBk is perma-
nent
1: Fast PLL1, high current
Sad16/D3 - HMoiMode
Horizontal Moiré Mode. In position “Internal”, the
H-moiré signal affects timing of H-drive signal on
HOut pin. In position “External”, the H-moiré sig-
nal is output on HMoiré pin and has no effect on
H-drive. In both cases, the amplitude of H-moiré
signal is adjusted through I2C Bus register
HMOIRE.
Sad17/D1 - VOutEn
Vertical Output Enable
0: Internal
1: External
0: Disabled, VoffVOut on VOut pin (see 7.5 -
Vertical section)
1: Enabled, vertical ramp with vertical position
offset on VOut pin
Sad16/D4 - SDetReset
Reset to 0 of Synchronization Detection flags
VDet, HVDet and VExtrDet of status register ef-
fected with ACK bit of I2C Bus data transfer into
register containing the SDetReset bit. Also see
description of the flags.
Sad17/D2 - HBOutEn
Horizontal and B+ Output Enable
0: Disabled, levels corresponding to “power
transistor off” on HOut and BOut pins (high
for HOut, high or low for BOut, depending
on BOutPol bit).
0: No effect
1: Reset with automatic return of the bit to 0
1: Enabled, horizontal deflection drive signal
on HOut pin providing that it is not inhibited
by another internal event (activated XRay
protection). B+ drive signal on BOut pin.
Sad16/D5 - VSyncSel
Vertical Synchronization input Selection be-
tween the one extracted from composite HV sig-
nal on pin H/HVSyn and the one on pin VSyn. No
effect if VSyncAuto bit is at 1.
Programming the bit to 1 after prior value of 0,
will initiate soft start mechanism of horizontal
drive and of B+ DC/DC convertor if this is in ex-
ternal sawtooth configuration.
0: V. sync extracted from composite signal on
H/HVSyn pin selected
1: V. sync applied on VSyn pin selected
Sad17/D3 - BOHEdge
Selection of Edge of Horizontal drive signal to
phase B+ drive Output signal on BOut pin. Only
applies if the bit BOutPh is set to 1, otherwise
BOHEdge has no effect.
Sad16/D6 - VSyncAuto
Vertical Synchronization input selection Auto-
matic mode. If enabled, the device automatically
selects between the vertical sync extracted from
composite HV signal on pin H/HVSyn and the
one on pinVSyn, based on detection mecha-
0: Falling edge
1: Rising edge
23/47
STV6888
Sad17/D4,D5,D6,D7 - THM, TVM, TH, TV
SadXX/D4 - HVPol
Test bits. They must be kept at 0 level by appli-
cation S/W.
Flag indicating Polarity of H or HV synchroniza-
tion pulses applied on H/HVSyn pin with respect
to mean level of the sync signal
0: Positive
Read-out flags
1: Negative
SadXX/D0 - VDet(47)
Flag indicating Detection of V synchronization
pulses on VSyn pin.
SadXX/D5 - XRayAlarm
Alarm indicating that an event of excessive volt-
age has passed on XRay pin. Can only be reset
to 0 through I2C Bus bit XRayReset or by power-
on reset.
0: Not detected
1: Detected
SadXX/D1 - HVDet (47)
0: No excess since last reset of the bit
1: At least one event of excess appeared
since the last reset of the bit, HOut inhibited
Flag indicating Detection of H or HV synchroni-
zation pulses applied on H/HVSyn pin. Once the
sync pulses are detected, the flag is set and
latched. Disappearance of the sync signal will
not lead to reset of the flag.
SadXX/D6 - VLock
Status of “Locking” or stabilization of Vertical os-
cillator amplitude to an internal reference by
AGC regulation loop.
0: Not detected
1: Detected.
0: Locked (amplitude stabilized)
1: Not locked (amplitude non-stabilized)
SadXX/D2 - VExtrDet (47)
Flag indicating Detection of Extracted Vertical
synchronization signal from composite H+V sig-
nal applied on H/HVSyn pin
0: Not detected
SadXX/D7 - HLock
Status of Locking of Horizontal PLL1
0: Locked
1: Not locked
1: Detected
SadXX/D3 - VPol
Flag indicating Polarity of V synchronization
pulses applied on VSyn pin with respect to mean
level of the sync signal
0: Positive
1: Negative
Note 47: This flag, by its value of 1, indicates an event of detection of at least one synchronization pulse since its last
2
reset (by means of the SDetReset I C Bus bit). This is to be taken into account by application S/W in a way
that enough time (at least the period between 2 synchronization pulses of analyzed signal) must be provided
between reset of the flag through SDetReset bit and validation of information provided in the flag after read-
out of status register.
24/47
STV6888
10 - OPERATING DESCRIPTION
10.1 - SUPPLY AND CONTROL
10.1.1 - Power supply and voltage references
V
RefO that is lead out to RefOut pin for external fil-
tering against ground as well as for external use
with load currents limited to IRefO. The filtering is
necessary to minimize interference in output sig-
nals, causing adverse effects like e.g. jitter.
The device is designed for a typical value of power supply
voltage of 12 V.
In order to avoid erratic operation of the circuit at
power supply ramp-up or ramp-down, the value of
VCC is monitored. See Figure 1 and electrical
specifications. At switch-on, the device enters a
“normal operation” as the supply voltage exceeds
VCCEn and stays there until it decreases bellow
10.1.2 - I2C Bus Control
The I2C bus is a 2 line bi-directional serial commu-
nication bus introduced by Philips. For its general
description, refer to corresponding Philips I2C bus
specification.
This device is an I2C bus slave, compatible with
fast (400kHz) I2C bus protocol, with write mode
slave address of 8C (read mode slave address
8D). Integrators are employed at the SCL (Serial
Clock) input and at the input buffer of the SDA (Se-
rial Data) input/output to filter off the spikes of up to
50ns.
VCCDis. The two thresholds provide, by their differ-
ence, a hysteresis to bridge potential noise. Out-
side the “normal operation”, the signals on HOut,
BOut and VOut outputs are inhibited and the I2C
bus interface is inactive (high impedance on SDA,
SCL pins, no ACK), all I2C bus control registers
being reset to their default values (see chapter i2c
bus control register map on page 21).
Figure 1. Supply voltage monitoring
The device supports multiple data byte messages
(with automatic incrementation of the I2C bus sub-
address) as well as repeated Start Condition for
I2C bus subaddress change inside the I2C bus
messages. All I2C bus registers with specified I2C
bus subaddress are of WRITE ONLY type, where-
as the status register providing a feedback infor-
mation to the master I2C bus device has no attrib-
uted I2C bus subaddress and is of READ ONLY
type. The master I2C bus device reads this register
sending directly, after the Start Condition, the
READ device I2C bus slave address (8D) followed
by the register read-out, NAK (No Acknowledge)
signal and the Stop Condition.
V
CC
V
(Vcc)
V
CCEn
hysteresis
V
CCDis
Disabled
Normal operation
Disabled
t
For the I2C bus control register map, refer to chap-
Internal thresholds in all parts of the circuit are de-
rived from a common internal reference supply
ter i2c bus control register map on page 21.
10.2 - SYNC. PROCESSOR
10.2.1 - Synchronization signals
The vertical sync. signal applied to the vertical de-
flection processor is selected between the signal
extracted from the composite signal on H/HVSyn
input and the one applied on VSyn input. The se-
lector is controlled by VSyncSel I2C bus bit.
The device has two inputs for TTL-level synchroni-
zation signals, both with hysteresis to avoid erratic
detection and with a pull-down resistor. On H/
HVSyn input, pure horizontal or composite hori-
zontal/vertical signal is accepted. On VSyn input,
only pure vertical sync. signal is accepted. Both
positive and negative polarities may be applied on
either input, see Figure 2. Polarity detector and
programmable inverter are provided on each of
the two inputs. The signal applied on H/HVSyn pin,
after polarity treatment, is directly lead to horizon-
tal part and to an extractor of vertical sync. pulses,
working on principle of integration, see Figure 3.
Besides the polarity detection, the device is capa-
ble of detecting the presence of sync. signals on
each of the inputs and at the output of vertical
sync. extractor. The information from all detectors
is provided in the I2C bus status register (5 flags:
VDet, HVDet, VExtrDet, VPol, HVPol). The device
is equipped with an automatic mode (switched on
or off by VSyncAuto I2C bus bit) that also uses the
detection information.
25/47
STV6888
Figure 2. Horizontal sync signal
Positive
t
T
PulseHSyn
H
Negative
10.2.2 - Sync. presence detection flags
der to reset them to 0 (all at once), a 1 must be
written into SDetReset I2C bus bit, the reset action
taking effect with ACK bit of the I2C bus transfer to
the register containing the SDetReset bit. The de-
tection circuits are then ready to capture another
event (pulse). See Note 47.
The sync. signal presence detection flags in the
status register (VDet, HVDet, VExtrDet) do not
show in real time the presence or absence of the
corresponding sync. signal. They are latched to 1
as soon as a single sync. pulse is detected. In or-
Figure 3. Extraction of V-sync signal from H/V-sync signal
H/V-sync
T
t
PulseHsyn
H
Internal
Integration
t
extrV
Extracted
V-sync
10.2.3 - MCU controlled sync. selection mode
10.2.4 - Automatic sync. selection mode
I2C bus bit VSyncAuto is set to 0. The MCU reads
the polarity and signal presence detection flags,
after setting the SDetReset bit to 1 and an appro-
priate delay, to obtain a true information of the sig-
nals applied, reads and evaluates this information
and controls the vertical signal selector according-
ly. The MCU has no access to polarity inverters,
they are controlled automatically.
I2C bus bit VSyncAuto is set to 1. In this mode, the
device itself controls the I2C bus bits switching the
polarity inverters (HVPol, VPol) and the vertical
sync. signal selector (VSyncSel), using the infor-
mation provided by detection circuitry. If both ex-
tracted and pure vertical sync. signals are present,
the one already selected is maintained. No inter-
vention of the MCU is necessary.
See also chapter i2c bus control register map on
page 21.
10.3 - HORIZONTAL SECTION
10.3.1 - General
10.3.2 - PLL1
The horizontal section consists of two PLLs with
various adjustments and corrections, working on
horizontal deflection frequency, then phase shift-
ing and output driving circuitry providing H-drive
signal on HOut pin. Input signal to the horizontal
section is output of the polarity inverter on H/
HVSyn input. The device ensures automatically
that this polarity be always positive.
The PLL1 block diagram is in Figure 5. It consists
of a voltage-controlled oscillator (VCO), a shaper
with adjustable threshold, a charge pump with inhi-
bition circuit, a frequency and phase comparator
and timing circuitry. The goal of the PLL1 is to
make the VCO ramp signal match in frequency the
sync. signal and to lock this ramp in phase to the
sync. signal, with a possibility to adjust a perma-
nent phase offset. On the screen, this offset re-
26/47
STV6888
sults in the change of horizontal position of the pic-
ture. The loop, by tuning the VCO accordingly,
gets and maintains in coincidence the rising edge
of input sync. signal with signal REF1, which is de-
rived from the VCO ramp by a comparator with
threshold adjustable through HPOS I2C bus con-
trol. The coincidence is identified and flagged by
lock detection circuit on pin HLckVBk as well as by
HLock I2C bus flag.
“CRC” filter is generally used (see Figure 4 on
page 27).
Figure 4. H-PLL1 filter configuration
HPLL1F
9
The charge pump provides positive and negative
currents charging the external loop filter on HPosF
pin. The loop is independent of the trailing edge of
sync. signal and only locks to its leading edge. By
design, the PLL1 does not suffer from any dead
band even while locked. The speed of the PLL1
depends on the current value provided by the
charge pump. While not locked, the current is very
low, to slow down the changes of VCO frequency
and thus protect the external power components
at sync. signal change. In locked state, the cur-
rents are much higher, two different values being
selectable via PLL1Pump I2C bus bit to provide a
mean to control the PLL1 speed by S/W. Lower
values make the PLL1 slower, but more stable.
Higher values make it faster and less stable. In
general, the PLL1 speed should be higher for high
deflection frequencies. The response speed and
stability (jitter level) depends on the choice of ex-
ternal components making up the loop filter. A
R2
C1
C2
The PLL1 is internally inhibited during extracted
vertical sync. pulse (if any) to avoid taking into ac-
count missing or wrong pulses on the phase com-
parator. Inhibition is obtained by forcing the charge
pump output to high impedance state. The inhibi-
tion mechanism can be disabled through
PLL1Pump I2C bus bit.
The Figure 7, in its upper part, shows the position
of the VCO ramp signal in relation to input sync.
pulse for three different positions of adjustment of
horizontal position control HPOS.
Figure 5. Horizontal PLL1 block diagram
PLL1InhEn
2
V-sync (extracted)
(I C)
Lock
Status
(pin & I C)
PLL1
HPLL1F
9
HOscF
4
R0 C0
2
8
6
Sync
Polarity
LOCK
DETECTOR
PLL
INHIBITION
High
Low
H/HVSyn
1
INPUT
INTERFACE
CHARGE
PUMP
VCO
HOSC
COMP
REF1
HPosF
10
Extracted
V-sync
PLL1Pump
2
(I C)
HPOS
2
(I C)
SHAPER
27/47
STV6888
Figure 6. Horizontal oscillator (VCO) schematic diagram
HOscF
4
I
V
0
HOThrHi
+
-
I
2
0
(PLL1 filter)
HPLL1F
V
RS
HO
+
-
9
Flip-Flop
-
+
V
HOThrLo
4 I
0
8
RO
VCO discharge
control
6
CO
from charge pump
V
V
HOThrHi
HOThrLo
10.3.3 - Voltage controlled oscillator
the external filter on pin HPLL2C to obtain
smoothed voltage, used, in comparison with VCO
ramp, as a threshold for H-drive rising edge gener-
ation.
The VCO makes part of both PLL1 and PLL2
loops, being an “output” to PLL1 and “input” to
PLL2. It delivers a linear sawtooth. Figure 6 ex-
plains its principle of operation. The linears are ob-
tained by charging and discharging an external ca-
pacitor on pin CO, with currents proportional to the
current forced through an external resistor on pin
RO, which itself depends on the input tuning volt-
age VHO (filtered charge pump output). The rising
and falling linears are limited by VHOThrLo and
As both leading and trailing edges of the H-drive
signal in the Figure 7 must fall inside the rising part
of the VCO ramp, an optimum middle position of
the threshold has been found to provide enough
margin for horizontal output transistor storage time
as well as for the trailing edge of H-drive signal
with maximum duty cycle. Yet, the constraints
thereof must be taken into account while consider-
ing the application frequency range and H-flyback
duration. The Figure 7 also shows regions for ris-
ing and falling edges of the H-drive signal on HOut
pin. As it is forced high during the H-flyback pulse
and low during the VCO discharge period, no edge
during these two events takes effect.
VHOThrHi thresholds filtered through HOscF pin.
At no signal condition, the VHO tuning voltage is
clamped to its minimum (see chapter ELECTRI-
CAL PARAMETERS AND OPERATING CONDI-
TIONS, part horizontal section), which corre-
sponds to the free-running VCO frequency fHO(0)
.
Refer to Note 1 for the formula to calculate this fre-
quency using external components values. The ra-
tio between the frequency corresponding to maxi-
mum VHO and the one corresponding to minimum
VHO (free-running frequency) is about 4.5. This
range can easily be increased in the application.
The PLL1 can only lock to input frequencies falling
inside these two limits.
The flyback input configuration is in Figure 8.
10.3.5 - Dynamic PLL2 phase control
The dynamic phase control of PLL2 is used to
compensate for picture asymmetry versus vertical
axis across the middle of the picture. It is done by
modulating the phase of the horizontal deflection
with respect to the incoming video (synchroniza-
tion). Inside the device, the threshold VS(0) is com-
pared with the VCO ramp, the PLL2 locking the
middle of H-flyback to the moment of their match.
The dynamic phase is obtained by modulation of
the threshold by correction waveforms. Refer to
Figure 12 and to chapter TYPICAL OUTPUT
WAVEFORMS. The correction waveforms have
no effect in vertical middle of the screen (for mid-
dle vertical position). As they are summed, their ef-
fect on the phase tends to reach maximum span at
top and bottom of the picture. As all the compo-
nents of the resulting correction waveform (linear
for parallelogram correction and parabola of 2nd
order for Pin cushion asymmetry correction) are
10.3.4 - PLL2
The goal of the PLL2 is, by means of phasing the
signal driving the power deflection transistor, to
lock the middle of the horizontal flyback to a cer-
tain threshold of the VCO sawtooth. This internal
threshold is affected by geometry phase correc-
tions, like e.g., parallelogram. The PLL2 is much
faster than PLL1 to be able to follow the dynamism
of this phase modulation. The PLL2 control current
(see Figure 7) is significantly increased during dis-
charge of vertical oscillator (during vertical retrace
period) to be able to make up for the difference of
dynamic phase at the bottom and at the top of the
picture. The PLL2 control current is integrated on
28/47
STV6888
generated from the output vertical deflection drive
waveform, they both track with real vertical ampli-
tude and position (including breathing compensa-
tion), thus being fixed on the screen. Refer to i2c
bus control register map on page 21 for details on
I2C bus controls.
The duty cycle of the H-drive signal is controlled
via I2C bus register HDUTY. This is overruled dur-
ing soft-start and soft-stop procedures (see sub
chapter Soft-start and soft-stop on H-drive on
page 29 and Figure 10).
The PLL2 is followed by a rapid phase shifting
which accepts the signal from H-moiré canceller
(see sub chapter Horizontal moiré cancellation on
page 29)
Figure 7. Horizontal timing diagram
t
Hph
min max
HPOS
(I C)
The output stage consists of a NPN bipolar tran-
sistor, the collector of which is routed to HOut pin
(see Figure 9).
2
H-sync
(polarized)
max.
med.
min.
PLL1
lock
Figure 9. HOut configuration
REF1
(internal)
26 HOut
int. ext.
V
HOThrHi
V
HPosF
max.
med.
min.
V
S(0)
H-Osc
(VCO)
V
HOThrLo
7/8T
H
T
H
Non-conductive state of HOT (Horizontal Output
Transistor) must correspond to non-conductive
state of the device output transistor.
V
ThrHFly
H-flyback
10.3.7 - Soft-start and soft-stop on H-drive
t
S
PLL2
control
current
The soft-start and soft-stop procedure is carried
out at each switch-on or switch-off of the H-drive
signal, either via HBOutEn I2C bus bit or after re-
set of XRayAlarm I2C bus flag, to protect external
power components. By its second function, the ex-
ternal capacitor on pin HPosF is used to time out
this procedure, during which the duty cycle of H-
drive signal starts at its maximum (“tHoff/TH for soft
start/stop” in electrical specifications) and slowly
decreases to the value determined by the control
I2C bus register HDUTY (vice versa at soft-stop).
This is controlled by voltage on pin HPosF. See
Figure 10 and sub chapter Safety functions on
page 36.
+
-
ON
ON
OFF
H-drive
(on HOut)
t
Hoff
forced high forced low
H-drive
region
t
ph(max)
H-drive
region
inhibited
t : HOT storage time
S
Figure 8. HFly input configuration
10.3.8 - Horizontal moiré cancellation
~500Ω
The horizontal moiré canceller is intended to blur a
potential beat between the horizontal video pixel
period and the CRT pixel width, which causes vis-
ible moiré patterns in the picture.
HFly
12
~20kΩ
On pin HMoiré, in position “External” of I2C bus bit
HMoiMode, it generates a square line-synchro-
nized waveform with amplitude adjustable through
HMOIRE I2C bus control. In position “Internal” of
I2C bus bit HMoiMode, it introduces a microscopic
indent on horizontal scan lines by injecting little
controlled phase shifts to output circuitry of the
horizontal section. Their amplitude is adjustable
through HMOIRE I2C bus control.
ext. int.
GND
10.3.6 - Output Section
The H-drive signal is inhibited (high level) during
flyback pulse, and also when VCC is too low, when
X-ray protection is activated (XRayAlarm I2C bus
flag set to 1) and when I2C bus bit HBOutEn is set
to 0 (default position).
Only one H-moiré, internal or external, is generat-
ed at a time.
29/47
STV6888
The behaviour of horizontal moiré is to be opti-
mised for different deflection design configurations
using HMoiré I2C bus bit. This bit is to be kept at 0
for common architecture (B+ and EHT common
regulation) and at 1 for separated architecture (B+
and EHT each regulated separately).
Figure 10. Control of HOut and BOut at start/stop at nominal Vcc
minimum value
V
HPosMin
V
(HPosF)
2
HPOS (I C)
range
V
HPosMax
maximum value
V
HBNorm
V
BOn
V
Soft start
Normal operation
Soft stop
HOn
Stop Stop
BOut HOut
Start Start
HOut BOut
t
HOut
100%
H-duty cycle
BOut (positive)
B-duty cycle
0%
10.4 - VERTICAL SECTION
10.4.1 - General
reference REF (VVOT), the result thereof control-
ling the gain of the transconductance amplifier pro-
viding the charging current. Speed of this AGC
loop depends on the storage capacitance on pin
VAGCCap. The VLock I2C bus flag is set to 1
when the loop is stabilized, i.e. when the voltage
on pin VAGCCap matches VVOT value. On the
screen, this corresponds to stabilized vertical size
of picture. After a change of frequency on the
sync. input, the stabilization time depends on the
frequency difference and on the capacitor value.
The lower its value, the shorter the stabilization
time, but on the other hand, the lower the loop sta-
bility. A practical compromise is a capacitance of
470nF. The leakage current of this capacitor re-
sults in difference in amplitude between low and
high frequencies. The higher its parallel resistance
The goal of the vertical section is to drive vertical
deflection output stage. It delivers a sawtooth
waveform with an amplitude independent of de-
flection frequency, on which vertical geometry cor-
rections of C- and S-type are superimposed (see
chapter TYPICAL OUTPUT WAVEFORMS).
Block diagram is in Figure 11. The sawtooth is ob-
tained by charging an external capacitor on pin
VCap with controlled current and by discharging it
via transistor Q1. This is controlled by the CON-
TROLLER. The charging starts when the voltage
across the capacitor drops below VVOB threshold.
The discharging starts either when it exceeds
VVOT threshold or a short time after arrival of syn-
chronization pulse. This time is necessary for the
AGC loop to sample the voltage at the top of the
sawtooth. The VVOB reference is routed out onto
VOscF pin in order to allow for further filtration.
R
L(VAGCCap), the lower this difference.
When the synchronization pulse is not present, the
charging current is fixed. As a consequence, the
free-running frequency fVO(0) only depends on the
value of the capacitor on pin VCap. It can be
roughly calculated using the following formula
The charging current influences amplitude and
shape of the sawtooth. Just before the discharge,
the voltage across the capacitor on pin VCap is
sampled and stored on a storage capacitor con-
nected on pin VAGCCap. During the following ver-
tical period, this voltage is compared to internal
150nF
C(VCap)
.
100Hz
fVO(0)
=
30/47
STV6888
The frequency range in which the AGC loop can
regulate the amplitude also depends on this ca-
pacitor.
The biasing voltage for external DC-coupled verti-
cal power amplifier is to be derived from VRefO
voltage provided on pin RefOut, using a resistor di-
vider, this to ensure the same temperature drift of
mean (DC) levels on both differential inputs and to
compensate for spread of VRefO value (and so
mean output value) between particular devices.
The C- and S-corrections of shape serve to com-
pensate for the vertical deflection system non-line-
arity. They are controlled via CCOR and SCOR
I2C bus controls.
10.4.2 - Vertical moiré
Shape-corrected sawtooth with regulated ampli-
tude is lead to amplitude control stage. The dis-
charge exponential is replaced by VVOB level,
which, under control of the CONTROLLER, cre-
ates a rapid falling edge and a flat part before be-
ginning of new ramp. Mean value of the waveform
output on pin VOut is adjusted by means of VPOS
I2C bus control, its amplitude through VSIZE I2C
bus control. Vertical moiré is superimposed.
To blur the interaction of deflection lines with CRT
mask grid pitch that can generate moiré pattern,
the picture position is to be alternated at half-frame
frequency. For this purpose, a square waveform at
half-frame frequency is superimposed on the out-
put waveform’s DC value. Its amplitude is adjusta-
ble through VMOIRE I2C bus control,.
Figure 11. Vertical section block diagram
Transconductance amplifier
REF
Charge current
OSC
Cap.
VCap
22
20
VAGCCap
Sampling
Sampling
Capacitance
Discharge
VSyn
Synchro
Polarity
Controller
Q1
2
S-correction
2
SCOR (I C)
2
CCOR (I C)
C-correction
sawtooth
discharge
18
VEHTIn
23 VOut
V
2
VOB
VSIZE (I C)
19
2
VMOIRE (I C)
VOscF
2
VPOS (I C)
31/47
STV6888
10.5 - EW DRIVE SECTION
The goal of the EW drive section is to provide, on
pin EWOut, a waveform which, used by an exter-
nal DC-coupled power stage, serves to compen-
sate for those geometry errors of the picture that
are symmetric versus vertical axis across the mid-
dle of the picture.
correction waveform are generated from the out-
put vertical deflection drive waveform, they all
track with real vertical amplitude and position (in-
cluding breathing compensation), thus being fixed
vertically on the screen. They are also affected by
C- and S-corrections. The sum of components oth-
er than DC is affected by value in HSIZE I2C bus
control in reversed sense. Refer to electrical spec-
ifications for value. The DC value, adjusted via
HSIZE control, is also affected by voltage on HE-
HTIn input, thus providing a horizontal breathing
compensation (see electrical specifications for val-
ue). The resulting waveform is conditionally multi-
plied with voltage on HPLL1F, which depends on
frequency. Refer to electrical specifications for val-
ue and more precision. This tracking with frequen-
cy provides a rough compensation of variation of
picture geometry with frequency and allows to fix
the adjustment ranges of I2C bus controls through-
out the operating range of horizontal frequencies.
It can be switched off by EWTrHFr I2C bus bit (off
by default).
The waveform consists of an adjustable DC value,
corresponding to horizontal size, a parabola of 2nd
order for “pin cushion” correction, a linear for “key-
stone” correction and independent half-parabolas
of 4th order for top and bottom corner corrections.
All of them are adjustable via I2C bus, see i2c bus
control register map on page 21 chapter.
Refer to Figure 12, Figure 13 and to chapter TYP-
ICAL OUTPUT WAVEFORMS. The correction
waveforms have no effect in the vertical middle of
the screen (if the VPOS control is adjusted to its
medium value). As they are summed, the resulting
waveform tends to reach its maximum span at top
and bottom of the picture. The voltage at the
EWOut is top and bottom limited (see parameter
V
EW). According to Figure 13, especially the bot-
The EW waveform signal is buffered by an NPN
emitter follower, the emitter of which is directly
routed to EWOut output, with no internal resistor to
ground. It is to be biased externally.
tom limitation seems to be critical for maximum
horizontal size (minimum DC). Actually it is not
critical since the parabola component must always
be applied. As all the components of the resulting
32/47
STV6888
Figure 12. Geometric corrections’ schematic diagram
2
Controls:
VDC-AMP (I C)
one-quadrant
2
VDyCorPol (I C)
two-quadrant
VDyCor
32
V
mid(VOut)
2
VOut
23
Top parabola
generator
2
2
(I C)
PCC
(I C)
TCC
BCC
HSize
Vertical ramp
Tracking
2
HEHTIn/HSize
17
2
(I C)
2
Tracking
with Hor
Frequency
KEYST (I C)
2
HEHTIn
2
(I C)
PCAC
Bottom parabola
generator
To horizontal
dyn. phase control
24
EWOut
2
(I C)
PARAL
33/47
STV6888
Figure 13. EWOut output waveforms
V
(max)
2
EW
V
(EWOut)
V
EW-DC
HSIZE (I C)
V
EW-TCor
V
V
EW-PCC
EW-Key
V
EW-BCor
V
(min)
EW
Top
Bottom
Keystone
alone
PCC
alone
Corners
alone
Breathing
compensation
V
(min)
V
HEHT
RefO
V
(HEHT)
V
(VCap)
Vertical sawtooth
T
0
T
VR
T
0
0
VR
VR
t
VR
10.6 - DYNAMIC CORRECTION OUTPUT SECTION
10.6.1 - Vertical dynamic correction output
cal amplitude and position (including breathing
compensation). It is also affected by C- and S-cor-
rections.
VDyCor
A parabola at vertical deflection frequency is avail-
able on pin VDyCor. Its amplitude is adjustable via
VDC-AMP I2C bus control and polarity controlled
via VDyCorPol I2C bus bit. It tracks with real verti-
The use of the correction waveform is up to the ap-
plication (e.g. dynamic focus).
10.7 - DC/DC CONTROLLER SECTION
The section is designed to control a switch-mode
DC/DC converter. A switch-mode DC/DC conver-
tor generates a DC voltage from a DC voltage of
different value (higher or lower) with little power
losses. The DC/DC controller is synchronized to
horizontal deflection frequency to minimize poten-
tial interference into the picture.
pulses synchronized on horizontal deflection fre-
quency, the phase of which depends on I2C bus
configuration, see the table at the end of this chap-
ter. Their duration depends on feedback provided
to the circuit, generally a copy of DC/DC converter
output voltage and a copy of current passing
through the DC/DC converter circuitry (e.g. current
through external power component). The polarity
of the output can be controlled by BOutPol I2C bus
bit. A NPN transistor open-collector is routed out to
the BOut pin.
Its operation is similar to that of standard UC3842.
The schematic diagram of the DC/DC controller is
in Figure 14. The BOut output controls an external
switching circuit (a MOS transistor) delivering
34/47
STV6888
During the operation, a sawtooth is to be found on
pin BISense, generated externally by the applica-
tion. According to BOutPh I2C bus bit, the R-S flip-
flop is set either at H-drive signal edge (rising or
falling, depending on BOHEdge I2C bus bit), or a
certain delay (tBTrigDel / TH) after middle of H-fly-
back. The output is set On at the end of a short
pulse generated by the monostable trigger.
depends on the voltage applied on input BISense
of the error amplifier O1. The two voltages are
compared, and the reset signal generated by the
comparator C1. The error amplifier amplifies (with
a factor defined by external components) the dif-
ference between the input voltage proportional to
DC/DC convertor output voltage and internal refer-
ence VBReg. The internal reference and so the out-
put voltage is I2C bus adjustable by means of
BREF I2C bus control.
Timing of reset of the R-S flip-flop affects duty cy-
cle of the output square signal and so the energy
transferred from DC/DC converter input to its out-
put. A reset edge is provided by comparator C2 if
the voltage on pin BISense exceeds the internal
threshold VThrBIsCurr. This represents current limi-
tation if a voltage proportional to the current
through the power component or deflection stage
is available on pin BISense. This threshold is af-
fected by the voltage on pin HPosF, which rises at
soft start and descends at soft stop. This ensures
self-contained soft control of duty cycle of the out-
put signal on pin BOut. Refer to Figure 10. Another
condition for the reset of the R-S flip-flop, OR-ed
with the one described before, is that the voltage
on pin BISense exceeds the voltage VC1, which
Both step-up (DC/DC converter output voltage
higher than its input voltage) and step-down (out-
put voltage lower than input) are possible.
DC/DC controller Off-to-On edge timing
BOutPh BOHEdge
Timing of Off-to-On transition
(Sad07/
D7)
(Sad17/
D3)
on BOut output
0
1
1
don’t care Middle of H-flyback plus t
BTrigDel
0
1
Falling edge of H-drive signal
Rising edge of H-drive signal
Figure 14. DC/DC converter controller block diagram
BOHEdge
2
BOutPh
(I C)
(I C)
2
H-drive edge
Monostable
~500ns
H-flyback
V
I1
CC
(+delay)
I2
VBReg
N type
Feedback
+
V
C1
2R
R
-
O1
BOut
S
R
-
C1
C2
Q
+
I3
P type
BOutPol
BRegIn
-
2
(I C)
BComp
V
+
HBOutEn
ThrBIsCurr
XRayAlarm
2
(I C)
Soft start
HPosF
BIsense
35/47
STV6888
10.8 - MISCELLANEOUS
10.8.1 - Safety functions
to phase-in and last to phase-out being the H-drive
signal, which is to better protect the power stages
at abrupt changes like switch-on and off. The tim-
ing of phase-in and phase-out only depends on
the capacitance connected to HPosF pin which is
virtually unlimited for this function. Yet it has a dual
function (see paragraph PLL1 on page 26), so a
compromise thereof is to be found.
The safety functions comprise supply voltage
monitoring with appropriate actions, soft start and
soft stop features on H-drive and B-drive signals
on HOut and BOut outputs and X-ray protection.
For supply voltage supervision, refer to paragraph
Power supply and voltage references on page 25
and Figure 1. A schematic diagram putting togeth-
er all safety functions and composite PLL1 lock
and V-blanking indication is in Figure 15.
10.8.3 - X-ray protection
The X-ray protection is activated if the voltage lev-
el on XRay input exceeds VThrXRay threshold. As a
consequence, the H-drive and B-drive signals on
HOut and BOut outputs are inhibited (switched off)
after a 2-horizontal deflection line delay provided
to avoid erratic excessive X-ray condition detec-
tion at short parasitic spikes. The XRayAlarm I2C
bus flag is set to 1 to inform the MCU.
10.8.2 - Soft start and soft stop functions
For soft start and soft stop features for H-drive and
B-drive signal, refer to paragraph Soft-start and
soft-stop on H-drive on page 29 and sub chapter-
DC/DC CONTROLLER SECTION on page 34, re-
spectively. See also the Figure 10. Regardless
why the H-drive or B-drive signal are switched on
or off (I2C bus command, power up or down, X-ray
protection), the signals always phase-in and
phase-out in the way drawn in the figure, the first
This protection is latched; it may be reset either by
V
CC drop or by I2C bus bit XRayReset (see chap-
ter i2c bus control register map on page 21).
36/47
STV6888
Figure 15. Safety functions - block diagram
HBOutEn
HPosF
(timing)
10
2
I C
V
supervision
CC
VCCEn
VCCDis
+
_
SOFT START
& STOP
29
Vcc
2
XRayReset
R
S
Q
I C
2
I C
XRayAlarm
Out
In
XRay
25
:2
+
_
B-drive inhibit
H-drive inhibit
R
VThrXRay
H-VCO
discharge
control
H-drive inhibition
HFly
12
(overrule)
+
_
VThrHFly
VOutEn
V-drive inhibition
2
I C
B-drive inhibition
BlankMode
2
I C
HLckVbk
HlockEn
L1=No blank/blank level
L2=H-lock/unlock level
2
3
Σ
I C
L3=L1+L2
H-lock detector
HLock
2
R
S
Q
I C
V-sawtooth
discharge
V-sync
2
2
Int. signal
3
Pin
I C I C bit/flag
37/47
STV6888
10.8.4 - Composite output HLckVBk
the leading edge of any of the two signals, which-
ever comes first. The blanking pulse is ended with
the trailing edge of vertical oscillator discharge
pulse. The device has no information about the
vertical retrace time. Therefore, it does not cover,
by the blanking pulse, the whole vertical retrace
period. By means of BlankMode I2C bus bit, when
at 1 (default), the blanking level (one of two ac-
cording to PLL1 status) is made available on the
HLckVBk permanently. The permanent blanking,
irrespective of the BlankMode I2C bus bit, is also
provided if the supply voltage is low (under VCCEn
or VCCDis thresholds), if the X-ray protection is ac-
tive or if the V-drive signal is disabled by VOutEn
I2C bus bit.
The composite output HLckVBk provides, at the
same time, information about lock state of PLL1
and early vertical blanking pulse. As both signals
have two logical levels, a four level signal is used
to define the combination of the two. Schematic di-
agram putting together all safety functions and
composite PLL1 lock and V-blanking indication is
in Figure 15, the combinations, their respective
levels and the HLckVBk configuration in Figure 16.
The early vertical blanking pulse is obtained by a
logic combination of vertical synchronization pulse
and pulse corresponding to vertical oscillator dis-
charge. The combination corresponds to the draw-
ing in Figure 16. The blanking pulse is started with
Figure 16. Levels on HLckVBk composite output
L1 - No blank/blank level
L2 - H-lock/unlock level
V
CC
L1 +L2
(H)
(H)
3 HLckVBk
L1 +L2
(L)
(H)
I
SinkLckBlk
L1 +L2
V
(H)
(L)
OLckBlk
L1 +L2
(L)
(L)
V-early blanking
HPLL1 locked
No
Yes
Yes
No
No
Yes
No
Yes
38/47
STV6888
Figure 17. Ground layout recommendations
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
STV6888
General Ground
10
11
12
13
14
15
16
39/47
STV6888
11 - INTERNAL SCHEMATICS
Figure 18.
Figure 21.
RefOut
13
12V
5V
5
HPLL2C
Pins 1-2
H/HVSyn
VSyn
200Ω
Figure 19.
Figure 22.
12V
RefOut
13
12V
13
RefOut
6
C0
3
HLckVBkl
Figure 20.
Figure 23.
12V
RefOut
13
12V
Pin 13
8
R0
HOSCF
Pin 4
41/47
STV6888
Figure 24.
Figure 27.
12V
9
HPLL1F
12
HFly
Figure 25.
Figure 28.
RefOut
12V
HPosF
10
BComp
14
Figure 26.
Figure 29.
12V
5V
5V
12V
15
BRegIn
HMoiré
11
42/47
STV6888
Figure 30.
Figure 33.
12V
12V
BISense
16
VAGCCap 20
Figure 31.
Figure 34.
12V
22
VCap
12V
18 VEHTIn
17
HEHTIn
Figure 32.
Figure 35.
12V
Pin 13
12V
VOSCF
19
23
VOut
43/47
STV6888
Figure 36.
Figure 39.
12V
30 SCL
31SDA
24 EWOut
32 VDyCor
Figure 37.
12V
XRay
25
Figure 38.
12V
26 HOut
28 BOut
44/47
STV6888
12 - PACKAGE MECHANICAL DATA
32 PINS - PLASTIC SHRINK
E
E1
C
Stand-off
e
B
B1
eA
eB
D
32
1
17
16
Millimeters
Typ.
Inches
Typ.
Dimensions
Min.
3.556
0.508
3.048
0.356
0.762
.203
Max.
Min.
0.140
0.020
0.120
0.014
0.030
0.008
1.080
0.390
0.300
Max.
A
A1
A2
B
3.759
5.080
0.148
0.200
3.556
0.457
1.016
0.254
27.94
10.41
8.890
1.778
10.16
4.572
0.584
1.397
0.356
28.45
11.05
9.398
0.140
0.018
0.040
0.010
1.100
0.410
0.350
0.070
0.400
0.180
0.023
0.055
0.014
1.120
0.435
0.370
B1
C
D
27.43
9.906
7.620
E
E1
e
eA
eB
L
12.70
3.810
0.500
0.150
2.540
3.048
0.100
0.120
45/47
STV6888
Revision follow-up
DATASHEET
December 2001
version 4.0
Document created from last version 4.0 of TDA9116
February 2002 version 4.1
Created new version from existing version 4.0 of TDA9116 as the previous was not compliant with the
customer’s request.
The vertical frequency is kept the same as for the TDA9116
The satus registers are kept as for TDA9116
correction in Block diagram: double arrow between I²c bus registers and I²C bus interface
corrction in figure 15: no gate for B-drive inhibition signal
February 2002
version 4.1
Publication on www.st.com
2
STV6888
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for
the consequences of use of such information nor for any infringement of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectron-
ics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and re-
places all information previously supplied. STMicroelectronics products are not authorized for use as critical components
in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
ÿ2003 STMicroelectronics - All Rights Reserved.
2
2
Purchase of I C Components by STMicroelectronics conveys a license under the Philips I C Patent. Rights to use these
2
2
components in an I C system is granted provided that the system conforms to the I C Standard Specification as defined
by Philips.
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