STV6889 [STMICROELECTRONICS]
HIGH-END IC CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR; 高端IC可控弯曲处理器的MultiSync显示器
| 型号： | STV6889 |
| 厂家： | 
ST |
| 描述： | HIGH-END IC CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR |
| 文件： | 总56页 (文件大小：1382K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STV6889
HIGH-END I²C CONTROLLED DEFLECTION PROCESSOR
FOR MULTISYNC MONITOR
PRODUCT PREVIEW
FEATURES
• Compensation of horizontal breathing with EHT
variation, I2C-bus gain adjustment
General
• Advanced I2C-bus controlled deflection
Dynamic correction section
processor dedicated for high-end CRT monitors
• Single supply voltage 12V
• Generates vertical waveform for dynamic
corrections like focus, brightness uniformity, ...
• 1 output with vertical dynamic correction
waveform, both polarities, tracking with vertical
size and position
• Very low jitter
• DC/DC converter controller
• Advanced EW drive
• Advanced asymmetry corrections
• Automatic multistandard synchronization
• Vertical dynamic correction waveform output
• X-ray protection and Soft-start & stop on
horizontal and DC/DC drive outputs
• I2C-bus status register
DC/DC controller section
• Step-up and step-down conversion modes
• External sawtooth configuration
• I2C-bus-controlled output voltage
• Synchronized on hor. frequency with phase
selection
• Selectable polarity of drive signal
• Protection at H unlock condition
Horizontal section
• 150 kHz maximum frequency
• Corrections of geometric asymmetry: Pin
cushion asymmetry, Parallelogram, separate
Top/Bottom corner asymmetry
• Tracking of asymmetry corrections with vertical
size and position
DESCRIPTION
The STV6889 is a monolithic integrated circuit as-
sembled in a 32-pin shrink dual-in-line plastic
package. This IC controls all the functions related
to horizontal and vertical deflection in multimode
or multi-frequency computer display monitors.
• Fully integrated horizontal moiré cancellation
Combined with other ST components dedicated
for CRT monitors (microcontroller, video preampli-
fier, video amplifier, OSD controller), the STV6889
allows fully I2C bus-controlled computer display
monitors to be built with a reduced number of ex-
ternal components.
Vertical section
• 200 Hz maximum frequency
• Vertical ramp for DC-coupled output stage with
adjustments of: C-correction, S-correction for
super-flat CRT, Vertical size, Vertical position
• Vertical size and position prescales for factory
adjustment
• Vertical moiré cancellation through vertical
ramp waveform
• Compensation of vertical breathing with EHT
variation; I2C-bus gain adjustment
EW section
• Symmetrical geometry corrections: Pin cushion,
Keystone, Top/Bottom corners separately, S-
and W-corrections
SDIP 32 (Shrink DIP package)
ORDER CODE: STV6889
• Horizontal size adjustment
• Tracking of EW waveform with Vertical size and
position, horizontal size and frequency
Version 1.1
1/56
May 2004
This is preliminary information on a new product now in development. Details are subject to change without notice.
1
Table of Contents
1
2
3
4
5
6
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PIN FUNCTION REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
QUICK REFERENCE DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ELECTRICAL PARAMETERS AND OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . 9
6.1 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.2 Supply and Reference voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.3 Synchronization inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.4 Horizontal section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.5 Vertical section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.6 EW drive section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.7 Dynamic correction outputs section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.8 DC/DC controller section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.9 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
TYPICAL OUTPUT WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7
8
9
I²C-BUS CONTROL REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
OPERATING DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.1 Supply and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.1.1 Power supply and voltage references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.1.2 I²C-bus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.2 Synchronization processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.2.1 Synchronization signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.2.2 Sync. presence detection flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.2.3 MCU controlled sync. selection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.2.4 Automatic sync. selection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.3 Horizontal section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.3.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.3.2 PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.3.3 Voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.3.4 PLL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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1
STV6889
9.3.5 Dynamic PLL2 phase control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.3.6 Output Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.3.7 Soft-start and soft-stop on H-drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.3.8 Horizontal moiré cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.4 Vertical section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.4.2 S and C corrections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.4.3 Vertical breathing compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.4.4 Vertical after-gain and offset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.4.5 Vertical moiré . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.4.6 Biasing of vertical booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.5 EW drive section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.6 Dynamic correction outputs section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.6.1 Vertical dynamic correction output VDyCor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.7 DC/DC controller section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.7.1 Synchronization of DC/DC controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.7.2 Soft-start and soft-stop on B-drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.8 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.8.1 Safety functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.8.2 Composite output HLckVBk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10 INTERNAL SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
12 GLOSSARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
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1
STV6889
1 PIN CONFIGURATION
H/HVSyn
VSyn
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDyCor
SDA
1
2
HLckVBk
HOscF
HPLL2C
CO
3
SCL
4
Vcc
5
BOut
GND
6
HGND
RO
HOut
7
XRay
8
HPLL1F
HPosF
IC
EWOut
VOut
9
10
11
12
13
14
15
16
VCap
VGND
VAGCCap
VOscF
VEHTIn
HEHTIn
HFly
RefOut
BComp
BRegIn
BISense
4/56
2
STV6889
2 BLOCK DIAGRAM
5/56
STV6889
3 PIN FUNCTION REFERENCE
Pin
1
Name
H/HVSyn
VSyn
Function
TTL compatible Horizontal / Horizontal and Vertical Sync. input
TTL compatible Vertical Sync. input
2
3
HLckVBk
HOscF
HPLL2C
CO
Horizontal PLL1 Lock detection and Vertical early Blanking composite output
High Horizontal Oscillator sawtooth threshold level Filter input
Horizontal PLL2 loop Capacitive filter input
Horizontal Oscillator Capacitor input
4
5
6
7
HGND
RO
Horizontal section GrouND
8
Horizontal Oscillator Resistor input
9
HPLL1F
HPosF
IC
Horizontal PLL1 loop Filter input
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Horizontal Position Filter and soft-start time constant capacitor input
Internally Connected (to be left open)
HFly
Horizontal Flyback input
RefOut
BComp
BRegIn
BISense
HEHTIn
VEHTIn
VOscF
VAGCCap
VGND
VCap
Reference voltage Output
B+ DC/DC error amplifier (Compensation) output
Regulation feedback Input of the B+ DC/DC converter controller
B+ DC/DC converter current (I) Sense input
Input for compensation of Horizontal amplitude versus EHT variation
Input for compensation of Vertical amplitude versus EHT variation
Vertical Oscillator sawtooth low threshold Filter (capacitor to be connected to VGND)
Input for storage Capacitor for Automatic Gain Control loop in Vertical oscillator
Vertical section GrouND
Vertical sawtooth generator Capacitor
VOut
Vertical deflection drive Output for a DC-coupled output stage
E/W Output
EWOut
XRay
X-Ray protection input
HOut
Horizontal drive Output
GND
Main GrouND
BOut
B+ DC/DC converter controller Output
Vcc
Supply voltage
SCL
I²C-bus Serial CLock Input
SDA
I²C-bus Serial DAta input/output
VDyCor
Vertical Dynamic Correction output
6/56
STV6889
4 QUICK REFERENCE DATA
Characteristic
Value
Unit
General
Package
Supply voltage
SDIP 32
12
V
Supply current
65
mA
Application category
Means of control • Maximum clock frequency
EW drive
High-end
I²C-bus • 400
Yes
kHz
kHz
DC/DC converter controller
Horizontal section
Frequency range
Autosync frequency ratio (can be enlarged in application)
Positive • Negative polarity of horizontal sync signal • Automatic adaptation
Duty cycle range of the drive signal
Position adjustment range with respect to H period
Soft start • Soft stop feature
Yes
15 to 150
4.28
Yes • Yes • Yes
30 to 65
±10
%
%
Yes • Yes
Yes • Yes
Yes
Hardware • Software PLL lock indication
Parallelogram
Pin cushion asymmetry correction (also called Side pin balance)
Top • Bottom • Common corner asymmetry correction
Tracking of asymmetry corrections with vertical size & position
Horizontal moiré cancellation (int.) for Combined • Separated architecture
Vertical section
Yes
Yes • Yes • No
Yes
Yes • Yes
Frequency range
35 to 200
50 to 180
Yes • Yes • Yes
Yes • Yes • Yes
Yes • Yes • Yes
Yes
Hz
Hz
Autosync frequency range (150nF at VCap and 470nF at VAGCCap)
Positive • Negative polarity of vertical sync signal • Automatic adaptation
S-correction • C-correction • Super-flat tube characteristic
Vertical size • Vertical position • Prescale adjustments
Vertical moiré cancellation (internal)
EHT breathing compensation • With I²C-bus gain control
EW section
Yes • Yes
Pin cushion correction
Keystone correction
Yes
Yes
Top • Bottom • Common corner correction
S-correction • W-correction
Horizontal size adjustment
Yes • Yes • No
Yes • Yes
Yes
Tracking of EW waveform with Frequency • Vertical size & position
EHT breathing compensation • With I²C-bus gain control
Dynamic correction section (dyn. focus, dyn. brightness,...)
Vertical dynamic correction output VDyCor • Positive or negative polarity
Horizontal dynamic correction output HDyCor
Composite HV dynamic correction output HVDyCor • Positive or negative polarity
Shape control on H waveform component of HVDyCor output
Tracking of horizontal waveform component with Horizontal size • EHT
Tracking of vertical waveforms (component) with V. size & position
DC • DC controller section
Yes • Yes
Yes • Yes
Yes • Yes
No
No • No
No
No • No
Yes
Step-up • Step-down conversion mode
Internal • External sawtooth configuration
Bus-controlled output voltage • Inhibition at H unlock
Mute • Soft start • Soft stop feature
Positive (N-MOS) • Negative(P-MOS) polarity of BOut signal
Phase selection • Max current selection • Frequency selection
Yes • Yes
No • Yes
Yes • Yes
Yes • Yes • Yes
Yes • Yes
Yes • Yes • Yes
7/56
STV6889
5 ABSOLUTE MAXIMUM RATINGS
All voltages are given with respect to ground.
Currents flowing from the device (sourced) are signed negative. Currents flowing to the device are signed
positive.
Value
Symbol
Parameter
Unit
Min
Max
V
Supply voltage (pin Vcc)
-0.4
13.5
V
CC
Pins HEHTIn, VEHTIn, XRay, HOut, BOut
Pins H/HVSyn, VSyn, SCL, SDA
Pins HLckVBk, CO, RO, HPLL1F, HPosF, BRegIn,
BISense, VAGCCap, VCap, VDyCor, HOscF, VOscF
Pin HPLL2C
-0.4
-0.4
-0.4
V
5.5
V
V
V
CC
V
RefO
V
(pin)
-0.4
-0.4
V
/2
V
V
RefO
Pin HFly
V
RefO
Latch-up current
I
All pins except XRay
Pin XRay
-200
-100
200
200
mA
mA
latch(pin)
ESD susceptibility
(human body model: discharge of 100pF through 1.5kꢀ)
V
ESD
-2000
-40
2000
150
V
T
Storage temperature
Junction temperature
°C
°C
stg
T
150
j
8/56
STV6889
6 ELECTRICAL PARAMETERS AND OPERATING CONDITIONS
Medium (middle) value of an I²C-bus control or adjustment register composed of bits D0, D1,...,Dn is the
one having Dn at "1" and all other bits at "0". Minimum value is the one with all bits at 0, maximum value
is the one with all at "1".
Currents flowing from the device (sourced) are signed negative. Currents flowing to the device are signed
positive.
TH is period of horizontal deflection.
6.1 Thermal data
Value
Symbol
Parameter
Unit
Min.
Typ.
Max.
T
Operating ambient temperature
0
70
°C
amb
R
Junction-ambience thermal resistance
65
°C/W
th(j-a)
6.2 Supply and Reference voltages
Tamb = 25°C
Value
Symbol
Parameter
Test Conditions
Units
Min.
Typ.
12
Max.
V
Supply voltage at Vcc pin
10.8
13.2
V
mA
V
CC
I
Supply current to Vcc pin
V
V
= 12V
65
CC
CC
CC
V
Reference output voltage at RefOut pin
Current capability of RefOut output
= 12V, I
= -2mA
RefO
7.65
-5
7.9
8.2
0
RefO
RefO
I
mA
6.3 Synchronization inputs
Vcc = 12V, Tamb = 25°C
Value
Typ.
Symbol
Parameter
Test Conditions
Units
Min.
0
Max.
0.8
5
V
LOW level voltage on H/HVSyn
HIGH level voltage on H/HVSyn
LOW level voltage on VSyn
V
V
LoH/HVSyn
V
2.2
0
HiH/HVSyn
V
0.8
5
V
LoVSyn
V
HIGH level voltage on VSyn
2.2
100
0.5
V
HiVSyn
R
Internal pull-down on H/HVSyn, VSyn
H sync. pulse duration on H/HVSyn pin
Proportion of H sync pulse to H period
V sync. pulse duration
175
250
kꢀ
ꢁs
PdSyn
PulseHSyn
t
t
t
Pin H/HVSyn
0.2
750
0.15
/T
PulseHSyn
H
V
t
Pins H/HVSyn, VSyn
Pins H/HVSyn, VSyn
0.5
ꢁs
PulseVSyn
Proportion of V sync pulse to V period
/T
PulseVSyn
Proportion of H sync pulse length to H pe- Pin H/HVSyn,
t
0.21
0.75
0.35
/T
extrV
H
riod for extraction as V sync pulse
cap. on pin CO = 820pF
t
Polarity detection time (after change)
Pin H/HVSyn
ms
HPolDet
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STV6889
6.4 Horizontal section
Table 1. Horizontal section ( Vcc = 12V, Tamb = 25°C)
Value
Typ.
Symbol
PLL1
Parameter
Test Conditions
Units
Min.
Max.
I
Current load on RO pin
1.5
mA
pF
RO
C
Capacitance on CO pin
390
CO
f
Frequency of hor. oscillator
Free-running frequency of hor. oscill.
150
29.9
122
kHz
kHz
kHz
HO
(1)
f
R
=5.23kꢀ, C =820pF 27
28.5
HO(0)
RO
CO
(4)
f
Hor. PLL1 capture frequency
f
= 28.5kHz
29
HOCapt
HO(0)
ꢂfHOꢀ0ꢁ
fHOꢀ0ꢁ ꢄ ꢂT
(3)
--------------------------
Temperature drift of free-running freq.
-150
20.2
5.0
ppm/°C
ꢂf ꢃꢂV
Average horizontal oscillator sensitivity
H. oscill. control voltage on pin HPLL1F
f
= 28.5kHz
=8V
kHz/V
V
HO
HO
HO(0)
V
V
1.4
6.0
HO
RefO
RefO
Threshold on H. oscill. control voltage on
HPLL1F pin for tracking of EW with freq.
V
V
=8V
V
HOThrfr
HPOS (Sad01h):
11111111b
10000000b
2.8
3.4
4.0
V
V
V
V
Control voltage on HPosF pin
HPosF
00000000b
(6)
V
Bottom of hor. oscillator sawtooth
1.6
6.4
V
V
HOThrLo
(6)
V
Top of hor. oscillator sawtooth
HOThrHi
PLL2
(2)
R
Input impedance on HFly input
Current into HFly input
V
>V
ThrHFly
300
0.5
500
700
5
ꢀ
mA
V
In(HFly)
(HFly)
I
At top of H flyback pulse
InHFly
V
Voltage threshold on HFly input
0.6
4.0
ThrHFly
No PLL2 phase modula-
tion
(6)
V
H flyback lock middle point
V
S(0)
(5)
V
Low clamping voltage on HPLL2C pin
1.6
4.0
V
V
BotHPLL2C
(5)
V
High clamping voltage on HPLL2C pin
TopHPLL2C
Min. advance of H-drive OFF before
middle of H flyback
t
(min)
Null asym. correction
Null asym. correction
0
%
%
/T
(7)
ph
H
Max. advance of H-drive OFF before
t
(max)
44
/T
(8)
ph
H
middle of H flyback
H-drive output on pin HOut
I
Current into HOut output
Output driven LOW
30
mA
HOut
f
= 31kHz;
H
HDUTY (Sad00h):
x1111111b
x0000000b
t
Duty cycle of H-drive signal
27
65
85
%
%
%
/T
Hoff
H
Soft-start/Soft-stop value
10/56
STV6889
Table 1. Horizontal section ( Vcc = 12V, Tamb = 25°C)
Value
Typ.
Symbol
Parameter
Test Conditions
Units
Min.
Max.
Picture geometry corrections through PLL1 & PLL2
HPOS (Sad01h):
11111111b
10000000b
Hor. VCO phase vs. sync signal (via
PLL1), see Figure 7
+11
0
-11
%
%
%
t
/T
Hph
H
00000000b
PCAC (Sad11h) full span
(9)
Contribution of pin cushion asymmetry
correction to phase of H-drive vs. static
phase (via PLL2), measured in corners
VPOS at medium
VSIZE at minimum
VSIZE at medium
VSIZE at maximum
t
/T
PCAC
H
±0.9
±1.6
±2.6
%
%
%
PARAL (Sad12h) full span
(9)
Contribution of parallelogram correction
to phase of H-drive vs. static phase (via
PLL2), measured in corners
VPOS at medium
VSIZE at minimum
VSIZE at medium
VSIZE at maximum
t
/T
ParalC
H
±1.4
±1.9
±2.4
%
%
%
TCAC (Sad13h) full span
(9)
Contribution of top corner asymmetry
correction to phase of H-drive vs. static
phase (via PLL2), measured in corners
VPOS at medium
VSIZE at minimum
VSIZE at medium
VSIZE at maximum
t
/T
TCAC
BCAC
H
H
±0.4
±1.4
±3.5
%
%
%
BCAC (Sad14h) full span
(9)
Contribution of bottom corner asymmetry
correction to phase of H-drive vs. static
phase (via PLL2), measured in corners
VPOS at medium
VSIZE at minimum
VSIZE at medium
VSIZE at maximum
t
/T
±0.4
±1.4
±3.5
%
%
%
Notes about horizontal section
Note 1: Frequency at no sync signal condition. For correct operation, the frequency of the sync signal applied must
always be higher than the free-running frequency. The application must consider the spread of values of real
electrical components in R and C positions so as to always meet this condition. The formula to calculate
RO
CO
the free-running frequency is f
=0.122/(R
C
)
HO(0)
RO CO
Note 2: Base of NPN transistor with emitter to ground is internally connected on pin HFly through a series resistance of
about 500ꢀ and a resistance to ground of about 20kꢀꢅ
Note 3: Evaluated and figured out during the device qualification phase. Informative. Not tested on every single unit.
Note 4: This capture range can be enlarged by external circuitry.
Note 5: The voltage on HPLL2C pin corresponds to immediate phase of leading edge of H-drive signal on HOut pin with
respect to internal horizontal oscillator sawtooth. It must be between the two clamping levels given. Voltage
equal to one of the clamping values indicates a marginal operation of PLL2 or non-locked state.
Note 6: Internal threshold. See Figure 6.
Note 7: The t (min) parameter is fixed by the application. For correct operation of asymmetry corrections through
ph
dynamic phase modulation, this minimum must be increased by maximum of the total dynamic phase required
in the direction leading to bending of corners to the left. Marginal situation is indicated by reach of V
TopHPLL2C
high clamping level by waveform on pin HPLL2C. Also refer to Note 5 and Figure 6.
11/56
STV6889
Notes about horizontal section (continued)
Note 8: The t (max) parameter is fixed by the application. For correct operation of asymmetry corrections through
ph
dynamic phase modulation, this maximum must be reduced by maximum of the total dynamic phase required in
the direction leading to bending of corners to the right. Marginal situation is indicated by reach of V
BotHPLL2C
low clamping level by waveform on pin HPLL2C. Also refer to Note 5 and Figure 6.
Note 9: All other dynamic phase corrections of picture asymmetry set to their neutral (medium) positions.
6.5 Vertical section
Table 2. Vertical section (Vcc = 12V, Tamb = 25°C)
Value
Symbol
Parameter
Test Conditions
Units
Min.
Typ.
Max.
AGC-controlled vertical oscillator sawtooth; V
= 8V
RefO
Ext. load resistance on
VAGCCap pin
R
ꢂV
/V (R=A) ?1%
amp amp
65
Mꢀ
V
(10)
L(VAGCCap)
Sawtooth bottom voltage on
(11)
V
No load on VOscF pin
2
5
5
(11)
VOB
VCap pin
Sawtooth top voltage internal ref-
erence
V
V
VOTref
Sawtooth top voltage on VCap
pin
V
AGC loop stabilized
V
VOT
t
Sawtooth Discharge time
Free-running frequency
AGC loop capture frequency
C
C
C
=150nF
=150nF
=150nF
80
ꢁs
Hz
Hz
VODis
VCap
VCap
VCap
f
100
VO(0)
f
50
185
VOCapt
ꢂVVOdev
(12)(17)
(12)
Sawtooth non-linearity
AGC loop stabilized
0.5
%
--------------------
VVOamp
ꢂVVOamp
VOamp ꢄ ꢂfVO
Frequency drift of sawtooth
amplitude
AGC loop stabilized
---------------------------------
(18)(19)
ppm/Hz
V
f
(min)?f ?f
VO VOCapt
(max)
200
3.5
V
VOCapt
Vertical output drive signal (on pin VOut); V
= 8V
RefO
Internal reference for vertical
sawtooth middle point
V
midref
(22)
VPOS (Sad08h):
x0000000b
3.1
3.45
3.8
3.3
2.5
V
V
V
x1000000b
x1111111b
3.65
V
Middle point on VOut sawtooth
mid(VOut)
(21)
(23)
(20)
VPOF (Sad1Eh):
x0000000b
x1000000b
3.3
3.45
3.6
V
V
V
x1111111b
VSIZE (Sad07h):
x0000000b
x1000000b
2.25
3.0
3.75
V
V
V
x1111111b
3.5
Amplitude of VOut sawtooth
(peak-to-peak voltage)
V
amp
VSAG (Sad1Dh):
x0000000b
x1000000b
2
2.5
3.0
V
V
V
x1111111b
V
Level on VOut pin at V-drive "off" I²C-bus bit VOutEn at 0
4.0
V
offVOut
12/56
STV6889
Table 2. Vertical section (Vcc = 12V, Tamb = 25°C)
Value
Typ.
Symbol
Parameter
Test Conditions
Units
Min.
Max.
0.25
I
Current delivered by VOut output
-5
mA
VOut
(13)(20)(21)
AGC loop stabilized
V
V
/V
S-correction range
C-correction range
SCor
amp
(15)
t
t
=1/4 T
=3/4 T
-4.5
+4.5
%
%
VR
VR
VR
VR
(14)(20)(21)
AGC loop stabilized
(15)
t
=1/2 T
VR
VR
/V
CCOR(Sad0Ah):
CCor amp
x0000000b
x1000000b
x1111111b
-2.5
0
+2.5
%
%
%
Control input voltage range on-
VEHTIn pin
V
1
4
4.0
0
6
V
V
VEHT
Neutral point on breathing char-
V
(16)
VEHTnull
acteristics
V
V
ꢀꢁꢀV
ꢀꢁꢀV
VEHT CC
RefO
%/V
?V
?V
(min)
VEHT
VEHT VE-
(max):
HT
ꢂVamp
Breathing compensation
VEHTG (Sad1Ch):
x0000000b
-----------------------------------
5
0
-5
%/V
%/V
%/V
V
amp ꢄ ꢂVVEHT
x1000000b
x1111111b
Notes about vertical section
Note 10: Value of acceptable cumulated parasitic load resistance due to humidity, AGC storage capacitor leakage, etc.,
for less than 1% of V change.
amp
Note 11: The threshold for V
is generated internally and routed to VOscF pin. Any DC current on this pin will
VOB
influence the value of V
.
VOB
Note 12: Maximum of deviation from an ideally linear sawtooth ramp at null S-correction (SCOR at 0000000b) and null
C-correction (CCOR at 1000000b). The same rate applies to V-drive signal on VOut pin, no effect on EWOut.
Note 13: Maximum S-correction (SCOR at x1111111b), null C-correction (CCOR at 1000000b).
Note 14: Null S-correction (SCOR at 0000000b).
Note 15: "t " is time from the beginning of vertical ramp of V-drive signal on VOut pin. "T " is the duration of this ramp,
VR
VR
see Chapter 7 - page 21 and Figure 17.
Note 16: If V
=V
or V
=V
, respectively, the influence of V on vertical drive amplitude or the
VEHT
VEHT
VEHTnull
HEHT
HEHTnull
influence of V
on EW drive signal, respectively, is null.
HEHT
Note 17: V
= V
-V
VOT VOB
VOamp
Note 18: Only the top of the saw tooth drifts. The same rate applies to V-drive signal on VOut pin.
Note 19: Informative, not tested on each unit.
Note 20: VSIZE at medium value 1000000b.
Note 21: VPOS at medium value 1000000b.
Note 22: VPOF at medium value 1000000b.
Note 23: VSAG at maximum value 1111111b.
13/56
STV6889
6.6 EW drive section
Table 3. EW drive section (VCC = 12V, Tamb = 25°C)
Value
Typ.
Symbol
Parameter
Test Conditions
Units
Min.
Max.
V
Output voltage on EWOut pin
1.8
6.5
V
EW
Current delivered by EWOut out-
put
I
-1.5
1
0.1
6
mA
EWOut
Control voltage range on HEH-
TIn pin
V
V
V
HEHT
Neutral point on breathing char-
V
4.0
(16)
HEHTnull
acteristics. See Figure 15.
(24)(25)(26)(27)(28)(36)(42)(43)
EWTrHFrꢀ0 or V ꢁV
HO HOThrfr
DC component of the EW-drive HSIZE (Sad10h):
V
(30)
EW-DC
signal on EWOut pin
00000000b
10000000b
11111111b
2
3.25
4.5
V
V
V
DC reference for the EW-drive
signal on EWOut pin
V
2
V
EW-base
(24)(25)(26)(27)(42)(43)
V
V
ꢀꢁꢀV
ꢀꢁꢀV
HEHT
RefO
CC
?V
0
V/V
(min)?V
HEHT
HEHT HE-
Breathing compensation on DC
component of the EW-drive sig-
nal
ꢂVEW–DC
-----------------------
ꢂVHEHT
(max):
HT
0
V/V
V/V
V/V
V/V
HEHTG (Sad1Bh):
x0000000b
x1000000b
x1111111b
(30)
-0.25
0
+0.25
24 25 26 27 28 36 42 43
)( )( )( )( )( )( )(
(
(
)
ꢂVEW–DC
VEW–DC ꢄ ꢂT
Temperature drift of DC compo-
nent of the EW-drive signal
100
ppm/°C
-------------------------------
44
)
(30)
(24)(25)(26)(28)(29)(31)
(32)(36)(42)(43)
VSIZE at maximum
PCC (Sad0Ch):
x0000000b
x1000000b
x1111111b
0
0.75
1.5
V
V
V
Pin cushion correction compo-
nent of the EW-drive signal
V
EW-PCC
Tracking with VSIZE:
PCC at x1000000b
VSIZE (Sad07h):
x0000000b
0.25
0.5
V
V
x1000000b
24 25 26 29 33 35 36 42 43
)( )( )( )( )( )( )( )(
(
)
Tracking of PCC component of PCC at x1111111b
the EW-drive signal with vertical VPOS (Sad08h):
V
EW–PCCꢆtvr= 0ꢇ
--------------------------------------------
EW–PCCꢆtvr= TVRꢇ
V
position adjustment
x0000000b
x1111111b
0.5
2.0
25 26 27 28 29 33 34 36 42
)( )( )( )( )( )( )( )( )(
(
43
)
Keystone correction component
of the EW-drive signal
V
KEYST (Sad0Dh):
x0000000b
x1111111b
EW-Key
0.4
-0.4
V
V
14/56
STV6889
Table 3. EW drive section (VCC = 12V, Tamb = 25°C)
Value
Typ.
Symbol
Parameter
Test Conditions
Units
Min.
Max.
24 26 27 28 29 31 33 36 42
)( )( )( )( )( )( )( )(
(
(
)
)
)
)
43
)
Top corner correction compo-
nent of the EW-drive signal
TCC (Sad0Eh):
x0000000b
x1000000b
x1111111b
V
-1.4
0
+1.4
V
V
V
EW-TCor
24 25 27 28 29 32 33 36 42
)( )( )( )( )( )( )( )(
(
43
)
(
Bottom corner correction compo- BCC (Sad0Fh):
V
-1.4
0
+1.4
V
V
V
EW-BCor
nent of the EW-drive signal
x0000000b
x1000000b
x1111111b
24 25 26 27 28 29 33 36 41
)( )( )( )( )( )( )( )(
(
(
43
)
Pin Cushion S correction compo- EWSC (Sad19h):
V
-0.3
0
0.3
V
V
V
EW-S
nent of EW-drive signal
x0000000b
x1000000b
x1111111b
24 25 26 27 28 29 33 36 41
)( )( )( )( )( )( )( )(
(
(
42
)
Pin Cushion W correction com- EWWC (Sad1Ah):
V
-0.1
0
0.1
V
V
V
EW-W
ponent of EW-drive signal
x0000000b
x1000000b
x1111111b
Tracking of AC component of
I²C bit EWTrHFr=1
ꢂVEW–AC
----------------------------------------------------- EW-drive signal with horizontal
V
V
ꢈV
0
20
%/V
%/V
HO
HO
HOThrfr
V
EW–ACꢆfmaxꢇ ꢄ ꢂVHO
(37)(38)(39)
frequency
(min)?V ?V
HO
HOThrfr
Tracking of DC component of
I²C bit EWTrHFr=1
ꢂVEW–DC
---------------------------------------------------- EW-drive signal with horizontal
V
V
ꢈV
0
20
%/V
%/V
HO
HO
HOThrfr
V
EW–DCꢆspanꢇ ꢄ ꢂVHO
(30)(38)(39)
frequency
(min)?V ?V
HO
HOThrfr
I²C bit EWTrHSize=1
HSIZE (Sad10h):
00000000b
10000000b
11111111b
Tracking of AC component of
EW-drive signal with horizontal
size
VEW–AC
--------------------------------------------------
V
138
119
100
%
%
%
(37)
EW–ACꢆHSIZEmaxꢇ
V
V
ꢀꢁꢀV
ꢀꢁꢀV
HEHT
RefO
CC
?V
0
%/V
(min)?V
HEHT
HEHT HE-
Breathing compensation on AC
(max):
HT
ꢂVEW–AC
------------------------------------------
EW–AC ꢄ ꢂVHEHT
component of the EW-drive sig- HEHTG (Sad1Bh):
3.5
0
-3.5
%/V
%/V
%/V
V
(37)
nal
0000000b
1000000b
1111111b
15/56
STV6889
Notes about EW drive section
Note 24: KEYST at medium (neutral) value.
Note 25: TCC at medium (neutral) value.
Note 26: BCC at medium (neutral) value.
Note 27: PCC at minimum value.
Note 28: VPOS at medium (neutral) value.
Note 29: HSIZE I²C field at maximum value.
Note 30: V
is defined as voltage at t =1/2 T
.
VR
EW-DC
VR
Note 31: Defined as difference of (voltage at t =0) minus (voltage at t =1/2 T ).
VR
VR
VR
Note 32: Defined as difference of (voltage at t =T ) minus (voltage at t =1/2 T ).
VR
VR
VR
VR
Note 33: VSIZE at maximum value.
Note 34: Difference (voltage at t =0) minus (voltage at t =T ).
VR
VR
VR
Note 35: Ratio "A/B"of parabola component voltage at t =0 versus parabola component voltage at t =T .
VR
VR
VR
See Figure 2.
Note 36: V
Note 37: V
ꢈV
, V
ꢈV
VEHT RefO
HEHT
RefO
is defined as overall peak-to-peak value between t =0 and t =T of all components other than V
EW-
EW-AC
VR
VR
VR
(contribution of PCC, keystone correction, corner corrections and S- and W-corrections).
DC
Note 38: More precisely tracking with voltage on HPLL1F pin which itself depends on frequency at a rate given by
external components on PLL1 pins
Note 39: V
[span] = V
[V ꢈV
] - V
[HSIZE=0000000b].
EW-DC
EW-DC
EW-DC HO
HOThrfr
V
[f
] = V
[V ꢈV
].
HOThrfr
EW-AC max
EW-AC HO
Note 40: Defined as difference of (voltage at t =1/4 T ) minus (voltage at t =3/4 T ).
VR
VR
VR
VR
Note 41: Defined as difference of (voltage at t =1/2 T ) minus (voltage at t =1/4 T ).
VR
VR
VR
VR
Note 42: EWSC at medium (neutral) value.
Note 43: EWWC at medium (neutral) value.
Note 44: Informative, not tested on each unit.
16/56
STV6889
6.7 Dynamic correction outputs section
Table 4. Dynamic correction outputs section (VCC = 12V, Tamb = 25°C)
Value
Typ.
Symbol
Parameter
Test Conditions
Units
Min.
Max.
Vertical Dynamic Correction output VDyCor
I
Current delivered by VDyCor output
-1.5
0.1
mA
V
VDyCor
DC component of the drive signal
on VDyCor output
V
R
=10kꢀ
4
VD-DC
L(VDyCor)
(28)
VSIZE at medium
VDC-AMP (Sad15h):
x0000000b
0
0.5
1
V
V
V
Amplitude ofV-parabola onVDyCor x1000000b
V
VD-V
output
x1111111b
VDC-AMP at maximum
VSIZE (Sad07h):
x0000000b
0.6
1.6
V
V
x1111111b
VDC-AMP at maximum
Tracking of V-parabola on VDyCor VPOS (Sad08h):
VVD–VꢆtVR=0ꢇ
-------------------------------------------------------
(45)
output with vertical position
x0000000b
x1111111b
0.5
2.0
VVD–VꢆtVR=TVR
ꢇ
Notes about dynamic output section
Note 45: Ratio "A/B"of vertical parabola component voltage at t =0 versus vertical parabola component voltage at
VR
t
=T
.
VR
VR
17/56
STV6889
6.8 DC/DC controller section
Table 5. DC/DC controller section (VCC = 12V, Tamb = 25°C)
Value
Symbol
Parameter
Test Conditions
Units
Min.
Typ.
Max.
Ext. resistance applied between
BComp output and BRegIn input
R
5
kꢀ
B+FB
Open loop gain of error amplifier on
BRegIn input
(19)
A
Low frequency
100
dB
OLG
Unity gain bandwidth of error amplifier
on BRegIn input
(19)
f
6
MHz
UGBW
I
Bias current delivered by BRegIn
-0.2
ꢁA
RI
Output current capability of BComp out- BOut enabled
-0.5
2.0
mA
mA
I
(46)
BComp
put.
BOut disabled
0.5
3
A
Voltage gain on BISense input
BISense
Threshold voltage on BISense input
corresponding to current limitation
ThrBlsense = 0
ThrBlsense = 1
TBD
TBD
2.1
1.2
V
V
ThrBIsCurr
I
Bias current delivered by BISense
Conduction time of the power transistor
Output current capability of BOut output
-1
ꢁA
BISense
t
T - 300ns
H
BOn
I
0
10
mA
BOut
Saturation voltage of the internal output
transistor on BOut
V
I
=10mA
BOut
0.25
V
BOSat
V
=8V
RefO
BREF (Sad03h):
x0000000b
x1000000b
Regulation reference for BRegIn volt-
age
V
3.8
4.9
6.0
V
V
V
(47)
BReg
x1111111b
Delay of BOut “Off-to-On” edge after
middle of flyback pulse
BOutPh = 0 and BO-
HEdge = 0
t
16
%
/T
(48)
BTrigDel
H
Note 46: A current sink is provided by the BComp output while BOut is disabled.
Note 47: Internal reference related to V
. The same values to be found on pin BRegIn, while regulation loop is
RefO
stabilized.
Note 48: Only applies to configuration specified in "Test conditions" column, i.e. synchronization of BOut “Off-to-On”
edge with horizontal fly-back signal. Refer to chapter "DC/DC controller" for more details.
18/56
STV6889
6.9 Miscellaneous
Table 6. Miscellaneous (VCC = 12V, Tamb = 25°C)
Value
Typ.
Symbol
Parameter
Test Conditions
Units
Min.
Max.
Vertical blanking and horizontal lock indication composite output HLckVBk
(49)
I
Sink current to HLckVBk pin
100
ꢁA
SinkLckBk
V. blank
No
H. lock
Yes
Yes
No
0.1
1.1
5
V
V
V
V
Yes
V
Output voltage on HLckVBk output
OLckBk
No
Yes
No
6
Horizontal moiré canceller
HMoiréMode = 0
HMOIRE (Sad02h):
x0000000b
x1111111b
0
0.02
%
%
ꢂT
ꢀ
ꢁ
H H–moire
TH
----------------------------
Modulation of T by H. moiré function
H
HMoiréMode = 1
HMOIRE (Sad02h):
x0000000b
0
0.04
%
%
x1111111b
Vertical moiré canceller
VMOIRE (Sad0Bh):
x0000000b
x1111111b
Amplitude of modulation of V-drive sig-
nal on VOut pin by vertical moiré.
V
0
3
mV
mV
V-moiré
Protection functions
Input threshold on XRay input
V
V
RefO
+10mV
(50)
RefO
V
V
RefO
ThrXRay
-10mV
Delay time between XRay detection
event and protection action
t
T
H
2T
XRayDelay
H
Minimum V value for operation of
XRay detection and protection
CC
V
10.2
8.0
10.8
V
V
V
(53)
CCXRayEn
V
value for start of operation at V
CC
CC
CC
V
(51)
CCEn
ramp-up
V
value for stop of operation at V
CC
V
6.8
(51)
CCDis
ramp-down
(19)(52)
Control voltages on HPosF pin and V for Soft start/stop operation
CC
Threshold for start/stop of H-drive sig-
nal
V
1
V
V
HOn
BOn
Threshold for start/stop of B-drive sig-
nal
V
1.7
2.4
Threshold for full operation duty cycle
of H-drive and B-drive signals
V
HBNorm
Minimum supply voltage when voltage
V
on HPosF pin reaches V
old
thresh-
4.8
CCStop
HOn
(54)
19/56
STV6889
Notes about Miscellaneous section
Note 49: Current sunk by the pin if the external voltage is higher than one the circuit tries to force.
Note 50: See V
in Section 6.2.
RefO
Note 51: In the regions of V where the device's operation is disabled, the H-drive, V-drive and B+-drive signals on
CC
HOut, VOut and BOut pins, resp., are inhibited, the I²C-bus does not accept any data and the XRayAlarm flag
is reset. Also see Figure 10.
Note 52: See Figure 10.
Note 53: When V is below V
XRay detection and protection are disabled.
CCXRayEn
CC
Note 54: Minimum momentary supply voltage to ensure a correct performance of Soft stop function at V fall down is
CC
defined at the moment when the voltage on HPosF pin reaches V
threshold.
HOn
20/56
STV6889
7 TYPICAL OUTPUT WAVEFORMS
Table 7. Typical output waveforms - Note 55
Function
Sad
Pin
Byte
Waveform
Effect on Screen
V
x0000000
amp
V
mid(VOut)
VOut
(23)
Vertical Size
07
V
V
V
amp
x1111111
x0000000
V
mid(VOut)
amp
V
mid(VOut)
Vertical Size
After Gain
VOut
(23)
1D
x1111111
x0000000
x1000000
x1111111
x0000000
x1000000
x1111111
amp
V
mid(VOut)
V
midref
V
mid(VOut)
Vertical
Position
VOut
(23)
08
V
midref
V
mid(VOut)
V
mid(VOut)
V
V
midref
midref
V
mid(VOut)
Vertical
Position
Offset
VOut
(23)
V
1E
midref
V
mid(VOut)
V
mid(VOut)
V
midref
V
V
amp
x0000000:
Null
0
½
T
T
VR
VR
t
VR
VOut
(23)
S-correction
09
V
SCor
x1111111:
Max.
amp
0
¼
T
¾T
T
VR
VR
VR
t
VR
21/56
STV6889
Table 7. Typical output waveforms - Note 55
Function
Sad
Pin
Byte
Waveform
Effect on Screen
V
amp
V
x0000000
CCor
0
½
T
T
VR
VR
t
VR
V
amp
VOut
(23)
x1000000 :
Null
C-correction
0A
0
½
T
T
T
VR
VR
t
VR
V
amp
V
CCor
x1111111
0
½
T
VR
VR
t
VR
V
amp
x0000000:
Null
(n-1)T
nT
(n+1)T
V
V
V
t
Vertical moiré
amplitude
VOut
(23)
0B
V
V-moiré
V
x1111111: amp
Max.
(n-1)T
nT
(n+1)T
T
V
V
V
t
V
00000000
11111111
EW-DC
0
½T
VR
VR
t
VR
EWOut
(24)
Horizontal size 10h
V
EW-DC
0
½
T
T
T
VR
VR
VR
t
VR
V
V
EW-DC
EW-Key
x0000000
x1111111
0
½
T
VR
t
VR
Keystone
0D
EWOut
(24)
correction
V
EW-Key
V
EW-DC
V
EW-PCC
x0000000
x1111111
0
½T
T
VR
VR
t
VR
Pin cushion
0C
EWOut
(24)
correction
V
EW-PCC
0
½
T
T
VR
VR
t
VR
22/56
STV6889
Table 7. Typical output waveforms - Note 55
Function
Sad
Pin
Byte
Waveform
Effect on Screen
V
EW-TCor
x1111111
0
½
T
T
VR
Top corner
correction
EWOut
(24)
VR
t
VR
0E
V
EW-TCor
x0000000
x1111111
0
½
T
T
T
VR
VR
t
VR
V
EW-BCor
0
½T
Bottom corner
correction
EWOut
(24)
VR
VR
t
VR
0F
V
EW-BCor
x0000000
x1111111
0
½
T
T
VR
VR
VR
t
VR
V
V
EW-S
EW-S
0
0
½T
T
t
VR
VR
Pin Cushion
S-correction
EWOut
(24)
19
x0000000
T
½
T
t
VR
VR
VR
V
EW-W
x1111111
x0000000
x0000000
0
0
½
T
T
VR
Pin Cushion
W-correction
EWOut
(24)
t
VR
VR
1A
V
t
EW-W
½
T
T
VR
t
VR
VR
VR
VR
static H-phase
ParalC
0
½
T
T
VR
VR
t
Parallelogram
correction
12h
t
ParalC
static H-phase
x1111111
x0000000
x1111111
0
½
T
T
VR
VR
t
static
H-phase
t
PCAC
0
½T
T
VR
VR
t
VR
Pin cushion
asymmetry
correction
11h
t
PCAC
static
H-phase
0
½T
T
VR
VR
t
VR
23/56
STV6889
Table 7. Typical output waveforms - Note 55
Function
Sad
Pin
Byte
Waveform
Effect on Screen
t
TCAC
static
H-phase
x0000000
0
½
T
T
T
Top corner
asymmetry
correction
VR
VR
t
VR
13h
static
H-phase
t
x1111111
TCAC
0
½T
VR
VR
t
VR
t
BCAC
static
H-phase
x0000000
x1111111
01111111
Bottom corner
asymmetry
correction
0
½
T
T
VR
VR
t
VR
14h
static
H-phase
t
BCAC
0
½T
T
VR
VR
t
VR
VDyCorPol=0
V
V
VD-V
V
VD-DC
0
0
½
T
T
VR
VR
V
t
VR
Vertical
dynamic
correction
amplitude
VDyCor
(32)
VD-V
VD-DC
15h
Application dependent
x0000000
11111111
½
T
T
VR
VR
t
VR
VDyCorPol=1
V
V
VD-DC
VD-V
0
½
T
T
VR
VR
t
VR
Note 55: For any H and V correction component of the waveforms on EWOut and VOut pins and internal waveform for
corrections of H asymmetry, displayed in the table, the weight of the other relevant components is nullified
(minimum for parabola, S-correction, medium for keystone, all corner corrections, C-correction, S- and W-pin
cushion corrections, parallelogram, pin cushion asymmetry correction, written in corresponding registers).
24/56
STV6889
8 I²C-BUS CONTROL REGISTER MAP
The device slave address is 8C in write mode and 8D in read mode. The control register map is given in
Table .
Bold weight denotes default value at Power-On-Reset.
I²C-bus data in the adjustment register is buffered and internally applied with discharge of the vertical os-
)
56
cillator (
.
In order to ensure compatibility with future devices, all “Reserved” bits should be set to 0.
Table 8. I²C-bus control registers
Sad
D7
D6
D5
D4
D3
D2
D1
D0
WRITE MODE (SLAVE ADDRESS = 8C)
HDutySyncV
HDUTY Horizontal duty cycle
00
01
02
03
1: Synchro.
0: Asynchro.
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HPOS Horizontal position
1
0
0
0
HMoiréMode
1: Separated
0: Combined
HMOIRE Horizontal moiré amplitude
0
0
0
BREF B+reference
B+SyncV
0: Asynchro.
0
0
0
04
05
Reserved
Reserved
BOutPol
0: Type N
06
Reserved
BOutPh
VSIZE Vertical size
07
0: H-flyback
1: H-drive
1
0
0
0
0
0
0
VPOS Vertical position
EWTrHFr
0: No tracking
08
09
0A
0B
0C
0D
0E
0F
10
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SCOR S-correction
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
CCOR C-correction
0
0
VMOIRE Vertical moiré amplitude
0
0
0
PCC Pin cushion correction
0
0
0
KEYST Keystone correction
0
0
0
0
0
TCC Top corner correction
0
0
BCC Bottom corner correction
0
0
HSIZE Horizontal size
1
0
0
0
25/56
STV6889
Table 8. I²C-bus control registers
Sad
D7
D6
1
D5
D4
D3
D2
D1
D0
0
PCAC Pin cushion asymmetry correction
11
12
13
14
15
Reserved
Reserved
Reserved
0
0
0
0
0
0
PARAL Parallelogram correction
1
0
0
0
0
0
TCAC Top corner asymmetry correction
1
0
0
0
0
0
0
BCAC Bottom corner asymmetry correction
Reserved
1
0
0
0
0
0
0
0
VDC-AMP Vertical dynamic correction
VDyCorPol
0: ”ꢉ"
1
0
0
0
0
0
PLL1Pump
1,1: Fastest
XRayReset
0: No effect
VSyncAuto VSyncSel
SDetReset
0: No effect
PLL1InhEn
HLockEn
1: On
16
1: On
0:Comp
1: On
1: Reset
1:Sep
1: Reset
0,0: Slowest
TV
TH
0: Off
TVM
0: Off
THM
0: Off
BOHEdge
0: Falling
HBOutEn
0: Disable
VOutEn
0: Disable
BlankMode
1: Perm.
17
18
19
(58)
(58)
(58)
(58)
0: Off
Reserved
EWSC East-West S-correction
Reserved
0:
1
1
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
EWWC East-West W-correction
Reserved
1A
1B
1C
1D
1E
1F
0:
0
0
0
HEHTG Horizontal EHT compensation gain
Reserved
0:
0
0
0
0
VEHTG Vertical EHT compensation gain
Reserved
0:
0
0
0
0
0
VSAG Vertical size after-gain
Reserved
0:
1
0
0
VPOF Vertical position offset
Reserved
0:
1
0
0
0
0
0
BMute
0: Off
BSafeEn
0: Disable
EWTrHSize
0: Tracking 0: No effect 0: Slow
Ident
HLockSpeed
ThrBlsense
0: High
Reserved
Reserved
READ MODE (SLAVE ADDRESS = 8D)
Polarity detection
Sync detection
HLock
0: Locked
VLock
0: Locked
XRayAlarm
1: On
57
XX(
HVPol
VPol
VExtrDet
HVDet
VDet
)
1: Not locked 1: Not lock. 0: Off
1: Negative 1: Negative 0: Not det. 0: Not det. 0: Not det.
Note 56: With exception of HDUTY and BREF adjustments data that can take effect instantaneously if switches
HDutySyncV and B+SyncV are at 0, respectively.
Note 57: In Read Mode, the device always outputs data of the status register, regardless of sub address previously
selected.
Note 58: The TV, TH, TVM and THM bits are for testing purposes and must be kept at 0 by application.
26/56
STV6889
DESCRIPTION OF I²C-BUS SWITCHES AND FLAGS
Write-to bits
Sad00h/D7 - HDutySyncV
Sad16h/D0 - HLockEn
Synchronization of internal application of Hori-
zontal Duty cycle data, buffered in I²C-bus latch,
with internal discharge of Vertical oscillator.
Enable of output of Horizontal PLL1 Lock/unlock
status signal on pin HLckVBk
0: Disabled, vertical blanking only on the pin
HLckVBk
1: Enabled
0: Asynchronous mode, new data applied
with ACK bit of I²C-bus transfer on this sub
address
1: Synchronous mode
Sad16h/D1 - PLL1InhEn
Enable of Inhibition of horizontal PLL1 during
extracted vertical synchronization pulse
0: Disabled, PLL1 is never inhibited
1: Enabled
Sad02h/D7 - HMoiréMode
Horizontal Moiré characteristics.
0: Adapted to an architecture with EHT gener-
ated in deflection section
1: Adapted to an architecture with separated
deflection and EHT sections
Sad16h/D2 and D3- PLL1Pump
Horizontal PLL1 charge Pump current
Sad03h/D7 - B+SyncV
Same as HDutySyncV, applicable for B+ refer-
ence data
D3
0
D2
0
Time Constant
Slowest PLL1, lowest current
Moderate Slow PLL1, low current
Moderate Fast PLL1, high current
Fastest PLL1, highest current
1
0
0
1
Sad06h/D7 - BOutPol
Polarity of B+ drive signal on BOut pin.
1
1
0: adapted to N type of power MOS - high
Sad16h/D4 - SDetReset
level to make it conductive
Reset to 0 of Synchronization Detection flags
VDet, HVDet and VExtrDet of status register ef-
fected with ACK bit of I²C-bus data transfer into
register containing the SDetReset bit. Also see
description of the flags.
1: adapted to P type of power MOS - low level
to make it conductive
Sad07h/D7 - BOutPh
Phase of start of B+ drive signal on BOut pin
0: No effect
0: End of horizontal flyback or horizontal fre-
quency divided by 2, see BOHEdge bit.
1: With one of edges of line drive signal on
HOut pin, selected by BOHEdge bit
1: Reset with automatic return of the bit to 0
Sad16h/D5 - VSyncSel
Vertical Synchronization input Selection be-
tween the one extracted from composite HV sig-
nal on pin H/HVSyn and the one on pin VSyn. No
effect if VSyncAuto bit is at 1.
Sad08h/D7 - EWTrHFr
Tracking of all corrections contained in wave-
form on pin EWOut with Horizontal Frequency
0: Not active
0: V. sync extracted from composite signal on
H/HVSyn pin selected
1: V. sync applied on VSyn pin selected
1: Active
Sad15h/D7 - VDyCorPol
Sad16h/D6 - VSyncAuto
Polarity of Vertical Dynamic Correction wave-
form (parabola)
Vertical Synchronization input selection Auto-
matic mode. If enabled, the device automatically
selects between the vertical sync extracted from
composite HV signal on pin H/HVSyn and the one
on pin VSyn, based on detection mechanism. If
both are present, the one coming first is kept.
0: Concave (minimum in the middle of the pa-
rabola)
1: Convex (maximum in the middle of the pa-
rabola)
0: Disabled, selection done according to bit
VSyncSel
1: Enabled, the bit VSyncSel has no effect
27/56
STV6889
Sad16h/D7 - XRayReset
If the bit BOutPh is at 0, selection of signal to
phase B+ drive output on BOut pin:
Reset to 0 of XRay flag of status register effect-
ed with ACK bit of I²C-bus data transfer into reg-
ister containing the XRayReset bit. Also see de-
scription of the flag.
1: Horizontal frequency divided by 2 signal,
top of horizontal VCO
0: End of horizontal flyback
0: No effect
1: Reset with automatic return of the bit to 0
Sad17h/D4,D5,D6,D7 - THM, TVM, TH, TV
Test bits. They must be kept at 0 level by appli-
cation S/W.
Sad17h/D0 - BlankMode
Blanking operation Mode.
Sad1Fh/D2 - HLockSpeed
Response Speed of lock-to-unlock transition of
H-lock component on HLock output and HLock
I²C-bus flag at signal change.
0: Blanking pulse starting with detection of
vertical synchronization pulse and ending
with end of vertical oscillator discharge
(start of vertical sawtooth ramp on the VOut
pin)
1: Permanent blanking - high blanking level in
composite signal on pin HLckVBk is perma-
nent
0: Low
1: High
Sad1Fh/D3 - Ident
Device Identification bit.
If HBOutEn is at 1, the bit has no effect.
If HBOutEn is at 0, then
Sad17h/D1 - VOutEn
Vertical Output Enable.
0: Disabled, VoffVOut on VOut pin (see Section
6.5 Vertical section)
1: Enabled, vertical ramp with vertical position
offset on VOut pin
0: The value of Hlock status bit is 1
1: The value of Hlock status bit is 0
Sad1Fh/D4 - EWTrHSize
Tracking of all corrections contained in wave-
form on pin EWOut with Horizontal Size I²C-bus
register HSIZE.
Sad17h/D2 - HBOutEn
Horizontal and B+ Output Enable.
0: Disabled, levels corresponding to “power
transistor off” on HOut and BOut pins (high
for HOut, high or low for BOut, depending on
BOutPol bit).
1: Enabled, horizontal deflection drive signal
on HOut pin providing that it is not inhibited
by another internal event (activated XRay
protection). B+ drive signal on BOut pin if not
inhibited by another internal event.
0: Active
1: Not active
Sad1Fh/D5 - BSafeEn
B+ Output Safety Enable.
0: Disabled
1: Enabled, BOut goes off as soon as HLock
status of Horizontal PLL1 indicates “unlock”
state. Retrieval of “lock” state will initiate
soft start mechanism of DC/DC controller
on BOut output.
Programming the bit to 1 after prior value of 0,
will initiate soft start mechanism of horizontal
drive and, if this is not inhibited by another inter-
nal event, also the soft start of B+ DC/DC con-
vertor controller. See also bits BMute and BSa-
feEn.
Sad1Fh/D6 - BMute
B+ Output Mute.
0: Disabled
Sad17h/D3 - BOHEdge
1: Enabled, BOut goes unconditionally off.
Programming this bit back to 0 will initiate
soft start mechanism of DC/DC controller
on BOut output.
If the bit BOutPh is at 1, selection of Edge of Hor-
izontal drive signal to phase B+ drive Output sig-
nal on BOut pin.
1: Rising edge
0: Falling edge
Sad1Fh/D7 - ThrBlsense
Threshold on BISense input corresponding to
current limitation.
0: High
1: Low
28/56
STV6889
Read-out flags
)
SadXX/D0 - VDet(59
SadXX/D4 - HVPol
Flag indicating Detection of V synchronization
pulses on VSyn pin.
Flag indicating Polarity of H or HV synchroniza-
tion pulses applied on H/HVSyn pin with respect
to mean level of the sync signal.
0: Positive
0: Not detected
1: Detected
1: Negative
)
59
SadXX/D1 - HVDet (
SadXX/D5 - XRayAlarm
Flag indicating Detection of H or HV synchroni-
zation pulses applied on H/HVSyn pin. Once the
sync pulses are detected, the flag is set and
latched. Disappearance of the sync signal will
not lead to reset of the flag.
Alarm indicating that an event of excessive volt-
age has passed on XRay pin. Can only be reset
to 0 through I²C-bus bit XRayReset or by power-
on reset.
0: Not detected
1: Detected.
0: No excess since last reset of the bit
1: At least one event of excess appeared
since the last reset of the bit, HOut inhibited
SadXX/D2 - VExtrDet (
Flag indicating Detection of Extracted Vertical
synchronization signal from composite H+V sig-
nal applied on H/HVSyn pin.
)
59
SadXX/D6 - VLock
Status of “Locking” or stabilizing of Vertical oscil-
lator amplitude to an internal reference by AGC
regulation loop.
0: Not detected
1: Detected
0: Locked (amplitude stabilized)
1: Not locked (amplitude non-stabilized)
SadXX/D3 - VPol
SadXX/D7 - HLock
Lock status of Horizontal PLL1.
0: Locked
Flag indicating Polarity of V synchronization
pulses applied on VSyn pin with respect to mean
level of the sync signal.
0: Positive
1: Not locked
1: Negative
See also bit Ident (Sad1Fh/D3)
Note 59: This flag, by its value of 1, indicates an event of detection of at least one synchronization pulse since its last
reset (by means of the SDetReset I²C-bus bit). This is to be taken into account by application S/W in a way that
enough time (at least the period between 2 synchronization pulses of analyzed signal) must be provided
between reset of the flag through SDetReset bit and validation of information provided in the flag after read-out
of status register.
29/56
STV6889
9 OPERATING DESCRIPTION
9.1 Supply and control
9.1.1 Power supply and voltage references
Internal thresholds in all parts of the circuit are de-
rived from a common internal reference supply
RefO that is lead out to RefOut pin for external filter-
ing against ground as well as for external use with
load currents limited to IRefO. The filtering is neces-
sary to minimize interference in output signals,
causing adverse effects like e.g. jitter.
The device is designed for a typical value of power
supply voltage of 12 V.
V
In order to avoid erratic operation of the circuit at
power supply ramp-up or ramp-down, the value of
V
CC is monitored. See Figure 1 and electrical spec-
ifications. At switch-on, the device enters a “nor-
mal operation” as the supply voltage exceeds V
9.1.2 I²C-bus control
C-
and stays there until it decreases bellow V
The I²C-bus is a 2 line bidirectional serial commu-
nication bus introduced by Philips. For its general
description, refer to corresponding Philips I²C-bus
specification.
CEn . The two thresholds provide, by their diffeCr--
CDis
ence, a hysteresis to bridge potential noise. Out-
side the “normal operation”, the signals on HOut,
BOut and VOut outputs are inhibited and the I²C-
bus interface is inactive (high impedance on SDA,
SCL pins, no ACK), all I²C-bus control registers be-
ing reset to their default values (see Chapter 8 -
page 25). The stop of HOut and BOut drive signals
when the V falls from normal operation below
This device is an I²C-bus slave, compatible with
fast (400kHz) I²C-bus protocol, with write mode
slave address of 8Ch (read mode slave address
8Dh). Integrators are employed at the SCL (Serial
Clock) input and at the input buffer of the SDA (Se-
rial Data) input/output to filter off the spikes up to
50ns.
V
CCDis is notCinCstantaneous. It is only a trigger point
of Soft Stop mechanism (see Subsection 9.3.7- page
35).
The device supports multiple data byte messages
(with automatic incrementing of the I²C-bus subad-
dress) as well as repeated Start Condition for I²C-
bus subaddress change inside the I²C-bus mes-
sages. All I²C-bus registers with specified I²C-bus
subaddress are of WRITE ONLY type, whereas
the status register providing a feedback informa-
tion to the master I²C-bus device has no attributed
I²C-bus subaddress and is of READ ONLY type.
The master I²C-bus device reads this register
sending directly, after the Start Condition, the
READ device I²C-bus slave address (8Dh) fol-
lowed by the register read-out, NAK (No Acknowl-
edge) signal and the Stop Condition.
Figure 1. Supply voltage monitoring
V
CC
V
(Vcc)
V
CCEn
hysteresis
V
CCDis
Disabled
Normal operation
Disabled
t
For the I²C-bus control register map, refer to Chap-
ter 8 - page 25.
9.2 Synchronization processor
9.2.1 Synchronization signals
part and to an extractor of vertical sync. pulses,
working on principle of integration, see Figure 3.
The vertical sync. signal applied to the vertical de-
flection processor is selected between the signal
extracted from the composite signal on H/HVSyn in-
put and the one applied on VSyn input. The selec-
tor is controlled by VSyncSel I²C-bus bit.
The device has two inputs for TTL-level synchroni-
zation signals, both with hysteresis to avoid erratic
detection and with a pull-down resistor. On H/
HVSyn input, pure horizontal or composite horizon-
tal/vertical signal is accepted. On VSyn input, only
pure vertical sync. signal is accepted. Both posi-
tive and negative polarities may be applied on ei-
ther input, see Figure 2. Polarity detector and pro-
grammable inverter are provided on each of the
two inputs. The signal applied on H/HVSyn pin, af-
ter polarity treatment, is directly lead to horizontal
Besides polarity detection, the device is capable of
detecting presence of sync. signals on each of the
inputs and at the output of vertical sync. extractor.
The information from all detectors is provided in
the I²C-bus status register (5 flags: VDet, HVDet,
30/56
STV6889
VExtrDet, VPol, HVPol). The device is equipped
with an automatic mode (switched on or off by
VSyncAuto I²C-bus bit) that also uses the detec-
tion information.
9.2.2 Sync. presence detection flags
The sync. signal presence detection flags in the
status register (VDet, HVDet, VExtrDet) do not
show in real time the presence or absence of cor-
responding sync. signal. They are latched to 1 as
soon as a single sync. pulse is detected. In order
to reset them to 0 (all at once), a 1 must be written
into SDetReset I²C-bus bit, the reset action taking
effect with ACK bit of the I²C-bus transfer to the
register containing SDetReset bit. The detection
circuits are ready to capture another event (pulse).
See Note 59.
Figure 2. Horizontal sync signal
Positive
t
T
PulseHSyn
H
Negative
Figure 3. Extraction of V-sync signal from H/V-sync signal
H/V-sync
T
t
PulseHSyn
H
Internal
Integration
t
extrV
Extracted
V-sync
9.2.3 MCU controlled sync. selection mode
9.2.4 Automatic sync. selection mode
I²C-bus bit VSyncAuto is set to 0. The MCU reads
the polarity and signal presence detection flags,
after setting the SDetReset bit to 1 and an appro-
priate delay, to obtain a true information of the sig-
nals applied, reads and evaluates this information
and controls the vertical signal selector according-
ly. The MCU has no access to polarity inverters,
they are controlled automatically.
I²C-bus bit VSyncAuto is set to 1. In this mode, the
device itself controls the I²C-bus bits switching the
polarity inverters (HVPol, VPol) and the vertical
sync. signal selector (VSyncSel), using the infor-
mation provided by the detection circuitry. If both
extracted and pure vertical sync. signals are
present, the one already selected is maintained.
No intervention of the MCU is necessary.
See also chapter Chapter 8 - page 25.
31/56
STV6889
9.3 Horizontal section
9.3.1 General
sync. signal change. In locked state, the currents
are much higher, four different values being se-
lectable via PLL1Pump I²C-bus bits to provide a
means to control the PLL1 speed by S/W. Lower
value make the PLL1 slower, but more stable.
Higher values make it faster and less stable. In
general, the PLL1 speed should be higher for high
deflection frequencies. The response speed and
stability (jitter level) depend on the choice of exter-
nal components making up the loop filter. A “CRC”
filter is generally used (see Figure 4).
The horizontal section consists of two PLLs with
various adjustments and corrections, working on
horizontal deflection frequency, then phase shift-
ing and output driving circuitry providing H-drive
signal on HOut pin. Input signal to the horizontal
section is output of the polarity inverter on H/HVSyn
input. The device ensures automatically that this
polarity be always positive.
9.3.2 PLL1
The PLL1 block diagram is in Figure 5. It consists of
a voltage-controlled oscillator (VCO), a shaper
with adjustable threshold, a charge pump with inhi-
bition circuit, a frequency and phase comparator
and timing circuitry. The goal of the PLL1 is to
make the VCO ramp signal match in frequency the
sync. signal and to lock this ramp in phase to the
sync. signal. On the screen, this offset results in
the change of horizontal position of the picture.
The loop, by tuning the VCO accordingly, gets and
maintains in coincidence the rising edge of input
sync. signal with signal REF1, deriving from the
VCO ramp by a comparator with threshold adjust-
able through HPOS I²C-bus control. The coinci-
dence is identified and flagged by lock detection
circuit on pin HLckVBk as well as by HLock I²C-bus
flag.
Figure 4. H-PLL1 filter configuration
HPLL1F
9
R
2
C
1
C
2
The PLL1 is internally inhibited during extracted
vertical sync. pulse (if any) to avoid taking into ac-
count missing or wrong pulses on the phase com-
parator. Inhibition is obtained by forcing the charge
pump output to high impedance state. The inhibi-
tion mechanism can be disabled through
PLL1InhEn I²C-bus bit.
The charge pump provides positive and negative
currents charging the external loop filter on HPLL1F
pin. The loop is independent of the trailing edge of
sync. signal and only locks to its leading edge. By
design, the PLL1 does not suffer from any dead
band even while locked. The speed of the PLL1
depends on current value provided by the charge
pump. While not locked, the current is very low, to
slow down the changes of VCO frequency and
thus protect the external power components at
The Figure 7, in its upper part, shows the position of
the VCO ramp signal in relation to input sync.
pulse for three different positions of adjustment of
horizontal position control HPOS.
32/56
STV6889
Figure 5. Horizontal PLL1 block diagram
PLL1InhEn
(I²C)
V-sync (extracted)
HLckVBk
3
HLock
(I²C)
Blank
PLL1
HPLL1F RO CO HOscF
9
8
6
4
Sync
Polarity
LOCK
DETECTOR
PLL
INHIBITION
High
Low
H/HVSyn
1
INPUT
INTERFACE
CHARGE
PUMP
VCO
HOSC
COMP
REF1
HPosF
10
Extracted
V-sync
PLL1Pump
(I²C)
HPOS
(I²C)
SHAPER
Figure 6. Horizontal oscillator (VCO) schematic diagram
HOscF
4
I
0
+
-
I
V
2
0
(PLL1 filter)
HPLL1F
HOThrHi
V
RS
Flip-Flop
HO
9
+
-
-
+
V
HOThrLo
4 I
0
RO 8
VCO discharge
control
CO
6
from charge pump
V
HOThrHi
HOThrLo
V
9.3.3 Voltage controlled oscillator
At no signal condition, the V tuning voltage is
HO
clamped to its minimum (see section 6.4 - page
10), which corresponds to the free-running VCO
frequency fHO(0). Refer to subsection 9.3.1 for formu-
la to calculate this frequency using external com-
ponents values. The ratio between the frequency
corresponding to maximum VHO and the one corre-
The VCO makes part of both PLL1 and PLL2
loops, being an “output” to PLL1 and “input” to
PLL2. It delivers a linear sawtooth. Figure 6 ex-
plains its principle of operation. The linears are ob-
tained by charging and discharging an external ca-
pacitor on pin CO, with currents proportional to the
current forced through an external resistor on pin
RO, which itself depends on the input tuning volt-
sponding to minimum V (free-running frequen-
HO
cy) is about 4.5. This range can easily be in-
creased in the application. The PLL1 can only lock
to input frequencies falling inside these two limits.
age V (filtered charge pump output). The rising
HO
and falling linears are limited by VHOThrLo and V
HO-
ThrHi thresholds filtered through HOscF pin.
33/56
STV6889
9.3.4 PLL2
rabola of 2nd order for Pin cushion asymmetry cor-
rection and half-parabolas of 4th order for corner
corrections independently at the top and at the
bottom) are generated from the output vertical de-
flection drive waveform, they all track with real ver-
tical amplitude and position, thus being fixed on
the screen. Refer to Chapter 8 - page 25 for details
on I²C-bus controls.
The goal of the PLL2 is, by means of phasing the
signal driving the power deflection transistor, to
lock the middle of the horizontal flyback to a cer-
tain threshold of the VCO sawtooth. This internal
threshold is affected by geometry phase correc-
tions, like e.g., parallelogram. The PLL2 is fast
enough to be able to follow the dynamism of phase
modulation, this speed is strongly related to the
value of the capacitor on HPLL2C. The PLL2 con-
trol current (see Figure 7) is significantly increased
during discharge of vertical oscillator (during verti-
cal retrace period) to be able to make up for the
difference of dynamic phase at the bottom and at
the top of the picture. The PLL2 control current is
integrated on the external filter on pin HPLL2C to
obtain smoothed voltage, used, in comparison
with VCO ramp, as a threshold for H-drive rising
edge generation.
Figure 7. Horizontal timing diagram
t
Hph
min max
HPOS
(I²C)
H-sync
(polarized)
max.
med.
min.
PLL1
lock
REF1
(internal)
V
HOThrHi
V
HPosF
max.
med.
As both leading and trailing edges of the H-drive
signal in the Figure 7 must fall inside the rising part
of the VCO ramp, an optimum middle position of
the threshold has been found to provide enough
margin for horizontal output transistor storage time
as well as for the trailing edge of H-drive signal
with maximum duty cycle. Yet, the constraints
thereof must be taken into account while consider-
ing the application frequency range and H-flyback
duration. The Figure 7 also shows regions for rising
and falling edges of the H-drive signal on HOut pin.
As it is forced high during the H-flyback pulse and
low during the VCO discharge period, no edge
during these two events takes effect.
V
S(0)
H-Osc
(VCO)
min.
V
HOThrLo
7/8T
H
T
H
V
ThrHFly
H-fly-back
t
S
PLL2
control
current
+
t
-
ON
ON
OFF
H-drive
(on HOut)
Hoff
forced high forced low
H-drive
region
The flyback input configuration is in Figure 8.
t
(max)
9.3.5 Dynamic PLL2 phase control
ph
H-drive
region
The dynamic phase control of PLL2 is used to
compensate for picture asymmetry versus vertical
axis across the middle of the picture. It is done by
modulating the phase of the horizontal deflection
with respect to the incoming video (synchroniza-
tion). Inside the device, the threshold VS(0) is com-
pared with the VCO ramp, the PLL2 locking the
middle of H-flyback to the moment of their match.
The dynamic phase is obtained by modulation of
the threshold by correction waveforms. Refer to
Figure 14 and Chapter 7 - page 21. The correction
waveforms have no effect in vertical middle of the
screen (for middle vertical position). As they are
summed, their effect on the phase tends to reach
maximum span at top and bottom of the picture.
As all the components of the resulting correction
waveform (linear for parallelogram correction, pa-
inhibited
t : HOT storage time
S
Figure 8. HFly input configuration
~500ꢀ
HFly
12
~20kꢀ
ext. int.
GND
34/56
STV6889
9.3.6 Output Section
9.3.8 Horizontal moiré cancellation
The H-drive signal is inhibited (high level) during
flyback pulse, and also when VCC is too low, when
X-ray protection is activated (XRayAlarm I²C-bus
flag set to 1) and when I²C-bus bit HBOutEn is set
to 0 (default position).
The horizontal moiré canceller is intended to blur a
potential beat between the horizontal video pixel
period and the CRT pixel width, which causes vis-
ible moiré patterns in the picture.
It introduces a microscopic indent on horizontal
scan lines by injecting little controlled phase shifts
to output circuitry of the horizontal section. Their
amplitude is adjustable through HMOIRE I²C-bus
control.
The duty cycle of the H-drive signal is controlled
via I²C-bus register HDUTY. This is overruled dur-
ing soft-start and soft-stop procedures (see Section
9.3.7 and Figure 10).
The PLL2 is followed by a rapid phase shifting
which accepts the signal from H-moiré canceller
(see Section 9.3.8)
The behaviour of horizontal moiré is to be opti-
mized for different deflection design configurations
using HMoiréMode I²C-bus bit. This bit is to be
kept at 0 for common architecture (B+ and EHT
common regulation) and at 1 for separated archi-
tecture (B+ and EHT each regulated separately).
The maximum amplitude adjustable though HMOI-
RE I²C-bus control is optimized according to selec-
tion by HMoiréMode I²C-bus bit: larger when B+
and EHT are each regulated separately, smaller
when B+ and EHT are common regulation.
The output stage consists of a NPN bipolar tran-
sistor, the collector of which is routed to HOut pin
(see Figure 9).
Figure 9. HOut configuration
HOut
26
int. ext.
9.3.7 Soft-start and soft-stop on H-drive
The soft-start and soft-stop procedure is carried
out at each switch-on or switch-off of the H-drive
signal, either via HBOutEn I²C-bus bit or after re-
set of XRayAlarm I²C-bus flag, to protect external
power components. By its second function, the ex-
ternal capacitor on pin HPosF is used to time out
this procedure, during which the duty cycle of H-
drive signal starts at its maximum (t
for soft
start/stop in electrical specifications) Haonffd slowly
decreases to the value determined by the control
I²C-bus register HDUTY (vice versa at soft-stop).
This is controlled by voltage on pin HPosF. In case
of supply voltage switch off, the transients on HOut
and BOut have different characteristics. See
Figure 10, Figure 11 and Section 9.8.1.
35/56
STV6889
Figure 10. Control of HOut and BOut at start/stop at nominal V
CC
minimum value
V
(HPosF)
HPOS range
V
HPosF
(I²C)
maximum value
V
HBNorm
V
BOn
Soft start
Normal operation
Soft stop
V
HOn
Stop Stop
B-drv H-drv
Start Start
H-drv B-drv
t
HOut
100%
H-duty cycle
BOut (positive)
B-duty cycle
0%
Figure 11. Events triggering Soft start and Soft stop
maximum V fall down speed
CC
for correct operation
V[HPosF]
Soft start
V[HPosF]
V
CCDis
Soft stop
event
event
V
V
CC
CCStop
V
(HPosF)
V
(HPosF)
V
V
HPosF
HPosF
HBOutEn=1
V
V
HBNorm
HBNorm
XRayAlarm=0
V
’
V
HBNorm
V
BOn
BOn
V
’
BOn
V
V
HOn
HOn
V
’
HOn
ꢀ
ꢀ
ꢀ
t
t
100%
100%
HOut duty cycle
BOut duty cycle
HOut duty cycle
BOut duty cycle
0%
0%
NOMINAL V
FALLING V
CC
CC
36/56
STV6889
9.4 Vertical section
9.4.1 General
The goal of the vertical section is to drive vertical
deflection output stage. It delivers a sawtooth
waveform with an amplitude independent of de-
flection frequency, on which vertical linearity cor-
rections of C- and S-type are superimposed (see
Chapter 7 - page 21).
150nF
C(VCap)
.
100Hz
f
=
VO(0)
The frequency range in which the AGC loop can
regulate the amplitude also depends on this ca-
pacitor.
Block diagram is in Figure 12. The sawtooth is ob-
tained by charging an external capacitor on pin
VCap with controlled current and by discharging it
via transistor Q1. This is controlled by the CON-
TROLLER. The charging starts when the voltage
The vertical sawtooth with regulated amplitude is
lead to amplitude control stage. The discharge ex-
ponential is replaced by V
level, which, under
VOB
control of the CONTROLLER, creates a rapid fall-
ing edge and a flat part before beginning of new
ramp.
across the capacitor drops below V
threshold.
The discharging starts either when itVeOxBceeds V
threshold (free run mode) or a short time afterVaOrT-
rival of synchronization pulse. This time is neces-
sary for the AGC loop to sample the voltage at the
top of the sawtooth. The VVOB reference is routed
out onto VOscF pin in order to allow for further filtra-
tion.
The AGC output signal passes through gain and
position adjustment stages controlled through
VSIZE and VPOS I²C-bus registers. The resulting
signal serves as input to all geometry correction
circuitry including EW-drive signal, horizontal
phase modulation and dynamic correction outputs.
9.4.2 S and C corrections
The charging current influences amplitude of the
sawtooth. Just before the discharge, the voltage
across the capacitor on pin VCap is sampled and
compared to VVOTref. The comparison error voltage
is stored on a storage capacitor connected on pin
VAGCCap. This voltage tunes gain of the transcon-
ductance amplifier providing the charging current
in the next vertical period. Speed of this AGC loop
depends on the storage capacitance on pin
VAGCCap. The VLock I²C-bus flag is set to 1 when
the loop is stabilized, i.e. when the tops of saw
For the sake of vertical picture linearity, the S- and
C-corrections are now superimposed on the linear
ramp signal. They both track with VSIZE and
VPOS adjustments to ensure unchanged linearity
on the screen at changes of vertical size or vertical
position. As these corrections are not included in
the AGC loop, their adjustment via CCOR and
SCOR I²C-bus registers, controlling shape of verti-
cal output sawtooth affects by principle its peak-to-
peak amplitude. However, this stage is conceived
in a way that the amplitude be independent of
these adjustments if VSIZE and VPOS registers
are set to their medium values.
tooth on pin VCap match V
value. On the
VOT
screen, this corresponds to stabilized vertical size
of picture. After a change of frequency on the
sync. input, the stabilization time depends on the
frequency difference and on the capacitor value.
The lower its value, the shorter the stabilization
time, but on the other hand, the lower the loop sta-
bility. A practical compromise is a capacitance of
470nF. The leakage current of this capacitor re-
sults in difference in amplitude between low and
high frequencies. The higher its parallel resistance
9.4.3 Vertical breathing compensation
The signal provided with the linearity corrections is
amplitude affected in a gain control stage, ruled by
the voltage on VEHTIn input and its I²C-bus control
VEHTG.
9.4.4 Vertical after-gain and offset control
Another gain control is applied via VSAG I²C-bus
register. Then an offset is added, its amount corre-
sponding to VPOF I²C-bus register value. These
two controls result in size and position changes
with no effect on shape of output vertical sawtooth
or any geometry correction signal.
R
L(VAGCCap), the lower this difference.
When the synchronization pulse is not present, the
charging current is fixed. As a consequence, the
free-running frequency fVO(0) only depends on the
value of the capacitor on pin VCap. It can be rough-
ly calculated using the following formula
37/56
STV6889
9.4.5 Vertical moiré
9.4.6 Biasing of vertical booster
To blur potential moiré patterns due to interaction
of deflection lines with CRT mask grid, the picture
position is to be slightly alternated at frame fre-
quency. For this purpose, a square waveform at
half-frame frequency is superimposed on the out-
put waveform. Its amplitude is adjustable through
VMOIRE I²C-bus control.
The biasing voltage for external DC-coupled verti-
cal power amplifier is to be derived from VRefO volt-
age provided on pin RefOut, using a resistor divid-
er, this to ensure the same temperature drift of
mean (DC) levels on both differential inputs and to
compensate for spread of V
value (and so
mean output value) between pRaerftOicular devices.
Figure 12. Vertical section block diagram
Trans-conductance amplifier
Charge current
V
VOTref
OSC
VCap
22
Cap.
Sampling
20
VAGCCap
Discharge
Q1
Sampling
Capacitance
VSyn
Synchro
Polarity
2
Controller
R
V
V
midref
midref
To geometry processing
R
sawtooth
discharge
Internal
V-ramp
V
midref
V
VOB
(I²C)
(I²C)
VSIZE
VPOS
19
VOscF
VEHTIn
18
V
VEHTnull
VEHTG (I²C)
(
)
SCOR I²C
VMOIRE (I²C)
S-correction
VOut
23
VPOF (I²C)
VSAG (I²C)
(
)
CCOR I²C
(I²C)
VPOS
C-correction
38/56
STV6889
9.5 EW drive section
The goal of the EW drive section is to provide, on
pin EWOut, a waveform which, used by an external
DC-coupled power stage, serves to compensate
for those geometry errors of the picture that are
symmetric versus vertical axis across the middle
of the screen.
rections, by prescale adjustments (VSAG and
VPOF), by vertical breathing compensation and by
vertical moire cancellation. The sum of compo-
nents other than DC is conditionally affected by
value in HSIZE I²C-bus control in reversed sense.
Refer to electrical specifications for value. This
tracking with HSIZE can be switched off by
EWTrHSize I²C-bus bit. The DC value, adjusted
via HSIZE control, is also affected by voltage on
HEHTIn input, thus providing a horizontal breathing
compensation. The effect of this compensation is
controlled by HEHTG. The resulting waveform is
conditionally multiplied with voltage on HPLL1F,
which depends on frequency. Refer to electrical
specifications for values. This tracking with fre-
quency provides a rough compensation of varia-
tion of picture geometry with frequency and allows
to fix the adjustment ranges of I²C-bus controls
throughout the operating range of horizontal fre-
quencies. It can be switched off by EWTrHFr I²C-
bus bit (off by default). The functionality is ex-
plained in Figure 13. The upper part gives the influ-
ence on DC component, the lower part on AC
component, showing also the tracking with HSIZE.
Grey zones give the total span of breathing correc-
tion using the whole range of input operating volt-
age on HEHTIn input and whole range of adjust-
ment of HEHTG register.
The waveform consists of an adjustable DC value,
corresponding to horizontal size, a parabola of 2nd
order for “pin cushion” correction, a linear for “key-
stone” correction, independent half-parabolas of
4th order for top and bottom corner corrections, S-
shape for “S” correction and W shape for “W” cor-
rection. All of them are adjustable via I²C-bus, see
Chapter 8 - page 25.
Refer to Figure 14, Figure 15 and chapter Chapter 7 -
page 21. The adjustments of these correction
waveforms have no effect in the middle of the ver-
tical scan period (if the VPOS control is adjusted to
its medium value). As they are summed, the re-
sulting waveform tends to reach its maximum span
at top and bottom of the picture. The voltage at the
EWOut is top and bottom limited (see parameter
V
EW). According to Figure 15, especially the bottom
limitation seems to be critical for maximum hori-
zontal size (minimum DC). Actually it is not critical
since the parabola component must always be ap-
plied to obtain a picture without pin cushion distor-
tion. As all the components of the resulting correc-
tion waveform are generated from an internal line-
ar vertical sawtooth waveform bearing VSIZE and
VPOS adjustments, they all track with vertical am-
plitude and position, thus being fixed vertically on
the screen. They are not affected by C- and S-cor-
The EW waveform signal is buffered by an NPN
emitter follower, the emitter of which is directly
routed to EWOut output. It is internally biased (see
electrical specifications for current value).
39/56
STV6889
Figure 13. Tracking of EWOut signal with frequency
HSIZE=max
breathing
breathing
breathing
breathing
HSIZE=min
HSIZE=min
V
V
EW-base
EW-base
min
min
EWTrHFr=0
EWTrHFr=1
min
V
min
V
HOThrfr
max
max
HOThrfr
V
V
HO
HO
breathing
HSIZE=min
HSIZE=max
breathing
breathing
breathing
x
a
m
=
E
Z
I
S
H
EWTrHSize=1
EWTrHFr=0
EWTrHSize=1
EWTrHFr=1
0
0
min
V
min
V
HOThrfr
max
max
HOThrfr
V
V
HO
HO
40/56
STV6889
Figure 14. Geometric corrections’ schematic diagram
V
VDC-AMP
VDyCorPol
-1
V
VD-DC
midref
VDyCor
32
2
4
X
H-size control
X
Int. V-ramp
(linear, before
corrections)
DC
0...2.5V
HSIZE
Breathing
KEYST
PCC
Keystone
Pin cushion
Top corner
Bot. corner
“W”
HEHTG
tracking
V
HEHTnull
17
TCC
HEHTIn
V
(max)
EW
BCC
0V
EWOut
24
EWWC
EWSC
0V
V
V
(min)
EW-base
EW
“S”
3
X
1
0
Tracking
with hor.
frequency
9
HPLL1F
PARAL
PCAC
TCAC
BCAC
0V
Parallelogram
EWTrHFr
V
HOThrfr
Pin cushion
asymmetry
To HPLL2
Controls:
Top corner
asymmetry
1-quadrant
Internal dynamic
phase waveform
2-quadrant
Bottom corner
asymmetry
41/56
STV6889
Figure 15. EWOut output waveforms
max
Tracking with frequency off. (EWTrHFr = 0)
HEHTG (I²C)
V
EW-Key
V
00h
V
EW-TCor
V
EW-PCC
V
EW-S
EW-W
max.
mid.
min.
V
EW-BCor
7Fh
00h
7Fh
00h
min
7Fh
Breathing
compensation
on DC
Top
Bottom
Corners
alone
Keystone
alone
PCC
alone
S alone
W alone
0
VHEHT
Vertical sawtooth
t
VR
0
T
0
T
0
T
0
T
VR
0
TVR
VR
VR
VR
42/56
STV6889
9.6 Dynamic correction outputs section
9.6.1 Vertical dynamic correction output
and S-corrections or breathing compensation. It
does not track with Vertical size after-gain
(Sad1Dh) nor with Vertical position offset
(Sad1Eh) adjustments.
VDyCor
A parabola at vertical deflection frequency is avail-
able on pin VDyCor. Its amplitude is adjustable via
VDC-AMP I²C-bus control and polarity controlled
via VDyCorPol I²C-bus bit. It tracks with real verti-
cal amplitude and position. It is not affected by C-
The use of both correction waveforms is up to the
application (e.g. dynamic focus, dynamic bright-
ness control).
9.7 DC/DC controller section
The section is designed to control a switch-mode
DC/DC converter. A switch-mode DC/DC conver-
tor generates a DC voltage from a DC voltage of
different value (higher or lower) with little power
losses. The DC/DC controller is synchronized to
horizontal deflection frequency to minimize poten-
tial interference into the picture.
BOut. Refer to Figure 10. Another condition for reset
of the R-S flip-flop, OR-ed with the one described
before, is that the voltage on pin BISense exceeds
the voltage VC2, which depends on the voltage ap-
plied on input BRegIn of the error amplifier O1. The
two voltages are compared, and the reset signal
generated by the comparator C1. The error ampli-
fier amplifies (with a factor defined by external
components) the difference between the input
voltage proportional to DC/DC convertor output
voltage and internal reference VBReg. The internal
reference and so the output voltage is I²C-bus ad-
justable by means of BREF I²C-bus control.
Its operation is similar to that of standard UC3842.
The schematic diagram of the DC/DC controller is
in Figure 16. The BOut output controls an external
switching circuit (a MOS transistor) delivering
pulses synchronized on horizontal deflection fre-
quency, the phase of which depends on H/W and
I²C-bus configuration. See the table at the end of
this chapter. Their duration depends on the feed-
back provided to the circuit, generally a copy of
DC/DC converter output voltage and a copy of cur-
rent passing through the DC/DC converter circuitry
(e.g. current through external power component).
The polarity of the output can be controlled by
BOutPol I²C-bus bit. A NPN transistor open-collec-
tor is routed out to the BOut pin.
Both step-up (DC/DC converter output voltage
higher than its input voltage) and step-down (out-
put voltage lower than input) can be built.
9.7.1 Synchronization of DC/DC controller
For sake of application flexibility, the output drive
signal on BOut pin can be synchronized with one of
four events in Table 9. For the first line case, the
synchronization instant is every second top of hor-
izontal VCO saw tooth. See Figure 7.
During the operation, a sawtooth is to be found on
pin BISense, generated externally by the applica-
tion. According to BOutPh I²C-bus bit, the R-S flip-
flop is set either at H-drive signal edge (rising or
falling, depending on BOHEdge I²C-bus bit), or a
certain delay (tBTrigDel) after middle of H-flyback, or
at horizontal frequency divided by two (phase cor-
responding to VHOThrHi on the VCO ramp). The out-
put is set On at the end of the short pulse generat-
ed by the monostable trigger.
9.7.2 Soft-start and soft-stop on B-drive
The soft-start and soft-stop procedure is carried
out at each switch-on or switch-off of the B-drive
signal, either via HBOutEn I²C-bus bit or after re-
set of XRayAlarm I²C-bus flag, to protect external
power component. See Figure 10 and sub chapter
Safety functions on page 45.
The drive signal on BOut pin can be switched off
alone by means of BMute I²C-bus bit, without
switching off the drive signal on pin HOut. The
switch-off is quasi-immediate, without the soft-stop
procedure. At switching back on, the soft-start of
the DC/DC controller is performed, timed by an in-
ternal timing circuit, see Figure 16.
Timing of reset of the R-S flip-flop affects duty cy-
cle of the output square signal and so the energy
transferred from DC/DC converter input to its out-
put. A reset edge is provided by comparator C2 if
the voltage on pin BISense exceeds the internal
threshold VThrBIsCurr. This represents current limita-
tion if a voltage proportional to the current through
the power component or deflection stage is availa-
ble on pin BISense. This threshold is affected by
voltage on pin HPosF, which rises at soft start and
descends at soft stop. This ensures self-contained
soft control of duty cycle of the output signal on pin
When BSafeEn I²C-bus bit is enabled, the drive
signal on BOut pin will go off as soon as the hori-
zontal PLL1 indicates unlocked state, without the
soft-stop. Resuming of locked state will initiate the
soft-start mechanism of the DC/DC controller,
timed by an internal timing circuit.
43/56
STV6889
Table 9. IDC/DC controller Off-to-On edge timing
BOutPh
(Sad07h/D7)
BOHEdge
(Sad17h/D3)
Timing of Off-to-On transition on BOut output
0
0
1
1
1
0
0
1
VCO ramp top at Horizontal frequency divided by two
Middle of H-flyback plus t
BTrigDel
Falling edge of H-drive signal
Rising edge of H-drive signal
Figure 16. DC/DC converter controller block diagram
BOutPh
(I²C)
0
1
H-drive edge
1
0
Monostable
~500ns
BOHEdge
(I²C)
H-fly-back
I1
V
(+delay)
CC
0
1
VCO
I2
T2
N type
V
BReg
28
BOut
Feedback
+
V
C2
2R
R
-
O1
S
-
C1
15
BRegIn
Q
+
I3
P type
R
BOutPol
(I²C)
-
14
BComp
V
C2
+
B-drive inhibition
(safety functions)
ThrBIsCurr
+
C3
-
Safety block
Soft start
10
HPosF
B-drive protection at H-unlock
(safety functions)
timing
16
BISense
44/56
STV6889
9.8 Miscellaneous
9.8.1 Safety functions
The soft stop at power down condition can be con-
sidered as a special case. As at this condition the
The safety functions comprise supply voltage
monitoring with appropriate actions, soft start and
soft stop features on H-drive and B-drive signals
on HOut and BOut outputs, B-drive cut-off at unlock
condition and X-ray protection.
thresholds VHOn, V
momentary level oBfOsnupply vHoBltNaogrme (marked VHOn’,
BOn’, VHBNorm’ in Figure 11), the timing of soft stop
and V
depend on the
V
mechanism depends, apart from the capacitance
on HPosF, also on the falling speed of supply volt-
age. The device is capable of performing a correct
soft stop sequence providing that, at the moment
the supply voltage reaches VCCStop, the voltage on
HPosF has already fallen below VHOn (Section 9.8).
For supply voltage supervision, refer to subsection
9.1.1 and Figure 1. A schematic diagram putting to-
gether all safety functions and composite PLL1
lock and V-blanking indication is in Figure 17.
9.8.1.1 Soft s tart and s oft s top function
9.8.1.2 B-drive cut-off at unlock condition
This function is described in subsection 9.7.2 .
9.8.1.3 X-ray protection
For soft start and soft stop features for H-drive and
B-drive signal, refer to subsection 9.3.7 and subsec-
tion 9.7 , respectively. See also the Figure 10 and
Figure 11. Regardless why the H-drive or B-drive
signal are switched on or off (I²C-bus command,
power up or down, X-ray protection), the signals
always phase-in and phase-out in the way drawn
in the figures, the first to phase-in and last to
phase-out being the H-drive signal, which is to bet-
ter protect the power stages at abrupt changes like
switch-on and off. The timing of phase-in and
phase-out depends on the capacitance connected
to HPosF pin which is virtually unlimited for this
function. However, as it has a dual function (see
subsection 9.3.2 ), a compromise thereof is to be
found.
The X-ray protection is activated if the voltage lev-
el on XRay input exceeds VThrXRay threshold and if
the VCC is higher than the voltage level V
.
CCXRayEn
As a consequence, the H-drive and B-drive signals
on HOut and BOut outputs are inhibited (switched
off) after a 2-horizontal deflection line delay provid-
ed to avoid erratic excessive X-ray condition de-
tection at short parasitic spikes. The XRayAlarm
I²C-bus flag is set to 1 to inform the MCU.
This protection is latched; it may be reset either by
V
CC drop or by I²C-bus bit XRayReset
(see Chapter 8 - page 25).
45/56
STV6889
Figure 17. Safety functions - block diagram
BSafeEn
I²C
B-drive protection at H-unlock
HPosF
BMute
I²C
H-lock detector
0 = Off
1 = On
= start
= stop
10
HBOutEn
I²C
(timing)
PLL1
PLL2
DC/DC
V
supervision
SOFT
START & STOP
INHIBITION
CONTROL
CC
V
CC
+
_
V
V
CCEn
CCDis
H-VCO
discharge
control
XRayAlarm
I²C
XRayReset
I²C
R
S
Q
:2
In
Out
XRay
25
+
_
Enable
B-drive inhibit
H-drive inhibit
V
ThrXRay
H-drive inhibition
(overrule)
V
CC
+
_
V
CCXRayEn
HFly
12
V-drive inhibition
B-drive inhibition
+
_
V
ThrHFly
VOutEn
I²C
BlankMode
I²C
HLockEn
I²C
HLckVBk
L1=No blank/blank level
L2=H-lock/unlock level
3
ꢀ
L3=L1+L2
H-lock detector
HLock
I²C
R
Q
V-sawtooth
discharge
S
V-sync
Int. signal
X
Pin
I²C I²C bit/flag
46/56
STV6889
9.8.2 Composite output HLckVBk
the leading edge of any of the two signals, which-
ever comes first. The blanking pulse is ended with
the trailing edge of vertical oscillator discharge
pulse. The device has no information about the
vertical retrace time. Therefore, it does not cover,
by the blanking pulse, the whole vertical retrace
period. By means of BlankMode I²C-bus bit, when
at 1 (default), the blanking level (one of two ac-
cording to PLL1 status) is made available on the
HLckVBk permanently. The permanent blanking, ir-
respective of the BlankMode I²C-bus bit, is also
The composite output HLckVBk provides, at the
same time, information about lock state of PLL1
and early vertical blanking pulse. As both signals
have two logical levels, a four level signal is used
to define the combination of the two. Schematic di-
agram putting together all safety functions and
composite PLL1 lock and V-blanking indication is
in Figure 17, the combinations, their respective lev-
els and the HLckVBk configuration in Figure 18.
The early vertical blanking pulse is obtained by a
logic combination of vertical synchronization pulse
and pulse corresponding to vertical oscillator dis-
charge. The combination corresponds to the draw-
ing in Figure 18. The blanking pulse is started with
provided if the supply voltage is low (under V
CCEn
or VCCDis thresholds), if the X-ray protection is ac-
tive or if the V-drive signal is disabled by VOutEn
I²C-bus bit.
Figure 18. Levels on HLckVBk composite output
L1 - No blank/blank level
L2 - H-lock/unlock level
V
CC
L1 +L2
(H)
(H)
3
HLckVBk
L1 +L2
(L)
(H)
I
SinkLckBk
V
L1 +L2
OLckBk
(H)
(L)
L1 +L2
(L)
(L)
V-early blanking
HPLL1 locked
No
Yes
Yes
Yes
No
No
Yes
No
47/56
STV6889
Figure 19. Ground layout recommendations
STV6889
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
General Ground
6
7
8
9
10
11
12
13
14
15
16
48/56
STV6889
49/56
STV6889
10 INTERNAL SCHEMATICS
Figure 20.
Figure 23.
V
CC
V
RefO
5V
5
HPLL2C
H/HVSyn
1
200ꢀ
Applies also for pin 2 (VSyn)
Figure 21.
Figure 24.
V
CC
V
CC
V
RefO
V
RefO
CO
6
HLckVBk
3
Figure 22.
Figure 25.
V
CC
V
RefO
12V
V
RefO
RO
8
HOscF
4
50/56
3
STV6889
Figure 26.
Figure 29.
V
CC
HPLL1F
9
BComp
14
Figure 27.
Figure 30.
V
RefO
12V
V
CC
HPosF
BRegIn
15
10
Figure 28.
Figure 31.
V
CC
V
CC
BISense
16
HFly
12
51/56
3
STV6889
Figure 32.
Figure 35.
V
CC
22
V
CC
VCap
HEHTIn
17
Applies also for pin 18 (VEHTIn)
Figure 33.
Figure 36.
V
V
RefO
CC
V
CC
VOut
23
VOscF
19
Figure 34.
Figure 37.
V
CC
V
CC
EWOut 24
VAGCCap
20
Applies also for pin 32 (VDyCor)
52/56
3
STV6889
Figure 38.
V
CC
XRay 25
Figure 39.
V
CC
HOut 26
Applies also for pin 28 (BOut)
Figure 40.
V
CC
SCL 30
Applies also for pin 31 (SDA)
53/56
3
STV6889
11 PACKAGE MECHANICAL DATA
32 PINS - PLASTIC SHRINK
E
E1
C
Stand-off
e
B
B1
eA
eB
D
32
1
17
16
Millimeters
Dimensions
Inches
Typ.
Min.
3.556
0.508
3.048
0.356
0.762
.203
Typ.
Max.
Min.
0.140
0.020
0.120
0.014
0.030
0.008
1.080
0.390
0.300
Max.
A
A1
A2
B
3.759
5.080
0.148
0.200
3.556
0.457
1.016
0.254
27.94
10.41
8.890
1.778
10.16
4.572
0.584
1.397
0.356
28.45
11.05
9.398
0.140
0.018
0.040
0.010
1.100
0.410
0.350
0.070
0.400
0.180
0.023
0.055
0.014
1.120
0.435
0.370
B1
C
D
27.43
9.906
7.620
E
E1
e
eA
eB
L
12.70
3.810
0.500
0.150
2.540
3.048
0.100
0.120
54/56
4
STV6889
12 GLOSSARY
AC
Alternate Current
ACK
AGC
COMP
CRT
DC
ACKnowledge bit of I²C-bus transfer
Automatic Gain Control
COMParator
Cathode Ray Tube
Direct Current
EHT
EW
Extra High Voltage
East-West
H/W
HOT
I2C
HardWare
Horizontal Output Transistor
Inter-Integrated Circuit
Inter-Integrated Circuit
Micro-Controller Unit
Negated AND (logic operation)
Negative-Positive-Negative
OSCillator
IIC
MCU
NAND
NPN
OSC
PLL
PNP
REF
RS, R-S
S/W
TTL
Phase-Locked Loop
Positive-Negative-Positive
REFerence
Reset-Set
SoftWare
Transistor Transistor Logic
Voltage-Controlled Oscillator
VCO
55/56
5
STV6889
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for
the consequences of use of such information nor for any infringement of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of
STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication
supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as
critical components in life support devices or systems without express written approval of STMicroelectronics.
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All other names are the property of their respective owners
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56/56
6
相关型号：
STV7619
DC PLASMA DISPLAY DRIVER, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
STMICROELECTR
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