BQ4845YSN_技术文档

bq4845/bq4845Y

Parallel RTC With CPU Supervisor

tects an out-of-tolerance condition, it

generates an interrupt warning and

General Description

Features

➤ Real-Time Clock counts seconds

The bq4845 Real-Time Clock is a

low-power microprocessor periph-

eral that integrates a time-of-day

clock, a 100-year calendar, and a

CPU supervisor in a 28-pin SOIC or

DIP. The bq4845 is ideal for fax ma-

chines, copiers, industrial control

syst em s, poin t -of-sa le t er m in a ls,

data loggers, and computers.

subsequently a microprocessor reset.

The reset stays active for 200ms after

V_CCrises within tolerance, to allow for

power supply and processor stabiliza-

tion.

through years in BCD format

➤ On-chip battery-backup switchover

circuit with nonvolatile control for

external SRAM

Th e bq4845 a ls o h a s a bu ilt -in

watchdog timer to monitor processor

operation. If the microprocessor does

not toggle the watchdog input (WDI)

within the programmed time-out pe-

riod, the bq4845 asserts WDO and

RST. WDI unconnected disables the

watchdog timer.

➤ Less than 500nA of clock opera-

tion current in backup mode

➤ Microprocessor reset valid to

The bq4845 provides direct connec-

tions for a 32.768KHz quartz crystal

and a 3V backup battery. Through

the use of the conditional chip en-

a ble ou t pu t (CE _OUT) a n d ba t t er y

volt a ge ou t pu t (V_{OU T}) p in s, t h e

bq4845 can write-protect and make

n on vola t ile external SRAMs. The

ba cku p cell powers t he rea l-t im e

clock and maintains SRAM infor-

m a t ion in t h e a bsen ce of syst em

voltage.

V_CC= V_SS

➤ I n d ep en d en t wa t ch d og t im er

with a programmable time-out

period

The bq4845 can generate other in-

terrupts based on a clock alarm con-

dit ion or a per iodic set t in g. Th e

alarm interrupt can be set to occur

from once per second to once per

month. The alarm can be made active

in the battery-backup mode to serve

as a system wake-up call. For inter-

rupts at a rate beyond once per sec-

ond, the periodic interrupt can be pro-

grammed with periods of 30.5µs to

500ms.

➤ Power-fail interrupt warning

➤ Programmable clock alarm inter-

r u pt a ct ive in ba t t er y-ba cku p

mode

➤ Programmable periodic interrupt

➤ Battery-low warning

The bq4845 contains a temperature-

compensated reference and comparator

circuit that monitors the status of its

voltage supply. When the bq4845 de-

Pin Names

Pin Connections

A₀–A₃

Clock/control address

inputs

BC

Backup battery input

Back-up battery output

Interrupt output

Microprocessor reset

Watchdog input

Watchdog output

+5V supply

V

28

1

V

CC

OUT

V_OUT

INT

X

1

X

2

27

26

2

3

WE

CE

DQ₀–DQ₇Data inputs/outputs

IN

4

CE

BC

WDO

INT

RST

25

24

23

22

21

20

19

18

17

16

15

OUT

WE

OE

Write enable

5

6

WDI

OE

RST

WDI

WDO

V_CC

V_SS

Output enable

Chip select input

A

3

7

A

8

9

CS

2

1

0

CS

V

SS

10

11

12

13

14

DQ

7

CE_IN

External RAM chip

enable

DQ

8

DQ

5

0

DQ

1

DQ

2

DQ

4

V

SS

DQ

3

CE_OUT

X1–X2

Conditional RAM chip

enable

Ground

28-DIP or SOIC

PN484501.eps

Crystal inputs

Aug. 1995

1

bq4845/bq4845Y

power-on reset timing, watchdog timer activation, and

interrupt generation.

Functional Description

Figure 1 is a block diagram of the bq4845. The follow-

ing sections describe the bq4845 functional operation

in clu d in g clock in t er fa ce, d a t a -r et en t ion m od es,

Figure 1. Block Diagram

Truth Table

V_CC

CS

V_IH

V_IL

X

OE

X

WE

X

CE_OUT

CE_IN

V_OH

V_OUT

V_OUT1

V_OUT2

Mode

Deselect

Write

DQ

Power

Standby

Active

< V_CC(max.)

High Z

D_IN

X

V_IL

V_IH

X

> V_CC(min.)

V_IL

V_IH

X

Read

D_OUT

High Z

Active

Read

Active

< V_PFD(min.) > V_SO

Deselect

CMOS standby

X

V_OHB

High Z Battery-backup mode

≤ V_SO

Aug. 1995

2

bq4845/bq4845Y

DQ₀–DQ₇Data in pu t an d ou tpu t

Pin Descriptions

DQ₀–DQ₇provide x8 data for real-time clock

information. These pins connect to the mem-

ory data bus.

Cr ystal in pu ts

X1–X2

X1–X2 are

a

direct connection for

a

32.768kHZ, 6pF crystal.

Gr ou n d

V_SS

CS

Reset ou tpu t

RST

Ch ip select

Ou tpu t en able

RST goes low whenever V_CCfalls below the

power fail threshold. RST will remain low for

200ms typical after V_CCcrosses the threshold

on power-up. RST also goes low whenever a

watchdog timeout occurs. RST is an open-

drain output.

OE

OE pr ovides t h e r ea d con t r ol for t h e RTC

m em or y loca t ion s.

Ch ip en able ou tpu t

CE_OUT

INT

In ter r u pt ou tpu t

CE_OUTgoes low only when CE_INis low and

V_CCis above the power fail threshold. If

CE_INis low, and power fail occurs, CE_OUT

stays low for 100µs or until CE_INgoes high,

whichever occurs first.

INT goes low when a power fail, periodic, or

alarm condition occurs. INT is an open-drain

output.

Watch dog in pu t

WDI

Ch ip en able in pu t

CE_IN

WDI is a three-level input. If WDI remains

either high or low for longer than the

watchdog time-out period (1.5 seconds de-

fault), WDO goes low. WDO remains low

until the next transition at WDI. Leaving

WDI unconnected disables the watchdog

function. WDI connects to an internal volt-

age divider between V_OUTand V_SS, which

sets it to mid-supply when left uncon-

nected.

CE_INis the input to the chip-enable gating

circuit.

Backu p batter y in pu t

BC

BC should be connected to a 3V backup

cell. A voltage within the V_BCrange on the

BC pin should be present upon power up to

provide proper oscillator start-up.

Ou tpu t su pply voltage

V_OUT

Watch dog ou tpu t

WDO

V_OUTprovides the higher of V_CCor V_BC

,

WDO goes low if WDI remains either high

or low longer than the watchdog time-out

period. WDO returns high on the next tran-

sition at WDI. WDO remains high if WDI is

unconnected.

switched internally, to supply external

RAM.

Wr ite en able

WE

WE provides the write control for the RTC

memory locations.

Clock addr ess in pu ts

A₀–A₃

In pu t su pply voltage

V_CC

A₀–A₃allow access to the 16 bytes of real-

time clock and control registers.

+5V input

Aug. 1995

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bq4845/bq4845Y

Read Mode

Address Map

The bq4845 is in read mode whenever OE (Output en-

able) is low and CS (chip select) is low. The unique ad-

dress, specified by the 4 address inputs, defines which

one of the 16 clock/calendar bytes is to be accessed. The

bq4845 makes valid data available at the data I/O pins

within t_AA(address access time). This occurs after the

last address input signal is stable, and providing the CS

and OE (output enable) access times are met. If the CS

and OE access times are not met, valid data is available

after the latter of chip select access time (t_ACS) or output

enable access time (t_OE).

The bq4845 provides 16 bytes of clock and control status

registers. Table 1 is a map of the bq4845 registers, and

Table 2 describes the register bits.

Clock Memory Interface

The bq4845 has the same interface for clock/calendar

and control information as standard SRAM. To read and

write to these locations, the user must put the bq4845 in

the proper mode and meet the timing requirements.

CS and OE control the state of the eight three-state

data I/O signals. If the outputs are activated before t_AA

,

Table 1. bq4845 Clock and Control Register Map

Ad-

dress

(h)

12-Hour

Range (h)

D7

D6

10-second digit

ALM0

D5

D4

D3

D2

D1

D0

Register

Seconds

0

1

2

3

4

5

0

1-second digit

1-minute digit

1-hour digit

00–59

ALM1

0

00–59

Seconds alarm

Minutes

10-second digit

10-minute digit

ALM0

10-minute digit

ALM1

Minutes alarm

PM/AM

ALM1

PM/AM

0

ALM0

0

10-hour digit

01–12 AM/ 81– 92 PM Hours

10-hour digit

1-hour digit

01–12 AM/ 81–92 PM Hours alarm

6

7

10-day digit

0

1-day digit

01–31

01–07

01–12

00–99

Day

ALM1 ALM0

0

Day alarm

Day-of-week

Month

8

0

Day-of-week digit

1-month digit

1-year digit

9

0

10 mo.

A

10-year digit

Year

Programmable

rates

B

C

*

WD2

WD1

*

WD0

RS3

AIE

RS2

PIE

RS1

RS0

PWRIE ABE

Interrupt en-

ables

D

E

F

*

AF

PF

PWRF BVF

24/12 DSE

Flags

UTI STOP

Control

Unused

*

Notes:

* = Unused bits; unwritable and read as 0.

0 = should be set to 0 for valid time/calendar range.

Clock calendar data in BCD. Automatic leap year adjustment.

PM/AM = 1 for PM; PM/AM = 0 for AM.

DSE = 1 enables daylight savings adjustment.

24/12 = 1 enables 24-hour data representation; 24/12 = 0 enables 12-hour data representation.

Day-of-Week coded as Sunday = 1 through Saturday = 7.

BVF = 1 for valid battery.

STOP = 1 turns the RTC on; STOP = 0 stops the RTC in back-up mode.

Aug. 1995

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bq4845/bq4845Y

Reading the Clock

Table 2. Clock and Control Register Bits

Once every second, the user-accessible clock/calendar lo-

cations are updated simultaneously from the internal

real time counters. To prevent reading data in transi-

tion, updates to the bq4845 clock registers should be

halted. Updating is halted by setting the update trans-

fer inhibit (UTI) bit D3 of the control register E. As long

as the UTI bit is 1, updates to user-accessible clock loca-

tions are inhibited. Once the frozen clock information is

retrieved by reading the appropriate clock memory loca-

tions, the UTI bit should be reset to 0 in order to allow

updates to occur from the internal counters. Because

the internal counters are not halted by setting the UTI

bit, reading the clock locations has no effect on clock ac-

curacy. Once the UTI bit is reset to 0, the internal regis-

ters update within one second the user-accessible regis-

ters with the correct time. A halt command issued dur-

ing a clock update allows the update to occur before

freezing the data.

Bits

Description

24- or 12-hour representation

24/12

ABE

Alarm interrupt enable in

battery-backup mode

AF

Alarm interrupt flag

AIE

Alarm interrupt enable

ALM0–ALM1 Alarm mask bits

BVF

Battery-valid flag

DSE

Daylight savings time enable

Periodic interrupt flag

Periodic interrupt enable

PM or AM indication

PF

PIE

PM/AM

PWRF

PWRIE

RS0–RS3

STOP

UTI

Setting the Clock

Power-fail interrupt flag

Power-fail interrupt enable

Periodic interrupt rate

Oscillator stop and start

Update transfer inhibit

Watchdog time-out rate

The UTI bit must also be used to set the bq4845 clock.

Once set, the locations can be written with the desired

information in BCD format. Resetting the UTI bit to 0

causes the written values to be transferred to the inter-

nal clock counters and allows updates to the user-

accessible registers to resume within one second.

Stopping and Starting the Clock Oscillator

WD0 - WD2

The bq4845 clock can be programmed to turn off when

the part goes into battery back-up mode by setting

STOP to 0 prior to power down. If the board using the

bq4845 is to spend a significant period of time in stor-

age, the STOP bit can be used to preserve some battery

capacity. STOP set to 1 keeps the clock running when

V_CCdrops below V_SO. With V_CCgreater than V_SO, the

bq4845 clock runs regardless of the state of STOP.

the data lines are driven to an indeterminate state until

t_AA. If the address inputs are changed while CS and OE

remain low, output data remains valid for t_OH(output

data hold time), but goes indeterminate until the next

address access.

Write Mode

The bq4845 is in write mode whenever WE and CS are

active. The start of a write is referenced from the

latter-occurring falling edge of WE or CS. A write is ter-

minated by the earlier rising edge of WE or CS. The ad-

dresses must be held valid throughout the cycle. CS or

WE must return high for a minimum of t_WR2from CS or

t_WR1from WE prior to the initiation of another read or

write cycle.

Power-Down/Power-Up Cycle

Th e bq4845 con t in u ou sly m on it or s V_CCfor ou t -of-

tolerance. During a power failure, when V_CCfalls below

V_PFD, the bq4845 write-protects the clock and storage

registers. When V_CCis below V_BC(3V typical), the

power source is switched to BC. RTC operation and

storage data are sustained by a valid backup energy

source. When V_CCis above V_BC, the power source is

V_CC. Write-protection continues for t_CSRtime after V_CC

Data-in must be valid t_DWprior to the end of write and

remain valid for t_DH1or t_DH2afterward. OE should be

kept high during write cycles to avoid bus contention; al-

though, if the output bus has been activated by a low on

CS and OE, a low on WE disables the outputs t_WZafter

WE falls.

rises above V_PFD

.

An external CMOS static RAM is battery-backed using

the V_OUTand chip enable output pins from the bq4845.

As the voltage input V_CCslews down during a power

failure, the chip enable output, CE_OUT,is forced inactive

independent of the chip enable input CE_IN.

Aug. 1995

5

bq4845/bq4845Y

This activity unconditionally write-protects the external

SRAM as V_CCfalls below V_PFD. If a memory access is in

progress to the external SRAM during power-fail detec-

tion, that memory cycle continues to completion before

the memory is write-protected. If the memory cycle is

not terminated within time t_WPT, the chip enable output

is unconditionally driven high, write-protecting the con-

trolled SRAM.

A primary backup energy source input is provided on

the bq4845. The BC input accepts a 3V primary battery,

typically some type of lithium chemistry. Since the

bq4845 provides for reverse battery charging protection,

no diode or current limiting resistor is needed in series

with the cell. To prevent battery drain when there is no

valid data to retain, V_OUTand CE_OUTare internally iso-

lated from BC by the initial connection of a battery. Fol-

lowing the first application of V_CCabove V_PFD, this iso-

lation is broken, and the backup cell provides power to

V_OUTand CE_OUTfor the external SRAM.

As the supply continues to fall past V_PFD, an internal

switching device forces V_OUTto the external backup en-

ergy source. CE_OUTis held high by the V_OUTenergy

source.

The crystal should be located as close to X1 and X2 as

possible and meet the specifications in the Crystal

Specifica t ion Ta ble. Wit h t h e specified cr yst a l, t h e

bq4845 RTC will be accurate to within one minute per

month at room temperature. In the absence of a crystal,

a 32.768 kHz waveform can be fed into X1 with X2

grounded.

During power-up, V_OUTis switched back to the 5V sup-

ply as V_CCrises above the backup cell input voltage

sourcing V_OUT. CE_OUTis held inactive for time t_CERaf-

ter the power supply has reached V_PFD, independent of

the CE_INinput, to allow for processor stabilization.

During power-valid operation, the CE_INinput is passed

through to the CE_OUToutput with a propagation delay of

less than 12ns.

Power-On Reset

The bq4845 provides a power-on reset, which pulls the

RST pin low on power-down and remains low on power-

up for t_RSTafter V_CCpasses V_PFD.With valid battery

Figure 2 shows the hardware hookup for the external

RAM, battery, and crystal.

voltage on BC, RST remains valid for V_CC= V_SS

.

Figure 2. bq4845 Application Circuit

Aug. 1995

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bq4845/bq4845Y

at WDI) biases WDI to approximately 1.6V. Internal

comparators detect this level and disable the watchdog

timer. When V_CCis below the power-fail threshold, the

bq4845 disables the watchdog function and disconnects

WDI from its internal resistor network, thus making it

high impedance.

Watchdog Timer

The watchdog monitors microprocessor activity through

the Watchdog input (WDI). To use the watchdog func-

tion, connect WDI to a bus line or a microprocessor I/O

line. If WDI remains high or low for longer than the

watchdog time-out period (1.5 seconds default), the

bq4845 asserts WDO and RST.

Watchdog Output

The Watchdog output (WDO) remains high if there is a

transition or pulse at WDI during the watchdog time-

out period. The bq4845 disables the watchdog function

and WDO is a logic high when V_CCis below the power

fail threshold, battery-backup mode is enabled, or WDI

is an open circuit. In watchdog mode, if no transition oc-

curs at WDI during the watchdog time-out period, the

bq4845 asserts RST for the reset time-out period t₁.

WDO goes low and remains low until the next transition

at WDI. If WDI is held high or low indefinitely, RST will

generate pulses (t₁seconds wide) every t₃seconds. Fig-

ure 3 shows the watchdog timing.

Watchdog Input

The bq4845 resets the watchdog timer if a change of

state (high to low, low to high, or a minimum 100ns

pulse) occurs at the Watchdog input (WDI) during the

watchdog period. The watchdog time-out is set by WD0-

WD2 in register B. The bq4845 maintains the watchdog

time-out programming through power cycles. The de-

fault state (no valid battery power) of WD0-WD2 is 000

or 1.5s on power-up. Table 3 shows the programmable

watchdog time-out rates. The watchdog time-out period

immediately after a reset is equal to the programmed

watchdog time-out.

To disable the watchdog function, leave WDI floating. An

internal resistor network (100kΩ equivalent impedance

Figure 3. Watchdog Time-out Period and Reset Active Time

Aug. 1995

7

bq4845/bq4845Y

ters with the corresponding alarm registers. If a match

between all the corresponding bytes is found, the alarm

flag AF in the flags register is set. If the alarm inter-

rupt is enabled with AIE, an interrupt request is gener-

ated on INT. The alarm condition is cleared by a read to

the flags register. ALM1 – ALM0 in the alarm registers,

m a sk ea ch a la r m com pa r e byt e. An a la r m byt e is

masked by setting ALM1 (D7) and ALM0 (D6) to 1.

Alarm byte masking can be used to select the frequency

of the alarm interrupt, according to Table 5.

Interrupts

The bq4845 allows three individually selected interrupt

events to generate an interrupt request on the INT pin.

These three interrupt events are:

■

The periodic interrupt, programmable to occur once

every 30.5µs to 500ms

The alarm interrupt, programmable to occur once per

second to once per month

The alarm interrupt can be made active while the

bq4845 is in the battery-backup mode by setting ABE in

the interrupts register. Normally, the INT pin goes

high-impedance during battery backup. With ABE set,

however, INT is driven low if an alarm condition occurs

and the AIE bit is set. Because the AIE bit is reset dur-

ing power-on reset, an alarm generated during power-on

reset updates only the flags register. The user can read

the flags register during boot-up to determine if an

alarm was generated during power-on reset.

The power-fail interrupt, which can be enabled to be

asserted when the bq4845 detects a power failure

The periodic, alarm, and power-fail interrupts are en-

abled by an individual interrupt-enable bit in register C,

the interrupts register. When an event occurs, its event

flag bit in the flags register, register D, is set. If the cor-

responding event enable bit is also set, then an interrupt

request is generated. Reading the flags register clears

all flag bits and makes INT high impedance. To reset

the flag register, the bq4845 addresses must be held sta-

ble at register D for at least 50ns to avoid inadvertent

resets.

Power-Fail Interrupt

Wh en V_CCfa lls t o t h e power-fa il-det ect poin t , t h e

power-fail flag PWRF is set. If the power-fail interrupt

enable bit (PWRIE) is also set, then INT is asserted low.

The power-fail interrupt occurs t_WPTbefore the bq4845

generates a reset and deselects. The PWRIE bit is

cleared on power-up.

Periodic Interrupt

Bits RS3–RS0 in the interrupts register program the

rate for the periodic interrupt. The user can interpret

the interrupt in two ways: either by polling the flags

register for PF assertion or by setting PIE so that INT

goes active when the bq4845 sets the periodic flag.

Reading the flags register resets the PF bit and returns

INT to the high-impedance state. Table 4 shows the pe-

riodic rates.

Battery-Low Warning

The bq4845 checks the battery on power-up. When the

battery voltage is approximately 2.1V, the battery-valid

flag BVF in the flags register is set to a 0 indicating that

clock and RAM data may be invalid.

Alarm Interrupt

Registers 1, 3, 5, and 7 program the real-time clock

alarm. During each update cycle, the bq4845 compares

the date, hours, minutes, and seconds in the clock regis-

Table 3. Watchdog Time-out Rates

Normal Watchdog

Time-out Period (t₂, t₃)

Reset Time-out

Period (t₁)

WD2

WD1

WD0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.5s

0.25s

3.9063ms

7.8125ms

15.625ms

31.25ms

62.5ms

125ms

23.4375ms

46.875ms

93.75ms

187.5ms

375ms

750ms

3s

0.5s

Aug. 1995

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bq4845/bq4845Y

Table 4. Periodic Interrupt Rates

Register B Bits

RS2

Periodic Interrupt

RS3

0

RS1

0

RS0

0

Period

None

30.5175

Units

0

1

0

1

0

1

µs

0

1

0

61.035

122.070

244.141

488.281

976.5625

1.95315

3.90625

7.8125

15.625

31.25

0

1

µs

0

µs

0

1

µs

0

1

0

µs

0

1

ms

1

0

1

0

1

0

1

0

62.5

1

0

1

125

1

0

250

1

500

Table 5. Alarm Frequency (Alarm Bits D6 and D7 of Alarm Registers)

1h

3h

5h

7h

ALM1•ALM0

ALM1•ALM0 ALM1•ALM0

Alarm Frequency

1

0

1

0

1

0

1

0

Once per second

Once per minute when seconds match

Once per hour when minutes, and seconds match

Once per day when hours, minutes, and seconds match

When date, hours, minutes, and seconds match

Aug. 1995

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bq4845/bq4845Y

Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

Conditions

V_CC

DC voltage applied on V_CCrelative to V_SS

-0.3 to 7.0

V

DC voltage applied on any pin excluding V_CC

relative to V_SS

V_T

-0.3 to 7.0

V

_T≤ V_CC+ 0.3

0 to +70

-40 to +85

-55 to +125

-40 to +85

+260

°C

Commercial

Industrial

T_OPR

Operating temperature

T_STG

Storage temperature

T_BIAS

Temperature under bias

T_SOLDERSoldering temperature

For 10 seconds

Note:

Permanent device damage may occur if Absolu te Maxim u m Ratin gs are exceeded. Functional operation

should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to con-

ditions beyond the operational limits for extended periods of time may affect device reliability.

Recommended DC Operating Conditions (T = T

)

OPR

A

Symbol

Parameter

Minimum

4.5

Typical

Maximum

Unit

V

Notes

bq4845Y

bq4845

5.0

5.5

V_CC

Supply voltage

4.75

0

5.0

5.5

V

V_SS

V_IL

V_IH

V_BC

Supply voltage

0

-

0

0.8

V

Input low voltage

Input high voltage

Backup cell voltage

-0.3

2.2

V

-

V_CC+ 0.3

4.0

V

2.3

-

V

Note:

Typical values indicate operation at T_A= 25°C.

Aug. 1995

10

bq4845/bq4845Y

DC Electrical Characteristics (T = T

≤ V

CC CCmax)

A

OPR, VCCmin

Symbol

Parameter

Minimum

Typical

Maximum

Unit

Conditions/Notes

I_LI

Input leakage current

-

± 1

µA

V_IN= V_SSto V_CC

CS = V_IHor OE = V_IHor WE

= V_IL

I_LO

Output leakage current

-

± 1

µA

V_OH

V_OHB

V_OL

Output high voltage

V_OH,BC Supply

2.4

V_BC- 0.3

-

V

I_OH= -2.0 mA

V_BC> V_CC, I_OH= -10µA

I_OL= 4.0 mA

Output low voltage

0.4

Min. cycle, duty = 100%,

CS = V_IL, I_I/O= 0mA

I_CC

Operating supply current

Standby supply current

-

12

3

25

-

mA

I_SB1

CS = V_IH

CS ≥ V_CC- 0.2V,

0V ≤ V_IN≤ 0.2V,

or V_IN≥ V_CC- 0.2V

I_SB2

Standby supply current

-

1.5

-

mA

V_SO

Supply switch-over voltage

Battery operation current

-

V_BC

0.3

-

V

V_BC= 3V, T_A= 25°C, no load

on V_OUTor CE_OUT

I_CCB

0.5

µA

Power-fail-detect voltage

V_OUTvoltage

4.55

4.62

4.75

V

-

bq4845

V_PFD

4.30

4.37

4.5

bq4845Y

V_OUT1

V_OUT2

V_RST

V_CC- 0.3V

-

I_OUT= 100mA, V_CC> V_BC

I_OUT= 100µA, V_CC< V_BC

I_RST= 4mA

V_OUTvoltage

V_BC- 0.3V

RST output voltage

INT output voltage

-

0.4V

-

V_INT

-

I_INT= 4mA

-

I_SINK= 4mA

V_WDO

WDO output voltage

2.4

-50

-

I_SOURCE= 2mA

0 < V_WDI< 0.8V

2.2 < V_WDI< V_CC

I_WDIL

I_WDIH

Watchdog input low current

Watchdog input high current

-10

20

-

µA

50

Notes:

Typical values indicate operation at T_A= 25°C, V_CC= 5V.

RST and INT are open-drain outputs.

Crystal Specifications (DT-26 or Equivalent)

Symbol

f_O

Parameter

Oscillation frequency

Minimum

Typical

Maximum

Unit

kHz

pF

-

32.768

-

C_L

T_P

Load capacitance

-

6

-

30

Temperature turnover point

Parabolic curvature constant

Quality factor

20

25

°C

k

-

-0.042

-

ppm/°C

Q

40,000

70,000

R₁

Series resistance

-

1.1

430

-

45

KΩ

C₀

Shunt capacitance

Capacitance ratio

1.8

600

1

pF

C₀/C₁

D_L

∆f/f_O

Drive level

µW

Aging (first year at 25°C)

1

-

ppm

Aug. 1995

11

bq4845/bq4845Y

Capacitance (T = 25°C, F = 1MHz, V

= 5.0V)

A

CC

Symbol

C_I/O

Parameter

Minimum

Typical

Maximum

Unit

pF

Conditions

Output voltage = 0V

Input voltage = 0V

Input/output capacitance

Input capacitance

-

7

5

C_IN

pF

Note:

These parameters are sampled and not 100% tested.

AC Test Conditions

Parameter

Test Conditions

0V to 3.0V

5 ns

Input pulse levels

Input rise and fall times

Input and output timing reference levels

Output load (including scope and jig)

1.5 V (unless otherwise specified)

See Figures 4 and 5

Figure 4. Output Load A

Figure 5. Output Load B

Aug. 1995

12

bq4845/bq4845Y

Read Cycle (T = T

≤ V

CC

A

OPR, VCCmin

Parameter

CCmax)

Min.

Symbol

Max.

-

Unit

ns

Conditions

t_RC

Read cycle time

70

-

t_AA

Address access time

70

35

-

Output load A

Output load B

Output load A

t_ACS

t_OE

Chip select access time

-

Output enable to output valid

Chip select to output in low Z

-

t_CLZ

t_OLZ

t_CHZ

t_OHZ

t_OH

5

Output enable to output in low Z

Chip deselect to output in high Z

Output disable to output in high Z

Output hold from address change

0

-

0

25

-

0

10

Write Cycle (T =T

Symbol

t_WC

≤ V

)

A

OPR , VCCmin

Parameter

Write cycle time

CC

CCmax

Min. Max. Unit

Conditions

70

65

-

ns

t_CW

Chip select to end of write

(1)

t_AW

Address valid to end of write

Measured from address valid to beginning

of write. (2)

t_AS

Address setup time

Write pulse width

0

-

ns

Measured from beginning of write to end of

write. (1)

t_WP

55

5

Measured from WE going high to end of

write cycle. (3)

t_WR1

t_WR2

t_DW

t_DH1

t_DH2

Write recovery time (write cycle 1)

Write recovery time (write cycle 2)

Data valid to end of write

Measured from CS going high to end of

write cycle. (3)

15

30

0

Measured to first low-to-high transition of

either CS or WE.

Measured from WE going high to end of

write cycle. (4)

Data hold time (write cycle 1)

Data hold time (write cycle 2)

Measured from CS going high to end of

write cycle. (4)

10

t_WZ

t_OW

Write enabled to output in high Z

Output active from end of write

0

25

-

ns

I/O pins are in output state. (5)

Notes:

1. A write ends at the earlier transition of CS going high and WE going high.

2. A write occurs during the overlap of a low CS and a low WE. A write begins at the later transition

of CS going low and WE going low.

3. Either t_WR1or t_WR2must be met.

4. Either t_DH1or t_DH2must be met.

5. If CS goes low simultaneously with WE going low or after WE going low, the outputs remain in

high-impedance state.

Aug. 1995

13

bq4845/bq4845Y

1,2

Read Cycle No. 1 (Address Access)

1,3,4

Read Cycle No. 2 (CS Access)

1,5

Read Cycle No. 3 (OE Access)

Notes:

1. WE is held high for a read cycle.

2. Device is continuously selected: CS = OE = V_IL

3. Address is valid prior to or coincident with CS transition low.

4. OE = V_IL

5. Device is continuously selected: CS = V_IL

.

Aug. 1995

14

bq4845/bq4845Y

1,2,3

Write Cycle No. 1 (WE-Controlled)

1,2,3,4,5

Write Cycle No. 2 (CS-Controlled)

Notes:

1. CS or WE must be high during address transition.

2. Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the

outputs must not be applied.

3. If OE is high, the I/O pins remain in a state of high impedance.

4. Either t_WR1or t_WR2must be met.

5. Either t_DH1or t_DH2must be met.

Aug. 1995

15

bq4845/bq4845Y

Power-Down/Power-Up Timing (T = T

)

OPR

A

Symbol

Parameter

Minimum Typical Maximum Unit

Conditions

t_F

V_CCslew from 4.75 to

4.25V

300

-

µs

t_FS

V_CCslew from 4.25 to V_SO

10

-

µs

V_CCslew from V_SOto

V_PFD(MAX)

t_R

100

6

-

µs

t_PF

Interrupt delay from

V_PFD

24

Delay after V_CCslews down past

V_PFDbefore SRAM is write-protected

and RST activated.

Write-protect time for

external RAM

t_WPT

90

100

125

µs

Internal write-protection period af-

ter V_CCpasses V_PFDon power-up.

t_CSR

t_RST

CS at V_IHafter power-up

V_PFDto RST inactive

100

200

-

300

ms

t_CSR

Reset active time-out period

Time during which external SRAM

is write-protected after V_CCpasses

V_PFDon power-up.

t_CER

Chip enable recovery

time

t_CSR

-

t_CSR

ms

Chip enable propagation

delay to external SRAM

t_CED

-

9

12

ns Output load A

Ca u tion : Nega tive u n d er sh oots below th e a bsolu te m a xim u m r a tin g of -0.3V in ba tter y-ba ck u p m od e

m a y a ffect d a ta in tegr ity.

Power-Down/Power-Up Timing

Notes:

PWRIE set to “1” to enable power fail interrupt.

RST and INT are open drain and require an external pull-up resistor.

Aug. 1995

16

bq4845/bq4845Y

28-Pin DIP (P)

Dimension

Minimum

0.160

0.015

0.045

0.008

1.440

0.600

0.530

0.600

0.090

0.115

0.070

Maximum

0.190

0.040

0.022

0.065

0.013

1.480

0.625

0.570

0.670

0.110

0.150

0.090

A

A1

B

B1

C

D

E

E1

e

G

L

S

All dimensions are in inches.

Aug. 1995

17

bq4845/bq4845Y

28-Pin SOIC (S)

Dimension

Minimum

0.095

0.004

0.013

0.008

0.700

0.290

0.045

0.395

0.020

Maximum

0.105

0.012

0.020

0.013

0.715

0.305

0.055

0.415

0.040

A

A1

B

C

D

E

e

H

L

All dimensions are in inches.

Aug. 1995

18

bq4845/bq4845Y

Ordering Information

bq4845

-

Tem p er a tu r e Ra n ge:

Blank = Commercial

N = Industrial

Pa ck a ge Op tion :

P = 28-pin plastic DIP (0.600)

S = 28-pin SOIC (0.300)

Volta ge Toler a n ce:

Blank = 5%

Y = 10%

Device:

bq4845 Real-Time Clock With CPU Supervisor

Aug. 1995

19

PACKAGE OPTION ADDENDUM

www.ti.com

17-Nov-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

PDIP

SOIC

Drawing

BQ4845P-A4

BQ4845S-A4

ACTIVE

N

28

13

TBD

Call TI

Level-NA-NA-NA

DW

20 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

BQ4845S-A4N

BQ4845S-A4NTR

BQ4845S-A4TR

BQ4845S-A4TRG4

ACTIVE

SOIC

DW

28

20 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

BQ4845YP-A4

BQ4845YS-A4

ACTIVE

PDIP

SOIC

N

28

13

TBD

Call TI

Level-NA-NA-NA

DW

20 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

BQ4845YS-A4N

BQ4845YS-A4NG4

BQ4845YS-A4NTR

BQ4845YS-A4TR

BQ4845YS-A4TRG4

ACTIVE

SOIC

DW

28

20 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

20 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

-

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

&

no Sb/Br)

-

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

17-Nov-2005

to Customer on an annual basis.

Addendum-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

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solutions:

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Amplifiers

amplifier.ti.com

www.ti.com/audio

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dsp.ti.com

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Military

www.ti.com/broadband

www.ti.com/digitalcontrol

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Logic

interface.ti.com

logic.ti.com

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power.ti.com

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Security

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www.ti.com/wireless

Mailing Address:

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Post Office Box 655303 Dallas, Texas 75265


型号：	BQ4845YSN
厂家：	TEXAS INSTRUMENTS
描述：	0 TIMER(S), REAL TIME CLOCK, PDSO28, 0.300 INCH, PLASTIC, SOIC-28 监控
文件：	总22页 (文件大小：1114K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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