DLPC350_14_技术文档

DLPC350

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DLP® Digital Controller for the DLP4500 DMD

Check for Samples: DLPC350

1

FEATURES

2

•

Supports Reliable Operation of the DLP4500

•

Microprocessor Peripherals

DMD

–

Programmable PWM and Capture timers

Two I²C Ports

•

Two Types of Input Interfaces

–

YUV, YCrCb, or RGB data format

One USB 1.1 Slave Port

–

8, 9, or 10 bits per color

32 kB of internal RAM

Pixel Clock support up to 150 MHz

Dedicated LED PWM generators

Single channel, LVDS Flat-Panel Display

(FPD-Link) compatible Input Interface

•

Integrated Clock Generation Circuitry

–

Operates on a single 32 MHz Crystal

Integrated spread spectrum clocking

Parallel Flash for microprocessor

–

Supports sources up to a 90 MHz

effective pixel clock rate

–

Four demodulated pixel mapped modes

supported for 8, 9, 10 YUV, YCrCb, or

RGB formatted input

System Control:

–

Integrated DMD Power and Reset Driver

Control

•

Two Modes of Operation

–

DMD Horizontal and Vertical Image Flip

–

Structured Light Mode

•

JTAG Boundary Scan Test support

–

Pixel Accurate Mode with no video

processing

419 Pin Plastic Ball Grid Array package

–

One-to-One Mapping of Input Data to

Micromirrors

APPLICATIONS

•

Machine Vision

–

1-Bit Binary Pattern Rates up to 4225 Hz

8-Bit Gray Pattern Rates up to 120 Hz

Industrial Inspection

3D Scanning

–

Video Projection Mode

3D Optical Metrology

Automated Fingerprint Identification

Face Recognition

Augmented Reality

Interactive Display

Information Overlay

Spectroscopy

–

Programmable color coordinate

adjustment

–

Programmable color space conversion

Programmable Degamma

Spatial-Temporal Multiplexing

(Dithering)

•

Dynamic and Anamorphic Scaling

Splash Screen Display support

Chemical Analyzers

Medical Instruments

Photo-Stimulation

Virtual Gauges

Supports 10 Hz to 120 Hz frame rates

High Speed, Double-Data-Rate DMD Interface

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

DLP is a registered trademark of Texas Insturments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DLPC350

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION

The DLPC350 digital controller, part of the DLP 0.45 WXGA chip set, supports reliable operation of the DLP4500

DMD, or Digital Micromirror Device. The DLPC350 controller provides a convenient, multi-functional interface

between user electronics and the DMD, enabling high-speed pattern rates, providing LED control and data

formatting for multiple input resolutions. The DLPC350 also outputs a trigger signal for synchronizing displayed

patterns with a camera, sensor, or other peripherals.

The DLPC350 controller enables integration of the DLP 0.45 WXGA chip set into small-form-factor and low-cost

light steering applications. Example applications for the 0.45 WXGA chip set include 3D scanning or metrology

systems with structured light, interactive displays, chemical analyzers, medical instruments, and other end

equipment requiring spatial light modulation (light steering and patterning).

The DLPC350 is one of the two devices in the 0.45 WXGA chip set (see Figure 1). The other device is the

DLP4500 DMD. Search the TI Website for 'DLPR350' for additional information, and see the 0.45 WXGA Chip-

Set data sheet DLPU009 for further details.

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BLOCK DIAGRAM

Figure 1. Chip Set Block Diagram

In DLP-based solutions, image data is 100% digital from the DLPC350 input port to the image on the DMD. The

image stays in digital form and is not converted into an analog signal. The DLPC350 processes the digital input

image and converts the data into a format needed by the DLP4500. The DLP4500 steers light by using binary

pulse-width-modulation (PWM) for each micromirror. Refer to DLP4500 Data Sheet (TI literature number

DLPS028) for further details.

Figure 2 is the DLPC350 functional block diagram. As part of the pixel processing functions, the DLPC350 offers

format conversion functions: chroma interpolation and color-space conversion. The DLPC350 also offers several

image-enhancement functions. The DLPC350 also supports the necessary functions to format the input data to

the DMD. The pixel processing functions allow the DLPC350 and DLP4500 to support a wide variety of

resolutions including NTSC, PAL, XGA, and WXGA. The pixel processing functions can be optionally bypassed

with the native 912 × 1140 pixel resolution to support direct one-to-one pixel mapping.

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When accurate pattern display is needed, the native 912 x 1140 input resolution pattern has a one-to-one

association with the corresponding micromirror on the DLP4500. The DLPC350 enables high-speed display of

these patterns. This functionality is well-suited for techniques such as structured light, additive manufacturing, or

digital exposure.

Figure 2. DLPC350 Functional Block Diagram

Commands can be input to the DLPC350 over an I²C interface.

The DLPC350 takes as input 24-, 27- or 30-bit RGB data at up to 120-Hz frame rate. This frame rate is

composed of three colors (red, green, and blue) with each color equally divided in the 120-Hz frame rate. Thus,

each color has a 2.78 ms time slot allocated. Because each color has an 8-, 9-, or 10-bit depth, each color time

slot is further divided into bit-planes. A bit-plane is the 2-dimensional arrangement of one-bit extracted from all

the pixels in the full color 2D image to implement dynamic depth. See Figure 3.

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8 Red Bit-Planes

8-bit Red Image

8-bit Green Image

8-bit Blue Image

24-bit RGB Image

8 Green Bit-Planes

8 Blue Bit-Planes

Figure 3. Bit Slices

The length of each bit-plane in the time slot is weighted by the corresponding power of two of its binary

representation. This provides a binary pulse-width modulation of the image. For example, a 24-bit RGB input has

three colors with 8-bit depth each. Each color time slot is divided into eight bit-planes, with the sum of the weight

of all bit planes in the time slot equal to 256. See Figure 4 for an illustration of this partition of the bits in a frame.

b1

bit 7

bit plane

b

3

bit 4

bit 5

bit 6

b0 b2

16

32

64

128

256

Figure 4. Bit Partition in a Frame for an 8-Bit Color

Therefore, a single video frame is composed of a series of bit-planes. Because the DMD mirrors can be either on

or off, an image is created by turning on the mirrors corresponding to the bit set in a bit-plane. With binary pulse-

width modulation, the intensity level of the color is reproduced by controlling the amount of time the mirror is on.

For a 24-bit RGB frame image inputted to the DLPC350, the DLPC350 creates 24 bit planes, stores them in a

double-buffered eDRAM embedded in the chip, and sends them to the DLP4500 DMD, one bit-plane at a time.

Depending on the bit weight of the bit-plane, the DLPC350 controls the time this bit-plane is illuminated,

controlling the intensity of the bit-plane. To improve image quality in video frames, these bit-planes, time slots,

and color frames are shuffled and interleaved with spatial-temporal algorithms by the DLPC350.

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Structured Light Applications

For other applications where this video enhancement is not desired, the video processing algorithms can be

bypassed and replaced with a specific set of bit-planes. The bit-depth of the pattern is then allocated into the

corresponding time slots. Furthermore, an output trigger signal is also synchronized with these time slots to

indicate when the image is displayed. For structured light applications, this mechanism provides the capability to

display a set of patterns and signal a camera to capture these patterns overlaid on an object.

The DLPC350 stores two 24-bit frames in its internal memory buffer. This 48 bit-plane display buffer allows the

DLPC350 to send one 24-bit buffer to the DMD array while the second buffer is filled from Flash or streamed in

through the 24-bit RGB interface. In streaming mode, the DMD array displays the previous 24-bit frame while the

current frame fills the second 24-bit frame of the display buffer. Once a 24-bit frame is displayed, the buffer

rotates accessing the next 24-bit frame to the DMD. Thus, the displayed image is a 24-bit frame behind the data

streamed through the 24-bit RGB parallel interface.

In structured light mode, the 48 bit-planes can be pre-loaded from Flash memory and then sequenced with a

combination of patterns with different bit depths. To synchronize a camera to the displayed patterns, the

DLPC350 supports three trigger modes: mode 0, mode 1, and mode 2.

In mode 0, the vertical sync is used as trigger input. In mode 1, a TRIG_IN_1 pulse indicates to the DLPC350 to

advance to the next pattern, while TRIG_IN_2 starts and stops the pattern sequence. In both modes 0 and 1,

TRIG_OUT_1 frames the exposure time of the pattern, while TRIG_OUT_2 indicates the start of the pattern

sequence or internal buffer boundary of 24-bit planes. In mode 2, the TRIG_IN_1 signal toggles between two

consecutive patterns, while a TRIG_IN_2 pulse advances to the next pair of patterns.

In trigger mode 0, shown in Figure 5, the VSYNC starts the pattern sequence display. The pattern sequence

consists of a series of three consecutive patterns. The first pattern sequence consists of P1, P2, and P3. Since

P3 is an RGB pattern, it is shown with its time sequential representation of P3.1, P3.2, and P3.3. The second

pattern sequence consists of three patterns: P4, P5, and P6. The third sequence consists of P7, P8, and P9.

TRIG_OUT_1 frames each pattern exposed, while TRIG_OUT_2 indicates the start of each of the three pattern

sequences.

An example of trigger mode 1 is shown in Figure 6. Pattern sequences of four are displayed. TRIG_OUT_1

frames each pattern exposed, while TRIG_OUT_2 indicates the start of each four-pattern sequence. TRIG_IN_1

pulses advance the pattern.

Another example for mode 1 is shown in Figure 7, where pattern sequences of three are displayed.

TRIG_OUT_1 frames each pattern displayed, while TRIG_OUT_2 indicates the start of each three-pattern

sequence. TRIG_IN_2 serves as a start/stop signal. When high, the pattern sequence starts or continues. Note

that in the middle of displaying the P4 pattern, TRIG_IN_2 is low, so the sequence stops displaying P4. When

TRIG_IN_2 is raised, the pattern sequence continues where it stopped by re-displaying P4.

For trigger mode 2, shown in Figure 8, TRIG-IN_1 alternates between two patterns, while TRIG_IN_2 advances

to the next pair of patterns. Table 1 shows the allowed pattern combinations in relation to the bit depth of the

pattern.

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Figure 5. Mode 0 Trigger Timing Diagram

Figure 6. Mode 1 Triggers Timing Diagram for 6-Bit Patterns

Figure 7. Mode 1 Trigger Timing Diagram

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Figure 8. Mode 2 Trigger Timing Diagram

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Table 1. Allowed Pattern Combinations

EXTERNAL RGB

INPUT PATTERN

RATE (Hz)

MAXIMUM NUMBER OF

PATTERNS (PRE-

LOADED)

PRE-LOADED

PATTERN RATE (Hz)

BIT DEPTH

1

2

3

4

5

6

7

8

2880

1428

636

588

480

400

222

120

4225

1428

636

588

500

400

222

120

48

24

16

12

8

6

Typical System Application

A typical embedded system application using the DLPC350 is shown in Figure 9. In this configuration, the

DLPC350 controller supports a 24-bit parallel RGB input, typical of LCD interfaces, from an external source or

processor. This system supports both still and motion video sources. However, the controller only supports

sources with periodic synchronization pulses. This is ideal for motion video sources, but can also be used for still

images by maintaining periodic syncs and only sending a new frame of data when needed. The still image must

be fully contained within a single video frame and meet the frame timing constraints. The DLPC350 refreshes the

displayed image at the source frame rate and repeats the last active frame for intervals in which no new frame

has been received.

Figure 9. Typical Embedded System Block Diagram

Related Documents

DOCUMENT

DLP4500 0.45 WXGA DMD Data Sheet

DLP^®0.45 WXGA Chip Set Data Manual

DLPC350 Programmer's Guide

TI LITERATURE NUMBER

DLPS028

DLPU009

DLPU010

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Device Nomenclature

Figure 10 provides a legend for reading the complete device name for any DLP device.

Figure 10. Device Nomenclature

Device Marking

The device marking consists of the fields shown in Figure 11.

Figure 11. Device Marking

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SIGNAL FUNCTIONAL DESCRIPTIONS

This section describes the input/output characteristics of signals that interface to the DLPC350 by functional

groups. includes I/O power and type characteristic references which are further described in subsequent

sections.

Table 2. Functional Pin Descriptions⁽¹⁾

I/O

POWER

I/O

TYPE

INTERNAL

TERMINATION

CLK

SYSTEM

DESCRIPTION

NAME

NO.

CONTROL

Power Good is an active high signal with

hysteresis that is generated by an external

power supply or voltage monitor. A high

value indicates all power is within operating

voltage specs and the system is safe to exit

its reset state. A transition from high to low

should indicate that the controller or DMD

supply voltage will drop below their rated

minimum level within the next 0.5ms

(POSENSE must remain active high during

this interval). This is an early warning of an

imminent power loss condition. This warning

is required to enhance long term DMD

reliability. A DMD park sequence, followed

by a full controller reset, is performed by the

DLPC350 when PWRGOOD goes low for a

minimum of 4us protecting the DMD. This

minimum de-assertion time is used to

I₄

H

PWRGOOD

H19

VDDC

Async

protect the input from glitches. Following this

the DLPC350 will be held in its reset state

as long as PWRGOOD is low. PWRGOOD

must be driven high for normal operation.

The DLPC350 will acknowledge PWRGOOD

as active once it’s been driven high for a

minimum of 625ns. Utilizes hysteresis.

Power-On Sense is an active high input

signal with hysteresis that is generated by

an external voltage monitor circuit.

POSENSE must be driven inactive (low)

when any of the controller supply voltages

are below minimum operating voltage specs.

POSENSE must be active (high) when all

controller supply voltages remain above

minimum specs.

I₄

H

POSENSE

G21

N21

Async

Power On/Off is an active high signal that

indicates the power of the system. Power

On/Off is high when the system is in power-

up state, and low when the system is in

standby. Power On/Off can also be used to

power on/off an external power supply.

POWER_ON_OFF

VDD33

B₂

Signal to host processor or power supply to

indicate that the DLPC350 is powered on.

Asserted just before INIT_DONE.

EXT_PWR_ON

D21

D18

VDD33

B₂

Async

N/A

HOLD_IN_BOOT

External pull-up required

Prior to transferring part of code from

parallel flash content to internal memory, the

internal memory is initialized and a memory

test is performed. The result of this test

(pass/fail) is recorded in the system status. If

memory test fails, the initialization process is

halted. INIT_DONE is asserted twice to

indicate an error situation. See Figure 25

and note that GPIO26 is the INIT_DONE

signal.

INIT_DONE

F19

F21

VDD33

B₂

Async

This signal is sampled during power-up. If

the signal is low, the I²C addresses are 0x34

and 0x35. If the signal is low, the I²C are

0x3A and 0x3B. Once the system has been

initialized, this signal is available as a GPIO.

I2C_ADDR_SEL

B₂

(1) I/O Type: I indicates input, O indicates output, B indicates bi-directional, and H indicates hysteresis. See Table 6 for subscript

explanation.

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Table 2. Functional Pin Descriptions (continued)

I/O

POWER

I/O

TYPE

INTERNAL

TERMINATION

CLK

SYSTEM

DESCRIPTION

NAME

NO.

Requires an external pull-up

to 3.3V. The minimum

acceptable pull-up value is 1

KΩ.

I²C clock. Bi-directional, open-drain signal.

I²C slave clock input from the external

processor. This bus supports 400 KHz.

I2C1_SCL

J3

VDD33

B₂

N/A

Requires an external pull-up

to 3.3V. The minimum

acceptable pull-up value is 1

KΩ.

I²C data. Bi-directional, open drain signal.

I²C slave to accept command or transfer

data to and from the external processor.

This bus supports 400 KHz.

I2C1_SDA

I2C0_SCL

J4

I2C1_SCL

Requires an external pull-up

to 3.3V. The minimum

acceptable pull-up value is 1

KΩ. This input is NOT 5V

tolerant.

I²C Bus 0, Clock; I²C master for on-board

peripherals such as Temperature Sensor.

This bus supports 400KHz, Fast Mode

operation.

M2

VDD33

B₈

N/A

Requires an external pull-up

to 3.3V. The minimum

acceptable pull-up value is 1 I2C0_SCL

KΩ. This input is NOT 5V

tolerant.

I²C Bus 0, Data; I²C master for on-board

peripherals such as Temperature Sensor.

This bus supports 400KHz, Fast Mode

operation.

I2C0_SDA

M3

B₈

SYSTEM CLOCK

MOSC

System clock oscillator input (3.3V

LVCMOS). Note that the MOSC must be

stable a maximum of 25 ms after POSENSE

transitions from high to low.

A14

A15

VDD33

I₁₀

N/A

MOSCN

O₁₀

MOSC Crystal return

(2)(3)(4)

PORT 1: PARALLEL VIDEO/GRAPHICS INPUT

Includes an internal pull-

P1A_CLK

P1B_CLK

P1C_CLK

P1_VSYNC

P1_HSYNC

P1_DATEN

P1_FIELD

P1_A_9

W15

AB17

Y16

VDD33

I₄

N/A

Port 1 Input Data Pixel Write Clock 'A'

Port 1 Input Data Pixel Write Clock 'B'

Port 1 Input Data Pixel Write Clock 'C'

down

Includes an internal pull-

VDD33

N/A

down

Includes an internal pull-

N/A

down

B₁

H

Includes an internal pull-

Y15

P1A_CLK Port 1 Vertical Sync. Utilizes hysteresis.

P1A_CLK Port 1 Horizontal Sync. Utilizes hysteresis.

P1A_CLK Port 1 Data Enable

down

B₁

H

Includes an internal pull-

down

AB16

AA16

W14

AB20

AA19

Y18

Includes an internal pull-

down

I₄

Includes an internal pull-

down

Port 1 Field Sync. Required for interlaced

P1A_CLK

sources only (and not progressive).

Includes an internal pull-

down

Port 1 A Channel Input Pixel Data (bit weight

P1A_CLK

128).

Includes an internal pull-

down

Port 1 A Channel Input Pixel Data (bit weight

P1_A_8

P1A_CLK

64).

Includes an internal pull-

down

Port 1 A Channel Input Pixel Data (bit weight

P1_A_7

P1A_CLK

32).

Includes an internal pull-

down

Port 1 A Channel Input Pixel Data (bit weight

P1_A_6

W17

AB19

AA18

Y17

P1A_CLK

16).

Includes an internal pull-

down

Port 1 A Channel Input Pixel Data (bit weight

P1_A_5

P1A_CLK

8).

Includes an internal pull-

down

Port 1 A Channel Input Pixel Data (bit weight

P1_A_4

P1A_CLK

4).

Includes an internal pull-

down

Port 1 A Channel Input Pixel Data (bit weight

P1_A_3

P1A_CLK

2).

Includes an internal pull-

down

Port 1 A Channel Input Pixel Data (bit weight

P1_A_2

AB18

P1A_CLK

1).

(2) Port 1 can be used to support multiple source options for a given product (that is. HDMI, BT656). To do so, the data bus from both

source components must be connected to the same port 1 pins and control given to the DLPC350 to tri-state the "inactive" source. Tying

them together like this will cause some signal degradation due to reflections on the tri-stated path.

(3) The A, B, and C input data channels of Port 1 can be internally swapped for optimum board layout.

(4) Sources feeding less than the full 10-bits per color component channel should be MSB justified when connected to the DLPC350 and

LSBs tied off to zero. For example, an 8-bit per color input should be connected to bits 9:2 of the corresponding A, B, or C input

channel. BT656 are 8 or 10 bits in width. If a BT656 type input is utilized, the data bits must be MSB justified as with the other types of

input sources on either of the A, B, or C data input channels.

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Table 2. Functional Pin Descriptions (continued)

I/O

POWER

I/O

TYPE

INTERNAL

TERMINATION

CLK

SYSTEM

DESCRIPTION

NAME

NO.

Includes an internal pull-

down

Port 1 A Channel Input Pixel Data (bit weight

0.5).

P1_A_1

W16

VDD33

I₄

P1A_CLK

Includes an internal pull-

down

Port 1 A Channel Input Pixel Data (bit weight

0.25).

P1_A_0

P1_B_9

P1_B_8

P1_B_7

P1_B_6

P1_B_5

P1_B_4

P1_B_3

P1_B_2

P1_B_1

P1_B_0

P1_C_9

P1_C_8

P1_C_7

P1_C_6

P1_C_5

P1_C_4

P1_C_3

P1_C_2

P1_C_1

P1_C_0

AA17

U21

U20

V22

U19

V21

W22

W21

AA20

Y19

W18

P21

P22

R19

R20

R21

R22

T21

Includes an internal pull-

down

Port 1 B Channel Input Pixel Data (bit weight

128).

Includes an internal pull-

down

Port 1 B Channel Input Pixel Data (bit weight

64).

Includes an internal pull-

down

Port 1 B Channel Input Pixel Data (bit weight

32).

Includes an internal pull-

down

Port 1 B Channel Input Pixel Data (bit weight

16).

Includes an internal pull-

down

Port 1 B Channel Input Pixel Data (bit weight

8).

Includes an internal pull-

down

Port 1 B Channel Input Pixel Data (bit weight

4).

Includes an internal pull-

down

Port 1 B Channel Input Pixel Data (bit weight

2).

Includes an internal pull-

down

Port 1 B Channel Input Pixel Data (bit weight

1).

Includes an internal pull-

down

Port 1 B Channel Input Pixel Data (bit weight

0.5).

Includes an internal pull-

down

Port 1 B Channel Input Pixel Data (bit weight

0.25).

Includes an internal pull-

down

Port 1 C Channel Input Pixel Data (bit weight

128).

Includes an internal pull-

down

Port 1 C Channel Input Pixel Data (bit weight

64).

Includes an internal pull-

down

Port 1 C Channel Input Pixel Data (bit weight

32).

Includes an internal pull-

down

Port 1 C Channel Input Pixel Data (bit weight

16).

Includes an internal pull-

down

Port 1 C Channel Input Pixel Data (bit weight

8).

Includes an internal pull-

down

Port 1 C Channel Input Pixel Data (bit weight

4).

Includes an internal pull-

down

Port 1 C Channel Input Pixel Data (bit weight

2).

Includes an internal pull-

down

Port 1 C Channel Input Pixel Data (bit weight

1).

T20

Includes an internal pull-

down

Port 1 C Channel Input Pixel Data (bit weight

0.5).

T19

Includes an internal pull-

down

Port 1 C Channel Input Pixel Data (bit weight

0.25).

U22

PORT 2: FPD-LINK COMPATIBLE VIDEO/GRAPHICS INPUT⁽⁵⁾

Includes weak internal pull-

down.

Positive differential input signal for Clock,

FPD-Link receiver.

RCK_IN_P

RCK_IN_N

RA_IN_P

RA_IN_N

RB_IN_P

Y9

W9

VDD33_FPD

I₅

N/A

Includes weak internal pull-

down.

Negative differential input signal for Clock,

FPD-Link receiver.

N/A

Includes weak internal pull-

down.

Positive differential input signal for data

channel A, FPD-Link receiver.

AB10

AA10

Y11

RCK_IN

Includes weak internal pull-

down.

Negative differential input signal for data

channel A, FPD-Link receiver.

Includes weak internal pull-

down.

Positive differential input signal for data

channel B, FPD-Link receiver.

(5) Port 2 is a single-channel FPD-Link compatible input interface. FPD-Link is a de-facto industry standard Flat-Panel Display Interface

which utilizes the high bandwidth capabilities of LVDS signaling to serialize Video/Graphics data down to a couple wires to provide a low

wire count and low EMI interface. Port 2 supports sources rates up to a maximum effective clock of 90 MHz. The Port 2 input pixel data

must adhere to one of four supported data mapping formats (See Table 10). Given that Port 2 inputs contain weak pull-down resistors,

they can be left floating when not used.

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Table 2. Functional Pin Descriptions (continued)

I/O

POWER

I/O

TYPE

INTERNAL

TERMINATION

CLK

SYSTEM

DESCRIPTION

NAME

NO.

Includes weak internal pull-

down.

Negative differential input signal for data

channel B, FPD-Link receiver.

RB_IN_N

W11

VDD33_FPD

I₅

RCK_IN

Includes weak internal pull-

down.

Positive differential input signal for data

channel C, FPD-Link receiver.

RC_IN_P

RC_IN_N

RD_IN_P

RD_IN_N

RE_IN_P

RE_IN_N

AB12

AA12

Y13

Includes weak internal pull-

down.

Negative differential input signal for data

channel C, FPD-Link receiver.

Includes weak internal pull-

down.

Positive differential input signal for data

channel D, FPD-Link receiver.

Includes weak internal pull-

down.

Negative differential input signal for data

channel D, FPD-Link receiver.

W13

Includes weak internal pull-

down.

Positive differential input signal for data

channel E, FPD-Link receiver.

AB14

AA14

Includes weak internal pull-

down.

Negative differential input signal for data

channel E, FPD-Link receiver.

DMD INTERFACE

DMD_D0

A8

B8

DMD_D1

DMD_D2

C8

DMD_D3

D8

DMD_D4

B11

C11

D11

E11

C7

DMD_D5

DMD_D6

DMD_D7

DMD_D8

DMD_D9

B10

E7

DMD_D10

DMD_D11

DMD_D12

DMD_D13

DMD_D14

DMD_D15

DMD_D16

DMD_D17

DMD_D18

DMD_D19

DMD_D20

DMD_D21

DMD_D22

DMD_D23

DMD_DCLK

DMD_LOADB

DMD_SCTRL

DMD_TRC

DMD data pins. DMD data pins are double

data rate (DDR) signals that are clocked on

DMD_DCLK both edges of DMD_DCLK.

All 24 DMD data signals are use to interface

D10

A6

VDD_DMD

O₇

to the DLP4500.

A12

B12

C12

D12

B7

A10

D7

B6

E9

C10

C6

A9

VDD_DMD

O₇

N/A

DMD data clock (DDR)

B9

DMD_DCLK DMD data load signal (active-low).

DMD_DCLK DMD data serial control signal

DMD_DCLK DMD data toggle rate control

C9

D9

DMD_SAC_

DMD_DRC_BUS

DMD_DRC_STRB

D5

C5

VDD_DMD

O₇

DMD reset control bus data

CLK

DMD_SAC_

DMD reset control bus strobe

CLK

Requires a 30kΩ to 51kΩ

external pull-up resistor to

VDD_DMD.

DMD_DRC_OE

B5

VDD_DMD

O₇

Async

DMD reset control enable (active-low).

DMD_SAC_

CLK

DMD_SAC_BUS

DMD_SAC_CLK

D6

A5

VDD_DMD

O7

O₇

DMD stepped-address control bus data

DMD stepped-address control bus clock

N/A

14

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Table 2. Functional Pin Descriptions (continued)

I/O

POWER

I/O

TYPE

INTERNAL

TERMINATION

CLK

SYSTEM

DESCRIPTION

NAME

NO.

DMD Power Enable control. This signal

indicates to an external regulator that the

DMD is powered.

DMD_PWR_EN

G20

VDD_DMD

O₂

O

Async

DMD drive strength adjustment precision

reference. A ± 1% external precision resistor

should be connected to this pin.

EXRES

A3

FLASH INTERFACE

Boot Flash (active low). Required for Boot

Memory

PM_CS_1

U2

VDD33

O₂

Async

PM_CS_2

U1

V3

Optional for Additional Flash (up to 128 Mb)

PM_ADDR_22

PM_ADDR_21

PM_ADDR_20

PM_ADDR_19

PM_ADDR_18

PM_ADDR_17

PM_ADDR_16

PM_ADDR_15

PM_ADDR_14

PM_ADDR_13

PM_ADDR_12

PM_ADDR_11

PM_ADDR_10

PM_ADDR_9

PM_ADDR_8

PM_ADDR_7

PM_ADDR_6

PM_ADDR_5

PM_ADDR_4

PM_ADDR_3

PM_ADDR_2

PM_ADDR_1

PM_ADDR_0

PM_WE

B₂

W1

W2

Y1

AB2

AA3

Y4

W5

AB3

AA4

Y5

W6

AB4

AA5

Y6

VDD33

Async

Flash memory address bit

O₂

W7

AB5

AA6

Y7

AB6

W8

AA7

AB7

V2

VDD33

O₂

Async

Write Enable (active low)

Output Enable (active low)

Upper Byte(15:8) Enable

Lower Byte(7:0) Enable

PM_OE

U4

PM_BLS_1

AA8

AB8

M1

PM_BLS_0

PM_DATA_15

PM_DATA_14

PM_DATA_13

PM_DATA_12

PM_DATA_11

PM_DATA_10

PM_DATA_9

PM_DATA_8

N1

N2

N3

VDD33

B₂

Async

Data bits, upper byte

N4

P1

P2

P3

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Table 2. Functional Pin Descriptions (continued)

I/O

POWER

I/O

TYPE

INTERNAL

TERMINATION

CLK

SYSTEM

DESCRIPTION

NAME

NO.

P4

R2

R3

R4

T1

T2

T3

T4

PM_DATA_7

PM_DATA_6

PM_DATA_5

PM_DATA_4

PM_DATA_3

PM_DATA_2

PM_DATA_1

PM_DATA_0

VDD33

B₂

Async

Data bits, lower byte

LED DRIVER INTERFACE

LED blinks continuously (heartbeat) to

indicate the system is running fine. Period of

1 second; 50% high and low.

HEARTBEAT

C16

VDD33

B₂

Async

FAULT_STATUS

LEDR_PWM

LEDG_PWM

LEDB_PWM

LEDR_EN

B16

K2

K3

K4

L3

LED off indicates any system fault

LED Red PWM Output Enable Control

LED Green PWM Output Enable Control

LED Blue PWM Output Enable Control

LED Red PWM Output

VDD33

O₂

Async

LEDG_EN

L4

LED Green PWM Output

LEDB_EN

K1

LED Blue PWM Output

TRIGGER CONTROL

In trigger mode 1, this signal will be used to

advance the pattern display. In trigger mode

2, the rising edge will display the pattern and

the falling edge will display the next indexed

pattern.

TRIG_IN_1

G19

F22

VDD33

B₂

Async

In trigger mode 1, this signal will be used to

start (rising edge)/stop (falling edge) the

pattern display. It will work along with the

software start/stop command. In trigger

mode 2, this signal will be used to advance

the pattern by two indexes.

TRIG_IN_2

B₂

Active high trigger output signal during

pattern exposure

TRIG_OUT_1

C17

K21

VDD33

B₂

Async

Active high trigger output to indicate first

pattern display

TRIG_OUT_2

PERIPHERAL INTERFACE

USB D- I/O for USB command interface. A

5.0 Watt external series resistance (of 22Ω)

is strongly recommended to limit the

potential impact of a continuous short circuit

USB_DAT_N

E3

between USB_DAT_N and either V_BUS,

GND, the other data line, or the cable. For

additional protection, an optional 200 mA

Shottky diode from USB_DAT_N to VDD33

can also be added.

VDD33

B₉

Async

USB D+ I/O for USB command interface. A

5.0 Watt external series resistance (of 22Ω)

is strongly recommended to limit the

potential impact of a continuous short circuit

USB_DAT_P

E2

between USB_DAT_P and either V_BUS,

GND, the other data line, or the cable. For

additional protection, an optional 200 mA

Shottky diode from USB_DAT_P to VDD33

can also be added.

USB_EN

C18

L19

VDD33

B₂

Async

USB Enable

Transmit Data Output. Reserved for debug

messages

UART_TXD

O₂

Receive Data Input. Reserved for debug

messages

UART_RXD

UART_RTS

L21

VDD33

I₄

Async

Ready to Send hardware flow control output.

Reserved for debug messages

M19

O₂

16

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Table 2. Functional Pin Descriptions (continued)

I/O

POWER

I/O

TYPE

INTERNAL

TERMINATION

CLK

SYSTEM

DESCRIPTION

NAME

NO.

Clear to Send hardware flow control input.

Reserved for debug messages

UART_CTS

L20

VDD33

I₄

Async

(6)

GPIOS

ALTERNATIVE MODE

GPIO_36

GPIO_35

GPIO_34

GPIO_33

GPIO_29

GPIO_28

GPIO_27

GPIO_25

GPIO_24

GPIO_21

GPIO_20

GPIO_15

GPIO_14

GPIO_13

GPIO_12

GPIO_11

GPIO_06

GPIO_05

GPIO_02

GPIO_00

G1

H4

VDD33

B₂

Async

None

H3

None

H2

None

F20

E22

E21

D22

E20

N20

N19

B19

B18

L2

None

M4

OCLKD (Output)

OCLKC (Output)

PWM_IN_1 (Input)

PWM_IN_0 (Input)

PWM_STD_2 (Output)

PWM_STD_0 (Output)

A19

A18

D16

A17

C15

OTHER INTERFACES

FAN_LOCKED

FAN_PWM

Feedback from Fan to indicate Fan is

connected and running

B17

D15

VDD33

B₂

Async

Fan PWM speed control

CONTROLLER MANUFACTURER TEST SUPPORT

Reserved for test. Should be connected

directly to ground on the PCB for normal

operation

I₄

H

HW_TEST_EN

V7

VDD33

Includes internal pull-down.

N/A

BOARD LEVEL TEST AND DEBUG

TDI

P18

R18

V15

L18

VDD33

I₄

Includes internal pull-up

TCK

N/A

JTAG serial data in.⁽⁷⁾

JTAG serial data clock.⁽⁷⁾

JTAG test mode select.⁽⁷⁾

JTAG serial data out.⁽⁷⁾

TCK

TMS1

TDO1

I₄

TCK

O₁

JTAG, RESET (active-low). This pin should

be pulled high (or left unconnected) when

the JTAG interface is in use for boundary

scan. Connect this pin to ground otherwise.

Failure to tie this pin low during normal

operation will cause startup and initialization

problems.⁽⁷⁾

I₄

H

TRST

V17

VDD33

Includes internal pull-up

Async

RTCK

G18

V6

VDD33

O₂

N/A

JTAG return clock.⁽⁸⁾

Includes internal pull down.

External pull-down

recommended for added

protection.

IC 3-State Enable (active high). Asserting

high will 3-state all outputs except the JTAG

interface.

I₄

H

ICTSEN

Async

(6) GPIO signals must be configured via software for input, output, bi-directional, or open-drain. Some GPIOs have one or more "alternative

use" modes which are also software configurable. The reset default for all optional GPIOs is as an input signal. However, any alternate

function connected to these GPIO pins with the exception of General Purpose Clocks and PWM Generation, will be reset. An external

pull-up to the 3.3V supply is required for each signal configured as open-drain. External pull-up or pull-down resistors may be required to

ensure stable operation before software is able to configure these ports.

(7) All JTAG signals are LVCMOS compatible.

(8) See General Handling Guidelines for Unused CMOS-type Pins in General PCB Recommendations for instructions on handling unused

pins.

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Table 2. Functional Pin Descriptions (continued)

I/O

POWER

I/O

TYPE

INTERNAL

TERMINATION

CLK

SYSTEM

DESCRIPTION

NAME

NO.

RESERVED PINS

N22, M22,

P19, P20

Includes an internal pull-

down

RESERVED

VDD33

I₄

N/A

Reserved.⁽⁸⁾

RESERVED

V16

VDD33

I₄

Includes an internal pull-up

N/A

D1, J2

F1, F2, G2,

G3, G4

RESERVED

VDD33

O₂

O₁

Includes internal pull-down

N/A

F3, J1, M21,

PM_CS_0,

U3

Leave these pins unconnected.⁽⁸⁾

H20, M18,

M20

H21, H22,

J19, J20,

J21, J22,

K19, K20

RESERVED

VDD33

B₂

Includes internal pull-down

N/A

Reserved⁽⁸⁾

C1, D2, F4

18

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Power and Ground Pins

Power and ground connections to the DLPC350 are made up of the groupings shown in Table 3.

Table 3. Power and Ground Pin Descriptions

POWER GROUP

PLLM_VSS

PLLM_VDD

PLLM_VAD

PLLM_VAS

PLLD_VSS

PLLD_VDD

PLLD_VAD

PLLD_VAS

PIN NUMBER(S)

DESCRIPTION

B15

E14

D14

C14

B14

E13

D13

C13

Master clock generator PLL ground return

1.2V Master clock generator PLL Digital Power⁽¹⁾

1.8V Master clock generator PLL Analog Power⁽¹⁾

Master clock generator PLL ground return

DDR clock generator PLL ground return

1.2V DDR clock generator PLL Digital Power

1.8V DDR clock generator PLL Analog Power⁽¹⁾

DDR clock generator PLL ground return

E5, D4, C3, B2, A2, N6, F11,

J9, J10, J11, J12, J13, J14, K9,

K10, K11, K12, K13, K14, L9,

L10, L11, L12, L13, L14, M9,

M10, M11, M12, M13, M14, N9,

N10, N11, N12, N13, N14, P9,

P10, P11, P12, P13, P14, H1,

B1, C2, D3, E4, V5, W4, Y3,

AA1, AA2, U8, U15, A21, A22,

B21, B22, C20, D19, E18, V18,

W19, Y20, AA21, AB22, M17,

C22, C21, D20, E19, K22, L22,

V19, V20, W20, Y21, R1, Y2,

W3, V4, F9, A7, B3, B4, C4,

A13, B13, B20, C19, Y14, Y12,

W12, W10, Y10, AA13, AB13,

AA11, AB11, Y8, AA9, F14,

V14, V8

VSS

Common Ground (105)

F12, F7, F6, G6, M6, F5, G5,

M5, U6, U7, F17, G17, U16,

VDDC

U17, F18, N17, U18, U5, F16, Core 1.2V Power

E6, E12, E17, K6, L6, P6, R6,

K17, L17, P17, R17

AB1, F15, T5, T6, AA22, H6,

J6, L1, E1, H5, J5, K5, L5, N5,

P5, U9, U14, H17, J17, T17,

Y22, T22, G22, H18, J18, N18, LVCMOS I/O 3.3V Power

R5, V1, A20, A16, E15, V9,

VDD33

AA15, AB15, AB21, AB9, T18,

K18, F13

VDD_DMD

VDD12_FPD

VDD33_FPD

F10, F8, A4, A11, E8, E10

U11, U12, V12, V11

1.9V DMD Interface Voltage

FPD-Link LVDS Interface 1.2V Power⁽¹⁾

FPD-Link LVDS Interface 3.3V Power⁽¹⁾

U10, U13, V13, V10

It is recommended that this signal be tied to ground via an external pull-down

resistor

Spare

E16

D17

Fuse Programming Pin (for manufacturing use only). This signal should be tied

directly to ground for normal operation.

VPGM

(1) Special Filter is required for proper operation. See PLL .

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ABSOLUTE MAXIMUM RATING

over operating free-air temperature range (unless otherwise noted). Stresses beyond those listed under Absolute Maximum

Ratings may cause permanent damage to the device. The Absolute Maximum Ratings are stress ratings only, and functional

performance of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to Absolute Maximum Rated conditions for extended periods may affect device reliability.

PARAMETER

CONDITIONS

MIN

MAX UNIT

Electrical

Supply Voltage⁽¹⁾⁽²⁾

VDDC (Core 1.2V Power)

VDD33

–0.5

-0.5

-1.00

-0.3

-0.5

-1.00

-0.3

-0.5

1.7

3.8

2.3

1.7

3.8

1.7

2.3

5.25

3.6

5.25

2.0

3.6

V

VDD_DMD

VDD12_FPD

VDD33_FPD

VDD12_PLLD

VDD12_PLLM

VDD_18_PLLD

VDD_18_PLLM

USB

Input Voltage (V_I)⁽³⁾

OSC

LVCMOS

I²C

LVDS

Output Voltage (V_O)

USB

DMD LPDDR

LVCMOS

I²C

Environmental

T_J

Junction temperature

0

105

125

ºC

V

T_stg

ESD⁽⁴⁾

Storage temperature

-40

Electrostatic discharge immunity

Human Body Model (V_ESDHBM

)

±2000

±500

±150

Charged Device Model (V_ESDCDM

Machine Model (V_{ESD MM}

)

(1) All voltages referenced to VSS (ground).

(2) All of the 3.3V, 1.9V, 1.8V, and 1.2V power should be applied and removed per the procedure defined in System Power and Reset.

(3) Applies to external input and bidirectional buffers.

(4) Tested in accordance with JESD22-A114-B Electrostatic Discharge (ESD) sensitivity testing Human Body Model (HBM).

20

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RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this

data sheet is achieved when operating the device by the Recommended Operating Conditions. No level of performance is

implied when operating the device above or below the Recommended Operating Conditions limits.

PARAMETER

CONDITIONS

MIN

NOM

MAX UNIT

Electrical

VDD33

3.3V Supply voltage, I/O

1.9V Supply voltage, I/O

1.8V Supply voltage, PLL Analog

1.2V Supply voltage, Core logic

1.2V Supply voltage, PLL Digital

USB

3.135

1.8

1.71

1.116

0

3.300

1.9

3.465

2.0

V

VDD_DMD

VDD_18_PLLD

VDD_18_PLLM

VDD12

1.80

1.89

1.80

1.89

1.200

1.26

VDD12_PLLD

VDD12_PLLM

V_I

1.26

VDD33

2.2

OSC

0

3.3V LVCMOS

3.3V I²C

0

3.3V LVDS

0.6

0

V_O

USB

VDD33

VDD_DMD

V

3.3V LVCMOS

3.3V I²C

0

1.9V LPDDR

0

Environmental

T_J

Operating junction temperature

0

85

ºC

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POWER CONSUMPTION

Table 4 lists the typical current and power consumption of the individual supplies.

Normal mode refers to operation during full functionality, active product operation. Typical values correspond to

power dissipated on nominal process devices operating at nominal voltage and 70°C junction temperature

(approximately 25°C ambient) displaying typical video-graphics content from a high frequency source. Maximum

values correspond to power dissipated on fast process devices operating at high voltage and 105°C junction

temperature (approximately 55°C ambient) displaying typical video-graphics content from a high frequency

source. The increased power dissipation observed on fast process devices operated at maximum recommended

temperatures is primarily a result of increased leakage current. Maximum power values are estimates and may

not reflect the actual final power consumption of the device.

Table 4. Power Consumption

PARAMETER

CONDITIONS

Normal Mode

MIN

NOM

600

30

MAX UNIT

I_CC12

Supply Voltage, 1.2V core power

Supply Voltage, 1.9V I/O power (DMD LPDDR)

Supply Voltage, 3.3V (I/O) power

1020

50

mA

I_{CC19_DMD}

I_CC33

Normal Mode

40

70

I_{CC12_FPD}

I_{CC33_FPD}

I_{CC12_PLLD}

I_{CC12_PLLM}

FPD-Link LVDS Interface Supply Voltage, 1.2V power Normal Mode

FPD-Link LVDS Interface Supply Voltage, 3.3V power Normal Mode

60

100

85

50

Supply Voltage, PLL Digital Power (1.2V)

Normal Mode

9

15

Supply Voltage, Master Clock Generator PLL Digital

power (1.2V)

9

10

15

I_{CC18_PLLD}

I_{CC18_PLLM}

Supply Voltage, PLL Analog power (1.8V)

Normal Mode

mA

Supply Voltage, Master Clock Generator PLL Analog Normal Mode

power (1.8V)

Total Power

Normal Mode

1225

2200

mW

22

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I/O Characteristics

Voltage and current characteristics for each I/O type signal. All inputs and outputs are LVCMOS.

Table 5. I/O Characteristics⁽¹⁾

PARAMETER

USB (9)

CONDITIONS

MIN

2.0

2.4

NOM

MAX UNIT

OSC (10)

V_IH

High-level input voltage

V

3.3V LVCMOS (1, 2, 3, 4)

3.3V I²C (8)

USB (9)

0.8

OSC (10)

0.8

V

V_IL

Low-level input voltage

3.3V LVCMOS (1, 2, 3, 4)

3.3V I²C

0.8

1.0

USB (9)

2.8

High-level output

voltage

3.3V LVCMOS (1, 2, 3)

1.9V DMD LPDDR (7)

I_OH= Max Rated

V_OH

V

0.9 ×

VDD_DMD

I_OH= -0.1 mA

USB (9)

0.3

0.4

3.3V LVCMOS (1, 2, 3)

1.9V DMD LPDDR (7)

I_OL= Max Rated

I_OL= +0.1 mA

I_OL= 3 mA sink

Low-level output

voltage

V_OL

V

0.1 ×

VDD_DMD

3.3V I²C (8)

0.4

Input differential

threshold

3.3V LVDS (5)

V_IDTH

-200

200

mV

USB (9)

200

0.8

Absolute input

differential voltage

|V_ID

|

3.3V LVDS (5)

USB (9)

600

2.5

3.3V LVDS (5)

at MIN absolute input differential

voltage

Input Common Mode

Voltage Range

0.7

0.9

2.1

1.9

V_ICM

V

3.3V LVDS (5)

at MAX absolute input differential

voltage

3.3V LVCMOS (1, 2, 3, 4)

3.3V I²C (8)

400

550

320

V_HYSHysteresis (V_T+- V_T-

)

mV

USB (9)

Receiver input

impedance

3.3V LVDS (5)

R_I

VDDH = 3.3V

V_IH= VDD33

90

110

132

Ω

USB (9)

10

OSC (10)

3.3V LVCMOS (1, 2, 3, 4) without

IPD

High-level input current

(IPD = internal pull-

down)

10

I_IH

µA

3.3V LVCMOS (1, 2, 3, 4) with

IPD

V_IH= VDD33

200

3.3V I²C (8)

USB (9)

10

-10

OSC (10)

3.3V LVCMOS (1, 2, 3, 4) without

IPU

Low-level input

current(IPU = internal

pull-up)

V_OH= VDD33

-10

I_IL

µA

3.3V LVCMOS (1, 2, 3, 4) with

IPU

V_OH= VDD33

-200

-10

3.3V I²C (8)

USB (9)

17.08

-4.0

1.9V DMD LPDDR (7)

3.3V LVCMOS (1)

3.3V LVCMOS (2)

3.3V LVCMOS (3)

V_O= 1.5V

V_O= 2.4V

High-level output

current

I_OH

-4.0

mA

-8.0

-12.0

(1) Numbers in parentheses correspond with Table 6.

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MAX UNIT

Table 5. I/O Characteristics⁽¹⁾(continued)

PARAMETER

CONDITIONS

MIN

-17.08

4.0

NOM

USB (9)

1.9V DMD LPDDR (7)

V_O= 0.4V

3.3V LVCMOS (1)

3.3V LVCMOS (2)

3.3V LVCMOS (3)

3.3V I²C (8)

4.0

Low-level output

current

I_OL

mA

8.0

12.0

3.0

USB (9)

-10

10

High-impedance

leakage current

3.3V LVCMOS (1, 2, 3)

3.3V I²C (8)

-10

10

I_OZ

µA

pF

-10

USB (9)

11.3

2.8

12.8

3.3

14.7

4.0

3.3V LVCMOS (2)

3.3V LVCMOS 4)

3.3V I²C (8)

Input capacitance

(including package)

C_I

2.7

3.4

4.2

3.0

3.2

3.5

Table 6. I/O Type Subscript Definition

I/O

SUBSCRIPT

DEFINITION

1

2

3.3V LVCMOS I/O Buffer, with 4 mA Drive

3.3V LVCMOS I/O Buffer, with 8 mA Drive

3.3V LVCMOS I/O Buffer, with 12 mA Drive

3.3V LVCMOS Receiver

3

4

5

3.3V LVDS Receiver (FPD-Link Interface)

N/A

6

7

1.9V LPDDR Output Buffer (DMD Interface)

3.3V I²C with 12 mA Sink

8

9

USB Compatible (3.3 Volts)

10

OSC 3.3V I/O Compatible LVCMOS

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Interface Timing Requirements

This section defines the timing requirements for the external interfaces for the DLPC350 Controller.

I²C Electrical Data/Timing

Table 7. I²C0 and I²C1 INTERFACE TIMING REQUIREMENTS

PARAMETER

MIN

0

MAX UNIT

f_scl

t_sch

t_scl

t_sp

I²C clock frequency

I²C clock high time

I²C clock low time

I²C spike time

I²C serial-data setup time

I²C serial-data hold time

I²C input rise time

I²C output fall time

I²C bus free time between stop and start conditions

I²C start or repeat start condition setup

I²C start or repeat start condition hold

I²C stop condition setup

400

kHz

µs

ns

µs

pF

1

20

t_sds

t_sdh

t_icr

100

30

1.3

1

t_ocf

t_buf

t_sts

t_sth

t_sph

50 pF

200

1

Valid-data time

SCL low to SDA output valid

1

t_vd

Valid-data time of ACK condition

I²C bus capacitive load

ACK signal from SCL low to SDA (out) low

t_sch

0

100

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V

CC

R

L

= 1 kΩ

SDA

DUT

C

L

= 50 pF

(see Note A)

SDA LOAD CONFIGURATION

Three Bytes for Complete

Device Programming

Stop

Condition Condition

(P) (S)

Start

Address

Bit 7

(MSB)

R/W

Bit 0

(LSB)

Data

Bit 7

(MSB)

Data

Bit 0 Condition

(LSB)

Stop

Address

Bit 6

Address

Bit 1

ACK

(A)

(P)

t

scl

t

sch

0.7 × V

0.3 × V

CC

SCL

SDA

CC

t

icr

t

sts

t

PHL

t

icf

t

buf

t

sp

PLH

0.7 × V

0.3 × V

CC

t

icf

t

icr

t

sdh

t

sps

t

sth

t

sds

Repeat

Start

Condition

Stop

Condition

Start or

Repeat

Start

Condition

VOLTAGE WAVEFORMS

BYTE

1

DESCRIPTION

2

I C address

2, 3

P-port data

A. C_Lincludes probe and jig capacitance.

Figure 12. I²C Interface Load Circuit and Voltage Waveforms

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Port 1 Input Pixel Interface

Table 8. Port 1 Input Pixel Interface Timing Requirements

PARAMETER

Clock frequency, P1A_CLK

TEST CONDITIONS

MIN

12

MAX

150

UNIT

MHz

ns

f_clock

t_c

Cycle time, P1A_CLK

6.666

83.330

t_jp

Clock jitter, P1A_CLK (Deviation in period from ideal)⁽¹⁾

Maximum f_clock

t_w(L)

t_w(H)

Pulse duration low, P1A_CLK

50% reference points

2.3

ns

Pulse duration high, P1A_CLK

Setup time – P1_(A-C)(9-0), P1_VSYNC, P1_HSYNC,

P1_FIELD, P1_DATEN; Valid before P1A_CLK↑↓

t_su

50% reference points

3

ns

Hold time – P1_(A-C)(9-0), P1_VSYNC, P1_HSYNC, P1_FIELD,

P1_DATEN; Valid after P1A_CLK↑↓

t_h

t_t

50% reference points

3

0.6

ns

Transition time -- P1A_CLK

20% to 80% reference points

2.0

3.0

Transition time -- P1_A(9-0), P1_B(9-0), P1_C(9-0),

P1_HSYNC, P1_VSYNC, P1_DATEN

t_t

(1) For frequencies ( f_clock) less than 150 MHz, clock jitter (in ns) should be calculated using this formula: Max Clock Jitter = ±[ 1/ f_clock

5414 ps].

–

Figure 13. Port 1 Input Pixel Timing

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Port 2 Input Pixel Interface (FPD-Link Compatible LVDS Input)

Table 9. Port 2 Input Pixel Interface (FPD-Link Compatible LVDS Input) Timing Requirements

PARAMETER

TEST CONDITIONS

MIN

20

MAX UNIT

f_clock

t_c

Clock frequency, P2_CLK (LVDS input clock)

Cycle time, P2_CLK (LVDS input clock)

90

MHz

ns

11.1

0.3

50.0

f_pxck< 90 MHz

f_pxck> 90 MHz

t_slew

Clock or data slew rate

V/ns

ms

0.5

t_startupLink startup time (internal)

1

Extra Notes:

Minimize cross-talk and match traces on PCB as close as possible.

It is recommended to keep the Common Mode Voltage as close to 1.2V as possible.

It is recommended to keep the Absolute Input Differential Voltage as high as possible.

The LVDS open input detection is only related to a low common mode voltage; it is not related to a low

differential swing.

LVDS power 3.3V supply (VDD33_FPD) noise level should be below 100 mV_p-p

.

LVDS power 1.2V supply (VDD12_FPD) noise level should be below 60 mV_p-p

.

Figure 14. LVDS Timing Diagram

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Figure 15. (LVDS) Link Start-Up Timing

Figure 16. (LVDS) Clock: Data Skew Definition

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Table 10. (LVDS) Receiver Supported Pixel Mapping Modes

Mapping Selection 4

LVDS Receiver Input

Mapping Selection 1

Mapping Selection 2

Mapping Selection 3

(18-bit Mode)

RA Input Channel

RDA(6)

RDA(5)

RDA(4)

RDA(3)

RDA(2)

RDA(1)

RDA(0)

map to GRN(4)

map to RED(9)

map to RED(8)

map to RED(7)

map to RED(6)

map to RED(5)

map to RED(4)

map to GRN(2)

map to RED(7)

map to RED(6)

map to RED(5)

map to RED(4)

map to RED(3)

map to RED(2)

map to GRN(0)

map to RED(5)

map to RED(4)

map to RED(3)

map to RED(2)

map to RED(1)

map to RED(0)

map to GRN(4)

map to RED(9)

map to RED(8)

map to RED(7)

map to RED(6)

map to RED(5)

map to RED(4)

RB Input Channel

RDB(6)

RDB(5)

RDB(4)

RDB(3)

RDB(2)

RDB(1)

RDB(0)

map to BLU(5)

map to BLU(4)

map to GRN(9)

map to GRN(8)

map to GRN(7)

map to GRN(6)

map to GRN(5)

map to BLU(3)

map to BLU(2)

map to GRN(7)

map to GRN(6)

map to GRN(5)

map to GRN(4)

map to GRN(3)

map to BLU(1)

map to BLU(0)

map to GRN(5)

map to GRN(4)

map to GRN(3)

map to GRN(2)

map to GRN(1)

map to BLU(5)

map to BLU(4)

map to GRN(9)

map to GRN(8)

map to GRN(7)

map to GRN(6)

map to GRN(5)

RC Input Channel

RDC(6)

RDC(5)

RDC(4)

RDC(3)

RDC(2)

RDC(1)

RDC(0)

map to DEN

map to VSYNC

map to HSYNC

map to BLU(9)

map to BLU(8)

map to BLU(7)

map to BLU(6)

map to BLU(7)

map to BLU(5)

map to BLU(4)

map to BLU(3)

map to BLU(2)

map to BLU(9)

map to BLU(8)

map to BLU(7)

map to BLU(6)

map to BLU(5)

map to BLU(4)

RD Input Channel

RDD(6)

RDD(5)

RDD(4)

RDD(3)

RDD(2)

RDD(1)

RDD(0)

map to Field (option 1 if available)

map to BLU(3)

map to BLU(2)

map to GRN(3)

map to GRN(2)

map to RED(3)

map to RED(2)

map to BLU(9)

map to BLU(8)

map to GRN(9)

map to GRN(8)

map to RED(9)

map to RED(8)

map to BLU(7)

map to BLU(6)

map to GRN(7)

map to GRN(6)

map to RED(7)

map to RED(6)

NO MAPPING

RE Input Channel

RDE(6)

RDE(5)

RDE(4)

RDE(3)

RDE(2)

RDE(1)

RDE(0)

map to Field (option 2 if available)

map to BLU(1)

map to BLU(9)

map to BLU(8)

map to GRN(9)

map to GRN(8)

map to RED(9)

map to RED(8)

NO MAPPING

map to BLU(0)

map to GRN(1)

map to GRN(0)

map to RED(1)

map to RED(0)

Mapping options are selected via software. If Mapping Option #4 above is the only mapping mode needed, and if

and only if a "Field 1" or "Field 2" input is not needed, then the board layout can leave the LVDS inputs for RD

and RE channels only.

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Video Timing Input Blanking Specification

The DLPC350 requires a minimum horizontal and vertical blanking for both Port 1 and Port 2. These parameters

indicate the time allocated to retrace the signal at the end of each line and field of a display. This section defines

the related parameters

Video Timing Parameter Definitions

VS

Vertical Sync

Timing reference point that indicates the start of the vertical interval (frame). The absolute

reference point is defined by the active edge of the VS signal. This active edge is the

reference from which all Vertical Blanking parameters are measured

HS

Horizontal Sync

Timing reference point that indicates the start of the horizontal interval (line). The absolute

reference point is defined by the active edge of the HS signal. This active edge is the

reference from which all Horizontal Blanking parameters are measured

TLPF Total Lines (active and inactive) Per Frame

Defines the Vertical Period (or frame time) in lines

ALPF Active Lines Per Frame

Number of lines in a frame containing displayable data. This is a subset of the TLPF

TPPL Total Pixel Per Line

Horizontal Line Period in pixel clocks. Total number of active and inactive pixel clocks per

line

APPL Active Pixels Per Line

Number of pixel clocks in a line containing displayable data. This is a subset of the TPPL

VBP Vertical Back Porch blanking

Number of blank lines after Vertical Sync but before the first active line

VFP Vertical Front Porch blanking

Number of blank lines after the last active line but before Vertical Sync

HBP Horizontal Back Porch blanking

Number of blank pixel clocks after Horizontal Sync but before the first active pixel. HBP

times are in reference to the leading (active) edge of the respective sync signal

HFP Horizontal Front Porch blanking

Number of blank pixel clocks after the last active pixel but before Horizontal Sync

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Source Input Blanking

The Vertical and Horizontal Blanking requirements for both input ports are defined below. Reference the Video

Timing Parameter Definitions listed above.

Table 11. Source Input Blanking Requirements

PORT

PARAMETER

MINIMUM BLANKING

VBP

370 µs

Port 1 Vertical Blanking

VFP

2 lines

Total Vertical Blanking

370 µs + 3 lines

VBP

370 µs

Port 2 Vertical Blanking

VFP

0 lines

370 µs + 3 lines

Total Vertical Blanking

HBP

10 pixels

Port 1 and 2 Horizontal

Blanking

HFP

0 pixels

Total Horizontal Blanking for 0.45 WXGA DMD

154,286 ÷ Source APPL pixels (round up)

Figure 17. Horizontal and Vertical Blanking Diagram

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Programmable Output Clocks

Table 12. Programmable Output Clocks Timing

PARAMETER

FROM (INPUT)

TO (OUTPUT)

OCLKC

MIN

MAX UNIT

f_clock

t_c

t_w(L)

t_w(H)

Clock frequency, OCLKC

N/A

0.7759

48

MHz

ns

Cycle time, OCLKC

OCLKC

20.83 1288.80

(t_c/2)-2

Pulse duration low (50% reference points)

Pulse duration high (50% reference points)

OCLKC

ns

OCLKC

(t_c/2)-2

ns

f_clock

t_c

t_w(L)

t_w(H)

Clock frequency, OCLKD

N/A

OCLKD

0.7759

48

MHz

ns

Cycle time, OCLKD

20.83 1288.80

(t_c/2)-2

Pulse duration low (50% reference points)

Pulse duration high (50% reference points)

ns

(t_c/2)-2

ns

Figure 18. Programmable Output Clocks Timing Diagram

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DMD Interface

The DLPC350 controller DMD interface is comprised of a combination of both single (SDR) and double data rate

(DDR), and output signals using LPDDR (as defined by JESD209A). SDR signals are referenced to

DMD_SAC_CLK and DDR signals are referenced to DMD_DCLK.

Switching characteristics over recommended operating conditions, C_L(minimum timing) = 5 pF, C_L(maximum

timing) = 25 pF (unless otherwise noted).

Table 13. DMD Interface Timing Requirements

FROM

(INPUT)

PARAMETER

TEST CONDITIONS

TO (OUTPUT)

MIN

MAX

UNIT

f_clock1

Clock frequency⁽¹⁾⁽²⁾

Clock period

n/a

DMD_DCLK

DMD_SAC_CLK

All

79.992 120.012

MHz

ns

t_{p1_clkper}

t_{p1_cwh}

t_{p1_cwl}

f_clock2

50% reference points

n/a

8.332

3.75

74.659

13.391

6

12.502

Clock pulse width low

Clock pulse width high

Clock frequency⁽²⁾

Clock period

n/a

ns

n/a

ns

n/a

74.675

13.394

MHz

ns

t_{p2_clkper}

t_{p2_cwh}

t_{p2_cwl}

t_slew

50% reference points

n/a

Clock pulse width low

Clock pulse width high

Slew rate^(3)(4)(5)

n/a

ns

n/a

6

ns

n/a

0.7

V/ns

both rising

and falling

edges of

DMD_D(23:0),

DMD_SCTRL,

DMD_LOADB,

DMD_TRC

t_{p1_su}

Output setup time⁽⁶⁾

Output hold time⁽⁶⁾

50% reference points

1.1

ns

DMD_DCLK

both rising

and falling

edges of

DMD_D(23:0),

DMD_SCTRL,

DMD_LOADB,

DMD_TRC

t_{p1_h}

DMD_DCLK

DMD_D(23:0),

DMD_SCTRL,

DMD_LOADB,

DMD_TRC,

relative to

each other

t_{p1_skew}

DMD data skew

50% reference points

0.2

ns

DMD_DCLK

rising edge

of

DMD_SAC_BUS,

DMD_DRC_OE,

DMD_SAC_ DMD_DRC_BUS,

t_{p2_su}

Output setup time⁽⁶⁾

Output hold time⁽⁶⁾

50% reference points

2.35

CLK

DMD_DRC_STRB

rising edge

of

DMD_SAC_BUS,

DMD_DRC_OE,

DMD_SAC_ DMD_DRC_BUS,

t_{p2_h}

CLK

DMD_DRC_STRB

DMD_SAC_BUS,

DMD_DRC_OE,

DMD_DRC_BUS,

DMD_DRC_STRB,

DMD_SAC_CLK

relative to

each other

t_{p2_skew}

DRC/SAC data skew

50% reference points

0.2

ns

(1) The controller supports a fixed number of programmable clock rates with the min and max values as shown. The performance may be

further limited by interface voltage and PCB routing.

(2) Note that these vales do not include any tolerance variation of the external crystal/oscillator, nor do they include any associated jitter.

(3) LPDDR Slew rate for the rising edge is measured between VILD(DC) to VIHD(AC) where VILD(DC) = 0.3*VDDQ and VILD(AC) =

0.8*VDDQ.

(4) LPDDR Slew rate for the rising edge is measured between VILD(DC) to VIHD(AC) where VILD(DC) = 0.7*VDDQ and VILD(AC) =

0.2*VDDQ.

(5) The DMD setup and hold time window must be de-rated by 300 ps for each 0.1 V/ns reduction in slew rate below 1V/ns. Thus a 0.7

V/ns slew rate increases this window by 900 ps from 1400 ps to 2300 ps.

(6) Output setup and hold values already include clock jitter, DCD, SSO, ISI noise and PCB variation. Only routing skew and DMD

setup/hold need to be considered in system timing analysis.

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Figure 19. DMD Interface Timing

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System Oscillator and JTAG Interfaces

Table 14. System Oscillator Timing Requirements

PARAMETER

Clock frequency, MOSC⁽⁷⁾

Cycle time, MOSC⁽⁷⁾

Pulse duration (high), MOSC⁽⁸⁾

Pulse duration (low), MOSC⁽⁸⁾

Transition time, MOSC⁽⁸⁾

TEST CONDITIONS

MIN

31.9968

31.188

12.5

MAX UNIT

f_clock

t_c

32.0032

MHz

ns

31.256

t_w(H)

t_w(L)

t_t

50% reference points

ns

12.5

ns

20% to 80% reference points

7.5

ns

Period jitter, MOSC⁽⁸⁾(Deviation in period from ideal

period solely due to high frequency jitter and not

spectrum clocking)

t_jp

-100

+100

ps

Figure 20. System Oscillators Timing

(7) The frequency range for MOSC is 32 MHz with ±100 PPM accuracy. This shall include impact to accuracy due to aging, temperature

and trim sensitivity. The MOSC input cannot support spread spectrum clock spreading.

(8) Applies only when driven via an external digital oscillator.

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Table 15. JTAG Interface: I/O Boundary Scan Application Timing Requirements

PARAMETER

Clock frequency, TCK

TEST CONDITIONS

MIN

MAX

UNIT

MHz

ns

f_clock

t_c

10

Cycle time, TCK

100

40

8

t_w(L)

t_w(H)

t_su

Pulse duration low, PCLK

50% reference points

ns

Pulse duration high, PCLK

Setup time – TDI, TMS1; Valid before TCK↑↓

Hold time – TDI, TMS1; Valid after TCK↑↓

Transition time

ns

20% to 80% reference points

ns

t_h

2

ns

t_t

5

ns

(1)

t_pd

Output propagation, Clock to Q

From (Input) TCK↓ to (Output) TDO1

3

12

ns

(1) Switching characteristics over recommended operating conditions, C_L(minimum timing) = 5 pF, C_L(maximum timing) = 85 pF (unless

otherwise noted).

Figure 21. Boundary Scan Timing

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System Power and Reset

There are several factors related to System Power and Reset which affect the DC error (offset) and AC noise at

the DLPC350 power pins.

Default Conditions

At system power-up, the DLPC350 performs a power-up initialization routine that will default the controller to its

normal power mode, related clocks will be enabled at their full rate, and associated resets will be released. Most

other clocks will default to "disabled" with associated resets asserted until released by the processor. These

same defaults will also be applied as part of all system reset events that occur without removing or recycling

power.

Following power-up or system reset initialization, the system will boot from an external flash memory after which

it will enable the rest of the controller clocks. Once system initialization is complete, application software will

determine if and when to enter standby mode.

1.2V System Power

The controller supports a low cost power delivery system with a single 1.2V power source derived from a

switching regulator. The main core should receive 1.2V power directly from the regulator output, and the internal

DLPC350 PLLs (VDD_12_PLLM, VDD_12_PLLD) should receive individually filtered versions of this 1.2V power.

See PLL for specific filter recommendations.

1.8V System Power

A single 1.8V power source should be used to supply both internal PLLs (VDD_18_PLLM, VDD_18_PLLD). In

order to keep the power as clean as possible, it is recommended that this power be sourced via a linear regulator

that is individually filtered for each PLL. See PLL for specific filter recommendations.

1.9V System Power

In order to maximize signal integrity, it is recommended that an independent linear regulator be used to source

the 1.9V supply that supports the DMD interface (VDD_DMD). To achieve maximum performance, this supply

must be tightly regulated to operating within a 1.9V ±0.1V range.

3.3V System Power

The DLPC350 supports a low cost power delivery system with a single 3.3V power source derived from a

switching regulator. This 3.3V power will supply all LVCMOS I/O. 3.3V power (VDD33) should remain active in all

power modes for which the 1.2V core power is applied.

FPD-Link Input LVDS System Power

The controller supports an FPD-Link compatible LVDS input for an additional method of inputting video/graphics

data for display. This interface has some special controller power considerations that are separate from the other

controller 1.2V or 3.3V power rails. An FPD-Link 1.2V power pin configuration example is shown in below.

Figure 22. FPD-Link 1.2V Power Pin Configuration

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In addition, it is recommended to place the 0.1µF low ESR (equivalent series resistance capacitors to ground as

close to the FPD-Link power pins of the DLPC350 as possible. FPD-Link 3.3V power pins should also use

external capacitors in the same manner as the 1.2V pins. When FPD-Link is not utilized, the filtering can be

omitted. The corresponding voltages, however, MUST still be provided in order to avoid potential long-term

reliability issues.

Figure 23. Initialization Timeline

System Power-Up/Down Sequence

Although the DLPC350 requires an array of power supply voltages, (e.g., VDDC, VDD_1X_PLLX, VCC_18,

VCC_DMD, VCCXX_FPD), there are no restrictions regarding the relative order of power supply sequencing to

avoid damaging the DLPC350. This is true for both power-up and power-down. Similarly, there is no minimum

time between powering up or powering down the different supplies of the DLPC350. Note, however, that it is not

uncommon for there to be power-sequencing requirements for other devices that share power supplies with the

DLPC350.

Although there is no risk of damaging the DLPC350 as a result of a given power sequence, from a functional

standpoint there are a few specific power-sequencing recommendations to ensure proper operation.

•

1.2V Core power should be applied whenever any I/O power is applied. This ensures that the powered I/O

pins are set to a known state. Thus, it is recommended that core power be applied first. Other supplies should

be applied only after the 1.2V DLPC350 core has ramped up.

•

All controller power should be applied before POSENSE is asserted to ensure proper power-up initialization is

performed. 1.8V PLL power, 1.9V I/O power and 3.3V I/O power should remain applied as long as 1.2V core

power is applied and POSENSE is asserted.

It is assumed that all DLPC350 power-up sequencing is handled by external hardware. It is also assumed that an

external power monitor will hold the DLPC350 in system reset during power-up (itaht is, POSENSE = 0). It

should continue to assert system reset until ALL DLPC350 voltages have reached minimum specified voltage

levels. During this time, all controller I/O will either be tri-stated or driven low. The master PLL (PLLM) will be

released from reset upon the low to high transition of POSENSE but the DLPC350 will keep the rest of the

controller in reset for an additional 100 ms to allow the PLL to lock and stabilize its outputs. After this 100 ms

delay, internal resets will be de-asserted causing the microprocessor to begin its boot-up routine.

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Figure 24. Power-Up/Down Timing

Power-On Sense (POSENSE) Support

It is difficult to set up a power monitor to trip exactly on the DLPC350 minimum supply voltages specifications.

Thus, it is recommended that the external power monitor generating POSENSE target its threshold to 90% of the

minimum supply voltages and ensure that POSENSE remain low for a sufficient amount of time to allow all

supply voltages to reach minimum controller requirements and stabilize. Note that the trip voltage for detecting

the loss of power is not critical for POSENSE and thus may be as low as 50% of rated supply voltages. In

addition, the reaction time to respond to a low voltage condition is not critical for POSENSE. INIT_DONE has

much more critical requirements in these areas.

Power-Good (PWRGOOD) Support

The PWRGOOD signal is defined to be an early warning signal that should alert the controller 500 µs before DC

supply voltages have dropped below specifications. This allows the controller time to park the DMD, ensuring the

integrity of future operation. It is recommended that monitor sensing PWRGOOD be on the input side of the

supply regulators.

5V Tolerant Support

With the exception of USB_DAT, the DLPC350 does not support any other 5V tolerant I/O.

40

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Power Reset Operation

Immediately following a power-up event, the DLPC350 hardware will automatically bring up the Master PLL and

place the controller in NORMAL power mode. It will then follow the standard System Reset procedure (see next

section).

System Reset Operation

Immediately following any type of system reset (power-up reset, PWRGOOD reset, etc.), the DLPC350 will

automatically return to NORMAL power mode and return to the following state:

•

All GPIO will tri-state and as a result all GPIO controlled voltage switches will default to enabling power to all

the DLPC350 supply lines (assuming that these outputs are externally pulled-high).

•

The Master PLL will remain active (it is only reset on a power-up reset) and most of the derived clocks will be

active. However, only those resets associated with the internal processor and its peripherals will be released.

•

The internal processor associated clocks will default to their full clock rates, as boot-up occurs at full speed).

The PLL feeding the DDR DMD Interface (PLLD) will default to its Power Down mode, and all derived clocks

will be inactive with the corresponding resets asserted.

•

The DMD interface (except DMD_DRC_OE) will default its outputs to a logic low state. DMD_DRC_OE will

default to tri-state, but should be pulled high via an external 30KΩ to 51KΩ pull-up resistor on the PCB.

All resets outputted by the DLPC350 will remain asserted until released by the internal processor (after boot-

up).

The DLPC350 will boot-up from external Flash. After the DLPC350 boots, it will:

–

Configure the programmable DDR Clock Generator (DCG) clock rates (i.e. the DMD LPDDR interface

rate).

–

Enable the DCG PLL (PLLD) while holding the divider logic in reset.

Once the DCG PLL locks, the firmware will set the DMD clock rates.

The DLPC350 firmware will then release the DCG divider logic resets, which in turn, will enable all derived

DCG clocks.

•

After the clocks are configured, an Internal Memory Test is performed. See Figure 25 and note that GPIO26

is the INIT_DONE signal.

Application software should wait for a wake-up command from the user. Once the controller is requested to

"wake-up," the software should place the controller back in NORMAL mode and re-initialize clocks and resets as

required.

Figure 25. Internal Memory Test Diagram

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Table 16. Reset Timing Requirements

PARAMETER

TEST CONDITIONS

50% reference points

MIN

MAX

625

1

UNIT

µs

t_w1(L)

t_t1

t_w2(L)

t_t2

Pulse duration, inactive low, PWRGOOD

Transition time, PWRGOOD

4

20% to 80% reference points

50% reference points

µs

Pulse duration, inactive low, POSENSE

Transition time, POSENSE

500

µs

20% to 80% reference points

µs

Power hold time, POSENSE remains active after

PWRGOOD is de-asserted

t_PH

20% to 80% reference points

µs

42

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General PCB Recommendations

General Handling Guidelines for CMOS-type Pins

To avoid potentially damaging current caused by floating CMOS input-only pins, it is recommended that unused

input pins be tied through a pull-up resistor to its associated power supply, or a pull-down to ground. For inputs

with internal pull-up or pull-down resistors, it is unnecessary to add an external pull-up or pull-down unless

specifically recommended. Note that internal pull-up and pull-down resistors are weak and should not be

expected to drive the external line.

Bi-directional pins are configured as inputs as a reset default.

Unless specifically specified, pull-up and pull-down resistors can be 10 kΩ.

Unused output-only pins can be left open.

Program Memory Flash Interface

The DLPC350 provides two external program memory chip selects.

•

PM_CS_1 - mandatory CS for Boot Flash device (Standard "NOR" Flash ≤ 128 Mb)

PM_CS_2 - available for optional Flash device ( ≤ 128 Mb)

The Flash access timing is software programmable up to 31 wait states. Wait state resolution is 6.7 nanoseconds

in normal mode, and 53.57 nanoseconds in low power modes. To calculate the wait state values:

Wait State Value = Device Access Time ÷ Wait State Resolution

where the Wait State Value is rounded up. This equation assume a maximum single direction trace length of 75

mm. When another device such as an additional Flash is used in conjunction with the Boot Flash, stub lengths

must be kept short and located as close as possible to the Flash end of the route.

The DLPC350 provides enough Program Memory address pins to support a flash device up to 128 Mb. There

are two bi-directional pins (PM_ADDR_22 and PM_ADDR_21) that can be programmed as additional address

pins once the software configures them. Enabling PM_ADDR_21 increases the Flash size from 32 Mb to 64 Mb.

Enabling PM_ADDR_22 as well as PM_ADDR_21 increases the Flash size to 128 Mb. If these pins are used,

then they require board-level pull-down resistors to prevent the Flash address bits from floating.

Thermal Considerations

The underlying thermal limitation for the DLPC350 is that the maximum operating junction temperature (T_J) must

not be exceeded (see Recommended Operating Conditions). This temperature is dependent on operating

ambient temperature, airflow, PCB design (including the component layout density and the amount of copper

used), power dissipation of the DLPC350, and power dissipation of surrounding components. The DLPC350

package is designed primarily to extract heat through the power and ground planes of the PCB, thus copper

content and airflow over the PCB are important factors.

Table 17. Thermal Characteristics

PARAMETER

MAXIMUM VALUE

UNITS

°C/W

(1)

R_θJC

Thermal Resistance, Junction to Case

Thermal Resistance, Junction to Air

6.6

R

_θJAat 0 m/s of forced airflow⁽²⁾

_θJAat 1 m/s of forced airflow⁽²⁾

_θJAat 2 m/s of forced airflow⁽²⁾

19.4

16.7

15.8

Temperature variance from junction to package top center

temperature, per unit power dissipation.

Psi-jt⁽³⁾

0.33

°C/W

(1)

R_θJCanalysis assumptions: The heat generated in the chip flows both into over-mold (top side) and into the package laminate (bottom

side) and then into the PCB via package solder balls. This should be used for heat sink analysis only.

(2) Thermal coefficients abide by JEDEC Standard 51. R_θJAis the thermal resistance of the package as measured using a JEDEC defined

standard test PCB. This JEDEC test PCB is not necessarily representative of the DLPC350 PCB and thus the reported thermal

resistance may not be accurate in the actual product application. Although the actual thermal resistance may be different , it is the best

information available during the design phase to estimate thermal performance.

(3) Example: (3 W) x (0.33 °C/W) = approximately a 1.00°C temperature rise.

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Recommended MOSC Crystal Oscillator Configuration

The DLPC350 requires an external reference clock to feed its internal PLL. This reference may be supplied via a

crystal or oscillator. The DLPC350 accepts a reference clock of 32 MHz with a maximum frequency variation of

100 ppm (including aging, temperature and trim component variation). When a crystal is used, several discrete

components are also required as shown in Figure 26.

Figure 26. Recommended Crystal Oscillator Configuration

Table 18. Crystal Port Electrical Characteristics

PARAMETER

NOM

3.9

UNIT

pF

MOSC TO GND capacitance

MOSCN TO GND capacitance

3.8

pF

44

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Table 19. Recommended Crystal Configuration

PARAMETER

RECOMMENDED

Parallel resonant

Fundamental (first harmonic)

32

UNIT

Crystal circuit configuration

Crystal type

Crystal nominal frequency

MHz

PPM

Crystal frequency tolerance (including accuracy,

temperature, aging and trim sensitivity)

±100

Crystal equivalent series resistance (ESR)

Crystal load

50 max

10

Ω

pF

Crystal shunt load

7 max

±30

pF

Crystal frequency temperature stability

R_Sdrive resistor (nominal)

R_FBfeedback resistor (nominal)

PPM

Ω

100

1

MΩ

Typical Drive Level with TCX9C3207001 crystal

(ESRmax = 30Ω) = 160 µW. See Figure 26

C_L1external crystal load capacitor (MOSC)

pF

Typical Drive Level with TCX9C3207001 crystal

(ESRmax = 30Ω) = 160 µW. See Figure 26

C_L2external crystal load capacitor (MOSCN)

PCB layout

A ground isolation ring around the crystal is recommended

If an external oscillator is used, then the oscillator output must drive the MOSC pin on the DLPC350 controller,

and the MOSCN pin should be left unconnected. The benefit of an oscillator is that it can be made to provide a

spread-spectrum clock that reduces EMI. Note, however, that the DLPC350 can only accept 0%, ±0.5%, and

±1.0% (center-spread modulation), and a triangular waveform.

Similar to the crystal option, the oscillator input frequency is limited to 32 MHz.

It is assumed that the external crystal or oscillator stabilizes within 50 ms after stable power is applied.

PLL

The following guidelines are recommended to achieve desired controller performance relative to the internal

PLLs.

The DLPC350 contains two PLLs (PLLM and PLLD), each of which have dedicated 1.2V digital and 1.8V analog

supply. These 1.2V PLL pins should be individually isolated from the main 1.2V system supply via a ferrite bead.

The impedance of the ferrite bead should be much greater than the capacitor at frequencies where noise is

expected. The impedance of the ferrite bead must also be less than 0.5Ω in the frequency range of 100-300KHz

and greater than 10Ω at frequencies greater than 100MHz.

As a minimum, the 1.8V analog PLL power and ground pins should be isolated using an LC filter with a ferrite

bead serving as the inductor and a 0.1µF capacitor on the DLPC350 side of the ferrite bead. It is recommended

that this 1.8V PLL power be supplied from a dedicated linear regulator and each PLL should be individually

isolated from the regulator. The same ferried recommendations described for the 1.8V analog PLL supply apply

to the 1.2V digital PLL supply.

When describing the overall supply filter network, care must be taken to ensure that no resonances occur.

Particular care must be taken in the 1-2MHz band, as this coincides with the PLL natural loop frequency.

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Figure 27. PLL Filter Layout

High frequency decoupling is required for both 1.2V and 1.8V PLL supplies and should be provided as close as

possible to each of the PLL supply package pins. It is recommended that decoupling capacitors be placed under

the package on the opposite side of the board. High quality, low-ESR, monolithic, surface mount capacitors

should be used. Typically 0.1 µF for each PLL supply should be sufficient. The length of a connecting trace

increases the parasitic inductance of the mounting and thus, where possible, there should be no trace, allowing

the via to butt up against the land itself. Additionally the connecting trance should be made as wide as possible.

Further improvement can be made by placing vias to the side of the capacitor lands or doubling the number of

vias.

The location of bulk decoupling depends on the system design. Typically a good ceramic capacitor in the 10 µF

range is adequate.

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Board Level Test Support

The In-Circuit Tri-State Enable signal (ICTSEN) is a board level test control signal. By driving ICTSEN to a logic

high state, all controller outputs (except TDO1) will be 3-stated.

The DLPC350 also provides JTAG boundary scan support on all I/O signals, non-digital I/O and a few special

signals. The table below defines these exceptions.

Table 20. Signals Not Covered by JTAG

Signal Name

USB_DAT_N

USB_DAT_P

HW_TEST_EN

VPGM

PKG Ball

E3

E2

V7

D17

A3

EXRES

MOSC

A14

MOSCN

A15

RA_IN_P

RA_IN_N

RB_IN_P

RB_IN_N

RC_IN_P

RC_IN_N

RD_IN_P

RD_IN_N

RE_IN_P

RE_IN_N

RCK_IN_P

RCK_IN_N

AB10

AA10

Y11

W11

AB12

AA12

Y13

W13

AB14

AA14

Y9

W9

spacer

REVISION HISTORY

Changes from Original (April 2013) to Revision A

Page

•

Changed the device From: Preview To: Production ............................................................................................................. 1

Changes from Revision A (May 2013) to Revision B

Page

•

Added PIB_CLK and P1C_CLK to Table 2 ........................................................................................................................ 12

Deleted PM_CS_0 from FLASH INTERFACE in Table 2 ................................................................................................... 15

Deleted Y16 and AB17 from the RESERVED PINS list in Table 2 .................................................................................... 18

Added PM_CS_0 to the RESERVED PINS LIST in Table 2 .............................................................................................. 18

Deleted "PM_CS_0 - available for optional Flash device ( ≤ 128 Mb)" From the Program Memory Flash Interface

section ................................................................................................................................................................................. 43

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型号：	DLPC350_14
厂家：	TEXAS INSTRUMENTS
描述：	Digital Controller for Portable Advanced Light Control
文件：	总50页 (文件大小：1995K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLPC350_14 [TI]

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