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DLPC410

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

DLPC410 DMD 数字控制器

1 特性

3 说明

•

操作以下 DLP^®芯片：

DLPC410 是一种数字控制器，支持五个 DMD 选

1

项：DLP650LNIR、DLP7000、DLP7000UV、

DLP9500 和 DLP9500UV。它是应用电子产品和 DMD

之间的便捷高速数据和控制接口。DLPC410 为

DLPA200 DMD 微镜驱动器提供 DMD 反射镜时钟脉

冲（复位）和时序信息。该器件使用 DLPR410 PROM

中存储的固件进行配置。

–

DLP650LNIR、DLP7000、DLP7000UV、

DLP9500 和 DLP9500UV DMD

–

DLPA200 DMD 微镜驱动器

DLPR410 配置 PROM

•

支持高速 DMD 图形速率

–

1 位二进制模式速率高达 32kHz

8 位单色图形速率高达 4kHz

该系列芯片组支持最高 48 千兆位/秒 (Gbps) 的像素数

据速率，提供单块、双块、四块和全局复位。此外还具

备随机行寻址和 LOAD4 功能。此系列芯片通常用于设

计 UV 和 NIR 光学系统，例如需要快速吞吐量和像素

精确控制的直接成像平版印刷系统、3D 打印和激光打

标系统。

•

400MHz 输入数据时钟速率

64 位 2xLVDS 数据总线接口输入/输出

支持随机行和 LOAD4 DMD 寻址

与多种用户定义的处理器或现场可编程门阵列

(FPGA) 兼容

2 应用

器件信息⁽¹⁾

•

工业：

器件型号

DLPC410

封装

封装尺寸（标称值）

–

直接成像平版印刷

FCBGA (676)

27.00mm x 27.00mm

3D 打印（SLA 和 SLS）

3D 机器视觉

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

用于机器人和检测的 3D 扫描仪

动态灰度激光打标和编码

工业印刷

高速投影和高级成像

消融和修复系统

显微镜

简化应用

LEDs, LASERs,

Lamp

PWMs, Triggers

LED, LASER, Lamp Driver

Optical Sensor

Optical Power Sense

LVDS Data Bus (A,B)

LVDS Data Bus (C, D)

LVDS Data Bus

Row, Block Signals

Control Signals

DLPC410 Info Signals

DLPC410

DLPA200 Control

MBRST 2

MBRST 1

JTAG

DLPA200

D0

Clk

DONE

OE

DLPA200 Control

SCP Bus

DLPR410

DMDs

DLP650LNIR

DLP7000

DLP7000UV

DLP9500

DLP9500UV

Oscillator

Power Managment

TI Components

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: DLPS024

DLPC410

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

www.ti.com.cn

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

说明（续）.............................................................. 5

Pin Configuration and Functions......................... 6

Specifications....................................................... 20

7.1 Absolute Maximum Ratings .................................... 20

7.2 ESD Ratings............................................................ 20

7.3 Recommended Operating Conditions..................... 20

7.4 Electrical Characteristics......................................... 21

7.5 Timing Requirements.............................................. 21

Detailed Description ............................................ 23

8.1 Overview ................................................................. 23

8.2 Functional Block Diagrams ..................................... 24

8.3 Feature Description................................................. 26

8.4 Device Functional Modes........................................ 49

8.5 Programming........................................................... 58

9

Application and Implementation ........................ 59

9.1 Application Information............................................ 59

9.2 Typical Application .................................................. 59

9.3 Initialization Setup................................................... 61

10 Power Supply Recommendations ..................... 65

10.1 Power Down Operation......................................... 65

11 Layout................................................................... 65

11.1 Layout Guidelines ................................................. 65

11.2 Layout Example .................................................... 67

11.3 DLPC410 Chipset Connections ........................... 68

12 器件和文档支持 ..................................................... 77

12.1 器件支持................................................................ 77

12.2 文档支持................................................................ 78

12.3 社区资源................................................................ 78

12.4 商标....................................................................... 78

12.5 静电放电警告......................................................... 78

12.6 术语表 ................................................................... 78

13 机械、封装和可订购信息....................................... 78

8

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision E (January 2019) to Revision F

Page

•

Modified functions for TP4-TP31 ......................................................................................................................................... 15

Corrected DLP650LNIR Bus A Pixel Mapping .................................................................................................................... 38

Corrected DLP650LNIR Bus A Pixel Mapping .................................................................................................................... 39

Corrected DLP650LNIR Bus B Pixel Mapping .................................................................................................................... 40

Corrected DLP650LNIR Bus B Pixel Mapping .................................................................................................................... 41

Removed ECP2M calibration feedback pins ....................................................................................................................... 62

Removed ECP2M DLPA200 Init Status pin ........................................................................................................................ 62

Removed ECP2M DMD Init Status pin ................................................................................................................................ 62

Adjusted pinouts of DMD OK Status bits ............................................................................................................................ 62

Adjusted pinouts of DMD OK Status bits ............................................................................................................................ 63

Removed the ECP2_M TP20 referring to AA18 instead ..................................................................................................... 63

Changes from Revision D (December 2018) to Revision E

Page

•

已更改 ARST description that was incorrectly described in DLPS024 Revision D. ............................................................. 48

Changes from Revision C (December 2015) to Revision D

Page

•

将 DLP650LNIR 新增至支持的 DMD（多个）........................................................................................................................ 1

将输入数据时钟速率更改为仅 400MHz................................................................................................................................... 1

更新了应用列表，以反映最新市场........................................................................................................................................ 1

更改了简化图表，以包括新的 DLP650LNIR........................................................................................................................... 1

Changed pin DDC_SPARE_0 to LOAD4 ............................................................................................................................ 16

Removed 200MHz - new revision tested at 400MHz only .................................................................................................. 21

Re-organization of Detailed Description for flow, clarity, and readability ............................................................................. 23

2

DLPC410

www.ti.com.cn

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

•

Added DLP650LNIR functional block diagram .................................................................................................................... 24

Updated DLP7000 functional block diagram (no technical changes)................................................................................... 25

Updated DLP9500 functional block diagram (no technical changes)................................................................................... 26

Added new DLP650LNIR DMD Characteristics to 表 2........................................................................................................ 28

Added DLP650LNIR DMD to Row Addressing and 表 11.................................................................................................... 41

Re-worded the Block Operations section for clarity. ........................................................................................................... 45

Added new DLP650LNIR DMD Characteristics ................................................................................................................... 48

Added/edited LOAD4 sections, enabled by DLPR410A....................................................................................................... 49

Removed reference to 200 MHz input data clock. ............................................................................................................... 49

Added the DLP650LNIR and its block load time to 表 16 ................................................................................................... 51

Added 表 17 ......................................................................................................................................................................... 54

Combined Application Example Diagrams to encompass all DLPC410 supported DMDs ................................................. 60

Added DLP650LNIR to Detailed Design procedure section ................................................................................................ 61

Added 图 25 - DLP650LNIR window transmittance ............................................................................................................ 61

Changed "Generate Data" to "Present Data to DLPC410" ................................................................................................. 63

已更改 "DLPC410 DMD data signals" to "LVDS data bus differential pairs"........................................................................ 66

移除了对 TI 器件型号 2510440-001 的引用。...................................................................................................................... 77

删除了 Discovery 芯片组数据表，添加了 DLP650LNIR 数据表，更正了其他器件名称....................................................... 78

Changes from Revision B (June 2013) to Revision C

Page

•

已添加 ESD 额定值表，特性描述部分、器件功能模式、应用和实施部分、电源建议部分、布局部分、器件和文档支

持部分以及机械、封装和可订购信息部分 ............................................................................................................................... 1

删除了对 Discovery 4100 的引用，通篇删除了 DLPR4101 ................................................................................................... 1

已添加 DLP7000UV 和 DLP9500UV 至特性和说明部分的文本 ........................................................................................... 1

Added note - Xlilinx System Monitor analog supply & ground - "must be connected to ground" (AVDD_0 & AVSS_0)....... 7

Changed "DAD A" descriptions to "DLPA200 number 1" and "DAD B" descriptions to "DLPA200 number 2" ..................... 7

Reversed DDC_Bnn_VR pairs pullups / pulldowns (for nn =12, 15, and 16)) ....................................................................... 8

Changed Pin # C22 name from DDC_B11_VRP (duplicate) to DDC_B15_VRP ................................................................. 8

Added "Not used" to description for DMD_B_RESET and DMD_B_SCPEN ...................................................................... 14

Added TP14 and TP17 note - Xilinx Temperature Diode .................................................................................................... 14

Added "in Reference Design" to ECP2 Mictor pin notes...................................................................................................... 14

Changed ECP2 pin description from "Not Defined" to "Not Used" ...................................................................................... 14

Added ECP2_M_TP[3:29] descriptions and active state...................................................................................................... 15

Deleted duplicate pin numbers M13 and M14 ..................................................................................................................... 16

Changed Description from "DMD Power" to "DMD Power Good indicator" ........................................................................ 16

Changed duplicate pin name from RSVD_0 to RSVD_1 ..................................................................................................... 17

Updated pin description for SCPDI and SCPDO ................................................................................................................. 17

Changed STEPVCC to connect to ground, active "Hi" to "-", and clock to "-" .................................................................... 17

Changed Description from "JTAG Data Clock" to "JTAG Data" .......................................................................................... 17

Changed pin names for VCCO_n_n pins to list each pin separately ................................................................................... 18

•

Added note about Xilinx System Monitor differential pins (VN_0 & VP_0) and reference voltage (VREFN_0 &

VREFP_0)............................................................................................................................................................................. 18

•

Changed Description from "DMD Reset Watchdog" to "DMD Mirror Clocking Pulse Watchdog" ....................................... 19

Deleted duplicate pin numbers in "UNUSED" pin list........................................................................................................... 19

Updated the functional block diagrams ................................................................................................................................ 25

Moved DLP7000 / DLP7000UV and DLP9500 / DLP9500UV Example Block Diagrams from Functional Block

Diagram section to Typical Application Section .................................................................................................................. 26

3

DLPC410

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

www.ti.com.cn

•

已删除 the "Step DMD SRAM Memory Voltage" and "Load 4" Enhanced Functionality (with DLPR4101 PROM only)"

sections................................................................................................................................................................................. 48

Updated the embedded example block diagrams................................................................................................................ 60

已添加 DLP7000UV and DLP9500UV well suited for direct imaging lithography, 3D printing, and UV applications .......... 61

已添加 Debugging Guidelines section.................................................................................................................................. 61

已更改 maximum differential trace length from 100 to 150 matching Table 13. .................................................................. 66

已添加 DLP7000UV 和 DLP9500UV 相关文档..................................................................................................................... 78

•

Changes from Revision A (September 2012) to Revision B

Page

•

已更改特性“1 位二进制模式速率高达 32kHz”至“1 位二进制模式速率高达 32kHz（与 DLPR4101 搭配使用时高达

48kHz）”................................................................................................................................................................................. 1

已添加 Section "Load 4" Enhanced Functionality (with DLPR4101 PROM only)................................................................. 49

已添加 DLPR4101 至 DLPR410........................................................................................................................................... 78

•

Changes from Original (August 2012) to Revision A

Page

•

将器件状态从：产品预览改为：生产 ...................................................................................................................................... 1

4

DLPC410

www.ti.com.cn

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

5 说明（续）

在基于 DLP 的电子解决方案中，从 DLPC410 输入端口到投影图像的图像数据是 100% 数字化的数据。图像保持

在数字格式并且永远不会被转换为一个模拟信号。DLPC410 处理数字输入图像并将数据转换为 DMD 所需的图像

格式。然后，针对每个像素镜，DMD 使用二元脉宽调制 (PWM) 来操纵光源。

DLPC410 是一种 DMD 数字控制器，控制 DLP650LNIR、DLP7000、DLP7000UV、DLP9500 和 DLP9500UV

DMD（请参阅图 4、图 5 和图 6）。DLPC410 能够使开发人员轻松访问 DMD 并使用高速独立微镜控制。请参阅

各 DMD 解决方案的必需芯片组元件列表：表 1：

表 1. DLPC410 器件配置

DMD

DMD 微镜驱动器

2 件DLPA200

1 件DLPA200

DMD 数字控制器

DLP9500 DLP 0.95 1080p 2xLVDS A 类 DMD

DLP9500UV DLP 0.95 UV 1080p 2xLVDS A 类 DMD

DLP7000 DLP 0.7 XGA 2xLVDS A 类 DMD

DLP7000UV DLP 0.7 UV XGA 2xLVDS A 类 DMD

DLP650LNIR 0.65 NIR WXGA S450 DMD

DLPC410（+ DLPR410 配置 PROM）

DLPC410UV 需要与表 1 中的其他芯片组元件结合使用才能实现可靠功能和操作。有关芯片组元件的更多信息，

请参阅表 26 中的数据表。

5

DLPC410

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

www.ti.com.cn

6 Pin Configuration and Functions

ZYR Package

676-Pin FCBGA

Bottom View

6

DLPC410

www.ti.com.cn

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

Pin Functions

TERMINATION

/NOTES

ACTIVE

(Hi or Lo)

DATA

RATE

TYPE

SIGNAL

CLOCK

DESCRIPTION

Not Used

NAME

APPS_CNTL_DPN

APPS_CNTL_DPP

ARST

NO.

F7

-

I

-

This pair connected with 100

Ω resistor between pair.

-

E7

Not Used

AC13

LVCMOS25_S_

12_I

Lo

DLPC410 Reset

AVDD_0

AVSS_0

M14

M13

-

Not used - connect to

Ground (no name in

Reference Design)

-

Xilinx System Monitor analog

supply - (not used - must be

connected to ground)

-

Not used - connect to

Ground (no name in

Reference Design)

Xilinx System Monitor analog

ground - (not used - must be

connected to ground)

BLKAD_0

BLKAD_1

BLKAD_2

BLKAD_3

BLKMD_0

BLKMD_1

CLKIN_R

COMP_DATA

E12

D13

E13

F13

I

LVCMOS25_S_

12_I

Hi = 1

-

DDC_DCLK_[A,B,C,D]

Reference Clock

Block Address bit 0

Block Address bit 1

Block Address bit 2

Block Address bit 3

Block Mode Bit 0

LVCMOS25_S_

12_I

LVCMOS25_S_

12_I

LVCMOS25_S_

12_I

H13

H14

AD13

G19

LVCMOS25_S_

12_I

LVCMOS25_S_

12_I

Block Mode Bit 1

LVCMOS25_S_

12_I

Reference Clock

LVCMOS25_S_

12_I

Hi

DDC_DCLK_[A,B,C,D]

Compliment Data (0 <--> 1)

CS_B_0

N18

W11

E1

-

1 kΩ pulldown to ground

Lo

-

Xilinx Config

Not Used

D_OUT_BUSY_0

DAD_A_ADDR0

NC

Do not connect

O

LVCMOS25_F_ Connected to DLPA200

12_O number 1 Address 0 pin

Hi = 1

DLPA200 Number 1 Reset

Block bit 0

DAD_A_ADDR1

DAD_A_ADDR2

DAD_A_ADDR3

DAD_A_MODE0

DAD_A_MODE1

DAD_A_SCPEN

DAD_A_SEL0

E2

E3

O

LVCMOS25_F_ Connected to DLPA200

12_O Number 1 Address 1 pin

Hi = 1

Lo

-

DLPA200 Number 1 Reset

Block bit 1

LVCMOS25_F_ Connected to DLPA200

12_O Number 1 Address 2 pin

DLPA200 Number 1 Reset

Block bit 2

F3

LVCMOS25_F_ Connected to DLPA200

12_O Number 1 Address 3 pin

DLPA200 Number 1 Reset

Block bit 3

C1

LVCMOS25_F_ Connected to DLPA200

12_O Number 1 Mode 0 pin

DLPA200 Number 1Mode bit 0

D1

LVCMOS25_F_ Connected to DLPA200

12_O Number 1 Mode 1 pin

DLPA200 Number 1 Mode bit

1

AE3

AB12

AC12

AF3

E26

E25

F25

F24

D26

D25

AB19

R22

R23

AB20

LVCMOS25_F_ Connected to DLPA200

12_O Number 1 SCPEN pin

DLPA200 Number 1 SCP

Communication Enable

LVCMOS25_F_ Connected to DLPA200

12_O Number 1 SEL 0 pin

Hi = 1

Hi

DLPA200 Number 1 Address

bit 0

DAD_A_SEL1

LVCMOS25_F_ Connected to DLPA200

12_O Number 1 SEL 1 pin

DLPA200 Number 1 Address

bit 1

DAD_A_STROBE

DAD_B_ADDR0

DAD_B_ADDR1

DAD_B_ADDR2

DAD_B_ADDR3

DAD_B_MODE0

DAD_B_MODE1

DAD_B_SCPEN

DAD_B_SEL0

LVCMOS25_F_ Connected to DLPA200

12_O Number 1 STROBE pin

DLPA200 Number 1 Transition

Strobe

LVCMOS25_F_ Connected to DLPA200

12_O Number 2 Address 1 pin

Hi = 1

Lo

DLPA200 Number 2 Reset

Block bit 0

LVCMOS25_F_ Connected to DLPA200

12_O Number 2 Address 2 pin

DLPA200 Number 2 Reset

Block bit 1

LVCMOS25_F_ Connected to DLPA200

12_O Number 2 Address 3 pin

DLPA200 Number 2 Reset

Block bit 2

LVCMOS25_F_ Connected to DLPA200

12_O Number 2 Address 0 pin

DLPA200 Number 2 Reset

Block bit 3

LVCMOS25_F_ Connected to DLPA200

12_O Number 2 Mode 0 pin

DLPA200 Number 2 Mode bit

0

LVCMOS25_F_ Connected to DLPA200

12_O Number 2 Mode 1 pin

DLPA200 Number 2 Mode bit

1

LVCMOS25_F_ Connected to DLPA200

12_O Number 2 SCPEN pin

DLPA200 Number 2 SCP

Communication Enable

LVCMOS25_F_ Connected to DLPA200

12_O Number 2 SEL 0 pin

Hi = 1

Hi

DLPA200 Number 2 Address

bit 0

DAD_B_SEL1

LVCMOS25_F_ Connected to DLPA200

12_O Number 2 SEL 1 pin

DLPA200 Number 2 Address

bit 1

DAD_B_STROBE

LVCMOS25_F_ Connected to DLPA200

12_O Number 2 STROBE pin

DLPA200 Number 2 Transition

Strobe

7

DLPC410

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

www.ti.com.cn

Pin Functions (continued)

TERMINATION

/NOTES

ACTIVE

(Hi or Lo)

DATA

RATE

TYPE

SIGNAL

CLOCK

DESCRIPTION

NAME

DAD_INIT

NO.

AF4

O

LVCMOS25_F_ Connected to DLPA200

Hi

-

DLPA200 Number 1 / Number

2 Init

12_O

Number 1 and Number 2

RESET pin

DAD_OE

AF5

O

LVCMOS25_F_ Connected to DLPA200

Lo

-

DLPA200 Number 1 / Number

2 Output Enable

12_O

Number 1 and Number 2 OE

DDC_B11_VRN

L23

L22

M5

M6

D23

C22

A4

-

REFERENCE

LVDS_25

51.1 Ω pullup to 2.5 V

-

Reference Voltage

DDC_B11_VRP

51.1 Ω pulldown to ground

51.1 Ω pullup to 2.5 V

Reference Ground

DDC_B12_VRN

-

Reference Voltage

DDC_B12_VRP

-

51.1 Ω pulldown to ground

51.1 Ω pullup to 2.5 V

Reference Ground

DDC_B15_VRN

-

Reference Voltage

DDC_B15_VRP

-

51.1 Ω pulldown to ground

51.1 Ω pullup to 2.5 V

Reference Ground

DDC_B16_VRN

-

Reference Voltage

DDC_B16_VRP

A5

-

51.1 Ω pulldown to ground

Reference Ground

DDC_DCLK_A_DPN

DDC_DCLK_A_DPP

DDC_DCLK_B_DPN

DDC_DCLK_B_DPP

DDC_DCLK_C_DPN

DDC_DCLK_C_DPP

DDC_DCLK_D_DPN

DDC_DCLK_D_DPP

DDC_DCLKOUT_A_DPN

DDC_DCLKOUT_A_DPP

B21

C21

A7

I

100 Ω across pair (not

terminated in the DLPC410)

Bank A Input Clock (Neg)

Bank A Input Clock (Pos)

Bank B Input Clock (Neg)

Bank B Input Clock (Pos)

Bank C Input Clock (Neg)

Bank C Input Clock (Pos)

Bank D Input Clock (Neg)

Bank D Input Clock (Pos)

Bank A Output Clock (Neg)

Bank A Output Clock (Pos)

I

LVDS_25_I

LVDS_25

I

100 Ω across pair (not

terminated in the DLPC410)

B7

I

LVDS_25_I

LVDS_25

K20

K21

L5

I

100 Ω across pair (not

terminated in the DLPC410)

I

LVDS_25_I

LVDS_25

I

100 Ω across pair (not

terminated in the DLPC410)

K5

I

LVDS_25_I

LVDS_25

N1

O

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

M1

LVDS_25_O

DDC_DCLKOUT_B_DPN

DDC_DCLKOUT_B_DPP

Y5

Y6

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

Bank B Output Clock (Neg)

Bank B Output Clock (Pos)

LVDS_25_O

DDC_DCLKOUT_C_DPN

DDC_DCLKOUT_C_DPP

AA22

AB22

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

Bank C Output Clock (Neg)

Bank C Output Clock (Pos)

LVDS_25_O

DDC_DCLKOUT_D_DPN

DDC_DCLKOUT_D_DPP

M26

M25

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

Bank D Output Clock (Neg)

Bank D Output Clock (Pos)

LVDS_25_O

DDC_DIN_A0_DPN

DDC_DIN_A0_DPP

DDC_DIN_A1_DPN

DDC_DIN_A1_DPP

DDC_DIN_A2_DPN

DDC_DIN_A2_DPP

DDC_DIN_A3_DPN

DDC_DIN_A3_DPP

DDC_DIN_A4_DPN

DDC_DIN_A4_DPP

DDC_DIN_A5_DPN

DDC_DIN_A5_DPP

DDC_DIN_A6_DPN

DDC_DIN_A6_DPP

DDC_DIN_A7_DPN

DDC_DIN_A7_DPP

DDC_DIN_A8_DPN

DDC_DIN_A8_DPP

DDC_DIN_A9_DPN

DDC_DIN_A9_DPP

DDC_DIN_A10_DPN

DDC_DIN_A10_DPP

DDC_DIN_A11_DPN

DDC_DIN_A11_DPP

A15

A14

B14

C14

B16

B15

C16

D16

A17

B17

C17

D18

A19

A18

C18

B19

D19

C19

B20

A20

A22

B22

A24

A23

I

LVDS_25

LVDS_25_I

LVDS_25

100 Ω across pair (not

terminated in the DLPC410)

-

DDC_DCLK_A

DDR

Data A bit 0 Input (Neg)

Data A bit 0 Input (Pos)

Data A bit 1 Input (Neg)

Data A bit 1 Input (Pos)

Data A bit 2 Input (Neg)

Data A bit 2 Input (Pos)

Data A bit 3 Input (Neg)

Data A bit 3 Input (Pos)

Data A bit 4 Input (Neg)

Data A bit 4 Input (Pos)

Data A bit 5 Input (Neg)

Data A bit 5 Input (Pos)

Data A bit 6 Input (Neg)

Data A bit 6 Input (Pos)

Data A bit 7 Input (Neg)

Data A bit 7 Input (Pos)

Data A bit 8 Input (Neg)

Data A bit 8 Input (Pos)

Data A bit 9 Input (Neg)

Data A bit 9 Input (Pos)

Data A bit 10 Input (Neg)

Data A bit 10 Input (Pos)

Data A bit 11 Input (Neg)

Data A bit 11 Input (Pos)

100 Ω across pair (not

terminated in the DLPC410)

LVDS_25_I

LVDS_25

100 Ω across pair (not

terminated in the DLPC410)

LVDS_25_I

LVDS_25

100 Ω across pair (not

terminated in the DLPC410)

LVDS_25_I

LVDS_25

100 Ω across pair (not

terminated in the DLPC410)

LVDS_25_I

LVDS_25

100 Ω across pair (not

terminated in the DLPC410)

LVDS_25_I

LVDS_25

100 Ω across pair (not

terminated in the DLPC410)

LVDS_25_I

LVDS_25

100 Ω across pair (not

terminated in the DLPC410)

LVDS_25_I

LVDS_25

100 Ω across pair (not

terminated in the DLPC410)

LVDS_25_I

LVDS_25

100 Ω across pair (not

terminated in the DLPC410)

LVDS_25_I

LVDS_25

100 Ω across pair (not

terminated in the DLPC410)

LVDS_25_I

LVDS_25

100 Ω across pair (not

terminated in the DLPC410)

LVDS_25_I

8

DLPC410

www.ti.com.cn

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

Pin Functions (continued)

TERMINATION

/NOTES

ACTIVE

(Hi or Lo)

DATA

RATE

TYPE

SIGNAL

CLOCK

DESCRIPTION

NAME

NO.

C23

B24

C24

D24

A25

B25

C26

B26

A12

A13

B12

C13

D10

D11

C12

C11

A10

B11

D9

DDC_DIN_A12_DPN

DDC_DIN_A12_DPP

DDC_DIN_A13_DPN

DDC_DIN_A13_DPP

DDC_DIN_A14_DPN

DDC_DIN_A14_DPP

DDC_DIN_A15_DPN

DDC_DIN_A15_DPP

DDC_DIN_B0_DPN

DDC_DIN_B0_DPP

DDC_DIN_B1_DPN

DDC_DIN_B1_DPP

DDC_DIN_B2_DPN

DDC_DIN_B2_DPP

DDC_DIN_B3_DPN

DDC_DIN_B3_DPP

DDC_DIN_B4_DPN

DDC_DIN_B4_DPP

DDC_DIN_B5_DPN

DDC_DIN_B5_DPP

DDC_DIN_B6_DPN

DDC_DIN_B6_DPP

DDC_DIN_B7_DPN

DDC_DIN_B7_DPP

DDC_DIN_B8_DPN

DDC_DIN_B8_DPP

DDC_DIN_B9_DPN

DDC_DIN_B9_DPP

DDC_DIN_B10_DPN

DDC_DIN_B10_DPP

DDC_DIN_B11_DPN

DDC_DIN_B11_DPP

DDC_DIN_B12_DPN

DDC_DIN_B12_DPP

DDC_DIN_B13_DPN

DDC_DIN_B13_DPP

DDC_DIN_B14_DPN

DDC_DIN_B14_DPP

DDC_DIN_B15_DPN

DDC_DIN_B15_DPP

DDC_DIN_C0_DPN

DDC_DIN_C0_DPP

DDC_DIN_C1_DPN

DDC_DIN_C1_DPP

DDC_DIN_C2_DPN

DDC_DIN_C2_DPP

DDC_DIN_C3_DPN

DDC_DIN_C3_DPP

DDC_DIN_C4_DPN

DDC_DIN_C4_DPP

DDC_DIN_C5_DPN

DDC_DIN_C5_DPP

DDC_DIN_C6_DPN

DDC_DIN_C6_DPP

I

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

100 Ω across pair (not

terminated in the DLPC410)

-

DDC_DCLK_A

DDC_DCLK_B

DDC_DCLK_C

DDR

Data A bit 12 Input (Neg)

Data A bit 12 Input (Pos)

Data A bit 13 Input (Neg)

Data A bit 13 Input (Pos)

Data A bit 14 Input (Neg)

Data A bit 14 Input (Pos)

Data A bit 15 Input (Neg)

Data A bit 15 Input (Pos)

Data B bit 0 Input (Neg)

Data B bit 0 Input (Pos)

Data B bit 1 Input (Neg)

Data B bit 1 Input (Pos)

Data B bit 2 Input (Neg)

Data B bit 2 Input (Pos)

Data B bit 3 Input (Neg)

Data B bit 3 Input (Pos)

Data B bit 4 Input (Neg)

Data B bit 4 Input (Pos)

Data B bit 5 Input (Neg)

Data B bit 5 Input (Pos)

Data B bit 6 Input (Neg)

Data B bit 6 Input (Pos)

Data B bit 7 Input (Neg)

Data B bit 7 Input (Pos)

Data B bit 8 Input (Neg)

Data B bit 8 Input (Pos)

Data B bit 9 Input (Neg)

Data B bit 9 Input (Pos)

Data B bit 10 Input (Neg)

Data B bit 10 Input (Pos)

Data B bit 11 Input (Neg)

Data B bit 11 Input (Pos)

Data B bit 12 Input (Neg)

Data B bit 12 Input (Pos)

Data B bit 13 Input (Neg)

Data B bit 13 Input (Pos)

Data B bit 14 Input (Neg)

Data B bit 14 Input (Pos)

Data B bit 15 Input (Neg)

Data B bit 15 Input (Pos)

Data C bit 0 Input (Neg)

Data C bit 0 Input (Pos)

Data C bit 1 Input (Neg)

Data C bit 1 Input (Pos)

Data C bit 2 Input (Neg)

Data C bit 2 Input (Pos)

Data C bit 3 Input (Neg)

Data C bit 3 Input (Pos)

Data C bit 4 Input (Neg)

Data C bit 4 Input (Pos)

Data C bit 5 Input (Neg)

Data C bit 5 Input (Pos)

Data C bit 6 Input (Neg)

Data C bit 6 Input (Pos)

100 Ω across pair (not

terminated in the DLPC410)

100 Ω across pair (not

terminated in the DLPC410)

100 Ω across pair (not

terminated in the DLPC410)

100 Ω across pair (not

terminated in the DLPC410)

100 Ω across pair (not

terminated in the DLPC410)

100 Ω across pair (not

terminated in the DLPC410)

100 Ω across pair (not

terminated in the DLPC410)

100 Ω across pair (not

terminated in the DLPC410)

100 Ω across pair (not

terminated in the DLPC410)

C9

B10

B9

100 Ω across pair (not

terminated in the DLPC410)

A8

100 Ω across pair (not

terminated in the DLPC410)

A9

D6

100 Ω across pair (not

terminated in the DLPC410)

D5

C7

100 Ω across pair (not

terminated in the DLPC410)

C6

B6

100 Ω across pair (not

terminated in the DLPC410)

B5

D4

100 Ω across pair (not

terminated in the DLPC410)

D3

B4

100 Ω across pair (not

terminated in the DLPC410)

C4

C3

100 Ω across pair (not

terminated in the DLPC410)

C2

A3

100 Ω across pair (not

terminated in the DLPC410)

A2

B2

100 Ω across pair (not

terminated in the DLPC410)

B1

E20

E21

F20

G20

H19

J19

E23

E22

F23

F22

G22

G21

J20

J21

100 Ω across pair (not

terminated in the DLPC410)

100 Ω across pair (not

terminated in the DLPC410)

100 Ω across pair (not

terminated in the DLPC410)

100 Ω across pair (not

terminated in the DLPC410)

100 Ω across pair (not

terminated in the DLPC410)

100 Ω across pair (not

terminated in the DLPC410)

100 Ω across pair (not

terminated in the DLPC410)

9

DLPC410

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

www.ti.com.cn

Pin Functions (continued)

TERMINATION

/NOTES

ACTIVE

(Hi or Lo)

DATA

RATE

TYPE

SIGNAL

CLOCK

DESCRIPTION

NAME

NO.

H22

H21

J23

H23

K22

K23

M19

M20

M21

M22

N19

P19

N21

N22

P20

P21

N23

P23

T3

DDC_DIN_C7_DPN

DDC_DIN_C7_DPP

DDC_DIN_C8_DPN

DDC_DIN_C8_DPP

DDC_DIN_C9_DPN

DDC_DIN_C9_DPP

DDC_DIN_C10_DPN

DDC_DIN_C10_DPP

DDC_DIN_C11_DPN

DDC_DIN_C11_DPP

DDC_DIN_C12_DPN

DDC_DIN_C12_DPP

DDC_DIN_C13_DPN

DDC_DIN_C13_DPP

DDC_DIN_C14_DPN

DDC_DIN_C14_DPP

DDC_DIN_C15_DPN

DDC_DIN_C15_DPP

DDC_DIN_D0_DPN

DDC_DIN_D0_DPP

DDC_DIN_D1_DPN

DDC_DIN_D1_DPP

DDC_DIN_D2_DPN

DDC_DIN_D2_DPP

DDC_DIN_D3_DPN

DDC_DIN_D3_DPP

DDC_DIN_D4_DPN

DDC_DIN_D4_DPP

DDC_DIN_D5_DPN

DDC_DIN_D5_DPP

DDC_DIN_D6_DPN

DDC_DIN_D6_DPP

DDC_DIN_D7_DPN

DDC_DIN_D7_DPP

DDC_DIN_D8_DPN

DDC_DIN_D8_DPP

DDC_DIN_D9_DPN

DDC_DIN_D9_DPP

DDC_DIN_D10_DPN

DDC_DIN_D10_DPP

DDC_DIN_D11_DPN

DDC_DIN_D11_DPP

DDC_DIN_D12_DPN

DDC_DIN_D12_DPP

DDC_DIN_D13_DPN

DDC_DIN_D13_DPP

DDC_DIN_D14_DPN

DDC_DIN_D14_DPP

DDC_DIN_D15_DPN

DDC_DIN_D15_DPP

DDC_DOUT_A0_DPN

DDC_DOUT_A0_DPP

I

O

LVDS_25

LVDS_25_I

LVDS_25

100 Ω across pair (not

terminated in the DLPC410)

-

DDC_DCLK_C

DDC_DCLK_D

DDC_DCLKOUT_A

DDR

Data C bit 7 Input (Neg)

Data C bit 7 Input (Pos)

Data C bit 8 Input (Neg)

Data C bit 8 Input (Pos)

Data C bit 9 Input (Neg)

Data C bit 9 Input (Pos)

Data C bit 10 Input (Neg)

Data C bit 10 Input (Pos)

Data C bit 11 Input (Neg)

Data C bit 11 Input (Pos)

Data C bit 12 Input (Neg)

Data C bit 12 Input (Pos)

Data C bit 13 Input (Neg)

Data C bit 13 Input (Pos)

Data C bit 14 Input (Neg)

Data C bit 14 Input (Pos)

Data C bit 15 Input (Neg)

Data C bit 15 Input (Pos)

Data D bit 0 Input (Neg)

Data D bit 0 Input (Pos)

Data D bit 1 Input (Neg)

Data D bit 1 Input (Pos)

Data D bit 2 Input (Neg)

Data D bit 2 Input (Pos)

Data D bit 3 Input (Neg)

Data D bit 3 Input (Pos)

Data D bit 4 Input (Neg)

Data D bit 4 Input (Pos)

Data D bit 5 Input (Neg)

Data D bit 5 Input (Pos)

Data D bit 6 Input (Neg)

Data D bit 6 Input (Pos)

Data D bit 7 Input (Neg)

Data D bit 7 Input (Pos)

Data D bit 8 Input (Neg)

Data D bit 8 Input (Pos)

Data D bit 9 Input (Neg)

Data D bit 9 Input (Pos)

Data D bit 10 Input (Neg)

Data D bit 10 Input (Pos)

Data D bit 11 Input (Neg)

Data D bit 11 Input (Pos)

Data D bit 12 Input (Neg)

Data D bit 12 Input (Pos)

Data D bit 13 Input (Neg)

Data D bit 13 Input (Pos)

Data D bit 14 Input (Neg)

Data D bit 14 Input (Pos)

Data D bit 15 Input (Neg)

Data D bit 15 Input (Pos)

Data A bit 0 Output (Neg)

Data A bit 0 Output (Pos)

100 Ω across pair (not

terminated in the DLPC410)

LVDS_25_I

LVDS_25

100 Ω across pair (not

terminated in the DLPC410)

LVDS_25_I

LVDS_25

100 Ω across pair (not

terminated in the DLPC410)

LVDS_25_I

LVDS_25

100 Ω across pair (not

terminated in the DLPC410)

LVDS_25_I

LVDS_25

100 Ω across pair (not

terminated in the DLPC410)

LVDS_25_I

LVDS_25

100 Ω across pair (not

terminated in the DLPC410)

LVDS_25_I

LVDS_25

100 Ω across pair (not

terminated in the DLPC410)

LVDS_25_I

LVDS_25

100 Ω across pair (not

terminated in the DLPC410)

LVDS_25_I

LVDS_25

100 Ω across pair (not

terminated in the DLPC410)

R3

LVDS_25_I

LVDS_25

R5

100 Ω across pair (not

terminated in the DLPC410)

R6

LVDS_25_I

LVDS_25

R7

100 Ω across pair (not

terminated in the DLPC410)

P6

LVDS_25_I

LVDS_25

N3

100 Ω across pair (not

terminated in the DLPC410)

P3

LVDS_25_I

LVDS_25

P4

100 Ω across pair (not

terminated in the DLPC410)

P5

LVDS_25_I

LVDS_25

N6

100 Ω across pair (not

terminated in the DLPC410)

N7

LVDS_25_I

LVDS_25

N4

100 Ω across pair (not

terminated in the DLPC410)

M4

M7

L7

LVDS_25_I

LVDS_25

100 Ω across pair (not

terminated in the DLPC410)

LVDS_25_I

LVDS_25

K7

100 Ω across pair (not

terminated in the DLPC410)

K6

LVDS_25_I

LVDS_25

J4

100 Ω across pair (not

terminated in the DLPC410)

J5

LVDS_25_I

LVDS_25

H7

100 Ω across pair (not

terminated in the DLPC410)

J6

LVDS_25_I

LVDS_25

G4

100 Ω across pair (not

terminated in the DLPC410)

H4

LVDS_25_I

LVDS_25

G5

100 Ω across pair (not

terminated in the DLPC410)

H6

LVDS_25_I

LVDS_25

G7

100 Ω across pair (not

terminated in the DLPC410)

G6

LVDS_25_I

LVDS_25

F4

100 Ω across pair (not

terminated in the DLPC410)

F5

LVDS_25_I

LVDS_25

E5

100 Ω across pair (not

terminated in the DLPC410)

E6

LVDS_25_I

LVDS_25

AE2

AF2

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

LVDS_25_O

DDC_DOUT_A1_DPN

DDC_DOUT_A1_DPP

AD1

AE1

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_A

DDR

Data A bit 1 Output (Neg)

Data A bit 1 Output (Pos)

LVDS_25_O

10

DLPC410

www.ti.com.cn

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

Pin Functions (continued)

TERMINATION

/NOTES

ACTIVE

(Hi or Lo)

DATA

RATE

TYPE

SIGNAL

CLOCK

DESCRIPTION

NAME

NO.

AC1

AC2

DDC_DOUT_A2_DPN

DDC_DOUT_A2_DPP

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_A

DDR

Data A bit 2 Output (Neg)

Data A bit 2 Output (Pos)

LVDS_25_O

DDC_DOUT_A3_DPN

DDC_DOUT_A3_DPP

AB1

AB2

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_A

DDR

Data A bit 3 Output (Neg)

Data A bit 3 Output (Pos)

LVDS_25_O

DDC_DOUT_A4_DPN

DDC_DOUT_A4_DPP

Y2

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_A

DDR

Data A bit 4 Output (Neg)

Data A bit 4 Output (Pos)

AA2

LVDS_25_O

DDC_DOUT_A5_DPN

DDC_DOUT_A5_DPP

W1

Y1

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_A

DDR

Data A bit 5 Output (Neg)

Data A bit 5 Output (Pos)

LVDS_25_O

DDC_DOUT_A6_DPN

DDC_DOUT_A6_DPP

V1

V2

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_A

DDR

Data A bit 6 Output (Neg)

Data A bit 6 Output (Pos)

LVDS_25_O

DDC_DOUT_A7_DPN

DDC_DOUT_A7_DPP

U1

U2

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_A

DDR

Data A bit 7 Output (Neg)

Data A bit 7 Output (Pos)

LVDS_25_O

DDC_DOUT_A8_DPN

DDC_DOUT_A8_DPP

R2

T2

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_A

DDR

Data A bit 8 Output (Neg)

Data A bit 8 Output (Pos)

LVDS_25_O

DDC_DOUT_A9_DPN

DDC_DOUT_A9_DPP

N2

M2

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_A

DDR

Data A bit 9 Output (Neg)

Data A bit 9 Output (Pos)

LVDS_25_O

DDC_DOUT_A10_DPN

DDC_DOUT_A10_DPP

K1

L2

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_A

DDR

Data A bit 10 Output (Neg)

Data A bit 10 Output (Pos)

LVDS_25_O

DDC_DOUT_A11_DPN

DDC_DOUT_A11_DPP

K2

K3

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_A

DDR

Data A bit 11 Output (Neg)

Data A bit 11 Output (Pos)

LVDS_25_O

DDC_DOUT_A12_DPN

DDC_DOUT_A12_DPP

J3

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_A

DDR

Data A bit 12 Output (Neg)

Data A bit 12 Output (Pos)

H3

LVDS_25_O

DDC_DOUT_A13_DPN

DDC_DOUT_A13_DPP

H2

J1

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_A

DDR

Data A bit 13 Output (Neg)

Data A bit 13 Output (Pos)

LVDS_25_O

DDC_DOUT_A14_DPN

DDC_DOUT_A14_DPP

H1

G1

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_A

DDR

Data A bit 14 Output (Neg)

Data A bit 14 Output (Pos)

LVDS_25_O

DDC_DOUT_A15_DPN

DDC_DOUT_A15_DPP

G2

F2

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_A

DDR

Data A bit 15 Output (Neg)

Data A bit 15 Output (Pos)

LVDS_25_O

DDC_DOUT_B0_DPN

DDC_DOUT_B0_DPP

AE5

AE6

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_B

DDR

Data B bit 0 Output (Neg)

Data B bit 0 Output (Pos)

LVDS_25_O

DDC_DOUT_B1_DPN

DDC_DOUT_B1_DPP

AD3

AD4

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_B

DDR

Data B bit 1 Output (Neg)

Data B bit 1 Output (Pos)

LVDS_25_O

DDC_DOUT_B2_DPN

DDC_DOUT_B2_DPP

AD5

AD6

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_B

DDR

Data B bit 2 Output (Neg)

Data B bit 2 Output (Pos)

LVDS_25_O

DDC_DOUT_B3_DPN

DDC_DOUT_B3_DPP

AC3

AC4

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_B

DDR

Data B bit 3 Output (Neg)

Data B bit 3 Output (Pos)

LVDS_25_O

DDC_DOUT_B4_DPN

DDC_DOUT_B4_DPP

AB5

AB6

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_B

DDR

Data B bit 4 Output (Neg)

Data B bit 4 Output (Pos)

LVDS_25_O

DDC_DOUT_B5_DPN

DDC_DOUT_B5_DPP

AB7

AC6

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_B

DDR

Data B bit 5 Output (Neg)

Data B bit 5 Output (Pos)

LVDS_25_O

DDC_DOUT_B6_DPN

DDC_DOUT_B6_DPP

AA5

AA4

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_B

DDR

Data B bit 6 Output (Neg)

Data B bit 6 Output (Pos)

LVDS_25_O

DDC_DOUT_B7_DPN

DDC_DOUT_B7_DPP

AA7

Y7

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_B

DDR

Data B bit 7 Output (Neg)

Data B bit 7 Output (Pos)

LVDS_25_O

DDC_DOUT_B8_DPN

DDC_DOUT_B8_DPP

Y3

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_B

DDR

Data B bit 8 Output (Neg)

Data B bit 8 Output (Pos)

W3

LVDS_25_O

DDC_DOUT_B9_DPN

DDC_DOUT_B9_DPP

W4

V4

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_B

DDR

Data B bit 9 Output (Neg)

Data B bit 9 Output (Pos)

LVDS_25_O

11

DLPC410

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

www.ti.com.cn

Pin Functions (continued)

TERMINATION

/NOTES

ACTIVE

(Hi or Lo)

DATA

RATE

TYPE

SIGNAL

CLOCK

DESCRIPTION

NAME

NO.

W6

W5

DDC_DOUT_B10_DPN

DDC_DOUT_B10_DPP

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_B

DDR

Data B bit 10 Output (Neg)

Data B bit 10 Output (Pos)

LVDS_25_O

DDC_DOUT_B11_DPN

DDC_DOUT_B11_DPP

V7

V6

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_B

DDR

Data B bit 11 Output (Neg)

Data B bit 11 Output (Pos)

LVDS_25_O

DDC_DOUT_B12_DPN

DDC_DOUT_B12_DPP

U4

V3

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_B

DDR

Data B bit 12 Output (Neg)

Data B bit 12 Output (Pos)

LVDS_25_O

DDC_DOUT_B13_DPN

DDC_DOUT_B13_DPP

T4

T5

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_B

DDR

Data B bit 13 Output (Neg)

Data B bit 13 Output (Pos)

LVDS_25_O

DDC_DOUT_B14_DPN

DDC_DOUT_B14_DPP

U6

U5

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_B

DDR

Data B bit 14 Output (Neg)

Data B bit 14 Output (Pos)

LVDS_25_O

DDC_DOUT_B15_DPN

DDC_DOUT_B15_DPP

U7

T7

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_B

DDR

Data B bit 15 Output (Neg)

Data B bit 15 Output (Pos)

LVDS_25_O

DDC_DOUT_C0_DPN

DDC_DOUT_C0_DPP

T22

T23

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_C

DDR

Data C bit 0 Output (Neg)

Data C bit 0 Output (Pos)

LVDS_25_O

DDC_DOUT_C1_DPN

DDC_DOUT_C1_DPP

R20

R21

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_C

DDR

Data C bit 1 Output (Neg)

Data C bit 1 Output (Pos)

LVDS_25_O

DDC_DOUT_C2_DPN

DDC_DOUT_C2_DPP

T19

T20

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_C

DDR

Data C bit 2 Output (Neg)

Data C bit 2 Output (Pos)

LVDS_25_O

DDC_DOUT_C3_DPN

DDC_DOUT_C3_DPP

U21

U22

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_C

DDR

Data C bit 3 Output (Neg)

Data C bit 3 Output (Pos)

LVDS_25_O

DDC_DOUT_C4_DPN

DDC_DOUT_C4_DPP

U20

U19

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_C

DDR

Data C bit 4 Output (Neg)

Data C bit 4 Output (Pos)

LVDS_25_O

DDC_DOUT_C5_DPN

DDC_DOUT_C5_DPP

V23

V24

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_C

DDR

Data C bit 5 Output (Neg)

Data C bit 5 Output (Pos)

LVDS_25_O

DDC_DOUT_C6_DPN

DDC_DOUT_C6_DPP

V22

V21

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_C

DDR

Data C bit 6 Output (Neg)

Data C bit 6 Output (Pos)

LVDS_25_O

DDC_DOUT_C7_DPN

DDC_DOUT_C7_DPP

W19

V19

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_C

DDR

Data C bit 7 Output (Neg)

Data C bit 7 Output (Pos)

LVDS_25_O

DDC_DOUT_C8_DPN

DDC_DOUT_C8_DPP

W23

W24

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_C

DDR

Data C bit 8 Output (Neg)

Data C bit 8 Output (Pos)

LVDS_25_O

DDC_DOUT_C9_DPN

DDC_DOUT_C9_DPP

Y22

Y23

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_C

DDR

Data C bit 9 Output (Neg)

Data C bit 9 Output (Pos)

LVDS_25_O

DDC_DOUT_C10_DPN

DDC_DOUT_C10_DPP

Y20

Y21

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_C

DDR

Data C bit 10 Output (Neg)

Data C bit 10 Output (Pos)

LVDS_25_O

DDC_DOUT_C11_DPN

DDC_DOUT_C11_DPP

AA24

AA23

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_C

DDR

Data C bit 11 Output (Neg)

Data C bit 11 Output (Pos)

LVDS_25_O

DDC_DOUT_C12_DPN

DDC_DOUT_C12_DPP

AA19

AA20

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_C

DDR

Data C bit 12 Output (Neg)

Data C bit 12 Output (Pos)

LVDS_25_O

DDC_DOUT_C13_DPN

DDC_DOUT_C13_DPP

AC24

AB24

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_C

DDR

Data C bit 13 Output (Neg)

Data C bit 13 Output (Pos)

LVDS_25_O

DDC_DOUT_C14_DPN

DDC_DOUT_C14_DPP

AC19

AD19

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_C

DDR

Data C bit 14 Output (Neg)

Data C bit 14 Output (Pos)

LVDS_25_O

DDC_DOUT_C15_DPN

DDC_DOUT_C15_DPP

AC22

AC23

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_C

DDR

Data C bit 15 Output (Neg)

Data C bit 15 Output (Pos)

LVDS_25_O

DDC_DOUT_D0_DPN

DDC_DOUT_D0_DPP

AB26

AC26

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_D

DDR

Data D bit 0 Output (Neg)

Data D bit 0 Output (Pos)

LVDS_25_O

DDC_DOUT_D1_DPN

DDC_DOUT_D1_DPP

AA25

AB25

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_D

DDR

Data D bit 1 Output (Neg)

Data D bit 1 Output (Pos)

LVDS_25_O

12

DLPC410

www.ti.com.cn

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

Pin Functions (continued)

TERMINATION

/NOTES

ACTIVE

(Hi or Lo)

DATA

RATE

TYPE

SIGNAL

CLOCK

DESCRIPTION

NAME

NO.

Y26

Y25

DDC_DOUT_D2_DPN

DDC_DOUT_D2_DPP

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_D

DDR

Data D bit 2 Output (Neg)

Data D bit 2 Output (Pos)

LVDS_25_O

DDC_DOUT_D3_DPN

DDC_DOUT_D3_DPP

W26

W25

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_D

DDR

Data D bit 3 Output (Neg)

Data D bit 3 Output (Pos)

LVDS_25_O

DDC_DOUT_D4_DPN

DDC_DOUT_D4_DPP

U26

V26

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_D

DDR

Data D bit 4 Output (Neg)

Data D bit 4 Output (Pos)

LVDS_25_O

DDC_DOUT_D5_DPN

DDC_DOUT_D5_DPP

U25

U24

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_D

DDR

Data D bit 5 Output (Neg)

Data D bit 5 Output (Pos)

LVDS_25_O

DDC_DOUT_D6_DPN

DDC_DOUT_D6_DPP

T25

T24

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_D

DDR

Data D bit 6 Output (Neg)

Data D bit 6 Output (Pos)

LVDS_25_O

DDC_DOUT_D7_DPN

DDC_DOUT_D7_DPP

R26

R25

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_D

DDR

Data D bit 7 Output (Neg)

Data D bit 7 Output (Pos)

LVDS_25_O

DDC_DOUT_D8_DPN

DDC_DOUT_D8_DPP

P24

P25

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_D

DDR

Data D bit 8 Output (Neg)

Data D bit 8 Output (Pos)

LVDS_25_O

DDC_DOUT_D9_DPN

DDC_DOUT_D9_DPP

N24

M24

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_D

DDR

Data D bit 9 Output (Neg)

Data D bit 9 Output (Pos)

LVDS_25_O

DDC_DOUT_D10_DPN

DDC_DOUT_D10_DPP

L25

L24

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_D

DDR

Data D bit 10 Output (Neg)

Data D bit 10 Output (Pos)

LVDS_25_O

DDC_DOUT_D11_DPN

DDC_DOUT_D11_DPP

K26

K25

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_D

DDR

Data D bit 11 Output (Neg)

Data D bit 11 Output (Pos)

LVDS_25_O

DDC_DOUT_D12_DPN

DDC_DOUT_D12_DPP

J26

J25

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_D

DDR

Data D bit 12 Output (Neg)

Data D bit 12 Output (Pos)

LVDS_25_O

DDC_DOUT_D13_DPN

DDC_DOUT_D13_DPP

J24

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_D

DDR

Data D bit 13 Output (Neg)

Data D bit 13 Output (Pos)

H24

LVDS_25_O

DDC_DOUT_D14_DPN

DDC_DOUT_D14_DPP

H26

G26

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_D

DDR

Data D bit 14 Output (Neg)

Data D bit 14 Output (Pos)

LVDS_25_O

DDC_DOUT_D15_DPN

DDC_DOUT_D15_DPP

G25

G24

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_D

DDR

Data D bit 15 Output (Neg)

Data D bit 15 Output (Pos)

LVDS_25_O

DDC_M0

W18

Y17

V18

R1

-

NC

4.7 kΩ pullup to 2.5V

Hi

-

Xilinx Configuration

DDC_M1

-

DDC_M2

-

NC

-

DDC_SCTRL_AN

O

LVDS_25

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

DDC_DCLKOUT_A

DDR

Bank A Serial Control Data

(Neg)

DDC_SCTRL_AP

DDC_SCTRL_BN

DDC_SCTRL_BP

DDC_SCTRL_CN

DDC_SCTRL_CP

DDC_SCTRL_DN

DDC_SCTRL_DP

DDC_VERSION_0

DDC_VERSION_1

DDC_VERSION_2

DDC_SPARE_1

P1

AA3

AB4

W20

W21

N26

P26

F18

O

-

LVDS_25_O

LVDS_25

-

DDC_DCLKOUT_A

Bank A Serial Control Data

(Pos)

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_B

Bank B Serial Control Data

(Neg)

LVDS_25_O

LVDS_25

-

DDC_DCLKOUT_B

Bank B Serial Control Data

(Pos)

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_C

Bank C Serial Control Data

(Neg)

LVDS_25_O

LVDS_25

-

DDC_DCLKOUT_C

Bank C Serial Control Data

(Pos)

Pair connected to DMD

(LVDS terminated internally

in DMD - 100 Ω)

-

DDC_DCLKOUT_D

Bank D Serial Control Data

(Neg)

LVDS_25_O

-

DDC_DCLKOUT_D

Bank D Serial Control Data

(Pos)

LVCMOS25_F_

12_O

Hi = 1

-

DLPC410 Firmware Rev

Number bit 0

G17

H18

AC21

LVCMOS25_F_

12_O

DLPC410 Firmware Rev

Number bit 1

LVCMOS25_F_

12_O

DLPC410 Firmware Rev

Number bit 2

LVCMOS25_F_ Do not connect

12_O

Not Used

13

DLPC410

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

www.ti.com.cn

Pin Functions (continued)

TERMINATION

/NOTES

ACTIVE

(Hi or Lo)

DATA

RATE

TYPE

SIGNAL

CLOCK

DESCRIPTION

NAME

NO.

DMD_A_RESET

AD14

O

LVCMOS25_F_ Connected in Reference

Lo

-

DMD Circuitry Reset (not data

reset)

12_O

Design to 36 Ω resistor with

27 pF cap to ground (signal

name DMD_A_RESET_FILT

after resistor - connects to

DMD signal DMDRST)

DMD_A_SCPEN

AB14

O

LVCMOS25_F_ Connected in Reference

Lo

-

DMD SCP Output Enable

12_O

Design to 36 Ω resistor with

27 pF cap to ground (called

DMD_A_SCPEN# in

Reference Design- signal

name

DMD_A_SCPEN#_FILT after

resistor - connects to DMD

signal DMDSEL )

DMD_B_RESET

DMD_B_SCPEN

AA12

AC14

O

LVCMOS25_S_ Connected in Reference

-

Not Used

12_O

Design to 36 Ω resistor with

27 pF cap to ground (signal

name DMD_B_RESET_FILT

after resistor - NC after that

point)

LVCMOS25_S_ Connected in Reference

12_O

Design to 36 Ω resistor with

27 pF cap to ground (called

DMD_B_SCPEN# in

Reference Design - signal

name

DMD_B_SCPEN#_FILT after

resistor - NC after that point )

DMD_TYPE_0

DMD_TYPE_1

DMD_TYPE_2

DMD_TYPE_3

DONE_DDC

AA17

AC16

AB17

AD15

K10

O

LVCMOS25_F_

12_O

Hi = 1

Hi

-

DMD Attached Type bit 0

DMD Attached Type bit 1

DMD Attached Type bit 2

DMD Attached Type bit 3

LVCMOS25_F_

12_O

LVCMOS25_F_

12_O

LVCMOS25_F_

12_O

-

4.7 kΩ pullup to 2.5V -

connected to DLPR410 CE

pin and LED D3 pin 3

(cathode) in series with 62 Ω

resistor to 3.3 V

DLPR410 Initialization Routine

Complete

DVALID_A_DPN

DVALID_A_DPP

DVALID_B_DPN

DVALID_B_DPP

DVALID_C_DPN

DVALID_C_DPP

DVALID_D_DPN

DVALID_D_DPP

DXN_0

D20

D21

C8

I

-

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

LVDS_25

LVDS_25_I

NC

100 Ω across pair (not

terminated in the DLPC410)

-

DDC_DCLK_A

DDC_DCLK_B

DDC_DCLK_C

DDC_DCLK_D

-

Bank A Valid Input Signal

(Neg)

Bank A Valid Input Signal

(Pos)

100 Ω across pair (not

terminated in the DLPC410)

Bank B Valid Input Signal

(Neg)

D8

Bank B Valid Input Signal

(Pos)

L19

L20

L3

100 Ω across pair (not

terminated in the DLPC410)

Bank C Valid Input Signal

(Neg)

Bank C Valid Input Signal

(Pos)

100 Ω across pair (not

terminated in the DLPC410)

Bank D Valid Input Signal

(Neg)

L4

Bank D Valid Input Signal

(Pos)

R13

TP17 in Reference Design

TP14 in Reference Design

Dedicated Xlilinx Temperature

Diode (anode); Not Used in

Reference Design

DXP_0

R14

Y18

-

NC

-

Dedicated Xlilinx Temperature

Diode (cathode); Not Used in

Reference Design

ECP2_FINISHED

O

LVCMOS25_F_ Connected to LED D3 pin 2

Hi

DLPR410 Initialization Routine

Complete

12_O

(anode) in series with 62 Ω

resistor to 3.3 V

ECP2_M_TP0

ECP2_M_TP1

ECP2_M_TP2

AD11

AD10

AD8

-

LVCMOS25_F_ Mictor J8 Pin 2 in Reference

12_O Design

-

Not Used - do not connect

Reserved - do not connect

LVCMOS25_F_ Mictor J8 Pin 4 in Reference

12_O Design

LVCMOS25_F_ Mictor J8 Pin 6 in Reference

12_O Design

14

DLPC410

www.ti.com.cn

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

Pin Functions (continued)

TERMINATION

/NOTES

ACTIVE

(Hi or Lo)

DATA

RATE

TYPE

SIGNAL

CLOCK

DESCRIPTION

NAME

NO.

ECP2_M_TP3

AC8

O

LVCMOS25_F_ Mictor J8 Pin 8 in Reference

12_O Design

-

Buffered data clock - test point

ECP2_M_TP4

ECP2_M_TP5

ECP2_M_TP6

ECP2_M_TP7

ECP2_M_TP8

ECP2_M_TP9

ECP2_M_TP10

ECP2_M_TP11

ECP2_M_TP12

ECP2_M_TP13

ECP2_M_TP14

ECP2_M_TP15

ECP2_M_TP16

ECP2_M_TP17

ECP2_M_TP18

ECP2_M_TP19

ECP2_M_TP20

ECP2_M_TP21

ECP2_M_TP22

ECP2_M_TP23

ECP2_M_TP24

ECP2_M_TP25

ECP2_M_TP26

ECP2_M_TP27

ECP2_M_TP28

ECP2_M_TP29

ECP2_M_TP30

ECP2_M_TP31

AC7

AC9

AB9

AA8

AA9

Y8

O

LVCMOS25_F_ Mictor J8 Pin 10 in

12_O Reference Design

-

Reserved - do not connect

DMD A/B bus OK - test point

DMD C/D bus OK - test point

Reserved - do not connect

LVCMOS25_F_ Mictor J8 Pin 12 in

12_O Reference Design

Hi

-

LVCMOS25_F_ Mictor J8 Pin 14 in

12_O Reference Design

LVCMOS25_F_ Mictor J8 Pin 16 in

12_O Reference Design

LVCMOS25_F_ Mictor J8 Pin 18 in

12_O Reference Design

LVCMOS25_F_ Mictor J8 Pin 20 in

12_O Reference Design

-

AB10

AA10

Y10

AC11

Y12

Y11

AB11

H8

LVCMOS25_F_ Mictor J8 Pin 22 in

12_O Reference Design

Lo

Hi

-

LVCMOS25_F_ Mictor J8 Pin 24 in

12_O Reference Design

LVCMOS25_F_ Mictor J8 Pin 26 in

12_O Reference Design

LVCMOS25_F_ Mictor J8 Pin 28 in

12_O Reference Design

LVCMOS25_F_ Mictor J8 Pin 30 in

12_O Reference Design

LVCMOS25_F_ Mictor J8 Pin 32 in

12_O Reference Design

LVCMOS25_F_ Mictor J8 Pin 34 in

12_O Reference Design

Hi

-

LVCMOS25_F_ Mictor J8 Pin 36 in

12_O Reference Design

H9

LVCMOS25_F_ Mictor J8 Pin 38 in

12_O Reference Design

F12

G11

G12

E11

E10

E8

LVCMOS25_F_ Mictor J8 Pin 37 in

12_O Reference Design

-

LVCMOS25_F_ Mictor J8 Pin 35 in

12_O Reference Design

Hi

-

LVCMOS25_F_ Mictor J8 Pin 33 in

12_O Reference Design

LVCMOS25_F_ Mictor J8 Pin 31 in

12_O Reference Design

LVCMOS25_F_ Mictor J8 Pin 29 in

12_O Reference Design

LVCMOS25_F_ Mictor J8 Pin 27 in

12_O Reference Design

F10

F9

LVCMOS25_F_ Mictor J8 Pin 25 in

12_O Reference Design

LVCMOS25_F_ Mictor J8 Pin 23 in

12_O Reference Design

F8

LVCMOS25_F_ Mictor J8 Pin 21 in

12_O Reference Design

G10

G9

LVCMOS25_F_ Mictor J8 Pin 19 in

12_O Reference Design

LVCMOS25_F_ Mictor J8 Pin 17 in

12_O Reference Design

H11

H12

LVCMOS25_F_ Mictor J8 Pin 15 in

12_O Reference Design

-

LVCMOS25_F_ Mictor J8 Pin 13 in

12_O Reference Design

-

15

DLPC410

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

www.ti.com.cn

Pin Functions (continued)

TERMINATION

/NOTES

ACTIVE

(Hi or Lo)

DATA

RATE

TYPE

SIGNAL

CLOCK

DESCRIPTION

Connect to Ground

NAME

NO.

GND

A1, A6, A11,

A16, A21, A26,

AA1, AA11,

-

GND

-

AA21, AA26,

AB8, AB18,

AC5, AC15,

AC25, AD2,

AD12, AD22,

AE4, AE9,

AE14, AE19,

AF1, AF6,

AF11, AF16,

AF21, AF26,

B3, B8, B13,

B18, C5, C15,

C25, D2, D12,

D22, E9, E19,

F1, F6, F16,

F26, G3, G13,

G18, G23, H10,

H20, J7, J9,

J13, J15, J17,

K4, K8, K12,

K14, K16, K19,

K24, L1, L9,

L11, L13, L15,

L17, L21, L26,

M3, M8, M10,

M12, M16, M18,

N5, N9, N11,

N15, N17, N25,

P2, P7, P8,

P10, P12, P16,

P22, R9, R11,

R15, R17, R19,

T1, T6, T8, T10,

T12, T14, T16,

T26, U3, U9,

U13, U15, U17,

U18, U23, V8,

V10, V14, V16,

V20, W7, W9,

W13, W15,

W17, Y4, Y14,

Y16, Y19, Y24

HSWAPEN

L18

-

4.7 kΩ pullup to 2.5 V

-

Xilinx Configuration

INIT_ACTIVE

AA18

O

LVCMOS25_F_

12_O

Hi

DLPC410 Initilization Routine

Active

INTB_DDC

LOAD4

J11

-

4.7 kΩ pullup to 2.5 V

connected to DLPR410

OE/RESET

Hi

-

Xilinx Configuration

AB21

LVCMOS25_F_ Previously DDC_SPARE_0,

LOAD4 mode enable

12_I/O

connected to Applications

FPGA (U5) pin AD19 in

Reference Design. Weak

internal pull-up. Pull-up to

logic '1' if LOAD4 is unused.

NS_FLIP

F19

J18

J10

I

LVCMOS25_S_

12_I

Hi

-

Top/Bottom image flip on DMD

Xilinx Configuration

PROGB_DDC

PROM_CCK_DDC

-

4.7 kΩ pullup to 2.5 V

connected to DLPR410 CF

-

LVCMOS25_S_ Connected to center of

PROM_CCK_DDC

Configuration PROM Clock

12

voltage divider (100/100 Ω)

and through R53 to

DLPR410 CLKOUT

PROM_D0_DDC

PWR_FLOAT

K11

-

I

-

Connected to DLPR410 Data

0 (D0)

-

PROM_CCK_DDC

-

Configuration PROM Data Out

DMD Power Good indicator

AC17

LVCMOS25_S_ Connected to output of U22

Hi

12_I

NOR Gate (inputs

V5_PWR_FLOAT and

PWRGD)

RDWR_B

P18

D14

-

I

-

1 kΩ pulldown to ground

-

Xilinx Configuration

ROWAD_0

LVCMOS25_S_

12_I

Hi = 1

DMD Row Address bit 0

ROWAD_1

ROWAD_2

D15

E15

I

LVCMOS25_S_

12_I

Hi = 1

-

DMD Row Address bit 1

DMD Row Address bit 2

LVCMOS25_S_

12_I

16

DLPC410

www.ti.com.cn

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

Pin Functions (continued)

TERMINATION

/NOTES

ACTIVE

(Hi or Lo)

DATA

RATE

TYPE

SIGNAL

CLOCK

DESCRIPTION

NAME

NO.

ROWAD_3

F14

I

LVCMOS25_S_

12_I

Hi = 1

-

DMD Row Address bit 3

ROWAD_4

ROWAD_5

ROWAD_6

ROWAD_7

ROWAD_8

ROWAD_9

ROWAD_10

ROWMD_0

ROWMD_1

RST_ACTIVE

RST2BLK

RSVD_0

G14

E16

F15

I

-

LVCMOS25_S_

12_I

-

DMD Row Address bit 4

DMD Row Address bit 5

DMD Row Address bit 6

DMD Row Address bit 7

DMD Row Address bit 8

DMD Row Address bit 9

DMD Row Address bit 10

DMD Row Mode bit 0

DMD Row Mode bit 1

DMD Reset in Progress

Dual Block Reset bit

LVCMOS25_S_

12_I

-

LVCMOS25_S_

12_I

-

G15

E17

F17

LVCMOS25_S_

12_I

-

LVCMOS25_S_

12_I

-

LVCMOS25_S_

12_I

-

G16

H17

H16

AB16

E18

R18

T18

LVCMOS25_S_

12_I

-

LVCMOS25_S_

12_I

-

LVCMOS25_S_

12_I

-

LVCMOS25_F_

12_O

-

LVCMOS25_S_

12_I

-

Connect to Ground

-

Not Used - must be tied to

Ground

RSVD_1

-

Not Used - must be tied to

Ground

SCPCLK

AB15

LVCMOS25_F_ Connected to DLPA200

-

SCPCLK

SCP Clock

12_O

Number 1 and Number 2

SCPCLK and to R105 36 Ω

filter resistor with 27 pF cap

after - called

DMD_A_SCPCLK_FILT after

- connects to DMD SCPCLK

(also connects to R97 filter

resistor with 27 pF cap after -

called

DMD_B_SCPCLK_FILT but

NC after)

SCPDI

AA15

I

LVCMOS25_S_ 1 kΩ pullup to 2.5 V -

-

SCPCLK

SCP data input to DLPC410

12_I

connects to DLPA200

Number 1 and Number 2

SCPDO and to DMD SCPDO

through flex A - on DMD

board there is an LCR filter

[2 x 100 pF caps, inductor

and 34 Ω resistor] also

connects to flex B but NC on

other end.

SCPDO

AA14

O

LVCMOS25_F_ 1 kΩ pullup to 2.5 V -

-

SCPCLK

SCP data output from

DLPC410

12_O

connects to DLPA200

Number 1 and Number 2

SCPDI and to R96 filter cap

with 27 pF cap after - called

DMD_A_FILTER - connect

through flex A to DMD

SCPDI - also connects to

R71 36 Ω filter resistor with

27 pF cap to

DMD_B_SCPDO_FILT but

NC on other end.

STEPVCC

TCK_JTAG

Y13

U11

-

LVCMOS25_S_ 1 kΩ pulldown to ground

-

Not Used

12_I

-

Connects to DLPC410,

DLPR410, and JTAG header

TCK (if user has JTAG they

must build their chain

accordingly)

TCK_JTAG

JTAG Clock

TDO_DDC

W10

V11

-

Connects to JTAG return

TDO on JTAG header

-

TCK_JTAG

JTAG data out of DLPC410

TDO_XCF16DDC

Connects to DLPR410 TDO

(DLPC410 internal signal

TDI_0)

JTAG data out of DLPR410 to

DLPC410

17

DLPC410

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

www.ti.com.cn

Pin Functions (continued)

TERMINATION

/NOTES

ACTIVE

(Hi or Lo)

DATA

RATE

TYPE

SIGNAL

CLOCK

DESCRIPTION

NAME

TMS_JTAG

NO.

V12

-

Connects to DLPC410,

DLPR410, and JTAG header

TMS

Hi

TCK_JTAG

JTAG

VBATT_0

VCCAUX

K18

-

Connecteto 4.7 kΩ pullup to

2.5 V

-

Not Used

J8, K17, L8,

M17, N8, P17,

R8, T17, U8,

V17, W8, W16

POWER

VCC_2P5V

VCC_1P0V

Aux Power

VCCINT

H15, J12, J14,

J16, K9, K13,

K15, L10, L12,

L14, L16, M9,

M11, M15, N10,

N12, N16, P9,

P11, P15, R10,

R12, R16, T9,

T11, T13, T15,

U10, U12, U14,

U16, V9, V13,

V15, W14, Y15

POWER

-

Power

VCCO_0_1

VCCO_0_2

VCCO_1_1

VCCO_1_2

VCCO_2_1

VCCO_2_2

VCCO_3_1

VCCO_3_2

VCCO_4_1

VCCO_4_2

VCCO_11_1

VCCO_11_2

VCCO_11_3

VCCO_12_1

VCCO_12_2

VCCO_12_3

VCCO_13_1

VCCO_13_2

VCCO_13_3

VCCO_14_1

VCCO_14_2

VCCO_14_3

VCCO_15_1

VCCO_15_2

VCCO_15_3

VCCO_16_1

VCCO_16_2

VCCO_16_3

VCCO_17_1

VCCO_17_2

VCCO_17_3

VCCO_18_1

VCCO_18_2

VCCO_18_3

VLED0

Y9

W12

C10

F11

AA16

AD17

E14

D17

AC10

AB13

F21

J22

POWER

VCC_2P5V

-

Power

-

H25

J2

-

H5

-

L6

-

R24

M23

N20

V5

-

R4

-

W2

-

E24

B23

C20

G8

-

D7

-

E4

-

V25

W22

T21

AD7

AA6

AB3

AC18

-

VCC_2P5V

LVCMOS25_F_ Connects to LED D9 in

-

O

-

Hi = On

Power Indicator LED Output

12_O

series with 22.1 Ω resistor to

2.5 V

VLED1

VN_0

AD18

P13

LVCMOS25_F_ Connects to LED D10 in

Hi = On

-

Heartbeat Indicator LED

Output

12_O

series with 22.1 Ω resistor to

2.5 V

-

Connect to Ground

-

Xilinx System Monitor (not

used - must be connected to

ground)

18

DLPC410

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ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

Pin Functions (continued)

TERMINATION

/NOTES

ACTIVE

(Hi or Lo)

DATA

RATE

TYPE

SIGNAL

CLOCK

DESCRIPTION

NAME

NO.

VP_0

N14

-

Connect to Ground

-

Xilinx System Monitor (not

used - must be connected to

ground)

VREFN_0

VREFP_0

N13

P14

-

I

LVCMOS25_S_ Connect to Ground

12

-

Xilinx System Monitor

reference voltage (not used -

must be connected to ground)

LVCMOS25_S_ Connect to Ground

12

Xilinx System Monitor

reference ground (not used -

must be connected to ground)

WDT_ENBL

UNUSED

AA13

LVCMOS25_S_

12_I

Lo

-

DMD Mirror Clocking Pulse

Watchdog Timer Enable

AB23, AC20,

AD9, AD16,

AD20, AD21,

AD23, AD24,

AD25, AD26,

AE7, AE8,

NC

No Connection (listed as

Xilinx NC0 - NC42)

Unused Pins

AE10, AE11,

AE12, AE13,

AE15, AE16,

AE17, AE18,

AE20, AE21,

AE22, AE23,

AE24, AE25,

AE26, AF7,

AF8, AF9,

AF10, AF12,

AF13, AF14,

AF15, AF17,

AF18, AF19,

AF20, AF22,

AF23, AF24,

AF25

19

DLPC410

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

www.ti.com.cn

7 Specifications

注

The information contained in the following sections has been adapted from the Xilinx

XC5VLX30 data sheet. For any information beyond what is listed here, consult the Xilinx

XC5VLX30 data sheet. Where appropriate, DLPC410 specific values have been

substituted in place of generic parameters.

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

ELECTRICAL

V_CCINT

–0.5

2.35

–0.75

–0.3

1.05

3.45

V

(2)

Supply voltage

V_CCO

V_CCAUX

2.5 V

2.625

(3)

V_I

Input voltage

V_CCO+ 0.5

V_CCO+ 0.3

V_O

Output voltage⁽⁴⁾

ENVIRONMENTAL

T_A

Operating free-air temperature⁽⁵⁾

0

85

°C

T_stg

Storage temperature

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to GND.

(3) Applies to external input and bidirectional buffers.

(4) Applies to external output and bidirectional buffers.

(5) Maximum Ambient Temperature may be further limited by the device’s power dissipation (which is data and configuration dependent),

air flow and resultant junction temperature.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

2000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC specification JESD22-C101,

all pins⁽²⁾

400

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

0.95

1.14

2.375

0

NOM

1.00

MAX UNIT

V_CCINT1-V Supply voltage, core logic

V_CCO2.5-V Supply voltage, I/O

V_CCAUX2.5-V Supply voltage, I/O

1.05

3.45

2.625

V_CCO

2.2

V

2.50

2.500

2.5-V CMOS

2.5-V LVDS

2.5-V CMOS

2.5-V LVDS

V_I

Input voltage

V

0.3

0

V_CCO

1.675

125

V_O

Output voltage

0.825

0

T_J

Operating junction temperature⁽¹⁾

°C

W

P_D

Continuous total power dissipation

2.7

2.8

(1) Thermal analysis and design should be carefully considered to ensure that the junction temperature is maintained within the above

specifications.

20

DLPC410

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ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

7.4 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

High-level Input voltage

Low-level Input voltage

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_IH

V_IL

2.5-V CMOS

2.5-V Interface

2.5-V LVDS

1.7

V

0.7

0.4

V

V_CCO-.4

V_OH

V_OL

C_I

High-level output voltage

Low-level output voltage

Input capacitance

V

1.38

2.5-V Interface

2.5-V LVDS

V

1.03

8

2.5-V Interface

2.5-V LVDS

pF

8

I_CCINT

I_CCO

Supply voltage range, core supply

Supply voltage range, I/O supply

300

850

mA

7.5 Timing Requirements

(1)

(see

)

MIN NOM

395 400

50

MAX UNIT

f_cd

f_cr

Clock frequency, DCLKIN_n⁽²⁾

Clock frequency, CLK_R

400

MHz

ns

t_c

Cycle time, DCLKIN_n

2.5

2.53

1.27

.6

t_w(H)

t_w(L)

t_t

Pulse duration, high

50% to 50% reference points (signal)

1.25 1.25

ns

Pulse duration, low

50% to 50% reference points (signal)

20% to 80% reference points (signal)

ns

Transition time, t_t= t_f/t_r

ns

t_jp

Period Jitter DCLKIN_n⁽³⁾

150

–150

ps

Skew, DIN_A(15-0) to DCLKIN_A

Skew, DIN_B(15-0) to DCLKIN_B

Skew, DIN_C(15-0) to DCLKIN_C

Skew, DIN_D(15-0) to DCLKIN_D

Skew, DVALID_n to DCLKIN_n↑

Skew, BLK_MD BLK_AD to DCLKIN_n↑⁽⁴⁾

Skew, ROWMD or ROWAD to DCLKIN_n↑⁽⁴⁾

Skew, STEPVCC to DCLKIN↑⁽⁴⁾

150

–150

t_SK

ps

–150

(1) It is recommended that the COMP_DATA, NS_FLIP and RST2BLK flags be set to one value and not adjusted during normal system

operation.

(2) Preferred DCLKIN_n duty cycle = 50%

(3) This is the deviation in period from ideal period due solely to high frequency jitter.

(4) First edge of DIN*, ROW*, BLK* and STEPVCC should be synchronous to DVALID rising edge

21

DLPC410

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

www.ti.com.cn

t_sk

t_t

t_c

t_w(H)

t_w(L)

50%

Cycle 1

80%

20%

DCLKIN

50%

Cycle#CLKS/

ROW

DVALID

DDR Data

Control

图 2. Input Interface Timing

t_t

t_c

t_w(H)

t_w(L)

50%

80%

20%

50%

t_h

DCLKIN

t_su

COMP_DATA/

NS_FLIP

Valid

图 3. Control Timing

注

Dynamic changes to NS_FLIP and COMP_DATA during normal operation is not

recommended.

22

DLPC410

www.ti.com.cn

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

8 Detailed Description

8.1 Overview

The DLPC410 DMD Digital Controller enables customers to stream binary pattern data to the DLP650LNIR,

DLP7000(UV), or DLP9500(UV) DMD for very high speed binary pattern imaging applications. The DLPC410

receives customer input binary pattern data on a row by row basis and passes the pattern data to the connected

DMD. Concurrent with the receipt of data, the DLPC410 captures the customer requested ROW mode and ROW

address which determines if row loading starts at the top (or bottom) of the DMD and increments (or decrements)

to the next row for the next Row Cycle, or if a specific row address is specified for loading the next pattern data.

Each DMD micromirror is individually configurable through this data loading process which enables precise,

predictable control of each and every micromirror in the DMD Micromirror array.

The DLPC410 also receives customer input control information instructing the DLPC410 to command the

DLPA200 device(s) to generate the Mirror Clocking Pulses (MCPs) to the DMD – these MCPs are necessary for

the DMD micromirrors to transition from their current state to their new state, the new state being determined by

the new data just loaded into the DMD. A feedback signal from the DLPC410 frames the MCP such that the

customer knows the MCP request has been received by the DLPC410 and when the MCP is completed.

The DLPC410 supports multiple MCP modes of operation. The DMD Micromirror arrays are arranged into

horizontal Reset Blocks – there are typically 16 horizontal Reset Blocks per DMD where each Reset Block

receives a single MCP to initiate the Micromirror state change. DMD blocks can be Reset one at a time or all at

once. In certain modes, adjacent blocks of 2 or of 4 Reset Blocks can be Reset at the same time. This flexibility

provides great advantages to optimizing the time certain DMD blocks are in certain states, which in turn can

provide speed advantages or extend DMD illumination windows (the duration for which a solid state illuminator

should be illuminating).

Behind the scenes, the DLPC410 also communicates directly with the control logic of the DMD to read part type

and status information and to configure the DMD for proper operation. The DLPC410 is always paired with the

DLPR410 PROM as the DLPR410 provides the configuration bit stream which configures the DLPC410 to be a

DMD Digital Controller. The DLPC410 also drives one DMD at a time, and that DMD could require either one or

two DLPA200 devices depending on the DMD type. For further information, refer to 表 11 or the individual DMD

datasheets (links can be found in 表 26).

23

DLPC410

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

www.ti.com.cn

8.2 Functional Block Diagrams

2x LVDS bus

DLPC410

DLP650LNIR

DCLK_A

DVALID_A

DIN_A[15:0]

DCLKOUT_A

SCTRL_A

DOUT_A[15,13,11,9,7,5,3,1]

DCLK_B

DVALID_B

DIN_B[15:0]

DCLKOUT_B

SCTRL_B

DOUT_B[15,13,11,9,7,5,3,1]

DCLK_C

DVALID_C

DIN_C[15:0]

DCLKOUT_C

SCTRL_C

DOUT_C[15,13,11,9,7,5,3,1]

DCLK_D

DVALID_D

DIN_D[15:0]

DCLKOUT_D

SCTRL_D

DOUT_D[15,13,11,9,7,5,3,1]

User Interface

Controller

FPGA

SCPCLK

SCPDO

SCPDI

DMD_A_SCPENZ

DMD_B_SCPENZ

A_SCPENZ

B_SCPENZ

COMP_DATA, NS_FLIP, WDT_ENZ,PWR_FLOAT

ROWMD[1:0]

ROWAD[10:0]

RST2BLKZ

BLKMD[1:0]

BLKAD[10:0]

LOAD4

DLPA200

RST_ACTIVE

INIT_ACTIVE

ECP2_FINISHED

DMD_TYPE[3:0]

VERSION[2:0]

A_STROBE

A_MODE[1:0]

A_SEL[1:0]

A_ADDR[3:0]

OEZ

MBRST[15:0]

INIT

DLPR410

TDI_JTAG

PROM_CCK_DDC

PROGB_DDC

PROM_DO_DDC

DONE_DDC

INTB_DDC

B_STROBE

TDO_XCF16DDC

B_MODE[1:0]

B_SEL[1:0]

B_ADDR[3:0]

TCK_JTAG

TMS_JTAG

TDO_DDC

VLED0

VLED1

ARSTZ

CLKIN_R

DMD_A_RESET

DMD_B_RESET

OSC

50 MHz

图 4. DLPC410 and DLP650LNIR DMD Functional Block Diagram

24

DLPC410

www.ti.com.cn

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

Functional Block Diagrams (接下页)

2x LVDS bus

DLPC410

DLP7000

DCLK_A

DVALID_A

DIN_A[15:0]

DCLKOUT_A

SCTRL_A

DOUT_A[15:0]

DCLK_B

DVALID_B

DIN_B[15:0]

DCLKOUT_B

SCTRL_B

DOUT_B[15:0]

DCLK_C

DVALID_C

DIN_C[15:0]

DCLKOUT_C

SCTRL_C

DOUT_C[15:0]

DCLK_D

DVALID_D

DIN_D[15:0]

DCLKOUT_D

SCTRL_D

DOUT_D[15:0]

User Interface

Controller

FPGA

SCPCLK

SCPDO

SCPDI

DMD_A_SCPENZ

DMD_B_SCPENZ

A_SCPENZ

B_SCPENZ

COMP_DATA, NS_FLIP, WDT_ENZ,PWR_FLOAT

ROWMD[1:0]

ROWAD[10:0]

RST2BLKZ

BLKMD[1:0]

BLKAD[10:0]

LOAD4

DLPA200

RST_ACTIVE

INIT_ACTIVE

ECP2_FINISHED

DMD_TYPE[3:0]

VERSION[2:0]

A_STROBE

A_MODE[1:0]

A_SEL[1:0]

A_ADDR[3:0]

OEZ

MBRST[15:0]

INIT

DLPR410

TDI_JTAG

PROM_CCK_DDC

PROGB_DDC

PROM_DO_DDC

DONE_DDC

INTB_DDC

B_STROBE

TDO_XCF16DDC

B_MODE[1:0]

B_SEL[1:0]

B_ADDR[3:0]

TCK_JTAG

TMS_JTAG

TDO_DDC

VLED0

VLED1

ARSTZ

CLKIN_R

DMD_A_RESET

DMD_B_RESET

OSC

50 MHz

图 5. DLPC410 and DLP7000 / DLP7000UV Functional Block Diagram

25

DLPC410

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

www.ti.com.cn

Functional Block Diagrams (接下页)

2x LVDS bus

DLPC410

DLP9500

DCLK_A

DVALID_A

DIN_A[15:0]

DCLKOUT_A

SCTRL_A

DOUT_A[15:0]

DCLK_B

DVALID_B

DIN_B[15:0]

DCLKOUT_B

SCTRL_B

DOUT_B[15:0]

DCLK_C

DVALID_C

DIN_C[15:0]

DCLKOUT_C

SCTRL_C

DOUT_C[15:0]

DCLK_D

DVALID_D

DIN_D[15:0]

DCLKOUT_D

SCTRL_D

DOUT_D[15:0]

User Interface

Controller

FPGA

SCPCLK

SCPDO

SCPDI

DMD_A_SCPENZ

DMD_B_SCPENZ

A_SCPENZ

COMP_DATA, NS_FLIP, WDT_ENZ,PWR_FLOAT

ROWMD[1:0]

ROWAD[10:0]

RST2BLKZ

BLKMD[1:0]

BLKAD[10:0]

LOAD4

DLPA200

B_SCPENZ

RST_ACTIVE

INIT_ACTIVE

ECP2_FINISHED

DMD_TYPE[3:0]

VERSION[2:0]

A_STROBE

A_MODE[1:0]

A_SEL[1:0]

A_ADDR[3:0]

OEZ

MBRST[15:0]

INIT

DLPR410

DLPA200

TDI_JTAG

PROM_CCK_DDC

PROGB_DDC

PROM_DO_DDC

DONE_DDC

INTB_DDC

MBRST[15:0]

B_STROBE

B_MODE[1:0]

B_SEL[1:0]

TDO_XCF16DDC

TCK_JTAG

TMS_JTAG

TDO_DDC

B_ADDR[3:0]

VLED0

VLED1

DMD_A_RESET

ARSTZ

CLKIN_R

DMD_B_RESET

OSC

50 MHz

图 6. DLPC410 and DLP9500 / DLP9500UV Functional Block Diagram

8.3 Feature Description

8.3.1 DLPC410 Binary Pattern Data Path

The DLPC410 receives binary pattern input data from the customer application formatted specifically for display

on one of the DLPC410 compatible DMDs. This data is captured on a row by row basis using specific data

formats with multiple signals which frame the data and provided control information from the customer defining

where in the DMD the data is destined. The DLPC410 then sends the pattern data to the DMD and uses the

received control information to decode and provide the correct control information to the DMD and other DLP

components.

8.3.1.1 DIN_A, DIN_B, DIN_C, DIN_D Input Data Buses

The DLPC410 has four differential 16-bit input data buses (A/B/C/D). Which of these input data bus signals are

used at any given time is specific to the DMD connected to the DLPC410 in the system. The data buses are

2xLVDS double-data-rate (DDR) buses which can transfer data at 800 MHz data rates per input. Data should be

synchronous and edge aligned with the input clocks for each specific data bus (A, B, C, or D). Depending on the

design, skewing the clock to data relationship may cause a problem. For timing constraints for the input data

clock to either the input data and/or DVALID, refer to Timing Requirements

26

DLPC410

www.ti.com.cn

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

Feature Description (接下页)

8.3.1.2 DCLKIN Input Clocks

DCLKIN is the differential input clock for each DLPC410 input data bus. There are four input clocks, one for each

bus (A/B/C/D). DCLKIN is a 400 MHz clock to the DMD which should be synchronous and edge aligned with all

data and control signals for that specific bus (A, B, C, or D). Depending on the design, skewing the clock to data

relationship may cause a problem. For timing constraints for the input data clock to either the input data and/or

DVALID, refer to Timing Requirements. Care should be take to keep clock jitter of these signals to a minimum.

8.3.1.3 DVALID Input Signals

The DVALID signal is a differential input signal, one for each input data bus (A/B/C/D), which indicates that data

being presented to the DLPC410 is valid. DVALID assertion latches the following types of data into the DLPC410

for decoding or passing information to the DMD:

•

Binary pattern data on input data buses A/B/C/D

Row Mode

Row Address

Block Mode

Block Address

RST2BLK signal

DVALID and all other inputs listed above should be synchronous to DCLKIN. DVALID can be asserted in one of

the three following ways:

•

DVALID can frame (remain active) individual DMD row loads with breaks between rows.

DVALID can frame continuous DMD block loads of multiple rows with breaks between blocks

DVALID can frame (remain active) the entire DMD device load (all rows) without any breaks.

If the DVALID frames individual blocks or the entire DMD, ensure that block and row controls are adjusted at the

proper locations in the data stream. See section DLPC410 Initialization and Training for further information.

注

After an active DVALID signal transitions inactive (low), DVALID should only transition to

active again on even number of clocks later, i.e. 2, 4, 6, etc.

8.3.1.4 DOUT_A, DOUT_B, DOUT_C, DOUT_D Output Data Buses

The DLPC410, having captured the incoming pattern data on its input data buses, provides this data on an

equivalent number of output data buses. The DLPC410 has four differential 16-bit output data buses (A/B/C/D),

which are aligned to its input data buses. Which of these input data bus signals are used at any given time is

specific to the DMD connected to the DLPC410 in the system. The data buses are 2xLVDS double-data-rate

(DDR) buses which can transfer data at 800 MHz data rates per output. Data should be synchronous and edge

aligned with the output clocks for each specific data bus (A, B, C, or D). Depending on the design, skewing the

clock to data relationship may cause a problem. For timing constraints for the output data clock to the output

data, refer to Timing Requirements.

8.3.1.5 DCLKOUT Output Clocks

DCLKOUT is the differential output clock for each DLPC410 output data bus. There are four output data clocks,

one for each bus (A/B/C/D) to the DMD. DCLKOUT is a 400 MHz clock to the DMD which should be

synchronous and edge aligned with all data and control signals for that specific bus (A, B, C, or D). Depending

on the design, skewing the clock to data relationship may cause a problem. For timing constraints for the output

data clocks to either the output data and/or SCTRL signals, refer to Timing Requirements.

27

DLPC410

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

www.ti.com.cn

Feature Description (接下页)

8.3.1.6 SCTRL Output Signals

The SCTRL signal is a differential output signal to the DMD which provides DMD control information. There are

four SCTRL differential pair signals, one for each bus (A/B/C/D). The control information is generated internally to

the DLPC410 and is specific to the connected DMD. Data should be synchronous and edge aligned with the

output clocks for each specific data bus (A, B, C, or D). Depending on the design, skewing the clock to SCTRL

relationship may cause a problem. For timing constraints for the output data clock to the SCTRL signals, refer to

Timing Requirements.

8.3.1.7 Supported DMD Bus Sizes

The DLPC410 supports the 2xLVDS Data Bus DMD types as shown in 表 11.

表 2. DMD Row Sizes, Bus Widths, and Row Lengths

NO. OF DATA

LINES

CLOCKS PER

ROW

TYPE

PIXELS PER ROW INPUT / OUTPUT BUSS

A[15,13,11,9,7,5,3,1]

1280

DLP650LNIR DMD

16

32

40

16

B[15,13,11,9,7,5,3,1]

A[15:0]

B[15:0]

DLP7000 and DLP7000UV DMDs

DLP9500 and DLP9500UV DMDs

1024

A[15:0]

B[15:0]

1920 (2048)

C[15:0]

64

16

D[15:0]

8.3.1.8 Row Cycle definition

A Row Cycle relates to specific number of input data clocks it takes for the customer to send one row of input

binary pattern data to one row of the DMD. DVALID starts the Row Cycle by transitioning to an active (logic '1')

state. The row cycle ends after the appropriate number of clock cycles per row are applied. Any input data on the

DIN input data buses should be appropriately provided during the Row Cycle. 表 2 shows the number of input

data clocks needing to populate one row of the DMD using the number of data lines identified in the table. Other

Row and Block related signals are captured at the start of a row cycle and will be discussed later.

There is also a unique row cycle called a No-Op Row Cycle which does not provide any valid input data nor any

valid block command. It is typically used to do nothing except provide the DLPC410 and DMD time to perform

internal actions already in process. The No-Op Row Cycle is discussed in No-Op Row Cycle Description.

28

DLPC410

www.ti.com.cn

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

8.3.1.9 DLP9500 and DLP9500UV Input Data Formatting

图 7 details one Row Cycle of input data formatting for the DLP9500 and DLP9500UV DMDs. For brevity, only

two data bits of all four 16 bit data bus (A/B/C/D) signals are shown, but there is enough information presented to

allow extrapolation to all data bus signals not shown.

表 3, 表 4, 表 5, and 表 6 show how each pixel of the DLP9500 and DLP9500UV DMDs maps to individual data

bus inputs and input clock edges within each row cycle. Because these DMDs are actually 2048 pixels per row

with only 1920 micromirrors per row, no visible data is loaded for the first clock cycle for A and B data and for the

last clock cycle for C and D data for each row load operation. This only applies to the DLP9500 and

DLP9500UV. For readability purposes, input buses DIN_A, DIN_B, DIN_C, and DIN_D are abbreviated as D_A,

D_B, D_C, and D_D. DCLKIN has been shortened to DCLK.

CLOCK CYCLE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

DCLK_N

DCLK_P

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

DVALID_P

D_AN(0)

D_AP(0)

D_AN(1)

D_AP(1)

D_BN(0)

D_BP(0)

D_BN(1)

D_BP(1)

D_CN(0)

D_CP(0)

D_CN(1)

D_CP(1)

D_DN(0)

D_DP(0)

D_DN(1)

D_DP(1)

图 7. DLP9500 / DLP9500UV 2XLVDS DMD Input Data Bus

29

DLPC410

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

www.ti.com.cn

表 3. DLP9500 / DLP9500UV 2XLVDS DMD Data Pixel Mapping D_A(15:0)

DCLK

EDGE

D_A(0)

D_A(1)

D_A(2)

D_A(3)

D_A(4)

D_A(5)

D_A(6)

D_A(7)

D_A(8)

D_A(9) D_A(10) D_A(11) D_A(12) D_A(13) D_A(14) D_A(15)

0

Not Visible

1

2

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

3

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

4

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

5

96

97

98

99

100

132

164

196

228

260

292

324

356

388

420

452

484

516

548

580

612

644

676

708

740

772

804

836

868

900

932

101

133

165

197

229

261

293

325

357

389

421

453

485

517

549

581

613

645

677

709

741

773

805

837

869

901

933

102

134

166

198

230

262

294

326

358

390

422

454

486

518

550

582

614

646

678

710

742

774

806

838

870

902

934

103

135

167

199

231

263

295

327

359

391

423

455

487

519

551

583

615

647

679

711

743

775

807

839

871

903

935

104

136

168

200

232

264

296

328

360

392

424

456

488

520

552

584

616

648

680

712

744

776

808

840

872

904

936

105

137

169

201

233

265

297

329

361

393

425

457

489

521

553

585

617

649

681

713

745

777

809

841

873

905

937

106

138

170

202

234

266

298

330

362

394

426

458

490

522

554

586

618

650

682

714

746

778

810

842

874

906

938

107

139

171

203

235

267

299

331

363

395

427

459

491

523

555

587

619

651

683

715

747

779

811

843

875

907

939

108

140

172

204

236

268

300

332

364

396

428

460

492

524

556

588

620

652

684

716

748

780

812

844

876

908

940

109

141

173

205

237

269

301

333

365

397

429

461

493

525

557

589

621

653

685

717

749

781

813

845

877

909

941

110

142

174

206

238

270

302

334

366

398

430

462

494

526

558

590

622

654

686

718

750

782

814

846

878

910

942

111

143

175

207

239

271

303

335

367

399

431

463

495

527

559

591

623

655

687

719

751

783

815

847

879

911

943

6

128

160

192

224

256

288

320

352

384

416

448

480

512

544

576

608

640

672

704

736

768

800

832

864

896

928

129

161

193

225

257

289

321

353

385

417

449

481

513

545

577

609

641

673

705

737

769

801

833

865

897

929

130

162

194

226

258

290

322

354

386

418

450

482

514

546

578

610

642

674

706

738

770

802

834

866

898

930

131

163

195

227

259

291

323

355

387

419

451

483

515

547

579

611

643

675

707

739

771

803

835

867

899

931

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

30

DLPC410

www.ti.com.cn

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

表 4. DLP9500 / DLP9500UV 2XLVDS DMD Data Pixel Mapping D_B(15:0)

DCLK

D_B(0)

EDGE

D_B(1)

D_B(2)

D_B(3)

D_B(4)

D_B(5)

D_B(6)

D_B(7)

D_B(8)

D_B(9) D_B(10) D_B(11) D_B(12) D_B(13) D_B(14) D_B(15)

0

1

Not Visible

2

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

3

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

4

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

5

112

144

176

208

240

272

304

336

368

400

432

464

496

528

560

592

624

656

688

720

752

784

816

848

880

912

944

113

145

177

209

241

273

305

337

369

401

433

465

497

529

561

593

625

657

689

721

753

785

817

849

881

913

945

114

146

178

210

242

274

306

338

370

402

434

466

498

530

562

594

626

658

690

722

754

786

818

850

882

914

946

115

147

179

211

243

275

307

339

371

403

435

467

499

531

563

595

627

659

691

723

755

787

819

851

883

915

947

116

148

180

212

244

276

308

340

372

404

436

468

500

532

564

596

628

660

692

724

756

788

820

852

884

916

948

117

149

181

213

245

277

309

341

373

405

437

469

501

533

565

597

629

661

693

725

757

789

821

853

885

917

949

118

150

182

214

246

278

310

342

374

406

438

470

502

534

566

598

630

662

694

726

758

790

822

854

886

918

950

119

151

183

215

247

279

311

343

375

407

439

471

503

535

567

599

631

663

695

727

759

791

823

855

887

919

951

120

152

184

216

248

280

312

344

376

408

440

472

504

536

568

600

632

664

696

728

760

792

824

856

888

920

952

121

153

185

217

249

281

313

345

377

409

441

473

505

537

569

601

633

665

697

729

761

793

825

857

889

921

953

122

154

186

218

250

282

314

346

378

410

442

474

506

538

570

602

634

666

698

730

762

794

826

858

890

922

954

123

155

187

219

251

283

315

347

379

411

443

475

507

539

571

603

635

667

699

731

763

795

827

859

891

923

955

124

156

188

220

252

284

316

348

380

412

444

476

508

540

572

604

636

668

700

732

764

796

828

860

892

924

956

125

157

189

221

253

285

317

349

381

413

445

477

509

541

573

605

637

669

701

733

765

797

829

861

893

925

957

126

158

190

222

254

286

318

350

382

414

446

478

510

542

574

606

638

670

702

734

766

798

830

862

894

926

958

127

159

191

223

255

287

319

351

383

415

447

479

511

543

575

607

639

671

703

735

767

799

831

863

895

927

959

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

DLPC410

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

www.ti.com.cn

表 5. DLP9500 / DLP9500UV 2XLVDS DMD Data Pixel Mapping D_C(15:0)

DCLK

EDGE

D_C(0)

D_C(1)

D_C(2)

D_C(3)

D_C(4)

D_C(5)

D_C(6)

D_C(7)

D_C(8)

D_C(9) D_C(10) D_C(11) D_C(12) D_C(13) D_C(14) D_C(15)

0

960

961

962

963

964

965

966

967

968

969

970

971

972

973

974

975

1

992

993

994

995

996

997

998

999

1000

1032

1064

1096

1128

1160

1192

1224

1256

1288

1320

1352

1384

1416

1448

1480

1512

1544

1576

1608

1640

1672

1704

1736

1768

1800

1832

1864

1896

1001

1033

1065

1097

1129

1161

1193

1225

1257

1289

1321

1353

1385

1417

1449

1481

1513

1545

1577

1609

1641

1673

1705

1737

1769

1801

1833

1865

1897

1002

1034

1066

1098

1130

1162

1194

1226

1258

1290

1322

1354

1386

1418

1450

1482

1514

1546

1578

1610

1642

1674

1706

1738

1770

1802

1834

1866

1898

1003

1035

1067

1099

1131

1163

1195

1227

1259

1291

1323

1355

1387

1419

1451

1483

1515

1547

1579

1611

1643

1675

1707

1739

1771

1803

1835

1867

1899

1004

1036

1068

1100

1132

1164

1196

1228

1260

1292

1324

1356

1388

1420

1452

1484

1516

1548

1580

1612

1644

1676

1708

1740

1772

1804

1836

1868

1900

1005

1037

1069

1101

1133

1165

1197

1229

1261

1293

1325

1357

1389

1421

1453

1485

1517

1549

1581

1613

1645

1677

1709

1741

1773

1805

1837

1869

1901

1006

1038

1070

1102

1134

1166

1198

1230

1262

1294

1326

1358

1390

1422

1454

1486

1518

1550

1582

1614

1646

1678

1710

1742

1774

1806

1838

1870

1902

1007

1039

1071

1103

1135

1167

1199

1231

1263

1295

1327

1359

1391

1423

1455

1487

1519

1551

1583

1615

1647

1679

1711

1743

1775

1807

1839

1871

1903

2

1024

1056

1088

1120

1152

1184

1216

1248

1280

1312

1344

1376

1408

1440

1472

1504

1536

1568

1600

1632

1664

1696

1728

1760

1792

1824

1856

1888

1025

1057

1089

1121

1153

1185

1217

1249

1281

1313

1345

1377

1409

1441

1473

1505

1537

1569

1601

1633

1665

1697

1729

1761

1793

1825

1857

1889

1026

1058

1090

1122

1154

1186

1218

1250

1282

1314

1346

1378

1410

1442

1474

1506

1538

1570

1602

1634

1666

1698

1730

1762

1794

1826

1858

1890

1027

1059

1091

1123

1155

1187

1219

1251

1283

1315

1347

1379

1411

1443

1475

1507

1539

1571

1603

1635

1667

1699

1731

1763

1795

1827

1859

1891

1028

1060

1092

1124

1156

1188

1220

1252

1284

1316

1348

1380

1412

1444

1476

1508

1540

1572

1604

1636

1668

1700

1732

1764

1796

1828

1860

1892

1029

1061

1093

1125

1157

1189

1221

1253

1285

1317

1349

1381

1413

1445

1477

1509

1541

1573

1605

1637

1669

1701

1733

1765

1797

1829

1861

1893

1030

1062

1094

1126

1158

1190

1222

1254

1286

1318

1350

1382

1414

1446

1478

1510

1542

1574

1606

1638

1670

1702

1734

1766

1798

1830

1862

1894

1031

1063

1095

1127

1159

1191

1223

1255

1287

1319

1351

1383

1415

1447

1479

1511

1543

1575

1607

1639

1671

1703

1735

1767

1799

1831

1863

1895

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Not Visible

32

DLPC410

www.ti.com.cn

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

表 6. DLP9500 / DLP9500UV 2XLVDS DMD Data Pixel Mapping D_D(15:0)

DCLK

D_D(0)

EDGE

D_D(1)

D_D(2)

D_D(3)

D_D(4)

D_D(5)

D_D(6)

D_D(7)

D_D(8)

D_D(9) D_D(10) D_D(11) D_D(12) D_D(13) D_D(14) D_D(15)

0

976

977

978

979

980

981

982

983

984

985

986

987

988

989

990

991

1

1008

1040

1072

1104

1136

1168

1200

1232

1264

1296

1328

1360

1392

1424

1456

1488

1520

1552

1584

1616

1648

1680

1712

1744

1776

1808

1840

1872

1904

1009

1041

1073

1105

1137

1169

1201

1233

1265

1297

1329

1361

1393

1425

1457

1489

1521

1553

1585

1617

1649

1681

1713

1745

1777

1809

1841

1873

1905

1010

1042

1074

1106

1138

1170

1202

1234

1266

1298

1330

1362

1394

1426

1458

1490

1522

1554

1586

1618

1650

1682

1714

1746

1778

1810

1842

1874

1906

1011

1043

1075

1107

1139

1171

1203

1235

1267

1299

1331

1363

1395

1427

1459

1491

1523

1555

1587

1619

1651

1683

1715

1747

1779

1811

1843

1875

1907

1012

1044

1076

1108

1140

1172

1204

1236

1268

1300

1332

1364

1396

1428

1460

1492

1524

1556

1588

1620

1652

1684

1716

1748

1780

1812

1844

1876

1908

1013

1045

1077

1109

1141

1173

1205

1237

1269

1301

1333

1365

1397

1429

1461

1493

1525

1557

1589

1621

1653

1685

1717

1749

1781

1813

1845

1877

1909

1014

1046

1078

1110

1142

1174

1206

1238

1270

1302

1334

1366

1398

1430

1462

1494

1526

1558

1590

1622

1654

1686

1718

1750

1782

1814

1846

1878

1910

1015

1047

1079

1111

1143

1175

1207

1239

1271

1303

1335

1367

1399

1431

1463

1495

1527

1559

1591

1623

1655

1687

1719

1751

1783

1815

1847

1879

1911

1016

1048

1080

1112

1144

1176

1208

1240

1272

1304

1336

1368

1400

1432

1464

1496

1528

1560

1592

1624

1656

1688

1720

1752

1784

1816

1848

1880

1912

1017

1049

1081

1113

1145

1177

1209

1241

1273

1305

1337

1369

1401

1433

1465

1497

1529

1561

1593

1625

1657

1689

1721

1753

1785

1817

1849

1881

1913

1018

1050

1082

1114

1146

1178

1210

1242

1274

1306

1338

1370

1402

1434

1466

1498

1530

1562

1594

1626

1658

1690

1722

1754

1786

1818

1850

1882

1914

1019

1051

1083

1115

1147

1179

1211

1243

1275

1307

1339

1371

1403

1435

1467

1499

1531

1563

1595

1627

1659

1691

1723

1755

1787

1819

1851

1883

1915

1020

1052

1084

1116

1148

1180

1212

1244

1276

1308

1340

1372

1404

1436

1468

1500

1532

1564

1596

1628

1660

1692

1724

1756

1788

1820

1852

1884

1916

1021

1053

1085

1117

1149

1181

1213

1245

1277

1309

1341

1373

1405

1437

1469

1501

1533

1565

1597

1629

1661

1693

1725

1757

1789

1821

1853

1885

1917

1022

1054

1086

1118

1150

1182

1214

1246

1278

1310

1342

1374

1406

1438

1470

1502

1534

1566

1598

1630

1662

1694

1726

1758

1790

1822

1854

1886

1918

1023

1055

1087

1119

1151

1183

1215

1247

1279

1311

1343

1375

1407

1439

1471

1503

1535

1567

1599

1631

1663

1695

1727

1759

1791

1823

1855

1887

1919

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Not Visible

33

DLPC410

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

www.ti.com.cn

8.3.1.10 DLP7000 and DLP7000UV Input Data Bus

图 8 details one row cycle of input data formatting for the DLP7000 and DLP7000UV DMDs. For brevity, only two

data bits of both 16 bit data bus (A/B) signals are shown, but there is enough information presented to allow

extrapolation to data bus signals not shown.

表 7 and 表 8 show how each pixel of the DLP7000 and DLP7000UV DMDs maps to individual data bus inputs

and input clock edges within each row load operation.

注

In the following charts, for readability purposes input buses DIN_A, DIN_B are abbreviated

as D_A, D_B. DCLKIN has been shortened to DCLK.

CLOCK CYCLE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

DCLK_N

DCLK_P

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

DVALID_P

D_AN(0)

D_AP(0)

D_AN(1)

D_AP(1)

D_BN(0)

D_BP(0)

D_BN(1)

D_BP(1)

图 8. DLP7000 / DLP7000UV 2XLVDS DMD Input Data Bus

34

DLPC410

www.ti.com.cn

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

表 7. DLP7000 / DLP7000UV 2XLVDS DMD Data Pixel Mapping D_A(15:0)

DCLK

D_A(0)

EDGE

D_A(1)

D_A(2)

D_A(3)

D_A(4)

D_A(5)

D_A(6)

D_A(7)

D_A(8)

D_A(9) D_A(10) D_A(11) D_A(12) D_A(13) D_A(14) D_A(15)

0

1

2

3

4

5

6

7

8

9

10

42

11

43

12

44

13

45

14

46

15

47

1

32

33

34

35

36

37

38

39

40

41

2

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

3

96

97

98

99

100

132

164

196

228

260

292

324

356

388

420

452

484

516

548

580

612

644

676

708

740

772

804

836

868

900

932

964

996

101

133

165

197

229

261

293

325

357

389

421

453

485

517

549

581

613

645

677

709

741

773

805

837

869

901

933

965

997

102

134

166

198

230

262

294

326

358

390

422

454

486

518

550

582

614

646

678

710

742

774

806

838

870

902

934

966

998

103

135

167

199

231

263

295

327

359

391

423

455

487

519

551

583

615

647

679

711

743

775

807

839

871

903

935

967

999

104

136

168

200

232

264

296

328

360

392

424

456

488

520

552

584

616

648

680

712

744

776

808

840

872

904

936

968

1000

105

137

169

201

233

265

297

329

361

393

425

457

489

521

553

585

617

649

681

713

745

777

809

841

873

905

937

969

1001

106

138

170

202

234

266

298

330

362

394

426

458

490

522

554

586

618

650

682

714

746

778

810

842

874

906

938

970

1002

107

139

171

203

235

267

299

331

363

395

427

459

491

523

555

587

619

651

683

715

747

779

811

843

875

907

939

971

1003

108

140

172

204

236

268

300

332

364

396

428

460

492

524

556

588

620

652

684

716

748

780

812

844

876

908

940

972

1004

109

141

173

205

237

269

301

333

365

397

429

461

493

525

557

589

621

653

685

717

749

781

813

845

877

909

941

973

1005

110

142

174

206

238

270

302

334

366

398

430

462

494

526

558

590

622

654

686

718

750

782

814

846

878

910

942

974

1006

111

143

175

207

239

271

303

335

367

399

431

463

495

527

559

591

623

655

687

719

751

783

815

847

879

911

943

975

1007

4

128

160

192

224

256

288

320

352

384

416

448

480

512

544

576

608

640

672

704

736

768

800

832

864

896

928

960

992

129

161

193

225

257

289

321

353

385

417

449

481

513

545

577

609

641

673

705

737

769

801

833

865

897

929

961

993

130

162

194

226

258

290

322

354

386

418

450

482

514

546

578

610

642

674

706

738

770

802

834

866

898

930

962

994

131

163

195

227

259

291

323

355

387

419

451

483

515

547

579

611

643

675

707

739

771

803

835

867

899

931

963

995

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

35

DLPC410

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

www.ti.com.cn

表 8. DLP7000 / DLP7000UV 2XLVDS DMD Data Pixel Mapping D_B(15:0)

DCLK

EDGE

D_B(0)

D_B(1)

D_B(2)

D_B(3)

D_B(4)

D_B(5)

D_B(6)

D_B(7)

D_B(8)

D_B(9) D_B(10) D_B(11) D_B(12) D_B(13) D_B(14) D_B(15)

0

16

48

17

49

18

50

19

51

20

52

21

53

22

54

23

55

24

56

25

57

26

58

27

59

28

60

29

61

30

62

31

63

1

2

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

3

112

144

176

208

240

272

304

336

368

400

432

464

496

528

560

592

624

656

688

720

752

784

816

848

880

912

944

976

1008

113

145

177

209

241

273

305

337

369

401

433

465

497

529

561

593

625

657

689

721

753

785

817

849

881

913

945

977

1009

114

146

178

210

242

274

306

338

370

402

434

466

498

530

562

594

626

658

690

722

754

786

818

850

882

914

946

978

1010

115

147

179

211

243

275

307

339

371

403

435

467

499

531

563

595

627

659

691

723

755

787

819

851

883

915

947

979

1011

116

148

180

212

244

276

308

340

372

404

436

468

500

532

564

596

628

660

692

724

756

788

820

852

884

916

948

980

1012

117

149

181

213

245

277

309

341

373

405

437

469

501

533

565

597

629

661

693

725

757

789

821

853

885

917

949

981

1013

118

150

182

214

246

278

310

342

374

406

438

470

502

534

566

598

630

662

694

726

758

790

822

854

886

918

950

982

1014

119

151

183

215

247

279

311

343

375

407

439

471

503

535

567

599

631

663

695

727

759

791

823

855

887

919

951

983

1015

120

152

184

216

248

280

312

344

376

408

440

472

504

536

568

600

632

664

696

728

760

792

824

856

888

920

952

984

1016

121

153

185

217

249

281

313

345

377

409

441

473

505

537

569

601

633

665

697

729

761

793

825

857

889

921

953

985

1017

122

154

186

218

250

282

314

346

378

410

442

474

506

538

570

602

634

666

698

730

762

794

826

858

890

922

954

986

1018

123

155

187

219

251

283

315

347

379

411

443

475

507

539

571

603

635

667

699

731

763

795

827

859

891

923

955

987

1019

124

156

188

220

252

284

316

348

380

412

444

476

508

540

572

604

636

668

700

732

764

796

828

860

892

924

956

988

1020

125

157

189

221

253

285

317

349

381

413

445

477

509

541

573

605

637

669

701

733

765

797

829

861

893

925

957

989

1021

126

158

190

222

254

286

318

350

382

414

446

478

510

542

574

606

638

670

702

734

766

798

830

862

894

926

958

990

1022

127

159

191

223

255

287

319

351

383

415

447

479

511

543

575

607

639

671

703

735

767

799

831

863

895

927

959

991

1023

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

36

DLPC410

www.ti.com.cn

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

8.3.1.11 DLP650LNIR Input Data Bus

图 9 details one row cycle of input data formatting for the DLP650LNIR DMD. For brevity, only two data bits of

both 8 bit data bus (A/B) signals are shown, but there is enough information presented to allow extrapolation to

data bus signals not shown.

表 9 and 表 10 show how each pixel of the DLP650LNIR DMD maps to individual data bus inputs and input clock

edges within each row load operation.

注

In the following charts, for readability purposes input buses DIN_A, DIN_B are abbreviated

as D_A, D_B. DCLKIN has been shortened to DCLK.

Since showing the entire 40 clock row cycle would make this chart unreadable, the chart

has been broken in the middle. However, there is enough information available to allow

extrapolation of the missing data.

CLOCK CYCLE

1

2

3

4

5

6

7

8

33

34

35

36

37

38

39

40

DCLK_N

DCLK_P

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

DVALID_P

D_AN(1)

D_AP(1)

D_AN(3)

D_AP(3)

D_BN(1)

D_BP(1)

D_BN(3)

D_BP(3)

图 9. DLP650LNIR 2xLVDS DMD Input Data Bus

37

DLPC410

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

www.ti.com.cn

表 9. DLP650LNIR 2xLVDS DMD Data Pixel Mapping D_A(15,13,11,9,7,5,3,1)

DCLK EDGE

0

D_A(1)

0

D_A(3)

2

D_A(5)

4

D_A(7

6

D_A(9)

8

D_A(11)

10

D_A(13)

12

D_A(15)

14

1

32

34

36

38

40

42

44

46

2

64

66

68

70

72

74

76

78

3

96

98

100

5

102

7

104

9

106

11

108

13

110

15

4

1

3

5

33

35

37

39

41

43

45

47

6

65

67

69

71

73

75

77

79

7

97

99

101

132

164

196

228

133

165

197

229

260

292

324

356

261

293

325

357

388

420

452

484

389

421

453

485

516

548

580

612

517

549

581

613

644

676

708

740

645

677

709

741

772

804

836

868

773

805

837

869

103

134

166

198

230

135

167

199

231

262

294

326

358

263

295

327

359

390

422

454

486

391

423

455

487

518

550

582

614

519

551

583

615

646

678

710

742

647

679

711

743

774

806

838

870

775

807

839

871

105

136

168

200

232

137

169

201

233

264

296

328

360

265

297

329

361

392

424

456

488

393

425

457

489

520

552

584

616

521

553

585

617

648

680

712

744

649

681

713

745

776

808

840

872

777

809

841

873

107

138

170

202

234

139

171

203

235

266

298

330

362

267

299

331

363

394

426

458

490

395

427

459

491

522

554

586

618

523

555

587

619

650

682

714

746

651

683

715

747

778

810

842

874

779

811

843

875

109

140

172

204

236

141

173

205

237

268

300

332

364

269

301

333

365

396

428

460

492

397

429

461

493

524

556

588

620

525

557

589

621

652

684

716

748

653

685

717

749

780

812

844

876

781

813

845

877

111

142

174

206

238

143

175

207

239

270

302

334

366

271

303

335

367

398

430

462

494

399

431

463

495

526

558

590

622

527

559

591

623

654

686

718

750

655

687

719

751

782

814

846

878

783

815

847

879

8

128

160

192

224

129

161

193

225

256

288

320

352

257

289

321

353

384

416

448

480

385

417

449

481

512

544

576

608

513

545

577

609

640

672

704

736

641

673

705

737

768

800

832

864

769

801

833

865

130

162

194

226

131

163

195

227

258

290

322

354

259

291

323

355

386

418

450

482

387

419

451

483

514

546

578

610

515

547

579

611

642

674

706

738

643

675

707

739

770

802

834

866

771

803

835

867

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

38

DLPC410

www.ti.com.cn

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

表 9. DLP650LNIR 2xLVDS DMD Data Pixel Mapping D_A(15,13,11,9,7,5,3,1) (接下页)

DCLK EDGE

D_A(1)

D_A(3)

D_A(5)

D_A(7

D_A(9)

D_A(11)

D_A(13)

D_A(15)

910

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

896

898

900

902

904

906

908

928

930

832

934

936

938

940

942

960

962

964

966

968

970

972

974

992

994

996

998

1000

905

1002

907

1004

909

1006

911

897

899

901

903

929

931

933

935

937

939

941

943

961

963

965

967

969

971

973

975

993

995

997

999

1001

1032

1064

1096

1128

1033

1065

1097

1129

1160

1192

1224

1256

1161

1193

1225

1257

1003

1034

1066

1098

1130

1035

1067

1099

1131

1162

1194

1226

1258

1163

1195

1227

1259

1005

1036

1068

1100

1132

1037

1069

1101

1133

1164

1196

1228

1260

1165

1197

1229

1261

1007

1038

1070

1102

1134

1039

1071

1103

1135

1166

1198

1230

1262

1167

1199

1231

1263

1024

1056

1088

1120

1025

1057

1089

1121

1152

1184

1216

1248

1153

1185

1217

1249

1026

1058

1090

1122

1027

1059

1091

1123

1154

1186

1218

1250

1155

1187

1219

1251

1028

1060

1092

1124

1029

1061

1093

1125

1156

1188

1220

1252

1157

1189

1221

1253

1030

1062

1094

1126

1031

1063

1095

1127

1158

1190

1222

1254

1159

1191

1223

1255

39

DLPC410

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

www.ti.com.cn

表 10. DLP650LNIR 2xLVDS DMD Data Pixel Mapping D_B(15,13,11,9,7,5,3,1)

DCLK EDGE

0

D_B(1)

16

D_B(3)

18

D_B(5)

20

D_B(7)

22

D_B(9)

24

D_B(11)

26

D_B(13)

28

D_B(15)

30

1

48

50

52

54

56

58

60

62

2

80

82

84

86

88

90

92

94

3

112

17

114

19

116

21

118

23

120

25

122

27

124

29

126

31

4

5

49

51

53

55

57

59

61

63

6

81

83

85

87

89

91

93

95

7

113

144

176

208

240

145

177

209

241

272

304

336

368

273

305

337

369

400

432

464

496

401

433

465

497

528

560

592

624

529

561

593

625

656

688

720

752

657

689

721

753

784

816

848

880

785

817

849

881

115

146

178

210

242

147

179

211

243

274

306

338

370

275

307

339

371

402

434

466

498

403

435

467

499

530

562

594

626

531

563

595

627

658

690

722

754

659

691

723

755

786

818

850

882

787

819

851

883

117

148

180

212

244

149

181

213

245

276

308

340

372

277

309

341

373

404

436

468

500

405

437

469

501

532

564

596

628

533

565

597

629

660

692

724

756

661

693

725

757

788

820

852

884

789

821

853

885

119

150

182

214

246

151

183

215

247

278

310

342

374

279

311

343

375

406

438

470

502

407

439

471

503

534

566

598

630

535

567

599

631

662

694

726

758

663

695

727

759

790

822

854

886

791

823

855

887

121

152

184

216

248

153

185

217

249

280

312

344

376

281

313

345

377

408

440

472

504

409

441

473

505

536

568

600

632

537

569

601

633

664

696

728

760

665

697

729

761

792

824

856

888

793

825

857

889

123

154

186

218

250

155

187

219

251

282

314

346

378

283

315

347

379

410

442

474

506

411

443

475

507

538

570

602

634

539

571

603

635

666

698

730

762

667

699

731

763

794

826

858

890

795

827

859

891

125

156

188

220

252

157

189

221

253

284

316

348

380

285

317

349

381

412

444

476

508

413

445

477

509

540

572

604

636

541

573

605

637

668

700

732

764

669

701

733

765

796

828

860

892

797

829

861

893

127

158

190

222

254

159

191

223

255

286

318

350

382

287

319

351

383

414

446

478

510

415

447

479

511

542

574

606

638

543

575

607

639

670

702

734

766

671

703

735

767

798

830

862

894

799

831

863

895

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

40

DLPC410

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ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

表 10. DLP650LNIR 2xLVDS DMD Data Pixel Mapping D_B(15,13,11,9,7,5,3,1) (接下页)

DCLK EDGE

D_B(1)

D_B(3)

D_B(5)

D_B(7)

D_B(9)

D_B(11)

D_B(13)

D_B(15)

926

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

912

914

916

918

920

922

924

944

946

948

950

952

954

956

958

976

978

980

982

984

986

988

990

1008

913

1010

915

1012

917

1014

919

1016

921

1018

923

1020

925

1022

927

945

947

949

951

953

955

957

959

977

979

981

983

985

987

989

991

1009

1040

1072

1104

1136

1041

1073

1105

1137

1168

1200

1232

1264

1169

1201

1233

1265

1011

1042

1074

1106

1138

1043

1075

1107

1139

1170

1202

1234

1266

1171

1203

1235

1267

1013

1044

1076

1108

1140

1045

1077

1109

1141

1172

1204

1236

1268

1173

1205

1237

1269

1015

1046

1078

1110

1142

1047

1079

1111

1143

1174

1206

1238

1270

1175

1207

1239

1271

1017

1048

1080

1112

1144

1049

1081

1113

1145

1176

1208

1240

1272

1177

1209

1241

1273

1019

1050

1082

1114

1146

1051

1083

1115

1147

1178

1210

1242

1274

1179

1211

1243

1275

1021

1052

1084

1116

1148

1053

1085

1117

1149

1180

1212

1244

1276

1181

1213

1245

1277

1023

1054

1086

1118

1150

1055

1087

1119

1151

1182

1214

1246

1278

1183

1215

1247

1279

8.3.2 Data Bus Operations

8.3.2.1 Row Addressing

The DIN (input data), DCLKIN (input data clock), and DVALID (data valid) signals enable the DLPC410 to

capture one row of customer input data and send that data to the DMD. For the DMD to know specifically to

which row the data will be applied, the ROW_MD(1:0) (row mode), the ROW_AD(10:0) (row address), and the

NS_FLIP (North/South Flip) signal inputs must be presented to the DLPC410 inputs during each row cycle. 表 11

shows the number of rows for each DMD supported by the DLPC410.

表 11. DMD Row and Columns

CLOCKS PER

ROW

NO. OF DATA

LINES

TYPE

COLUMNS

ROWS

DLP650LNIR DMD

1280

1024

1920 (2048)⁽¹⁾

800

768

40

16

32

64

DLP7000 and DLP7000UV DMDs

DLP9500 and DLP9500UV DMDs

1080

(1) The DLP9500 and DLP9500UV DMDs have 2048 memory cells per row . There are 64 bits at the beginning of each row and 64 bits at

the end of each row which do not have corresponding DMD micromirrors. These 128 memory cells must be loaded with data but the

data content can be arbitrary and will not affect the 1920 physical micromirrors within that row.

DMD data is loaded into the DMD SRAM pixels one row of data at a time. The DLP9500 and DLP9500UV

require pattern data input to all four input data buses (A,B,C,D) while the DLP650LNIR, DLP7000 and

DLP7000UV require pattern data to be input to two input data buses (A,B). The DLP650LNIR uses only the odd

data bus pins of input buses A and B. The DMD input data buses are provided by the following DLPC410

outputs:

•

DDC_DCLKOUT - high speed 2xLVDS data clock out to DMD

SCTRL - high speed control bus to DMD

DDC_DOUT[X:Y] - 2xLVDS data bus where X and Y depend on the DMD.

41

DLPC410

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

www.ti.com.cn

These signals are all output from the DLPC410 and are listed in Pin Configuration and Functions. Data and

control from the DLPC410 are clocked into the DMD on both the rising and falling edges of the DDR data clocks:

DDC_DCLKOUT_[A, B] for the 2 input bus DMDs and DDC_DCLKOUT_[A, B, C, D] for the 4 input bus DMDs.

Data loading does not cause mirror state changes - mirrors transition to the next state only when a Mirror

Clocking Pulse (Reset) operation is performed.

The row load length in clocks can be determined by the following equation: number row clocks = number of

pixels per row / (total data buses bit width × 2 edges per clock). The "2 edges per clock" in the denominator is a

direct results of the Dual Data Rate (DDR) nature of the DMD input data bus. This equation yields the results

shown in 表 11

The DMD incorporates single row write operations using a row address counter that has different modes of

operation. These modes are dependent on the state of the ROW_MD, ROW_AD, and NS_FLIP input signals. As

shown in 表 12, ROW_MD(1:0) determines the row mode for a given Row Cycle, and, when ROW_MD = "10",

then ROW_AD(10:0) selects the customer supplied single row address. ROW_MD and ROW_AD must be

asserted and deasserted synchronously with DVALID and must be valid synchronous to the beginning of the

data as shown in 图 10. If only one specific mode will be utilized in a customer system application, it is certainly

acceptable to leave these values at their same desired input levels for as long as desired.

Row address orientation depends on the North/South Flip Flag (NS_FLIP) input to the DLPC410. This input

controls if the DMD starting row address starts at the top of the DMD (Row 0) and increments downward, or from

the bottom of the DMD (last row) and decrements upward.

The row address counter does not automatically wrap-around when using the increment row address pointer

instructions. For example, after the final row is addressed, the row address pointer must be set to row 0.

表 12. Row Modes and Row Addresses

ROW_MD(1:0)

ROW_AD(10:0)⁽¹⁾

"xxxxxxxxxxx"

NS_FLIP⁽²⁾

ACTION

"00"

"01"

"x"

0

Row No-Op (No data write)

Increment internal row address by '1' - write concurrent data into that row

Decrement internal row address by '1' - write concurrent data into that row

1

Set Random row address as specified on ROW_AD(10:0) inputs - write

concurrent data into that row.

"10"

"11"

ROW_AD(10:0)

"xxxxxxxxxxx"

"x"

0

Set First row address (DMD Row 0) and write concurrent data into that row

Set Last row address (DMD last row ) - write concurrent data into that row

(Last row = 767 for DP7000, 799 for DLP650LNIR, 1079 for DLP9500)

1

(1) "xxxxxxxxxxx" and "x" are don't care situations.

(2) It is recommended NS_FLIP remain constant throughout the loading of the DMD and not change on a row cycle basis.

8.3.2.2 Single Row Write Operation

Once initialization is complete (INIT_ACTIVE = 0) the user is free to send data and control information to the

DLPC410. When the user asserts the DVALID signal for the LVDS input buses, the DLPC410 samples the

customer supplied binary input pattern data (DIN) as well as the Row Mode, Row Address, Block Mode, Block

Address, and other control information. The DLPC410 then sends pattern data synchronously to the DMD along

with row address and control information. The row cycle period is defined by the Clocks per Row in 表 11 and is

synchronous with DVALID as shown in 图 10. If DVALID is removed midway in a Row Cycle, the DLPC410

continues loading data regardless of data validity until the internal row cycle counter reaches the terminal count

of Clocks/Row for that DMD.

图 10 is an example of a single Row Cycle for the DLP7000 DMD. A total of 32 bits of input data are presented

to the DLPC410 on each clock edge (16 bits on Bus A + 16 bits on Bus B) . An entire line must be written for

data to be latched into DMD memory and it requires 16 DDR clock cycles to write a single row of 1024 bits.

42

DLPC410

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ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

0

1

29 30

31

DCLKIN

DVALID

ROWMD/ROWAD

BLK_MD/BLK_AD

STEP_VCC/NS_FLIP/

COMP_DATA

DIN_A/B

图 10. Single Row Write Operation (DLP7000 DMD)

8.3.2.3 No-Op Row Cycle Description

A Row No-Op is a row cycle in which setting ROW_MD = "00" commands the DLPC410 that within the current

row cycle, no Row Write operation is to be performed. A Block No-Op is a row cycle in which BLK_MD = "00"

commands the DLPC410 that within the current row cycle no Block Operation is to be performed. Row No-Ops

can be inserted when only block operations are desired, Block No-ops can be inserted when only Row Write

operations are desired, or both Row No-Ops and Block No-Ops can be performed at the same time when neither

type of operation is desired (as shown in 图 11). No-Ops are frequently inserted in the stream of data and

commands when delays are desired to complete on-going operations to avoid violating delay requirements.

0

1

29

30

31

DCLKIN

DVALID

00

ROWMD

BLK_MD

XXXX

BLK_AD

图 11. No-Op Row Cycle (DLP7000 example)

8.3.3 DMD Block Operations

Previous sections have described in detail how to send binary pattern data through the DLPC410 Controller to

the connected DMD. Although the data loading process involves loading the specified data into the SRAM cells

in the DMD array, this loading of data does not change the physical state of the DMD Micromirrors. The state of

the mirrors can only be changed (or left the same if the data under the mirrors is unchanged) when a Mirror

Clocking Pulse (Reset) is applied to the DMD MBRST pins from the DLPA200.

A sequence of Mirror Clocking Pulses (Resets) begins by asserting a row cycle with BLK_MD and BLK_AD as

described in 表 14. Shortly after the row cycle, RST_ACTIVE output to the customer transitions to logic '1' for

approximately 4.5 µs indicating a Mirror Clocking Pulse operation is in progress. During this time, no additional

Mirror Clocking Pulses may be initiated until RST_ACTIVE returns to logic '0'.

RST_ACTIVE does not return to logic '0' unless:

•

data load row cycles are issued to other DMD blocks as in 图 15 or,

No-Op row cycles are provided to the DLPC410 to enable MCP or Block Clear operations to continue

This is accomplished by asserting DVALID while holding ROWMD = “00” and BLKMD = “00” for the pre-requisite

number of CLKS per ROW (表 11) clock cycles, as in 图 11. If no other blocks need to be loaded then continuous

No-Op row cycles are applied as in 图 11 .

43

DLPC410

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

www.ti.com.cn

8.3.3.1 Mirror Clocking Pulse (MCP)

A Mirror Clocking Pulse is an analog voltage waveform provided to the DMD from the DLPA200 DMD

Micromirror Driver. This waveform times the electrostatic forces which cause each micromirror to transition to its

next state. This next state is determined by the data in the SRAM cell beneath each pixel. If the data has

changed, the micromirror will rotate its position 24 degrees to the opposite state. If the data is unchanged, the

mirror will remain in the same state. The DLPC410 instructions the DLPA200 to apply Mirror Clocking Pulses to

the DLPA200 based on instructions from the user.

注

A Mirror Clocking Pulse (MCP) is often referred to as a "Reset" operation.

8.3.3.2 Reset Active (RST_ACTIVE)

RST_ACTIVE is an output from the DLPC410 to indicate to the user that a user requested Reset (MCP) has

been accepted by the DLPC410. Shortly after the user requests a Reset (MCP) by asserting the appropriate

Block Control signals defined in DMD Block Control Signals, RST_ACTIVE output to the user will transition to

logic '1' for approximately 4.5 µs indicating a Mirror Clocking Pulse operation is in progress. While RST_ACTIVE

is logic '1', no additional Mirror Clocking Pulse requests may be initiated by the user until RST_ACTIVE returns to

logic '0'. RST_ACTIVE is synchronized to a version of DCLKIN. As such, circuits in the application FPGA should

consider this signal asynchronous and use standard synchronization techniques to assure reliable registering of

this signal.

注

After a Mirror Clocking Pulse or Clear command is given, RST_ACTIVE may not be

asserted until up to 60ns after the command. During this time, no other command should

be given.

8.3.3.3 DMD Block Control Signals

The DMD micromirrors and their corresponding SRAM pixels are organized into horizontal rows where data is

loaded one row at a time. DMD Blocks are defined as a group of sequential rows of mirrors. Each mirror block is

measured in groups of [ROWS per BLK] as described in 表 11. DMD blocks are typically numbered from 0 to 15

with 0 being the block at the top of the DMD (row 0) and 15 being the block at the bottom of the DMD.

表 13. DMD Block Characteristics

ROWS PER

BLOCK

DMD TYPE

COLUMNS

ROWS

BLOCKS

DLP650LNIR DMD

1280

1024

1920

800

768

16

15

50

DLP7000 and DLP7000UV DMDs

DLP9500 and DLP9500UV DMDs

48

1080

72

8.3.3.3.1 Block Mode - BLK_MD1:0)

The Block Mode signals define the type of block operation the user would like to take place. The allowed

operations which can be requested are defined in 表 14. These signals work along side the RST2BLK and the

Block Address signals to provide the gamut of Block Operations that enable DMD mirrors to update to their next

used desired state. These signals should be setup synchronously with the start of a row cycle.

8.3.3.3.2 Block Address - BLK_AD(3:0)

The Block Address signals help to specify which block or group of blocks will be acted upon in a user issued

Block Operation. They work with the RST2BLK and Block Mode signals to indicate which block or group of

blocks will see a Reset (MCP). These signals should be setup synchronously with the start of a row cycle.

44

DLPC410

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ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

8.3.3.3.3 Reset 2 Blocks - RST2BLK

The Reset 2 Blocks (RST2BLK) signal helps to signify a multiple block operation is requested by the user, where,

depending on the state of RST2BLK, either two blocks or 4 blocks will be Reset together. The specific blocks to

be Reset will then be determined by the Block Mode and Block Address. This signal should be setup

synchronously with the start of a row cycle.

注

RST2BLK needs to be kept low during initialization for proper setup of the system.

8.3.3.4 DMD Block Operations

Once a portion or all of the DMD is loaded with new data, the user typically requests a Block Operation to be

performed. This operation causes the DLPC410 to initiate one of the many block related activities to a block or

group of blocks to the DMD. Available Block operations are:

•

Block No-Op - user requests via BLK_MD(1:0) = "00" that no block operations are to take place in this row

cycle. This is typically the case for row cycles used for data loading purposes only without any block

operations.

•

Block Clear Request - user requests a single block to be cleared causing all SRAM cells within that block to

be reset to logic '0'.

Single Block Reset Request - user requests a single DMD block be provided a Reset (MCP) signal to cause

the micromirrors within that block to update to their new values.

Dual Block Reset Request - user requests two sequential DMD blocks be provided Reset (MCP) signals to

cause the micromirrors within those blocks to update to their new values.

Quad Block Reset Request - user requests four sequential DMD blocks be provided Reset (MCP) signals to

cause the micromirrors within those blocks to update to their new values.

Global Reset Request - user requests all DMD blocks be provided Reset (MCP) signals to cause all DMD

micromirrors to update to their new values.

DMD Park (Float) Request - user requests all DMD micromirrors be provided special Parking Reset (MCP)

signals causing the micromirrors within those blocks to relax to their unbiased state. This request is intended

to place the micromirrors in the Parked state prior to power removal (shutdown).

Mirror blocks are addressed using the Block Address (BLK_AD[3:0]) signals for application of either a Mirror

Clocking Pulse (Reset) or a Memory Clear operation by asserting the block control signals of 表 14 at the start of

each row data load. RST2BLK, Block Mode (BLK_MD[1:0]), and BLK_AD[3:0] define the requested operation as

shown in 表 14 and designate which mirror block or mirror blocks are issued a Mirror Clocking Pulse or are

Cleared. The number of DMD blocks and BLOCKS/ROW is unique to each DMD - refer to the individual DMD

data sheets for DMD block definition.

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表 14. Block Control Signals and Operations

RST2BLK

BLK_MD(1:0)

00

01

10

11

BLK_AD(3:0)

xxxx

OPERATION

None

OPERATION TYPE

x

0

1

x

Block No-OP

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0000

0001

0010

0011

0100

0101

0110

0111

000x

001x

010x

011x

10xx

11xx

Clear block 00

Clear block 01

Clear block 02

Clear block 03

Clear block 04

Clear block 05

Clear block 06

Clear block 07

Clear block 08

Clear block 09

Clear block 10

Clear block 11

Clear block 12

Clear block 13

Clear block 14

Clear block 15

Reset block 00

Reset block 01

Reset block 02

Reset block 03

Reset block 04

Reset block 05

Reset block 06

Reset block 07

Reset block 08

Reset block 09

Reset block 10

Reset block 11

Reset block 12

Reset block 13

Reset block 14

Reset block 15

Reset blocks 00-01

Reset blocks 02-03

Reset blocks 04-05

Reset blocks 06-07

Reset blocks 08-09

Reset blocks 10-11

Reset blocks 12-13

Reset blocks 14-15

Reset blocks 00-03

Reset blocks 04-07

Reset blocks 08-11

Reset blocks 12-15

Reset blocks 00-15

Float blocks 00-15

Block Clear Request⁽¹⁾⁽²⁾

Single Block Reset Request

Dual Block Reset Request

Quad Block Reset Request

Global Reset Request

DMD Park Request

(1) Each Block Clear operation for DLP650LNIR and DLP7000(UV) DMDs will clear all SRAM cells of one DMD block (reset to '0') within

one row cycle duration.

(2) Each Block Clear operation for DLP9500(UV) DMDs must be followed by two No-Op row cycles. To clear one DMD Block, one Block

Clear Request row cycle followed by two consecutive No Op row cycles are required. In total, 15 Block Clear Request row cycles and 30

No-Ops are required to clear the entire 15 block DMD array.

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Block operations cause the DMD micromirrors to transition to their next state. Some notes and restrictions

regarding block operations are:

•

A Block No-Op row cycle causes no new block operations to occur. Block No-Op row cycles can be used to

provide extended time for a previous operation.

•

The Block Clear operation resets all SRAM pixels in the designated block to logic zero during the current row

cycle.

•

It is not necessary to Clear a block if it will be reloaded with new data (just like a normal memory cell).

It is not possible to Clear a block while writing to a different block.

It is possible to issue a Mirror Clocking Pulse to a block while data loading a different block.

The DLP9500 and DLP9500UV DMDs have 15 blocks (block 0 – block 14). Block operations on block 15

have no function for this DMD.

•

RST2BLK should be set to one value and not adjusted during normal system operation. A change in

RST2BLK is not immediately effective and will require more than one row load cycle to complete.

8.3.3.4.1 Global Reset (MCP) Consideration

A Global Reset (BLK_MD = 11 and BLK_AD = 10XX) is an operation which Resets (MCP) all DMD blocks at the

same time. The Global Reset duration is the same as the Single, Dual, and Quad Block Reset (MCP). In addition

to requiring a No-Op row cycle to initiate the Global Reset, row cycles (either No-Op row cycles or data loading

row cycles) are required to continually be provided to complete the Global Reset operation. If continual provision

of row cycles is not provided, the customer interface monitoring RST_ACTIVE may never see RST_ACTIVE

transition back low to indicate the Reset is complete. Customers should always provide valid row cycles, either

No-Ops or data loading row cycles. To know when the reset operation is complete, customers can either monitor

RST_ACTIVE high-to-low transition, or use a counter to know when at least a 4.5 µs period has expired from the

start of the Global Reset. From that point on, the customer also needs to count the mirror settling time of the

DMD to expire prior to loading the next data into the DMD.

注

Reset (MCP) operations to a specific block or consecutive blocks of the DMD are also

referred to "Block Resets" or just "Reset" operations. This is because they are physically

"resetting" the micromirrors of the block to their next physical positions based on the

underlying data.

注

(DLP9500 and DLP9500UV DMDs Only) To clear one Mirror Clocking Pulse (Reset)

Group in the DMD Block, one Clear command followed by two consecutive No Operation

commands (No-Ops) are required. Therefore, 15 total Block Clear commands and 30 total

No-Ops commands are required to clear the entire DMD array.

8.3.4 Other Data Control Inputs

It is recommended that the Complement and Flip flags be set to one value and not adjusted during normal

system operation. These controls are asserted through a different mechanism than the input data bus and row

controls, hence their effect is asynchronous and cannot be expected to take effect immediately upon assertion.

8.3.4.1 Complement Data

By setting the COMP_DATA flag high, the user is able to command the DMD to internally complement its data

inputs prior to loading the data into the mirror array. At least 0.6 ms is needed for the signal to be loaded. This

signal should not be used to invert data on a row basis. When used with the “Clear” command, the mirrors are

still set to zero regardless of the COMP_DATA bit. The COMP_DATA signal should be kept low during

initialization to ensure proper setup of the system.

8.3.4.2 North/South Flip

NS_FLIP allows the user to specify the loading direction of rows in the DMD when used with ROWMD = “01”.

This control has no effect if ROWMD = “10”.

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Row Addressing and 表 12 describe the effect of N/S flip. If NS_FLIP is set, this does not reverse the direction of

Mirror Clocking Pulse groups (blocks). For example, the normal case is to Mirror Clocking Pulse blocks 0 – 15 in

order. When NS_FLIP is set, the order of block Mirror Clocking Pulses must be reversed to 15 – 0.

The NS_FLIP signal should be kept low during initialization to ensure proper setup of the system.

8.3.5 Miscellaneous Control Inputs

8.3.5.1 ARST

ARST is an active low, asynchronous reset. This reset can be sourced from a voltage supervisor or from the

customer interface. Be aware that the chipset will not operate correctly if all DLPC410 power supplies are not in

range at the time this reset is released.

8.3.5.2 CLKIN_R

The reference clock, CLKIN_R, supplied from an oscillator must be 50 MHz. This is required for precise timing

used to perform the DMD Mirror Clocking Pulse (Reset). This clock should be valid prior to releasing ARST.

8.3.5.3 DMD_A_RESET

DMD_A_RESET is an active low reset to the DMD. This signal is deasserted as appropriate at the end of system

initialization.

8.3.5.4 Watchdog Timer Enable (WDT_ENABLE)

The DLPC410 contains a watchdog timer that initiates a global DMD Mirror Clocking Pulse in the event that the

DMD has not received any Mirror Clocking Pulse by the user within the last 10 seconds. This auto-generated

Mirror Clocking Pulse function is to provide Mirror Clockling Pulses to the DMD mirrors to prevent long term

landed mirrors in the event the input data and source control has been inadvertently disrupted. This capability

can be user disabled by setting WDT_ENABLE to logic '1'. Note that the global DMD Mirror Clocking Pulse

generated by the watch dog timer is asynchronous to any/all activity on the DMD input data bus - therefore there

is no guarantee as to the validity of the data displayed on the DMD once this pulse occurs, at least until new data

is subsequently loaded and displayed.

8.3.6 Miscellaneous Status Outputs

8.3.6.1 INIT_ACTIVE

The INIT_ACTIVE signal ins an output which indicates that the DMD, Digital Micromirror Driver, and the Digital

Controller are in an initialization state after power is applied. During this initialization period, the DLPC410 is

calibrating the data interface, initializing the DMD, and DLPA200(s). When this signal goes low, the system has

completed initialization. See the section on System initialization

8.3.6.2 DMD_Type(3:0)

The DLPC410 only supports the DMDs indicated in 表 15.At power-up, the DLPC410 checks the DMD signature.

If the DLPC410 finds the DMD is not supported, it will not allow the user to display data on the DMD and

indicated that the DMD is unsupported.

DMD_TYPE(3:0) is an output from the DLPC410 to the user FPGA which will indicate to the user which DMD is

connected to the DLPC410, or in another case, the DMD is not supported or a DMD is not properly connected.

表 15. DMD Characteristics

DMD_TYPE(3:0)

0000

DMD Reported

DLP9500 and DLP9500UV DMDs

DLP7000 and DLP7000UV DMDs

DLP650LNIR DMD

0001

0111

1111

Unsupported DMD / No DMD

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8.3.6.3 DDC_VERSION(3:0)

These four pins identify the version of the DLPC410 determined by the contents of DLPR410. If a problem is

encountered which encourages you to contact a Texas Instruments representative, please provide the version

number along with the detailed information of the problem. See the DLPR410 datasheet (DLPS027) for the

version number reported on these pins.

8.3.6.4 LED0

The LED0 signal is typically connected to an LED to show that the DLPC410 is operating normally. The signal is

1 Hz with 50% duty cycle, otherwise known as the heartbeat.

8.3.6.5 LED1

The LED1 signal is typically connected to an LED indicator to show the status of system initialization and the

status of the clock circuits. The LED1 signal is asserted only when system initialization is complete and clock

circuits are initialized. Logically, these signals are ANDed together to show an indication of the health of the

system. If the Phase Locked Loop (PLL) connected to the data clock and the DMD clock are functioning correctly

after system initialization, the LED will be illuminated.

8.3.6.6 DLPA200 Control Signals

Coordinating the operation of the DLPA200 with the DMD is one of the primary functions of the DLPC410. During

system initialization, the DLPC410 releases the reset pin (DAD_INIT) and communicates with the DLPA200 via a

serial bus to configure the device. Once this is complete, the high voltage output pins are enabled to prepare for

command execution. As the DLPC410 is commanded to load data and perform Mirror Clocking Pulses, the

DAD_ADDR address, DAD_MODE mode, DAD_SEL select and DAD_STROBE strobe signals are asserted as

appropriate to cause the Mirror Clocking Pulses. The operation of these signals are managed by the DLPC410

and, besides board layout and good design practices, should be of little concern to the end user.

8.3.6.7 ECM2M_TP_ (31:0)

These are reserved signals for test signal output. Do not drive these signals.

8.4 Device Functional Modes

The DLPC410 has one basic function which is to receive customer data at the inputs of the DLPC410 and deliver

that data and any appropriate DMD control information to the DMD for displaying of binary patterns at very high

speeds. The Feature Description section describes how binary pattern data is loaded into the DMD and

ultimately where that data is displayed on the DMD. The following subsections describe the different display

modes of operation of the DMD as enabled by the DLPC410.

8.4.1 DLPC410 Initialization and Training

8.4.1.1 Initialization

The INIT_ACTIVE signal indicates that the DMD, Digital Micromirror Driver, and the Digital Controller are in an

initialization state after power is applied. During this initialization period, the DLPC410 is calibrating the data

interface, initializing the DMD, and DLPA200(s). When this signal goes low, the system has completed

initialization. System initialization takes approximately 220 ms to complete. Data and command row cycles must

not be presented to the DLPC410 during the initialization. INIT_ACTIVE should be considered an asynchronous

feedback signal to the user. Standard synchronization techniques should be applied. After initialization is

complete, a delay of at least 64 DCLKIN clocks (on all input data buses being used) should be observed before

the first DVALID is asserted on those data buses to ensure a clean start up process.

注

Note: NS_FLIP, COMP_DATA, and RST2BLK signals should be kept low ('0') during

initialization to ensure proper system setup.

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8.4.1.2 input Data Interface (DIN) Training Pattern

The DLPC410 detects the phase differences between the ½ speed clock (used in the customer device driving the

LVDS data) and the internally generated ½ speed data clocks and automatically corrects their alignment. This is

done by the customer FPGA supplying a simple repeating pattern on all of the data inputs while the

INIT_ACTIVE output of the DLPC410 is high/active. The details of the training pattern are described below.

This is a simple block diagram of the training pattern insertion logic.

Sys Clk

IO Clk

System Data

0

4:1 Serdes

Dout

Training Data

(0100)

Din 3:0

1

Init_active

图 12. Block Diagram of Training Pattern Logic

The expected training pattern is 0100. In 图 13 the data input to the 4:1 SERDES cells is captured on the rising

edge of the ½ speed system clock. The output latency shown is based on the documentation for the Xilinx

SERDES cells. Individual implementation may vary depending on the type of cells, technology, and design

technique used.

½ Speed

System Clk

Full Speed

IO Clk

4:1

SERDES

Data (at the

interface)

0100

Output Data

图 13. Training Pattern Alignment

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注

In Xilinx FPGAs (due to the construction of the ISERDES and OSERDES cells) a pattern

of 0010 needs to be applied to the output/transmitting SERDES cells data pins (D1 = 0,

D2 = 0, D3 = 1, D4 = 0) in order to receive a result of 0100 (Q1 = 0, Q2 = 1, Q3 = 0, Q4 =

0) at the input/receiving SERDES cell.

The patterns should be applied on all of the input data and DVALID pins. In this respect,

the interface is treated as a 17 bit interface with DVALID being the 17^thdata bit. The

receiving logic in the DLPC410 will shift the data until the correct pattern is seen at the

inputs. The SERDES cells align the incoming data with the ½ speed system clock (derived

from the full speed data clock). This allows DLPC410 to correctly align the DVALID signal

and the incoming data and will contribute to a more robust interface. It is important that the

training pattern is applied to the DVALID and data inputs of the DLPC410 before reset to

the device is deasserted, as training commences immediately on the deassertion of reset.

The INIT_ACTIVE signal is asserted while the device is held in reset in order to help

facilitate this behavior.

8.4.2 DLPC410 Operational Modes

The following modes of operation are frequently used operational modes enabling customers to update DMD

data and to control how, where, and how long their binary patterns are displayed on the DMD. Customers

frequently pick the mode which provides the best performance and simplicity for their specific system.

Combinations of these modes can also be used.

8.4.2.1 Single Block Mode

A single block of DMD memory cells can be updated by providing successive row cycles with valid data

(DVALID) to the DLPC410 until the desired amount of data is presented. Since different DMDs have different row

and block sizes (and therefore different number of clocks per row or per block), the amount of time it takes to

load a block of DMD data will be different for each DMD. Leveraging 表 11 and 表 13, we can calculate the single

block load time for each DMD by the following equation: Block Load Time = Clock Period × number CLKS per

ROW × number ROWS per BLK. The results are shown in 表 16 for DLPC410 supported DMDs.

表 16. DMD Block Load Time (400 MHz DMD Clock)

DMD

DMD BLOCK LOAD TIME

5.00 µsec

DLP650LNIR

DLP7000 / DLP7000UV

DLP9500 / DLP9500UV

1.92 µsec

2.88 µsec

Once the block is loaded with data, a Block Reset (MCP) for that block must be initiated. This can be performed

by providing a row cycle with BLKMD = "10" and with BLK_AD(3:0) equal to the block just loaded. Upon initiation

of the Block Reset, RST_ACTIVE will transition high for approximately 4.5 μs indicating a Reset operation is

taking place and that no additional Reset Requests will be accepted during that time. In the case of wanting to

reload the same block with new data, one must wait for the 12.5 μs (RST_ACTIVE (4.5 μs) + the micromirror

settling time (8 μs)) before the reload of the same block can start. Waiting this time allows for the DMD

micromirrors in that block to settle to a stable state prior to reloading the memory cells underneath with new data.

图 14 shows a single block load, Mirror Clocking Pulse and reload sequence with the 8 μs periods indicating

micromirror settling times.

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Load Block 8

No-Op

Row No-Op

Load Block 8

Row No-Op

Load Block 8

DIN_A/B

BLKMD/BLK_AD

Block Rst 8

Block No-op

Block Rst 8

Block No-Op

RST_ACTIVE

4.5 us

8 us

4.5 us

8 us

图 14. Block Load, Reset, and Same Block Reload

Although 图 14shows that one must wait for the mirror settling time of the current block (Block=8 in this case) to

complete before reloading data into the same block (8), it is possible to load data to a different block while

waiting for Block 8 to settle. However, it must be a block which is not currently being Reset nor which has

micromirrors which are still settling. This method is used in the Phased Mode of operation described in Single

Block Phased Mode .

注

The RST_ACTIVE and micromirror settling times indicated in this example are typical for

many DMDs. See each individual DMD data sheet for more information on the micromirror

switching and settling times.

注

Customers do not have to load the entire block at one time unless specifically directed.

The DLPC410 supports individual row loads and partial block loads. Customers can use

ROW_AD(10:0) to load one (or more) specific Row Addresses within any block. These

loading modes are defined in 表 12. Care must be taken to ensure all RST_ACTIVE time

plus DMD mirror settling times are taken into account prior to re-loading any rows in the

same block once a Reset has been requested.

8.4.2.2 Single Block Phased Mode

Single Block Phased Mode is best described as "phasing" the data load operation with the Block Reset

operation. The major advantages of Phased Modes (Single, Dual, and Quad) in general are the idea of not

having to wait for the micromirror settling time duration to complete prior to the next block reset, and for not

having to wait for the Reset Request to complete prior to loading more data. In the example of 图 15, Block 15 is

loaded with data while the Reset operation is taking place for Block 14 (Rst 14). The Reset Request (BLKMD

and BLK_AD) for Block 14 needs to be one row cycle in duration minimum but can be extended to additional row

cycles. Subsequent row cycles containing a valid Reset Request will be ignored until RST_ACTIVE goes low.

Therefore, BLKMD and BLK_AD should transition from a Reset Request to a Block No-Op while RST_ACTIVE is

still asserted as once RST_ACTIVE de-asserts there is the likelihood of an undesired Reset Request to be

generated on the same block.

In 图 15, Block 0 is issued a Block Reset concurrently with data being loaded into the next block (1). The Row

Cycles of the Block 1 data loading capture the Reset Request for Block 0, and provide continued Row Cycles for

the duration of both the Block Load and the Block Reset. Note that the loading of block 1 does not need to wait

for the mirror settling time of Block 0. This is repeated until the last block is Reset (which might also contain

loading the next Block 0 data). Since the DLP650LNIR block load time is already longer than the RST_ACTIVE

time, full utilization of its bandwidth is readily achieved in a single block phased mode.

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. . . . . . .

Load Block 15 Load Block 0 Load Block 1 Load Block 2

DIN_A/B

. . . . . . .

BLKMD/BLK_AD

Rst 14 No-Op Rst 15 No-Op Rst 0 No-Op Rst 1 No-Op

RST_ACTIVE

R_A 14

R_A 15

R_A 0

R_A 1

图 15. Single Block Phased Mode with Longer Block Load Times

Depending on the DMD type, the RST_ACTIVE duration of 4.5us may be longer than a single block load time.

For example, the sequence shown in图 16 shows that when the Block Load time is shorter than RST_ACTIVE,

one should include Row No-Ops to create a delay until the current RST_ACTIVE transitions low. Once

RST_ACTIVE transitions low, the first row cycle of the next block data load can occur while also providing the

Reset Request for the previously loaded block. At least one row cycle minimum must be completed to initiate the

Reset Request and the next Reset Request must wait until the data is loaded and RST_ACTIVE transitions low.

. . . . . . .

DIN_A/B

Ld 15 No-Op Ld 0 No-Op Ld 1 No-Op Ld 2 No-Op

. . . . . . .

Rst 14 No-Op Rst 15 No-Op Rst 0 No-Op Rst 1 No-Op

BLKMD/BLK_AD

RST_ACT 14 RST_ACT 15

RST_ACTIVE

RST_ACT 0

RST_ACT 1

图 16. Single Block Phased Mode with Short Block Load TImes

图 17 is nearly the same as Figure 16 except that the data loading of each block is timed such that it completes

loading the block just about the same time the RST_ACTIVE signal goes low. Row No-Op cycles are used to

provide the Reset Requests instead of data load row cycles. The benefit of this would be the delayed loading of

data could provide more time for the customer application data processing upstream. In both cases, the next

block Reset Request cannot be initiated until the previous Reset Request has completed.

. . . . . . .

DIN_A/B

No-Op Ld 15 No-Op Ld 0 No-Op Ld 1 No-Op Ld 2

. . . . . . .

Rst 14 No-Op Rst 15 No-Op Rst 0 No-Op Rst 1 No-Op

BLKMD/BLK_AD

RST_ACT 14 RST_ACT 15

RST_ACTIVE

RST_ACT 0

RST_ACT 1

图 17. 2nd Single Block Phased Mode with Short Block Load TImes

8.4.2.3 Dual Block Mode

Dual Block Mode can help to avoid the required delays (via No-Ops) encountered in a Single Phased Mode

where the load time is less than the Reset duration. In the case of the DLP9500 DMD with a block load time of

2.88 μs, loading two blocks ( 2 × 2.88 = 5.76 μs) takes more time than the Reset duration (4.5 μs) so once the

data is loaded, a Dual Block Reset Request can be issued immediately (instead of waiting for RST_ACTIVE) to

the two blocks by setting RST2BLK to “0” and BLK_MD to “11” and the appropriate address in BLK_AD. This

method is indicated in 图 18.

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Load Block 15

No-Op

Load Block 0

Load Block 1

Load Block 2

Load Block 3

Load Block 4

Load Block 5

Load Block 6

Load Block 7

DIN_A/B

Dual Blk Reset 12-15

RST_ACTIVE 14-15

No-Op

Dual Blk Reset 0-1

RST_ACTIVE 0-1

No-Op

Dual Blk Reset 2-3

RST_ACTIVE 2-3

No-Op

Dual Blk Reset 2-3

No-Op

BLKMD/BLK_AD

RST_ACTIVE

RST_ACTIVE 4-5

图 18. Dual Block Mode

8.4.2.4 Quad Block Mode

Quad Block mode is very similar to Dual Block mode but in Quad Block Mode, 4 Blocks are loaded with data and

then Reset. In the case of the DLP7000 DMD with a block load time of 1.92 μs, the loading of two blocks would

still be less than the 4.5 μs required for the Reset to complete so No-Ops would be required. To avoid inserting

No-Ops is this case, loading four blocks (4 × 1.92 = 7.68 μs) is longer than the RST_ACTIVE duration (4.5 μs) so

once loaded, the 4 blocks can immediately be issued a Reset Request by settingRST2BLK to “1”, BLK_MD to

“11”, and setting the appropriate BLK_AD address in the first row cycle of the next data block load.

Load Block 15 Load Block 0 Load Block 1 Load Block 2 Load Block 3 Load Block 4 Load Block 5 Load Block 6 Load Block 7

DIN_A/B

Quad Blk Reset 12-15

RST_ACTIVE 12-15

Block No-Op

Quad Blk Reset 0-3

RST_ACTIVE 0-3

BLKMD/BLK_AD

RST_ACTIVE

图 19. Quad Block Mode

Quad Block mode tends to offer customers the fastest full-DMD pattern rates combined with the largest solid

state illuminations windows. Pattern rates for Single Block Phased and Dual Block Phased modes can

sometimes be as fast as Quad Block rates, but the illumination windows can be smaller or even negative,

thereby requiring delays between patterns to widen the illumination windows for solid state illuminators. These

added delays will decrease the resulting pattern rates.

8.4.2.5 Global Mode

One of the simplest and most frequently utilized modes, the Global Mode involves loading the entire DMD with

new pattern data and then issuing a Global Reset to update all DMD mirrors at the same time. Loading the entire

DMD with data involves loading every row of every block. The time it takes to load the DMD is the block load

time × the number of blocks for that specific DMD. 表 17 shows the fastest DMD load times for DLPC410

supported DMDs.

表 17. DMD Load Times (Entire DMD)

DMD

DMD LOAD TIME (400 MHz Clock)

DLP650LNIR

80.0 µsec

30.7 µsec

43.2 µsec

DLP7000 / DLP7000UV

DLP9500 / DLP9500UV

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The Global Mode case is shown in 图 20. Following the loading of all rows in the device, a Row No-Op row cycle

with a Global Reset Request must be issued to initiate the Reset Pulse and No-Ops should continue until ready

to load the DMD again. If the global Reset Pulse is asserted prior to loading all rows of the device, rows which

were not updated will show old data. Global mode is similar to Single Block Mode in that the mirror settling time

must be taken into account prior to reloading the DMD data after a Reset Request is provided. This additional

delay makes the Global Mode of operation inherently slower. However, if speed is not as important in a customer

application, Global mode is great for its simplicity of DMD loading and Resetting.

8 us

.. ..

Load Block 0 Load Block 1

Load Block 14 Load Block 15

Row No-Op

Load Block 0

DIN_A/B

Global Rst

Block No-Op

BLKMD/BLK_AD

RST_ACTIVE

4.5 us

图 20. Full Device Load with Global Reset

8.4.2.6 DMD Park Mode

Park Mode places the DMD in a state where the micromirrors are not biased to either the plus or the minus side,

but are instead floating in an unbiased and uncontrolled state. Hence, this is also referred to as Mirror Float

mode. Parking (floating) the DMD mirrors should be performed when powering down the DMD to avoid leaving a

static image on the DMD during down time or storage. The mirror can be Parked in one of two ways:

1. PWR_FLOAT input pin (recommended method) : asserting this input to the DLPC410 will cause the

DLPC410 to automatically Park the mirrors in preparation for power removal. This operation is independent

of any activity on the input data bus or Block operations. It is often best to drive this pin from both a power

supervisor circuit which provides immediate DMD parking upon detecting input power removal, and from a

programmable/controllable output from the customer application FPGA or processor.

2. DMD Park (Float Blocks 0-15) operation per 表 14: A mirror float sequence begins with a row cycle with

assertion of the proper BLK_MD and BLK_AD as described in 表 14. Following the row cycle, the DMD

releases the tension under each mirror so that all mirrors relax to a relatively flat position. The float operation

takes approximately 3 µs to complete, during which time RST_ACTIVE is asserted.

注

Park the DMD only when DC power is going to be removed from the DMD. Recovery from

a PWR_FLOAT input pin assertion requires either a DLPC410 logic reset or a complete

power cycle.

8.4.2.7 DMD Idle Mode

When not powering down the DMD yet it is desired to place the system in an idle (non-functioning) state,

regardless of end application, all DMDs benefit from continuously operating the DMD near 50% landed on/off

duty cycle. This requires customers to understand how they can provide the DMD a sequence of patterns which

approximate a 50/50 duty cycle without interfering with normal operation of their system. See section 3 (Duty

Cycle Considerations) in application note DLPA052 - System Design Considerations Using TI DLP® Technology

down to 400 nm. Also see

•

DLPA060 - System Design Considerations Using TI DLP® Technology in UVA, and

DLPA104 - DLP® High-Power NIR Thermal Design Guide

for additional information.

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8.4.3 LOAD4 Functionality (enabled with DLPR410A)

The DLPR410A PROM enables a new LOAD4 feature for the DLPC410 and attached DMD. The LOAD4

capability enables the DMD to load 4 rows for every row of data provided by the DLPC410, thereby reducing the

number of rows to be transferred to 1/4 of the total of DMD rows, and the pattern load time to ¼ the total of row

cycles, all at the expense of vertical resolution (1/4). Faster global binary pattern rates at the expense of vertical

addressable resolution may make sense for certain applications like shutter/chopper solutions and vertical

structured light patterns. LOAD4 reduces data load time only and does not reduce the “Mirror Clocking Pulse”

and “Settling Time” durations.

8.4.3.1 Enabling LOAD4

LOAD4 is enabled by setting the DLPC410 input signal "LOAD4" to a logic '0'. When not using LOAD4, this input

should driven or pulled up to logic '1'.

注

The LOAD4 pin on the DLPC410 was previously defined as "DDC_SPARE_0" pin.

DLPC410 referenceschematics may still show this signal as DDC_SPARE_0 even though

the DLPR410A enables the LOAD4 capability using this pin. LOAD4 capability is available

starting with the DLPR410A and is not available with the DLPR410.

8.4.3.2 Loading Data with LOAD4

LOAD4 enables the attached DMD to load four rows of the same data for every one row of provided pattern data.

“Automatic Increment” mode and “Row Address” mode can be used as before, however the largest addressable

row will be the Vertical Resolution (VRes) of the attached DMD divided by four. For example, using LOAD4 the

XGA DMD will have 1024/4 = 256 addressable rows (0 . . . 255). The addressable vertical resolution is reduced

by four, although the physical mirror resolution remains unchanged.

“Automatic Increment” address mode will automatically increment the Row Address input by one (or decrement

by one for N/S flip). The Row Address input will be re-mapped as shown in the next section.

8.4.3.3 Row Mapping with LOAD4

The DMD row addresses are re-mapped per 表 18.

表 18. LOAD4 Row Address Mapping

Row Address Input

Physical Rows loaded on DMD

0

0, 1, 2, 3

1

4, 5, 6, 7

2

8, 9, 10, 11

3

12, 13, 14, 15

. . .

N

. . .

4N, 4N+1, 4N+2, 4N+3

. . .

(VRes/4) -1

VRes-4, VRes-3, VRes-2, VRes-1

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图 21. LOAD4 Row Address Mapping

8.4.3.4 Using Block Clear with LOAD4

While LOAD4 is enabled, Block Clear operations will be ignored. To use LOAD4 followed by Block Clear

operations, simply de-assert LOAD4 at the beginning of the Reset request(s) preceding the Block Clear

request(s). Re-assert LOAD4 at the beginning of the Reset request(s) preceding the next desired LOAD4

operation. This will ensure that the DLPC410 Controller has sufficient time to disable or enable LOAD4 before

data is loaded or Block Clear(s) are requested.

8.4.3.5 Timing Requirements for LOAD4

LOAD4 functionality is primarily intended to be used with Global Resets. However, It is possible to use a subset

of the DMD array including Block Resets. The driving software/hardware MUST ensure that the average “Reset”

(MCP) rate does not exceed an average rate of 50,000 MCPs/sec as this is the specification limit of the

DLPA200 Micromirror Driver device (see . The driving software/hardware MUST also ensure that the “Mirror

Settling Time” is not violated for any Block.

Average rate means averaged over 2-3 Load/Clear cycles. For example if a pattern is loaded and displayed with

a Mirror Clocking Pulse followed by a Block Clear and a Mirror Clocking Pulse the “on” display time is very short.

However, If the next pattern is loaded and displayed immediately, the average MCP rate may be exceeded,

depending on the DMD and the number of Blocks in use. Therefore idle time must be added in the Load or Block

Clear cycle to ensure an average MCP rate of 50,000 MCPs/sec or lower. Typically the smallest pattern display

time is desired so that the time is added during the Load cycle rather than the Block Clear cycle so that the “off”

time is extended, not the pattern display time.

8.4.3.6 Global Binary Pattern Rate increases using LOAD4

表 19 shows the improvements in binary pattern rates for the DLPC410 supported DMDs when using LOAD4

enhanced functionality of the DLPR410A PROM. When using solid state illuminators (which can be switched on

and off quickly), the illumination window is the period of time between when a solid state illuminator can be

turned on after the micromirrors have settled to when the micromirrors start to transition to their next state (after

the load and a Reset). This illumination window is typically equal to the DMD load time. When the DMD load time

is long (without LOAD4) there is a longer allowed illumination window for the application. As one moves to using

LOAD4 but yet keeps the illumination window unchanged, the illumination window becomes a higher percentage

of pattern period, and more the limiter of the maximum binary pattern rate.

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表 19. DMD Block Load Time at 400MHz DMD Clock

DMD

Global Frame Rate

(without LOAD4)

Global Frame Rate (with

LOAD4 mode)

DLP650LNIR

DLP7000

11k binary patterns/sec

23k binary patterns/sec

18k binary patterns/sec

30k binary patterns/sec

48k binary patterns/sec

42k binary patterns/sec

DLP9500

8.4.3.7 Special LOAD4 considerations

Take precautions when using LOAD4 mode with the DLP650LNIR DMD, or similar DMDs where the number of

rows per reset block is not evenly divisible by 4. In the case of the DLP650LNIR, the number of rows per block

for this DMD is 50 rows which is not evenly divisible by 4. Therefore, loading the last two rows of an even

number block (n = 0,2,4,...14) concurrently loads the first two rows in the subsequent odd number block (n+1).

Conversely, to address and load an odd block using LOAD4, the last two rows of the preceding even number

block will be loaded first, else the first two rows of the odd block will not be loaded with new data.

8.5 Programming

The DLPC410 has no software interfaces and is therefore not programmable from a software perspective. All

operational modes involve externally applied hardware signals.

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9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The DLP650LNIR, DLP7000, DLP7000UV, DLP9500, and DLP9500UV devices require they be coupled with the

DLPC410 controller to provide a reliable solution for many different applications. The DMDs are spatial light

modulators which reflect incoming light from an illumination source to one of two directions, with the primary

direction being into a projection collection optic. Each application is derived primarily from the optical architecture

of the system and the format of the data coming into the DLPC410. Applications of interest include industrial,

medical, and intelligent display.

9.1.1 Device Description

The DLPC410 Controller based chipsets offer developers a convenient way to design a wide variety of industrial,

medical, and advanced display applications by delivering maximum flexibility in formatting and sequencing

customer binary pattern data for display as projected light patterns from DMDs of varying resolutions.

These chipsets include the following components:

DLPC410 DMD Digital Controller

•

Captures 2xLVDS input pattern data plus control from the user.

Provides data and additional control to the DMD for high speed binary pattern display.

Commands the DLPA200 to generate Resets Pulses (MCP) with highly specific timing.

Supports random DMD row addressing, clear operations, and LOAD4 capability.

DLPR410 Configuration PROM

Contains DLPC410 Controller power up configuration information.

DLPA200 DMD Micromirror Driver

Creates Reset Pulses (MCP) to the DMD to initiate mirror transitions to the next state.

DMD: Digital Micromirror Device, a 2-dimensional array of aluminum micromirrors

•

DMD micromirrors tilt +12 degrees and -12 degrees to steer light in one of two directions.

DLP650LNIR DMD: 0.65-inch array diagonal, 1280 x 800 micromirror array, WXGA resolution.

DLP7000(UV) DMDs: 0.7-inch array diagonal, 1024 x 768 micromirror array, XGA resolution.

DLP9500(UV) DMDs: 0.95-inch array diagonal, 1920 x 1080 micromirror array, 1080p resolution.

Reliable function and operation of the DLP650LNIR, DLP7000, DLP7000UV, DLP9500, and DLP9500UV DMDs

require the DMDs to be used in conjunction with the components listed in 表 1. This document describes the

proper integration and use of the chipset components.

The DLPC410 chipset can be combined with a user programmable Application FPGA (not included) to create

high performance systems.

9.2 Typical Application

A typical embedded system application using the DLPC410 controller is shown in 图 22. The DLPC410, the

DMD, and their associated DLP components do not specifically determine the application in which the

components are used - customer applications and use cases may vary widely, from Digital Image Lithography to

3D Printing to 3D Scanners using Structured Light. The DMD is capable of being used with multiple illumination

source types, from Lasers and LEDs to wide band wavelength mercury halide lamps. The DLPC410 supported

DMDs cover applications utilizing ultraviolet (UV), visible, and/or near-infrared (NIR) wavelengths. The duration of

each binary pattern displayed on the DMD is totally under control of the Applications Processor. The displayed

patterns could be strictly binary patterns or could be bit weight exposures of varying durations representing

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Typical Application (接下页)

encoded PWM-based gray scales. The timing of the micromirrors and the illumination sources are controlled at

the discretion of a Customer Applications Processor and in many solid state cases, provide best performance

when source illuminators are synchronous to the commanded DMD micromirror transitions. The speed, diversity,

programmability, and flexibility of the DLPC410 building blocks provide an electro-optical cornerstone for

customers to build upon to create applications limited only by customer ingenuity.

In 图 22, the MBRST 2 signals and the C, D LVDS Data buses are shown with dashed lines to indicate that some

DMDs do not require these signals to be used. TI's Reference Design and Evaluation Modules leverage a

DLPC410 Controller Board which supports all 5 of the DLPC410 supported DMDs. The performance differences

for each application are determined by which DMD Board is plugged into the Controller Board. This provides a

single DLPC410 design platform which can then be used for multiple customer SKUs within an application

platform for product segmentation purposes.

NIR

PWMs/Triggers

LED/Laser/Lamp Driver

Laser Sensor

Cameras

LEDs/Laser/Lamp

Optical Power Sense

LVDS Data Bus(A,B)

LVDS Data Bus(C, D)

LVDS Data Bus

Row, Block Signals

Control Signals

User Interface

Connectivity

(USB, E-Net,etc.)

DLPC410 Info Signals

JTAG

User

Main Processor

FPGA

DLPC410

MBRST 2

DLPA200 Control

DLPA200

DLPR410

DLPA200 Control

SCP Bus

MBRST 1

Volatile and non-

Volatile Storage

DLP650LNIR

DLP7000

DLP7000UV

DLP9500

OSC

DLP9500UV

Power Management

AC Power

DLP Components

GND

图 22. DLPC410 Application Example Block Diagram

9.2.1 Design Requirements

All applications using the DLP650LNIR, DLP7000(UV) or DLP9500(UV) DMDs require the DLPC410

Controller, DLPR410 PROM, and one or two DLPA200 Micromirror Drivers for proper operation. The chipset

has several system interfaces and requires some support circuitry. The following interfaces and support

circuitry for the DLPC410 are required:

•

DLPC410 Application System Interfaces to the customer electronics and software:

–

Input LVDS Data Buses A, B, C, D

Row Address to specify DMD row to load

Block address and Block Mode to specify which DMD block(s) to "Reset" (MCP)

RST_ACTIVE feedback to indicated a "Reset" is in progress

Miscellaneous control inputs

Miscellaneous feedback signals

Power Supply inputs

•

DLPC410 to other DLP Component Interfaces

–

Output LVDS Data Buses A, B, C, D to DMD

Output control signals (SCP bus) to DMD

Output commands to DLPA200 for MCP generation

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Typical Application (接下页)

9.2.2 Detailed Design Procedure

The DLP7000 and DLP9500 DMD are designed to be operated by the DLPC410 controller and are well suited for

visible light applications requiring fast, spatially programmable light patterns using the micromirror array. In

addition the DLP7000UV and DLP9500UV are well suited for direct imaging lithography, 3D printing applications,

and other applications requiring ultraviolet light (UVA). The DLP650LNIR DMD is optimal for high power Near-

Infrared light (NIR) applications like 3D additive manufacturing (SLS), marking and coding, and FPD repair and

ablation. See the block diagrams in Functional Block Diagrams to see the connections between the

DLP650LNIR, DLP7000 / DLP7000UV or DLP9500 / DLP9500UV DMD, the DLPC410 digital controller, the

DLPR410 Configuration PROM, and the DLPA200 DMD micromirror drivers. Layout guidelines should be

followed for reliability.

9.2.3 Application Curves

图 24. DLP7000UV and DLP9500UV Transmittance (UV

图 23. DLP7000 and DLP9500 Transmittance (Visible

Window)

图 25. DLP650LNIR Transmittance (NIR2 Window)

9.3 Initialization Setup

9.3.1 Debugging Guidelines

Prior to checking the DLPC410 signals, make sure the reference clock to the DLPC410 is running at 50 MHz.

Check that DONE_DDC (pin K10) signal is asserted indicating the DLPR410 PROM has correctly programmed

the DLPC410 FPGA.

9.3.2 Initialization

Initialization will automatically start after ARST (pin AC13) is deasserted. The initialization process includes the

following components in the order presented here:

1. Calibration

2. DLPA200 number 1 Initialization (all DMDs)

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Initialization Setup (接下页)

3. DMD Initialization

4. DLPA200 number 2 Initialization (DLP9500 & DLP9500UV only)

5. Command Sequence

9.3.2.1 Calibration

Calibration is done on each of the data (DDC_DIN) and DVALID signal pairs using the training pattern as

specified in input Data Interface (DIN) Training Pattern. When calibration is successful, the Initialization will move

on to initializing the first DLPA200.

注

The training pattern going into the SERDES on the transmit side is different than the

pattern on the receive SERDES. On the receive side the value should be “0100”.

However, this could translate to “0010” on the transmit side. Please see input Data

Interface (DIN) Training Pattern for more information. An improper training pattern could

cause the part to not perform the commands correctly.

9.3.2.2 DLPA200 Number 1 Initialization

The DLPC410 will initialize the first DLPA200 (number 1) regardless of connected DMD type. The DLPC410

output DAD_A_SCPEN (pin AE3) signal will assert indicating that the DLPC410 is ready to communicate with

DLPA200 number 1. Signaling should be seen on SCPCLK (pin AB15), SCPDO (pin AA15 - SCP output from the

DLPC410) and SCPDI (pin AA15 - SCP input to the DLPC410) traces. Be sure that the direction of the SCP

input and output signals are connected correctly.

When DLPA200 Number 1 initialization is complete, check V_BIAS, V_RESET, and V_OFFSETvoltage values on the

DLPA200 number 1 and compare against the DLPA200 data sheet specifications for the particular DMD being

used with the DLPC410.

9.3.2.3 DMD Initialization

During DMD initialization, the DLPC410 output DMD_A_SCPEN (pin AB14) signal will assert indicating that the

DLPC410 is ready to communicate to the DMD. Signaling can be seen on SCPCLK (pin AB15), SCPDO (pin

AA15 - SCP output from the DLPC410) and SCPDI (pin AA15 - SCP input to the DLPC410) lines. Be sure that

the direction of the SCP input and output signals are connected correctly.

9.3.2.3.1 DMD Device ID Check

If the DLPC410 has successfully initialized the DMD, the four DMD_TYPE(3:0) pins (AA17, AC16, AB17, and

AD15)) will provide the DMD type as identified by the DLPC410. The possible DMD_TYPE values are shown in

表

15. DMD_TYPE(3:0) will return "1111" if the DMD is not attached or not recognized.

注

Only the DMDs listed in 表 1 are supported by the DLPC410. The DLPC410 will not

function for unsupported DMDs or when a DMD is not installed.

9.3.2.3.2 DMD Device OK

The signals ECP2_M_TP11 (pin AA10) and ECP2_M_TP12 (pin Y10) indicate the status of the DMD buses:

表 20. DMD Device OK Status

ECP2_M_TP12 (PIN

Y10 - A/B SIDE)

ECP2_M_TP13 (PIN

AC11 - C/D SIDE)

NOTE

0

DMD not supported or not initialized

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表 20. DMD Device OK Status (接下页)

ECP2_M_TP12 (PIN

Y10 - A/B SIDE)

ECP2_M_TP13 (PIN

AC11 - C/D SIDE)

NOTE

A/B side is attached and initialized.

(Expected for DLP650LNIR, DLP7000, DLP7000

UV DMDs but indicates a problem with C/D side

connection if DMD is DLP9500 or DLP9500UV )

1

0

1

Invalid output

All buses (A/B and C/D) are attached and initialized

(DLP9500, DLP9500UV only)

9.3.2.4 DLPA200 Number 2 Initialization

The DLPC410 will only initialize the second DLPA200 (number 2) when it detects a DLP9500 or DLP9500UV

DMD is connected. The DLPC410 output DAD_B_SCPEN (pin AB19) signal will assert indicating that the

DLPC410 is ready to communicate with DLPA200 number 2. Signaling should be seen on SCPCLK (pin AB15),

SCPDO (pin AA15 - SCP output from the DLPC410) and SCPDI (pin AA15 - SCP input to the DLPC410) traces.

Be sure that the direction of the SCP input and output signals are connected correctly.

When DLPA200 Number 2 initialization is complete, check V_BIAS, V_RESET, and V_OFFSETvoltage values on the

DLPA200 number 2 and compare against the DLPA200 data sheet specifications for the DLP9500 or

DLP9500UV DMD.

9.3.2.5 Command Sequence Initialization

The last portion of the initialization process involves a series of commands sent from the DLPC410 to the DMD.

During this step, check the output of the DLPA200(s). One should expect to see several Mirror Clocking Pulse

waveforms indicating the DLPA200(s) is (are) initialized correctly.

This will complete the initialization process. When the initialization process starts, the INIT_ACTIVE ouput signal

(pin AA18) will assert (go high) indicating that the initialization sequence is in process. At the end of the

initialization sequence, if the initialization is successful, the INIT_ACTIVE ouput signal (pin AA18) will deassert

(go low) indicating that the initialization process is complete.

注

Initialization complete indicates that the initialization sequence of the DLPC410 has

completed, but does not ensure that each step was completed correctly, only that it

finished. For example the initialization of a DLPA200 may complete, but if the voltages set

are incorrect further investigation is needed to uncover the reason.

9.3.3 Image Display Issues

There are three steps to displaying an image on the DMD, each of which can cause an image to fail to display

correctly or in some case not at all. These steps are:

1. Present Data to DLPC410 – Pattern data generated by the users device.

2. Load Data to the DMD – The DLPC410 loads data into the attached DMD CMOS memory array.

3. Issue Reset (MCP) – A Reset pulse (MCP) is issued to block(s) to change the state of the micromirrors

based on the data loaded in step two. See Mirror Clocking Pulse (MCP) .

9.3.3.1 Present Data to DLPC410

If there is a problem with the image displayed, one of the first places to check is the data being presented to the

DLPC410. This data is generated by customer application hardware/software and is then presented to the inputs

of the DLPC410. If the data is formatted incorrectly or the control information is incorrect, the DLPC410 may not

properly receive the data. Please see Row Addressing for a description of how to send data to the DLPC410.

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9.3.3.2 Load Data to DMD

After data and commands are sent to the DLPC410, the DLPC410 processes the information and passes it to the

DMD. If there is no image displayed, first check the data output and SCTRL lines of the DLPC410 to see if there

is data coming out. Data output (DDC_DOUT...) and DDC_SCTRL pins can be found in the Pin Configuration

and Functions.

PWR_FLOAT (pin AC17) will prevent the data from coming out of the DLPC410 if asserted. Check to make sure

that it is at logic level 0.

A Float blocks 00-15 command will also prevent data from the DLPC410. Please see the last entry of 表 14.

9.3.3.3 Mirror Clocking Pulse

For a new image to appear on the DMD, Mirror Clocking Pulses must be received for the DMD block or blocks

that have received new data. Check DAD_A_STROBE (pin AF3) and DAD_B_STROBE (pin AB20) [if applicable]

for pulses to verify that requests for mirror clocking pulses are being sent to the DLPA200(s). Also check the

DLPA200(s) output is enabled by checking that DAD_OE (pin AF5) is low.

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10 Power Supply Recommendations

10.1 Power Down Operation

For correct operation of the DMD, the following power down procedure must be executed. Prior to power

removal, assert PWR_FLOAT and allow approximately 300 µs for the procedure to complete. This procedure will

assure the mirrors are in a flat state, similar to the float operation. Following this procedure, the power can be

safely removed.

To restart after assertion of PWR_FLOAT the DLPC410 must be reset (ARST low then high) or power must be

cycled.

11 Layout

11.1 Layout Guidelines

The DLPC410 is part of a chipset that is controls a DLP650LNIR, DLP7000 / DLP7000UV or DLP9500 /

DLP9500UV DMD in conjunction with the DLPA200 driver(s). These guidelines are targeted at designing a PCB

board with these components.

11.1.1 Impedance Requirements

Signals should be routed to have a matched impedance of 50 Ω ±10% except for LVDS differential pairs

(DMD_DAT_Xnn, DMD_DCKL_Xn, and DMD_SCTRL_Xn), which should be matched to 100 Ω ±10% across

each pair.

11.1.2 PCB Signal Routing

When designing a PCB board for the DLP650LNIR, DLPC7000 / DLP7000UV or DLP9500 / DLP9500UV

controlled by the DLPC410 in conjunction with the DLPA200(s), the following are recommended:

Signal trace corners should be no sharper than 45°. Adjacent signal layers should have the predominate traces

routed orthogonal to each other. TI recommends that critical signals be hand routed in the following order: DDR2

Memory, DMD (LVDS signals), then DLPA200 signals.

TI does not recommend signal routing on power or ground planes.

TI does not recommend ground plane slots.

High speed signal traces should not cross over slots in adjacent power and/or ground planes.

表 21. Important Signal Trace Constraints

SIGNAL

CONSTRAINTS

P-to-N data, clock, and SCTRL: <10 mils (0.25 mm); Pair-to-pair <10 mils (0.25 mm); Bundle-to-bundle

<2000 mils (50 mm, for example DMD_DAT_Ann to DMD_DAT_Bnn)

Trace width: 4 mil (0.1 mm)

Trace spacing: In ball field – 4 mil (0.11 mm); PCB etch – 14 mil (0.36 mm)

Maximum recommended trace length <6 inches (150 mm)

LVDS (DMD_DAT_xnn,

DMD_DCKL_xn, and

DMD_SCTRL_xn)

表 22. Power Trace Widths and Spacing

MINIMUM TRACE

SPACING

SIGNAL NAME

GND

LAYOUT REQUIREMENTS

WIDTH

Maximize

5 mil (0.13 mm)

Maximize trace width to connecting pin as a minimum

Create mini planes and connect to devices as necessary with

multiple vias

P2P5V, P1P0V

50 mil (1.3 mm)

10 mil (0.25 mm)

30 mil (0.76 mm) -

stub width

P2P5V, P1P0V

10 mil (0.25 mm)

Stub width to connecting IC pins; maximize width when possible

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11.1.3 Fiducials

Fiducials for automatic component insertion should be 0.05-inch copper with a 0.1-inch cutout (antipad). Fiducials

for optical auto insertion are placed on three corners of both sides of the PCB.

11.1.4 PCB Layout Guidelines

A target impedance of 50 Ω for single ended signals and 100 Ω between LVDS signals (P/N) is specified for all

signal layers.

11.1.4.1 DMD Interface

The digital interface from the DLPC410 to the DMD are LVDS signals that run at clock rates up to 400 MHz.

DDR Data is clocked into the DMD on both the rising and falling edge of the clock, so the data rate is 800 MHz.

The LVDS signals should have 100-Ω differential impedance. The differential signals should be matched but kept

as short as possible. Parallel termination at the LVDS receiver is in the DMD; therefore, on board termination is

not necessary.

11.1.4.1.1 Trace Length Matching

The require precise length matching. LVDS data bus differential pairs should have an impedance of 100 Ω (with

5% tolerance). It is important that the propagation delays are matched. The maximum differential pair uncoupled

length is 150 mils with a relative propagation delay of ±25 mil between the p and n. Matching all signals exactly

will maximize the channel margin. The signal path through all boards, flex cables and internal DMD routing must

be considered in this calculation.

11.1.4.2 DLPC410 DMD Decoupling

General decoupling capacitors for the DMD should be distributed around the PCB and placed to minimize the

distance from IC voltage and ground pads. Each decoupling capacitor (0.1 µF recommended) should have vias

directly to the ground and power planes. Via sharing between components (discreet or integrated) is

discouraged. The power and ground pads of the DMD should be tied to the voltage and ground planes with their

own vias.

11.1.4.2.1 Decoupling Capacitors

Decoupling capacitors should be placed to minimize the distance from the decoupling capacitor to the supply and

ground pin of the component. It is recommended that the placement of and routing for the decoupling capacitors

meet the following guidelines:

•

The supply voltage pin of the capacitor should be located close to the device supply voltage pin(s). The

decoupling capacitor should have vias to ground and voltage planes. The device can be connected directly to

the decoupling capacitor (no via) if the trace length is less than 0.1 inch. Otherwise, the component should be

tied to the voltage or ground plane through separate vias.

•

The trace lengths of the voltage and ground connections for decoupling capacitors and components should

be less than 0.1 inch to minimize inductance.

The trace width of the power and ground connection to decoupling capacitors and components should be as

wide as possible to minimize inductance.

Connecting decoupling capacitors to ground and power planes through multiple vias can reduce inductance

and improve noise performance.

Decoupling performance can be improved by utilizing low ESR and low ESL capacitors.

11.1.4.3 VCC and VCC2

The VCC pins of the DMD should be connected directly to the DMD VCC plane. Decoupling for the VCC should

be distributed around the DMD and placed to minimize the distance from the voltage and ground pads. Each

decoupling capacitor should have vias directly connected to the ground and power planes. The VCC and GND

pads of the DMD should be tied to the VCC and ground planes with their own vias.

The VCC2 voltage can be routed to the DMD as a trace. Decoupling capacitors should be placed to minimize the

distance from the VCC2 and ground pads of the DMD. Using wide etch from the decoupling capacitors to the

DMD connection will reduce inductance and improve decoupling performance.

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11.1.4.4 DMD Layout

See the respective sections in this data sheet for package dimensions, timing and pin out information.

11.1.4.5 DLPA200

The DLPA200 generates the micromirror clocking pulses for the DMD. The DMD-drive outputs from the

DLPA200 should be routed with minimum trace width of 11 mil and a minimum spacing of 15 mil. The VCC and

VCC2 traces from the output capacitors to the DLPA200 should also be routed with a minimum trace width and

spacing of 11 mil and 15 mil, respectively. See the DLPA200 customer data sheet for mechanical package and

layout information.

11.2 Layout Example

For LVDS (and other differential signal) pairs and groups, it is important to match trace lengths. In the area of the

dashed lines, 图 26 shows correct matching of signal pair lengths with serpentine sections to maintain the correct

impedance.

图 26. Mitering LVDS Traces to Match Lengths

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11.3 DLPC410 Chipset Connections

The following tables list the signal connections between components of the Chipset when used with the

DLP650LNIR DMD, the DLP7000 / DLP700UV DMD, and with the DLP9500 / DLP9500UV DMD. These tables

do not include power, ground, pull-up, pull-down, termination, or any other connection requirements. Please see

the Pin Functions table in the respective data sheet of each chipset component for connection requirements.

表 23. DLPC410 Chipset Connections with the DLP650LNIR

DLPC410 (CONTROLLER)

DLPR410 (PROM)

DLPA200 (MICROMIRROR

DRIVER)

DLP650LNIR (DMD)

NAME

NO.

K10

NAME

NO.

B4

NAME

NO.

NAME

NO.

DONE_DDC

CE

INTB_DDC

J11

J18

J10

K11

U11

V11

V12

E1

OE/RESET

CF

A3

D1

C2

H6

H3

E6

E2

PROGB_DDC

PROM_CCK_DDC

PROM_D0_DDC

TCK_JTAG

CLKOUT

D0

TCK

TDO_XCF16DDC

TMS_JTAG

TDO

TMS

DAD_A_ADDR0

DAD_A_ADDR1

DAD_A_ADDR2

DAD_A_ADDR3

DAD_A_MODE0

DAD_A_MODE1

DAD_A_SEL0

ADDR0

ADDR1

ADDR2

ADDR3

MODE0

MODE1

SEL0

19

18

17

16

3

E2

E3

F3

C1

D1

2

AB12

AC12

AF3

AF4

AF5

AE3

AB15

AA15

AA14

AB14

AD14

N1

5

DAD_A_SEL1

SEL1

4

DAD_A_STROBE

DAD_INIT

STROBE

RESET

OE

15

59

6

DAD_OE

DAD_A_SCPEN

SCPCLK

SCPEN

SCPCLK

SCPDO

SCPDI

58

56

57

42

SCPCLK

E3

SCPDI

SCPDO

B2

SCPDO

SCPDI

F4

DMD_A_SCPEN

DMD_A_RESET

DDC_DCLKOUT_A_DPN

DDC_DCLKOUT_A_DPP

DDC_DCLKOUT_B_DPN

DDC_DCLKOUT_B_DPP

DDC_DOUT_A1_DPN

DDC_DOUT_A1_DPP

DDC_DOUT_A3_DPN

DDC_DOUT_A3_DPP

DDC_DOUT_A5_DPN

DDC_DOUT_A5_DPP

DDC_DOUT_A7_DPN

DDC_DOUT_A7_DPP

DDC_DOUT_A9_DPN

DDC_DOUT_A9_DPP

SCPEN

D4

PWRDN

DCLK_AN

DCLK_AP

DCLK_BN

DCLK_BP

D_AN(1)

D_AP(1)

D_AN(3)

D_AP(3)

D_AN(5)

D_AP(5)

D_AN(7)

D_AP(7)

D_AN(9)

D_AP(9)

C3

B22

B24

AB22

AB24

A13

A11

C17

C15

A17

A19

D22

D20

D28

B28

M1

Y5

Y6

AD1

AE1

AB1

AB2

W1

Y1

U1

U2

N2

M2

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DLPC410 Chipset Connections (接下页)

表 23. DLPC410 Chipset Connections with the DLP650LNIR (接下页)

DLPC410 (CONTROLLER)

DLPR410 (PROM)

DLPA200 (MICROMIRROR

DRIVER)

DLP650LNIR (DMD)

NAME

NO.

K2

NAME

NO.

NAME

NO.

NAME

D_AN(11)

NO.

DDC_DOUT_A11_DPN

F26

DDC_DOUT_A11_DPP

DDC_DOUT_A13_DPN

DDC_DOUT_A13_DPP

DDC_DOUT_A15_DPN

DDC_DOUT_A15_DPP

DDC_DOUT_B1_DPN

DDC_DOUT_B1_DPP

DDC_DOUT_B3_DPN

DDC_DOUT_B3_DPP

DDC_DOUT_B5_DPN

DDC_DOUT_B5_DPP

DDC_DOUT_B7_DPN

DDC_DOUT_B7_DPP

DDC_DOUT_B9_DPN

DDC_DOUT_B9_DPP

DDC_DOUT_B11_DPN

DDC_DOUT_B11_DPP

DDC_DOUT_B13_DPN

DDC_DOUT_B13_DPP

DDC_DOUT_B15_DPN

DDC_DOUT_B15_DPP

DDC_SCTRL_AN

K3

D_AP(11)

D_AN(13)

D_AP(13)

D_AN(15)

D_AP(15)

D_BN(1)

D26

H2

H28

J1

H30

G2

K26

F2

K28

AD3

AD4

AC3

AC4

AB7

AC6

AA7

Y7

AC13

AC11

AA17

AA15

AC17

AC19

Y22

D_BP(1)

D_BN(3)

D_BP(3)

D_BN(5)

D_BP(5)

D_BN(7)

D_BP(7)

Y20

W4

V4

D_BN(9)

Y28

D_BP(9)

AB28

V26

V7

D_BN(11)

D_BP(11)

D_BN(13)

D_BP(13)

D_BN(15)

D_BP(15)

SCTRL_AN

SCTRL_AP

SCTRL_BN

SCTRL_BP

V6

Y26

T4

R29

T5

T28

U7

N27

T7

P26

R1

C21

DDC_SCTRL_AP

P1

C23

DDC_SCTRL_BN

AA3

AB4

AA21

AA23

DDC_SCTRL_BP

表 24. DLPC410 Chipset Connections with the DLP7000

DLPC410 (CONTROLLER)

DLPR410 (PROM)

DLPA200 (MICROMIRROR

DRIVER)

DLP7000 / UV (DMD)

NAME

NO.

K10

NAME

NO.

B4

NAME

NO.

DONE_DDC

INTB_DDC

CE

J11

J18

J10

K11

U11

V11

V12

E1

OE/RESET

CF

A3

D1

C2

H6

H3

E6

E2

PROGB_DDC

PROM_CCK_DDC

PROM_D0_DDC

TCK_JTAG

CLKOUT

D0

TCK

TDO_XCF16DDC

TMS_JTAG

TDO

TMS

DAD_A_ADDR0

DAD_A_ADDR1

DAD_A_ADDR2

ADDR0

ADDR1

ADDR2

19

18

17

E2

E3

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表 24. DLPC410 Chipset Connections with the DLP7000 (接下页)

DLPC410 (CONTROLLER)

DLPR410 (PROM)

DLPA200 (MICROMIRROR

DRIVER)

DLP7000 / UV (DMD)

NAME

NO.

F3

NAME

NO.

NAME

NO.

DAD_A_ADDR3

ADDR3

MODE0

MODE1

SEL0

16

3

DAD_A_MODE0

C1

DAD_A_MODE1

D1

2

DAD_A_SEL0

AB12

AC12

AF3

AF4

AF5

AE3

AB15

AA15

AA14

AB14

AD14

N1

5

DAD_A_SEL1

SEL1

4

DAD_A_STROBE

STROBE

RESET

OE

15

59

6

DAD_INIT

DAD_OE

DAD_A_SCPEN

SCPEN

SCPCLK

SCPDO

SCPDI

58

56

57

42

SCPCLK

E3

SCPDI

SCPDO

B2

SCPDO

SCPDI

F4

DMD_A_SCPEN

SCPEN

D4

DMD_A_RESET

PWRDN

DCLK_AN

DCLK_AP

DCLK_BN

DCLK_BP

D_AN(0)

D_AP(0)

D_AN(1)

D_AP(1)

D_AN(2)

D_AP(2)

D_AN(3)

D_AP(3)

D_AN(4)

D_AP(4)

D_AN(5)

D_AP(5)

D_AN(6)

D_AP(6)

D_AN(7)

D_AP(7)

D_AN(8)

D_AP(8)

D_AN(9)

D_AP(9)

D_AN(10)

D_AP(10)

D_AN(11)

D_AP(11)

D_AN(12)

D_AP(12)

D_AN(13)

C3

DDC_DCLKOUT_A_DPN

DDC_DCLKOUT_A_DPP

DDC_DCLKOUT_B_DPN

DDC_DCLKOUT_B_DPP

DDC_DOUT_A0_DPN

DDC_DOUT_A0_DPP

DDC_DOUT_A1_DPN

DDC_DOUT_A1_DPP

DDC_DOUT_A2_DPN

DDC_DOUT_A2_DPP

DDC_DOUT_A3_DPN

DDC_DOUT_A3_DPP

DDC_DOUT_A4_DPN

DDC_DOUT_A4_DPP

DDC_DOUT_A5_DPN

DDC_DOUT_A5_DPP

DDC_DOUT_A6_DPN

DDC_DOUT_A6_DPP

DDC_DOUT_A7_DPN

DDC_DOUT_A7_DPP

DDC_DOUT_A8_DPN

DDC_DOUT_A8_DPP

DDC_DOUT_A9_DPN

DDC_DOUT_A9_DPP

DDC_DOUT_A10_DPN

DDC_DOUT_A10_DPP

DDC_DOUT_A11_DPN

DDC_DOUT_A11_DPP

DDC_DOUT_A12_DPN

DDC_DOUT_A12_DPP

DDC_DOUT_A13_DPN

B22

B24

AB22

AB24

B10

B12

A13

A11

D16

D14

C17

C15

B18

B16

A17

A19

A25

A23

D22

D20

C29

A29

D28

B28

E27

C27

F26

D26

G29

F30

H28

M1

Y5

Y6

AE2

AF2

AD1

AE1

AC1

AC2

AB1

AB2

Y2

AA2

W1

Y1

V1

V2

U1

U2

R2

T2

N2

M2

K1

L2

K2

K3

J3

H3

H2

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表 24. DLPC410 Chipset Connections with the DLP7000 (接下页)

DLPC410 (CONTROLLER)

DLPR410 (PROM)

DLPA200 (MICROMIRROR

DRIVER)

DLP7000 / UV (DMD)

NAME

NO.

J1

NAME

NO.

NAME

NO.

NAME

D_AP(13)

NO.

DDC_DOUT_A13_DPP

DDC_DOUT_A14_DPN

DDC_DOUT_A14_DPP

DDC_DOUT_A15_DPN

DDC_DOUT_A15_DPP

DDC_DOUT_B0_DPN

DDC_DOUT_B0_DPP

DDC_DOUT_B1_DPN

DDC_DOUT_B1_DPP

DDC_DOUT_B2_DPN

DDC_DOUT_B2_DPP

DDC_DOUT_B3_DPN

DDC_DOUT_B3_DPP

DDC_DOUT_B4_DPN

DDC_DOUT_B4_DPP

DDC_DOUT_B5_DPN

DDC_DOUT_B5_DPP

DDC_DOUT_B6_DPN

DDC_DOUT_B6_DPP

DDC_DOUT_B7_DPN

DDC_DOUT_B7_DPP

DDC_DOUT_B8_DPN

DDC_DOUT_B8_DPP

DDC_DOUT_B9_DPN

DDC_DOUT_B9_DPP

DDC_DOUT_B10_DPN

DDC_DOUT_B10_DPP

DDC_DOUT_B11_DPN

DDC_DOUT_B11_DPP

DDC_DOUT_B12_DPN

DDC_DOUT_B12_DPP

DDC_DOUT_B13_DPN

DDC_DOUT_B13_DPP

DDC_DOUT_B14_DPN

DDC_DOUT_B14_DPP

DDC_DOUT_B15_DPN

DDC_DOUT_B15_DPP

DDC_SCTRL_AN

H30

H1

D_AN(14)

D_AP(14)

D_AN(15)

D_AP(15)

D_BN(0)

D_BP(0)

J27

G1

J29

G2

K26

F2

K28

AE5

AE6

AD3

AD4

AD5

AD6

AC3

AC4

AB5

AB6

AB7

AC6

AA5

AA4

AA7

Y7

AB10

AB12

AC13

AC11

Y16

D_BN(1)

D_BP(1)

D_BN(2)

D_BP(2)

Y14

D_BN(3)

D_BP(3)

AA17

AA15

AB18

AB16

AC17

AC19

AC25

AC23

Y22

D_BN(4)

D_BP(4)

D_BN(5)

D_BP(5)

D_BN(6)

D_BP(6)

D_BN(7)

D_BP(7)

Y20

Y3

D_BN(8)

D_BP(8)

AA29

AC29

Y28

W3

W4

V4

D_BN(9)

D_BP(9)

AB28

W27

AA27

V26

W6

W5

V7

D_BN(10)

D_BP(10)

D_BN(11)

D_BP(11)

D_BN(12)

D_BP(12)

D_BN(13)

D_BP(13)

D_BN(14)

D_BP(14)

D_BN(15)

D_BP(15)

SCTRL_AN

SCTRL_AP

SCTRL_BN

SCTRL_BP

V6

Y26

U4

T30

V3

U29

T4

R29

T5

T28

U6

R27

U5

P28

U7

N27

T7

P26

R1

C21

DDC_SCTRL_AP

P1

C23

DDC_SCTRL_BN

AA3

AB4

AA21

AA23

DDC_SCTRL_BP

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表 25. DLPC410 Chipset Connections with the DLP9500

DLPC410 (CONTROLLER)

DLPR410 (PROM)

DLPA200 Number 1

(MICROMIRROR

DRIVER)

DLPA200 Number 2

(MICROMIRROR

DRIVER)

DLP9500 or UV

(DMD)

NAME

NO.

K10

NAME

NO.

NAME

NO.

NAME

NO.

NAME

NO.

DONE_DDC

CE

B4

A3

D1

C2

H6

H3

E6

E2

INTB_DDC

J11

OE/RESET

CF

PROGB_DDC

J18

PROM_CCK_DDC

PROM_D0_DDC

TCK_JTAG

J10

CLKOUT

D0

K11

U11

V11

V12

E1

TCK

TDO_XCF16DDC

TMS_JTAG

TDO

TMS

DAD_A_ADDR0

DAD_A_ADDR1

DAD_A_ADDR2

DAD_A_ADDR3

DAD_A_MODE0

DAD_A_MODE1

DAD_A_SEL0

ADDR0

19

E2

ADDR1

ADDR2

ADDR3

MODE0

MODE1

SEL0

18

17

16

3

E3

F3

C1

D1

2

AB12

AC12

AF3

E26

E25

F25

F24

D26

D25

R22

R23

AB20

AF4

AF5

AE3

AB19

AB15

AA15

AA14

AB14

AD14

N1

5

DAD_A_SEL1

SEL1

4

DAD_A_STROBE

DAD_B_ADDR0

DAD_B_ADDR1

DAD_B_ADDR2

DAD_B_ADDR3

DAD_B_MODE0

DAD_B_MODE1

DAD_B_SEL0

STROBE

15

ADDR0

19

ADDR1

ADDR2

ADDR3

MODE0

MODE1

SEL0

18

17

16

3

2

5

DAD_B_SEL1

SEL1

4

DAD_B_STROBE

DAD_INIT

STROBE

RESET

OE

15

59

6

RESET

OE

59

6

DAD_OE

DAD_A_SCPEN

DAD_B_SCPEN

SCPCLK

SCPEN

58

SCPEN

SCPCLK

SCPDO

SCPDI

58

56

57

42

SCPCLK

SCPDO

SCPDI

56

57

42

SCPCLK

SCPDO

AE1

SCPDI

AC3

AD2

AD4

B4

SCPDO

SCPDI

DMD_A_SCPEN

DMD_A_RESET

DDC_DCLKOUT_A_DPN

DDC_DCLKOUT_A_DPP

DDC_DCLKOUT_B_DPN

DDC_DCLKOUT_B_DPP

DDC_DCLKOUT_C_DPN

DDC_DCLKOUT_C_DPP

DDC_DCLKOUT_D_DPN

DDC_DCLKOUT_D_DPP

DDC_DOUT_A0_DPN

SCPEN

PWRDN

DCLK_AN

DCLK_AP

DCLK_BN

DCLK_BP

DCLK_CN

DCLK_CP

DCLK_DN

DCLK_DP

D_AN(0)

D10

D8

M1

Y5

AJ11

AJ9

C23

C21

AJ23

AJ21

F2

Y6

AA22

AB22

M26

M25

AE2

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表 25. DLPC410 Chipset Connections with the DLP9500 (接下页)

DLPC410 (CONTROLLER)

DLPR410 (PROM)

DLPA200 Number 1

(MICROMIRROR

DRIVER)

DLPA200 Number 2

(MICROMIRROR

DRIVER)

DLP9500 or UV

(DMD)

NAME

NO.

AF2

NAME

NO.

NAME

NO.

NAME

NO.

NAME

D_AP(0)

D_AN(1)

D_AP(1)

D_AN(2)

D_AP(2)

D_AN(3)

D_AP(3)

D_AN(4)

D_AP(4)

D_AN(5)

D_AP(5)

D_AN(6)

D_AP(6)

D_AN(7)

D_AP(7)

D_AN(8)

D_AP(8)

D_AN(9)

D_AP(9)

D_AN(10)

D_AP(10)

D_AN(11)

D_AP(11)

D_AN(12)

D_AP(12)

D_AN(13)

D_AP(13)

D_AN(14)

D_AP(14)

D_AN(15)

D_AP(15)

D_BN(0)

D_BP(0)

D_BN(1)

D_BP(1)

D_BN(2)

D_BP(2)

D_BN(3)

D_BP(3)

D_BN(4)

D_BP(4)

D_BN(5)

D_BP(5)

D_BN(6)

NO.

DDC_DOUT_A0_DPP

DDC_DOUT_A1_DPN

DDC_DOUT_A1_DPP

DDC_DOUT_A2_DPN

DDC_DOUT_A2_DPP

DDC_DOUT_A3_DPN

DDC_DOUT_A3_DPP

DDC_DOUT_A4_DPN

DDC_DOUT_A4_DPP

DDC_DOUT_A5_DPN

DDC_DOUT_A5_DPP

DDC_DOUT_A6_DPN

DDC_DOUT_A6_DPP

DDC_DOUT_A7_DPN

DDC_DOUT_A7_DPP

DDC_DOUT_A8_DPN

DDC_DOUT_A8_DPP

DDC_DOUT_A9_DPN

DDC_DOUT_A9_DPP

DDC_DOUT_A10_DPN

DDC_DOUT_A10_DPP

DDC_DOUT_A11_DPN

DDC_DOUT_A11_DPP

DDC_DOUT_A12_DPN

DDC_DOUT_A12_DPP

DDC_DOUT_A13_DPN

DDC_DOUT_A13_DPP

DDC_DOUT_A14_DPN

DDC_DOUT_A14_DPP

DDC_DOUT_A15_DPN

DDC_DOUT_A15_DPP

DDC_DOUT_B0_DPN

DDC_DOUT_B0_DPP

DDC_DOUT_B1_DPN

DDC_DOUT_B1_DPP

DDC_DOUT_B2_DPN

DDC_DOUT_B2_DPP

DDC_DOUT_B3_DPN

DDC_DOUT_B3_DPP

DDC_DOUT_B4_DPN

DDC_DOUT_B4_DPP

DDC_DOUT_B5_DPN

DDC_DOUT_B5_DPP

DDC_DOUT_B6_DPN

F4

AD1

AE1

AC1

AC2

AB1

AB2

Y2

H8

H10

E5

E3

G9

G11

D2

AA2

W1

Y1

D4

G3

G5

V1

E11

E9

V2

U1

F8

U2

F10

C9

R2

T2

C11

H2

N2

M2

H4

K1

B10

B8

L2

K2

G15

H14

D14

D16

F14

F16

C17

C15

H16

G17

AH2

AH4

AD8

AD10

AJ5

AJ3

AE3

AE5

AG9

AG11

AE11

AE9

AH10

K3

J3

H3

H2

J1

H1

G1

G2

F2

AE5

AE6

AD3

AD4

AD5

AD6

AC3

AC4

AB5

AB6

AB7

AC6

AA5

73

DLPC410

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www.ti.com.cn

表 25. DLPC410 Chipset Connections with the DLP9500 (接下页)

DLPC410 (CONTROLLER)

DLPR410 (PROM)

DLPA200 Number 1

(MICROMIRROR

DRIVER)

DLPA200 Number 2

(MICROMIRROR

DRIVER)

DLP9500 or UV

(DMD)

NAME

NO.

AA4

NAME

NO.

NAME

NO.

NAME

NO.

NAME

NO.

AH8

DDC_DOUT_B6_DPP

D_BP(6)

D_BN(7)

D_BP(7)

D_BN(8)

D_BP(8)

D_BN(9)

D_BP(9)

D_BN(10)

D_BP(10)

D_BN(11)

D_BP(11)

D_BN(12)

D_BP(12)

D_BN(13)

D_BP(13)

D_BN(14)

D_BP(14)

D_BN(15)

D_BP(15)

D_CN(0)

D_CP(0)

D_CN(1)

D_CP(1)

D_CN(2)

D_CP(2)

D_CN(3)

D_CP(3)

D_CN(4)

D_CP(4)

D_CN(5)

D_CP(5)

D_CN(6)

D_CP(6)

D_CN(7)

D_CP(7)

D_CN(8)

D_CP(8)

D_CN(9)

D_CP(9)

D_CN(10)

D_CP(10)

D_CN(11)

D_CP(11)

D_CN(12)

DDC_DOUT_B7_DPN

DDC_DOUT_B7_DPP

DDC_DOUT_B8_DPN

DDC_DOUT_B8_DPP

DDC_DOUT_B9_DPN

DDC_DOUT_B9_DPP

DDC_DOUT_B10_DPN

DDC_DOUT_B10_DPP

DDC_DOUT_B11_DPN

DDC_DOUT_B11_DPP

DDC_DOUT_B12_DPN

DDC_DOUT_B12_DPP

DDC_DOUT_B13_DPN

DDC_DOUT_B13_DPP

DDC_DOUT_B14_DPN

DDC_DOUT_B14_DPP

DDC_DOUT_B15_DPN

DDC_DOUT_B15_DPP

DDC_DOUT_C0_DPN

DDC_DOUT_C0_DPP

DDC_DOUT_C1_DPN

DDC_DOUT_C1_DPP

DDC_DOUT_C2_DPN

DDC_DOUT_C2_DPP

DDC_DOUT_C3_DPN

DDC_DOUT_C3_DPP

DDC_DOUT_C4_DPN

DDC_DOUT_C4_DPP

DDC_DOUT_C5_DPN

DDC_DOUT_C5_DPP

DDC_DOUT_C6_DPN

DDC_DOUT_C6_DPP

DDC_DOUT_C7_DPN

DDC_DOUT_C7_DPP

DDC_DOUT_C8_DPN

DDC_DOUT_C8_DPP

DDC_DOUT_C9_DPN

DDC_DOUT_C9_DPP

DDC_DOUT_C10_DPN

DDC_DOUT_C10_DPP

DDC_DOUT_C11_DPN

DDC_DOUT_C11_DPP

DDC_DOUT_C12_DPN

AA7

Y7

AF10

AF8

AK8

AK10

AG5

AG3

AL11

AL9

Y3

W3

W4

V4

W6

W5

V7

AE15

AD14

AH14

AH16

AF14

AF16

AJ17

AJ15

AD16

AE17

B14

V6

U4

V3

T4

T5

U6

U5

U7

T7

T22

T23

R20

R21

T19

T20

U21

U22

U20

U19

V23

V24

V22

V21

W19

V19

W23

W24

Y22

Y23

Y20

Y21

AA24

AA23

AA19

B16

E15

E17

A17

A15

G21

H20

B20

B22

F20

F22

D22

D20

G23

H22

B26

B28

F28

F26

C29

C27

G27

G29

D26

74

DLPC410

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ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

表 25. DLPC410 Chipset Connections with the DLP9500 (接下页)

DLPC410 (CONTROLLER)

DLPR410 (PROM)

DLPA200 Number 1

(MICROMIRROR

DRIVER)

DLPA200 Number 2

(MICROMIRROR

DRIVER)

DLP9500 or UV

(DMD)

NAME

NO.

AA20

AC24

AB24

AC19

AD19

AC22

AC23

AB26

AC26

AA25

AB25

Y26

NAME

NO.

NAME

NO.

NAME

NO.

NAME

D_CP(12)

D_CN(13)

D_CP(13)

D_CN(14)

D_CP(14)

D_CN(15)

D_CP(15)

D_DN(0)

D_DP(0)

NO.

DDC_DOUT_C12_DPP

DDC_DOUT_C13_DPN

DDC_DOUT_C13_DPP

DDC_DOUT_C14_DPN

DDC_DOUT_C14_DPP

DDC_DOUT_C15_DPN

DDC_DOUT_C15_DPP

DDC_DOUT_D0_DPN

DDC_DOUT_D0_DPP

DDC_DOUT_D1_DPN

DDC_DOUT_D1_DPP

DDC_DOUT_D2_DPN

DDC_DOUT_D2_DPP

DDC_DOUT_D3_DPN

DDC_DOUT_D3_DPP

DDC_DOUT_D4_DPN

DDC_DOUT_D4_DPP

DDC_DOUT_D5_DPN

DDC_DOUT_D5_DPP

DDC_DOUT_D6_DPN

DDC_DOUT_D6_DPP

DDC_DOUT_D7_DPN

DDC_DOUT_D7_DPP

DDC_DOUT_D8_DPN

DDC_DOUT_D8_DPP

DDC_DOUT_D9_DPN

DDC_DOUT_D9_DPP

DDC_DOUT_D10_DPN

DDC_DOUT_D10_DPP

DDC_DOUT_D11_DPN

DDC_DOUT_D11_DPP

DDC_DOUT_D12_DPN

DDC_DOUT_D12_DPP

DDC_DOUT_D13_DPN

DDC_DOUT_D13_DPP

DDC_DOUT_D14_DPN

DDC_DOUT_D14_DPP

DDC_DOUT_D15_DPN

DDC_DOUT_D15_DPP

DDC_SCTRL_AN

D28

H28

H26

E29

E27

J29

J27

AK14

AK16

AG15

AG17

AL17

AL15

AE21

AD20

AK20

AK22

AF20

AF22

AH22

AH20

AE23

AD22

AK26

AK28

AF28

AF26

AJ29

AJ27

AE27

AE29

AH26

AH28

AD28

AD26

AG29

AG27

AC29

AC27

J3

D_DN(1)

D_DP(1)

D_DN(2)

D_DP(2)

Y25

W26

W25

U26

V26

D_DN(3)

D_DP(3)

D_DN(4)

D_DP(4)

U25

U24

T25

D_DN(5)

D_DP(5)

D_DN(6)

D_DP(6)

T24

R26

R25

P24

D_DN(7)

D_DP(7)

D_DN(8)

D_DP(8)

P25

N24

M24

L25

D_DN(9)

D_DP(9)

D_DN(10)

D_DP(10)

D_DN(11)

D_DP(11)

D_DN(12)

D_DP(12)

D_DN(13)

D_DP(13)

D_DN(14)

D_DP(14)

D_DN(15)

D_DP(15)

SCTRL_AN

SCTRL_AP

SCTRL_BN

SCTRL_BP

SCTRL_CN

L24

K26

K25

J26

J25

J24

H24

H26

G26

G25

G24

R1

DDC_SCTRL_AP

P1

J5

DDC_SCTRL_BN

AA3

AB4

W20

AF4

DDC_SCTRL_BP

AF2

DDC_SCTRL_CN

E23

75

DLPC410

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

www.ti.com.cn

表 25. DLPC410 Chipset Connections with the DLP9500 (接下页)

DLPC410 (CONTROLLER)

DLPR410 (PROM)

DLPA200 Number 1

(MICROMIRROR

DRIVER)

DLPA200 Number 2

(MICROMIRROR

DRIVER)

DLP9500 or UV

(DMD)

NAME

NO.

W21

N26

P26

NAME

NO.

NAME

NO.

NAME

NO.

NAME

NO.

E21

DDC_SCTRL_CP

SCTRL_CP

SCTRL_DN

SCTRL_DP

DDC_SCTRL_DN

DDC_SCTRL_DP

AG23

AG21

76

DLPC410

www.ti.com.cn

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

12 器件和文档支持

12.1 器件支持

12.1.1 器件标记

图 27 显示了为 DLPC410 器件配置的典型 Xilinx XC5VLX30 FPGA。

图 27. Xilinx XC5VLX30 FGPA 图

图 28 提供了读取该 DLP 器件的 Xilinx 器件标志图例。

XC5VLX30-1FFG676C

Temperature Range

Number of Pins

PB-Free

Device Type

Speed Grade

Package Type

图 28. 图例

12.1.2 器件命名规则

图 29 提供了读取任一 DLP 器件完整器件名称的图例。

DLPC410 ZYR

Package Type

Device Descriptor

图 29. 器件命名规则

77

DLPC410

ZHCSA85F –AUGUST 2012–REVISED FEBRUARY 2019

www.ti.com.cn

12.2 文档支持

12.2.1 相关文档

表 26. 相关文档

文档

TI 文献编号

DLPS136

DLPS026

DLPS061

DLPS025

DLPS033

DLPS015

DLPS027

DLP650LNIR 0.65 NIR WXGA S450 DMD 数据表

DLP7000 DLP 0.7 XGA 2x LVDS A 类 DMD 数据表

DLP7000UV DLP 0.7 UV XGA 2x LVDS A 类 DMD 数据表

DLP9500 DLP 0.95 1080p 2x LVDS A 类 DMD 数据表

DLP9500UV DLP 0.95 UV 1080p 2x LVDS A 类 DMD 数据表

《DLPA200 DMD 微镜驱动器数据表》

DLPR410 配置 PROM 数据表

12.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.4 商标

E2E is a trademark of Texas Instruments.

DLP is a registered trademark of Texas Instruments.

12.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.6 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

78

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DLPC410
厂家：	TEXAS INSTRUMENTS
描述：	用于 DLP650LNIR、DLP7000/7000UV 和 DLP9500/DLP9500UV 数字微镜开发的数字控制器控制器
文件：	总80页 (文件大小：1377K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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