TLC6984ZXLR [TI]
48 个电流源，64 次扫描，共阴极矩阵 LED 显示驱动器 | ZXL | 96 | -40 to 85;
| 型号： | TLC6984ZXLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 48 个电流源，64 次扫描，共阴极矩阵 LED 显示驱动器 | ZXL | 96 | -40 to 85 驱动 显示驱动器 |
| 文件： | 总77页 (文件大小：3294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC6984
ZHCSPI8D –NOVEMBER 2021 –REVISED JULY 2022
TLC6984 48 个电流源、64 次扫描、共阴极矩阵LED 显示驱动器
– 支持高GCLK 频率的内部倍频器
• 优化的显示性能
1 特性
• 支持分立式VCC 和VR/G/B 电源
– 可编程的扫描线序列
– 去除上下重影
– 低灰度增强
– VCC 电压范围：2.5 V 至5.5 V
– VR/G/B 电压范围：2.5 V 至5.5 V
• 48 个电流源通道，范围从0.2 mA 到20 mA
– 检测和消除LED 开路、短路和弱短路
– 通道间精度：±0.5%（典型值），±2%（最大
值）；器件间一致性：±0.5%（典型值），±2%
（最大值）
– 低拐点电压：当IOUT = 5 mA 时为0.26V（最大
值）
2 应用
• 窄像素间距(NPP) LED 显示屏
• Mini/Micro-LED 产品
3 说明
– 3 位（8 级）全局亮度控制
随着窄像素间距LED 显示屏或 Mini/Micro-LED 产品的
像素密度不断提高，我们迫切需要使用 LED 驱动器来
应对各种关键挑战。这些挑战包括通过超高集成度满足
严格的布板空间限制条件，通过超低功耗最大限度地降
低系统级功耗，通过全新的接口实现高数据刷新率并减
少 EMI 带来的影响，以及通过出色的显示性能满足不
断增长的对更高显示质量的需求。
– 8 位（256 级）色彩亮度控制
– 最大16 位（65536 级）PWM 灰度控制
• 带190 mΩRDS(ON) 的16 个扫描线开关
• 超低功耗
– 低至2.5V 的独立VCC
– 超低ICC（低至3.6 mA），具有50 MHz GCLK
– 智能省电模式，ICC 低至0.9 mA
• 内置SRAM 支持1 至64 路复用
– 支持16 路复用的单个器件可驱动48 × 16 LED
或16 × 16 RGB 像素
器件信息
封装(1)
VQFN (76)
BGA (96)
封装尺寸（标称值）
9.00mm x 9.00mm
6.00mm × 6.00mm
器件型号
TLC6984
– 支持32 路复用的两个器件堆叠后可驱动96 ×
32 LED 或32 × 32 RGB 像素
– 三个可堆叠48 路复用器件，支持144×48 LED
或48×48 RGB 像素
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 四个可堆叠64 路复用器件，支持192 × 64 LED
或64 × 64 RGB 像素
• 高速和低EMI 连续时钟串行接口(CCSI)
– 仅三条总线：SCLK/SIN/SOUT
– 具有双沿传输机制的外部25MHz（最大值）
SCLK（内部50MHz）
具备四器件可堆叠连接的TLC6984
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSG10
TLC6984
www.ti.com.cn
ZHCSPI8D –NOVEMBER 2021 –REVISED JULY 2022
Table of Contents
8.5 Continuous Clock Series Interface............................27
8.6 PWM Grayscale Control........................................... 33
8.7 Register Maps...........................................................36
9 Application and Implementation..................................52
9.1 Application Information............................................. 52
9.2 Typical Application.................................................... 52
10 Power Supply Recommendations..............................60
11 Layout...........................................................................61
11.1 Layout Guidelines................................................... 61
11.2 Layout Example...................................................... 61
12 Device and Documentation Support..........................65
12.1 Documentation Support.......................................... 65
12.2 接收文档更新通知................................................... 65
12.3 支持资源..................................................................65
12.4 Trademarks.............................................................65
12.5 Electrostatic Discharge Caution..............................65
12.6 术语表..................................................................... 65
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明（续）.........................................................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................7
7.6 Timing Requirements................................................10
7.7 Switching Characteristics..........................................10
7.8 Typical Characteristics.............................................. 11
8 Detailed Description......................................................13
8.1 Overview...................................................................13
8.2 Functional Block Diagram.........................................14
8.3 Feature Description...................................................14
8.4 Device Functional Modes..........................................26
Information.................................................................... 66
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision C (March 2022) to Revision D (July 2022)
Page
• 通篇更新了BGA 封装信息..................................................................................................................................1
• Changed the description of FREQ_MOD......................................................................................................... 37
• Changed the name of register field...................................................................................................................43
Changes from Revision B (March 2022) to Revision C (March 2022)
Page
• 更新了特性和说明（续）部分中的GCLK 说明...................................................................................................1
Changes from Revision A (December 2021) to Revision B (March 2022)
Page
• 将数据表状态从“预告信息”更改为“量产数据”.............................................................................................1
Changes from Revision * (November 2021) to Revision A (December 2021)
Page
• 首次公开发布的数据表........................................................................................................................................1
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5 说明（续）
TLC6984 是高度集成的共阴极矩阵 LED 显示驱动器，具有 48 个恒流源和 16 个扫描 FET。除了像 TLC6983 一
样驱动 16 × 16 和 32 × 32 RGB LED 像素，三个 TLC6984 还能够驱动 48 × 48 RGB LED 像素，堆叠四个
TLC6984 则可以驱动 64 × 64 RGB LED 像素。为实现低功耗，该器件可通过其共阴极结构为红色、绿色和蓝色
LED 提供分立式电源。此外，通过超低的工作电压范围（Vcc 低至 2.5V）和超低的工作电流（Icc 低至
3.6mA），TLC6984 可显著降低运行功率。
TLC6984 实现了一个高速双沿传输接口，可支持高器件数菊花链和高刷新率，同时尽可能降低电磁干扰 (EMI)。
该器件支持高达 25 MHz 的 SCLK（外部）和 40 MHz 至 160 MHz 的 GCLK（内部典型值），并具有不同的
GCLK 乘法器模式和频率。同时，该器件集成了增强电路和智能算法，能够应对窄像素间距 (NPP) LED 显示应用
和 Mini/Micro-LED 产品中的各种显示挑战。这些挑战包括 LED 开路或短路引起的第一个扫描线过暗、上下重
影、低灰度不均匀、耦合以及毛虫问题(Caterpillar)，因此TLC6984 是此类应用的理想选择。
TLC6984 还可以在运行期间实现 LED 开路、弱短路和短路检测和消除，并可以将这些信息报告给配套的数字处
理器。
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6 Pin Configuration and Functions
1
2
57
56
55
54
53
52
51
50
49
48
47
46
R0
G0
R15
G15
B15
R14
G14
B14
VG
3
B0
4
R1
5
G1
6
B1
7
GND
8
VCC
VR
VG
VB
VB
9
10
11
12
VR
R2
G2
GND
R13
G13
B13
13
45
B2
R3
G3
B3
R4
G4
14
15
16
17
18
44
43
42
41
40
R12
G12
B12
R11
G11
B11
19
39
B4
图6-1. TLC6984 RRF Package 76-Pin VQFN With Exposed Thermal Pad Top View
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
SOU
T
SCL
K
L2
L1
R1
G1
B1
B0
G0
R0
NC
SIN
NC
GND
GND
R14
G14
B14
R13
G13
R12
R11
L14
L15
GND
VG
L0
GND
GND
GND
GND
R7
GND
GND
GND
GND
B8
GND
GND
GND
GND
B9
GND
R15
G15
B15
B10
GND
VCC
VR
GND
R2
GND
R3
VG
G
H
J
G2
B2
G3
VB
VR
B3
VB
IREF
G4
R4
B13
G12
B12
K
L
B4
R6
B5
G6
B6
G7
B7
G8
R8
G9
R9
G10
R10
B11
G11
R5
G5
图6-2. TLC6984 ZXL Package 96-Pin BGA Top View
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ZHCSPI8D –NOVEMBER 2021 –REVISED JULY 2022
表6-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
RRF NO.
ZXL NO.
Pin for setting the maximum constant-current value. Connecting an external
resistor between IREF and GND sets the maximum current for each constant-
current output channel. When this pin is connected directly to GND, all outputs
are forced off. The external resistor must be placed close to the device.
IREF
20
J1
I
VCC
VR
8
F1
I
I
I
I
Device power supply
9, 10
51, 50
49, 48
G1, H1
E11, F11
G11, H11
Red LED power supply
Green LED power supply
Blue LED power supply
VG
VB
1, 4, 11, 14, B5, B2,F2, F4,
17, 21, 24, J2, L1, K3, H5,
27, 32, 35, L6, L7, L8, L10,
38, 41, 44, K10, H10, E10,
R0-R15
G0-G15
B0-B15
O
O
O
Red LED constant-current output
Green LED constant-current output
Blue LED constant-current output
47, 54, 57
E8
2, 5, 12, 15, B4, C2, G2, G4,
18, 22, 25, K1, L2, K4, K5,
28, 31, 34, K6, K7, K8, L9,
37, 40, 43, K11, J10, F10,
46, 53, 56
F8
3, 6, 13, 16, B3, D2, H2, H4,
19, 23, 26, K2, L3, L4, L5,
29, 30, 33, H6, H7, H8, K9,
36, 39, 42, L11, J11, G10,
45, 52, 55
G8
76, 75, 74,
73, 72, 71,
70, 69, 68,
67, 66, 65,
64, 63, 62,
61
D1, C1, B1, A1,
A2, A3, A4, A5,
A6, A7, A8, A9,
A10, A11, B11,
C11
LINE0-
LINE15
O
Scan lines
SCLK
SIN
60
59
58
B9
B8
B7
I
I
Clock-signal input pin
Serial-data input pin
Serial data output pin
SOUT
O
C10, E1, E2,
D5, D6, D7, D8,
D10, D11,
E1,E2, E4, E5,
E6,E7, F5, F6,
F7,G5, G6, G7
GND
7
Power-ground reference
—
—
Thermal
pad
The thermal pad and the GND pin must be connected together on the board.
—
—
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–40
–55
MAX
6
UNIT
V
VCC
VR/G/B
6
V
Voltage
IREF, SCLK, SIN, SOUT, VSYNC
RX/GX/BX
6
V
6
V
LINE0 to LINE15
6
V
Operating junction temperature, TJ
Storage temperature, Tstg
150
150
°C
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
7.2 ESD Ratings
VALUE
±4000
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.5
NOM
MAX
5.5
UNIT
V
VCC
Device supply voltage
VLEDR/G/B LED supply voltage
2.5
5.5
V
VIH
VIL
IOH
IOL
ICH
ILINE
TA
High level logic input voltage (SCLK, SIN, VSYNC)
0.7 × VCC
V
Low level logic input voltage (SCLK, SIN, VSYNC)
High level logic output current (SOUT)
Low level logic output current (SOUT)
Constant output source current
0.3 × VCC
V
mA
mA
mA
A
–2
2
0.2
0
20
2
Line scan switch load current
Ambient operating temperature
85
°C
–40
7.4 Thermal Information
TLC6984
THERMAL METRIC(1)
RRF (VQFN)
76 PINS
22.2
ZXL (BGA)
UNIT
96 PINS
33.5
18.6
11.7
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
10.7
RθJB
ψJT
Junction-to-board thermal resistance
7.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.1
0.3
7.1
11.6
ψJB
RθJC(bot) Junction-to-case (bottom) thermal resistance
1.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
At VCC = VR = 2.8 V, VG/B = 3.8 V and TA = –40°C to +85°C; Typical values are at TA = 25°C (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC
VUVR
VUVF
Device supply voltage
Undervoltage restart
Undervoltage shutdown
2.5
5.5
V
V
V
VCC rising
2.3
VCC falling
2.0
Undervoltage shutdown
hysteresis
VUV(HYS)
0.1
0.9
V
SCLK/SIN = 10 MHz, MPSM_EN =
1bit, Matrix PSM enable, internal
GCLK off, GSn = 0000h, BC = 2h,
CCR/G/B = 63h, PS_EN= 1h,
mA
VOUTn = floating, RIREF = 7.8 kΩ(In
intelligent power save mode)
SCLK/SIN = 10 MHz, Standby
enable, internal GCLK off, GSn =
0000h, BC = 2h, CCR/G/B = 63h,
PS_EN= 1h, VOUTn = floating,
RIREF = 7.8 kΩ(In intelligent power
save mode)
0.9
3.6
mA
mA
SCLK/SIN = 10 MHz, PSP_MOD =
1bit, internal GCLK=50MHz, GSn =
0000h, BC = 2h, CCR/G/B = 63h,
PS_EN= 1h, VOUTn = floating,
RIREF = 7.8 kΩ(In power save
mode)
ICC
Device supply current
SCLK = 10 MHz, internal GCLK = 50
MHz, GSn = 1FFFh, BC = 2h,
CCR/G/B = 63h,VOUTn = floating,
RIREF = 7.8 kΩ, ICH = 2 mA
3.6
4.9
mA
mA
SCLK = 10 MHz, internal GCLK =
100 MHz, GSn = 1FFFh, BC = 2h,
CCR/G/B = 63h, VOUTn = floating,
RIREF = 7.8 kΩ, ICH = 2 mA
VR/G/B
VIH
LED supply voltage
2.5
5.5
V
V
High level input voltage (SCLK,
SIN)
0.7 × VCC
Low level input voltage (SCLK,
SIN)
VIL
0.3 × VCC
V
VOH
High level output voltage (SOUT)
VCC-0.4
-1
VCC
0.4
1
V
V
IOH = –2 mA at SOUT
VOL
Low level output voltage (SOUT) IOL = 2 mA at SOUT
ILOGIC
Logic pin current (SCLK, SIN)
SCLK/SIN = VCC or GND
VCC = 2.8 V, TA= 25°C
uA
Scan switches' on-state
resistance (LINE0 to LINE15)
RDS(ON)
190
0.8
mΩ
SCLK/SIN = GND, internal GCLK=
0MHz, GSn = 0000h, BC = 2h,
CCR/G/B = 63h, VOUTn = floating,
RIREF = 7.8 kΩ
VIREF
Reference voltage
V
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7.5 Electrical Characteristics (continued)
At VCC = VR = 2.8 V, VG/B = 3.8 V and TA = –40°C to +85°C; Typical values are at TA = 25°C (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VLEDR/G/B ≥2.8 V, all channel
outputs on, output current at 1 mA
0.25
V
VLEDR/G/B ≥2.8 V, all channel
outputs on, output current at 5 mA
0.26
0.3
V
V
VLEDR/G/B ≥2.8 V, all channel
outputs on, output current at 10 mA
Channel knee voltage (R0-R15 /
G0-G15 / B0-B15)
VKNEE
VLEDR/G/B ≥2.8 V, IMAX = 1b, all
channel outputs on, output current at
15 mA
0.37
V
VLEDR/G/B ≥2.8 V, IMAX=1b, all
channel outputs on, output current at
20 mA
0.41
1
V
Channel leakage current (R0-
R15 / G0-G15 / B0-B15)
ICH(LKG)
Channel voltage at 0 V
uA
All CHn = on, BC = 00h, CC = 31h,
VOUTn = (VLED-1)V, RIREF = 19.05
kΩ(ICH = 0.2-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
±1
±0.5
±0.5
±0.5
±0.5
±2.5
±1.5
±1.5
±2
%
%
%
%
%
All CHn = on, BC = 00h, CC = 7Dh,
VOUTn = (VLED-1)V, RIREF = 19.05
kΩ(ICH = 0.5-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
All CHn = on, BC = 00h, CC = FBh,
VOUTn = (VLED-1)V, RIREF = 19.05
kΩ(ICH = 1-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
Constant-current channel to
channel deviation (R0-R15 / G0-
G15 / B0-B15)(1)
ΔIERR(CC)
All CHn = on, BC = 2h, CC = FBh,
VOUTn = (VLED-1)V, RIREF = 7.8
kΩ(ICH = 5-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
All CHn = on, BC = 6h, CC = A7h,
VOUTn = (VLED-1)V, RIREF = 7.8
kΩ(ICH = 10-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
±2
All CHn = on, BC = 7h, CC = FBh,
IMAX=1b, VOUTn = (VLED-1)V,
RIREF = 6.8 kΩ(ICH = 20-mA target),
TA = 25°C, includes the VIREF
tolerance, at same color grouped
outputs of R0-R15 / G0-G15 / B0-
B15
±0.5
±2.5
%
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7.5 Electrical Characteristics (continued)
At VCC = VR = 2.8 V, VG/B = 3.8 V and TA = –40°C to +85°C; Typical values are at TA = 25°C (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
All CHn = on, BC = 00h, CC = 31h,
VOUTn = (VLED-1)V, RIREF = 19.05
kΩ(ICH = 0.2-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
±1
±2.5
%
All CHn = on, BC = 00h, CC = 7Dh,
VOUTn = (VLED-1)V, RIREF = 19.05
kΩ(ICH = 0.5-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
±0.5
±0.5
±0.5
±0.5
±1.5
%
%
%
%
All CHn = on, BC = 00h, CC = FBh,
VOUTn = (VLED-1)V, RIREF = 19.05
kΩ(ICH = 1-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
±1
Constant-current device to
device deviation (R0-R15 / G0-
G15 / B0-B15)(2)
ΔIERR(DD)
All CHn = on, BC = 2h, CC = FBh,
VOUTn = (VLED-1)V, RIREF = 7.8
kΩ(ICH = 5-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
±1.5
All CHn = on, BC = 6h, CC = A7h,
VOUTn = (VLED-1)V, RIREF = 7.8
kΩ(ICH = 10-mA target), TA = 25°C,
includes the VIREF tolerance, at
same color grouped outputs of R0-
R15 / G0-G15 / B0-B15
±2
All CHn = on, BC = 7h, CC = FBh,
IMAX=1b, VOUTn = (VLED-1)V,
RIREF = 6.8 kΩ(ICH = 20-mA target),
TA = 25°C, includes the VIREF
tolerance, at same color grouped
outputs of R0-R15 / G0-G15 / B0-
B15
±0.5
±2
%
VLED = 2.5 to 5.5 V, All CHn = on,
VOUTn = (VLED-1)V, at same color
grouped outputs of R0-R15 / G0-
G15 / B0-B15
Line regulation (R0-R15 / G0-
G15 / B0-B15)(3)
±1
±1
%/V
%/V
ΔIREG(LINE)
VOUTn = (VLED-1)V to (VLED-3)V,
VR=VG/B=VLED = 3.8 V, All CHn =
on, at same color grouped outputs of
R0-R15 / G0-G15 / B0-B15
Load regulation (R0-R15 / G0-
G15 / B0-B15)(4)
ΔIREG(LOAD)
TTSD
THYS
Thermal shutdown threshold
Thermal shutdown hysteresis
170
15
°C
°C
(1) The deviation of each output in same color group (OUTR0-15 or OUTG0-15 or OUTB0-15) from the average of same color group
+
:J
: ;
¿ % = N
F 1O × 100
+
:0 + +:1 + ® + +:14 + +:15
16
constant current. The deviation is calculated by the formula. (X = R or G or B, n = 0-15)
spacer
(2) The deviation of the average of constant-current in each color group from the ideal constant-current value. (X = R or G or B) :
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+
:0
+ +:1 + ® + +:14 + +:15
16
F Ideal Output Current
: ;
¿ % =
N
O
× 100
Ideal Output Current
Ideal current is calculated by the following equation:
8
1 + %%_4(KN %%_) KN %%_$)
+4'(
+
=
× )#+0
×
+&'#._4(KN ) KN $)
($%)
4+4'(
256
spacer
(3) Line regulation is calculated by the following equation. (X = R or G or B, n = 0-15):
I
at V
LED
= 5.5 V − I at V = 2.5 V
Xn LED
Xn
100
5.5 V − 2.5 V
∆ %V =
×
I
at V = 2.5 V
LED
Xn
(4) Load regulation is calculated by the following equation. (X = R or G or B, n = 0-15):
I
at V = 1 V − I at V = 3 V
Xn Xn Xn
Xn
100
3 V − 1 V
∆ %V =
×
I
at V = 3 V
Xn
Xn
spacer
7.6 Timing Requirements
At VCC = VR = 2.8 V, VG/B = 3.8 V and TA = –40°C to +85°C; Typical values are at TA = 25°C (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
ns
fSCLK
tw(H1)
tw(L1)
tsu(0)
tsu(1)
th(0)
Clock frequency (SCLK)
High level pulse duration (SCLK)
Low level pulse duration (SCLK)
Setup time
25
18
18
10
10
2
ns
ns
SIN to SCLK↑
Setup time
ns
SIN to SCLK↓
Hold time
ns
SCLK↑to SIN↑↓
SCLK↓to SIN↑↓
th(1)
Hold time
2
ns
7.7 Switching Characteristics
At VCC = VR = 2.8 V, VG/B = 3.8 V and TA = –40°C to +85°C; Typical values are at TA = 25°C (unless otherwise specified)
PARAMETER
Rise time (SOUT)
Fall time (SOUT)
TEST CONDITIONS
VCC = 3.3 V, CSOUT = 30 pF
VCC = 3.3 V, CSOUT = 30 pF
MIN
TYP
MAX
UNIT
tr
tf
2
10
ns
2
10
ns
SCLK↑to SOUT↑↓, full
temperature, CSOUT = 30 pF
tpd(0)
tpd(1)
Propagation delay
Propagation delay
3.5
3.5
14.2
14.2
ns
ns
SCLK↓to SOUT↑↓, full
temperature, CSOUT = 30 pF
tw(L1)
tw(H1)
SCLK(1)
50%
50%
tsu(0)
th(0)
tsu(1)
th(1)
SIN(1)
tpd(0)
tpd(1)
90%
SOUT
50%
10%
tf
tr
(1). Input pulse rise and fall time is 2 ns typically.
图7-1. Timing and Switching Diagram (Dual Edge)
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7.8 Typical Characteristics
0.016
0.014
0.012
0.01
0.016
0.014
0.012
0.01
0.2 mA
1 mA
5 mA
10 mA
15 mA
0.2 mA
1 mA
5mA
10 mA
15 mA
0.008
0.006
0.004
0.002
0
0.008
0.006
0.004
0.002
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
VLED - VCH (V)
VLED - VCH (V)
Vcc = 2.8 V
图7-2. Channel Current vs (VLED-Vchannel) Voltage
11
Vcc = 5. 5 V
图7-3. Channel Current vs (VLED-Vchannel) Voltage
1
0.75
0.5
-40oC
25oC
85oC
10
9
8
7
6
5
4
3
2
1
0
0.25
-40oC Min
25oC Min
0
-0.25
-0.5
85oC Min
-40oC Max
25oC Max
85oC Max
-0.75
-1
-1.25
0
2
4
6
8
10
12
14
16
18
20
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
Output Current (mA)
VLED - VCH (V)
图7-5. Channel-to-Channel Accuracy vs Output Current
图7-4. Channel Current vs (VLED-Vchannel) Voltage
0.016
0.012
0.011
0.01
0.2 mA, BC = 00h
1 mA, BC = 02h
5 mA, BC = 02h
10 mA, BC = 06h
15 mA, BC = 06h
0.014
0.012
0.01
0.009
0.008
0.007
0.006
0.005
0.004
0.003
0.008
0.006
0.004
0.002
0
0
30
60
90
120 150 180 210 240 270
40
60
80
100
120
140
160
180
Color Control Code (Decimal)
GCLK Frequency (MHz)
图7-6. Color Control Code vs Output Current
图7-7. Icc Current vs GCLK Frequency
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7.8 Typical Characteristics (continued)
4.68
4.66
4.64
4.62
4.6
4.58
4.56
4.54
4.52
2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
Vcc Voltage (V)
4
4.2 4.4 4.6
GCLK = 80 MHz
图7-8. Icc Current vs Vcc Voltage
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8 Detailed Description
8.1 Overview
The TLC6984 is a highly-integrated, common cathode LED-display driver with 48 constant current sources and
16 scanning FETs. A single TLC6984 is capable of driving 16 × 16 RGB LED pixels while stacking four
TLC6984s can drive 64 × 64 RGB LED pixels. To achieve low-power consumption, the device supports
separated power supplies for the red, green, and blue LEDs by its common cathode structure. Furthermore, the
operation power of the TLC6984 is significantly reduced by ultra-low operation voltage range (VCC down to 2.5
V) and ultra-low operation current (ICC down to 3.6 mA).
The TLC6984 supports per channel current from 0.2 mA to 20 mA, with typical 0.5% channel-to-channel current
deviation and typical 0.5% device-to-device current deviation. The DC current value of all 48 channels is set by
an external IREF resistor and can be adjusted by the 8-step global brightness control (BC) and the 256-step per-
color group brightness control (CC_R/CC_G/CC_B).
The TLC6984 implements a high-speed, dual-edge transmission interface to support high device count daisy-
chained and high-refresh rate while minimizing electrical-magnetic interference (EMI). The TLC6984 supports up
to 25-MHz SCLK (external) and up to 160-MHz GCLK (internal). Meanwhile, the device integrates enhanced
circuits and intelligent algorithms to solve the various display challenges in Narrow Pixel Pitch (NPP) LED
display applications and mini and micro-LED products: dim at the fist scan line, upper and downside ghosting,
non-uniformity in low grayscale, coupling, caterpillar caused by open or short LEDs, which make the TLC6984 a
perfect choice in such applications.
The TLC6984 also implements LED open, weak-short, short detections and removals during operations and can
also report this information out to the accompanying digital processor.
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8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Independent and Stackable Mode
The TLC6984 can operate in two different modes: independent or stackable. In independent mode, a single
TLC6984 can drive a 16 × 16 RGB LED matrix, while in stackable mode, up to four TLC6984s can be stacked
together, which means the line switches of one device can be shared to the others. Stacking three TLC6984s
can drive a 48 × 48 RGB LED matrix while stacking four TLC6984s can drive a 64 × 64 RGB matrix. The mode
can be configured by the MOD_SIZE (see FC2 for more details).
8.3.1.1 Independent Mode
图 8-1 shows an implementation of a 16 × 32 RGB LED matrix using two TLC6984s in independent mode. Each
device is responsible for its own 16 ×16 RGB LED matrix which means that all the data for section A is stored in
device 1 and the data for section B is stored in device 2.
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图8-1. Two Devices in Independent Mode
The unused line must be assigned to the last several lines of the device. For example, if there are only 14
scanning lines, then the two unused lines must be assigned to 1_LS14 and 1_LS15.
8.3.1.2 Stackable Mode
表8-1 shows operating the TLC6984 in stackable mode.
表8-1. Stackable Mode
Mode
Mode1
Mode2
Mode3
Mode4
Mode5
Mode6
Mode7
Mode8
Matrix Size
16 × 32
32 × 32
48 × 48
48 × 48
48 × 64
48 × 64
64 × 64
64 × 64
Register Value
000b
Scan Sequence
D1, D2 independent
D1->D2
001b
010b
D1->D2->D3
011b
D1->D3->D2
100b
D1->D2->D3
101b
D1->D3->D2
110b
D1->D2->D3->D4
D1->D4->D2->D3
111b
图 8-2 shows that device 2 must be rotated 180o relative to device 1. This action allows the position of line
switches to be near the center column of the LED matrix for better routing. For device 1, the lines are connected
sequentially (line switch 0 connected to scan line 1). However on device 2, it is connected in reverse order, with
the 16th scan line is connected to line switch 15 and the 32th scan line is connected to line switch 0.
图 8-2 shows the connection between two TLC6984 devices in stackable mode driving a 32 × 32 RGB LED
pixels. The MOD_SIZE must be configured to 001b. Device1 supplies 16 line switches for the first 16 scan line,
and device 2 supplies 16 line switches for scan line 17-32. The data for matrix sections A and C are stored in
device 1, while matrix sections B and D data are stored in device 2.
To make sure the scanning sequence is still from 1st line to 32nd line, the scan line switching order of the second
device must be reversed, This configuration can be completed by the SCAN_REV (see FC4 for more details).
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Physical Line0
A
B
1_LS0
Device1
1_LS15
Physical Line15
Physical Line16
C
D
2_LS15
Device2
2_LS0
Physical Line31
图8-2. Mode2 Diagram
图8-3. Mode3 and Mode4 Diagram
图8-4. Mode5 and Mode6 Diagram
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图8-5. Mode7 and Mode8 Diagram
When two TLC6984 devices are used in stackable mode, if there are unused line switches, these unused line
switches must be the last line switches of the first or the second device. For example, if there are only 30
scanning lines, and if,
SCAN_REV = '0'b, the unused line switches can be either of below,
• 1_LS14, 1_LS15
• 2_LS14, 2_LS15
SCAN_REV = '1'b, the unused line switches can be either of below,
• 1_LS14, 1_LS15
• 2_LS1, 2_LS0
If the unused line switches are 1_LS14, 1_LS15, the FC6-FC13 registers must be configured. If the unused line
switches are 2_LS14, 2_LS15 when SCAN_REV = '0' or 2_LS1, 2_LS0 when SCAN_REV = '1', there is no need
to configure FC6-FC13 registers.
8.3.2 Current Setting
8.3.2.1 Brightness Control (BC) Function
The TLC6984 device is able to adjust the output current of all constant-current outputs simultaneously. This
function is called global brightness control (BC). The global BC for all outputs is programmed with a 3-bit
register, thus all output currents can be adjusted in 8 steps for a given current-programming resistor, RIREF
.
When the 3-bit BC register changes, the gain of output current, GAINBC changes as 表8-2 below.
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表8-2. Current Gain Versus BC Code
BC Register (BC)
000b
Current Gain (GAINBC)
24.17
30.57
001b
010b
49.49
011b (default)
100b
86.61
103.94
129.92
148.48
173.23
101b
110b
111b
The maximum output current per channel, IOUTSET, is determined by resistor RIREF, and the GAINBC. The voltage
on IREF is typically 0.8 V. Use 方程式1 to calculate RIREF. For noise immunity purpose, suggest RIREF < 40 kΩ.
8
+4'((8)
8
+4'((8)
4+4'( (G×) =
=
× )#+0($%)
++4'( (I#)
+1765'6 (I#)
(1)
8.3.2.2 Color Brightness Control (CC) Function
The TLC6984 device is able to adjust the output current of each of the three color groups R0-R15, G0-G15, and
B0-B15 separately. This function is called color brightness control (CC). For each color, it has 8-bit data register,
CC_R, CC_G, or CC_B. Thus, all color group output currents can be adjusted in 256 steps from 0% to 100% of
the maximum output current, IOUTSET. Use 方程式2 to calculate the output current of each color, IOUT_R (or G or B)
.
1 + %%_4(KN %%_) KN %%_$)
+
= +1765'6 ×
176_4(KN ) KN $)
256
(2)
Table 表8-3 shows the CC data versus the constant-current against IOUTSET
.
表8-3. CC Data vs Current Ratio
CC Register (CC_R or CC_G or
Ratio of IOUTSET
CC_B)
0000 0000b
0000 0001b
...
1/256
2/256
...
0.39%
0.78%
...
0111 1111b (default)
...
128/256
...
50%
...
1111 1110b
1111 1111b
255/256
256/256
99.61%
100%
8.3.2.3 Choosing BC/CC for a Different Application
BC is mainly used for global brightness adjustment to adapt to ambient brightness, such as between day and
night, indoor and outdoor.
• Suggested BC is 3h or 4h, which is in the middle of the range, allowing flexible changes in brightness up and
down.
• If the current of one color group (usually R LEDs) is close to the output maximum current (10 mA or 20 mA),
to prevent the constant output current from exceeding the upper limit in case a larger BC code is input
accidentally, choose the maximum BC value, 7h.
• If the current of one color group (usually B LEDs) is close to the output minimum current (0.2 mA), to prevent
the constant output current from exceeding the lower limit in case a lower BC code is input accidentally,
choose the minimum BC code, 0h.
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CC can be used to fine tune the brightness in 256 steps. This action is suitable for white balance adjustment
between RGB color group. To get a pure white color, the general requirement for the luminous intensity ratio of
R, G, B LED is 5:3:2. Depending on the characteristics of the LED (Electro-Optical conversion efficiency), the
current ratio of R, G, B LED is much different from this ratio. Usually, the Red LED needs the largest current.
Choose 255d (the maximum value) CC code for the color group that needs the largest initial current, then
choose proper CC code for the other two color groups according to the current ratio requirement of the LED
used.
8.3.3 Frequency Multiplier
The TLC6984 has an internal frequency multiplier to generate the GCLK by SCLK. The GCLK frequency can be
configured by FREQ_MOD (See FC0 for more details) and FREQ_MUL (see FC0 for more details ) from 40 MHz
to 160 MHz. As 图 8-6 shows, if the GCLK frequency is not higher than 80 MHz, the GCLK_MOD is set to 0 to
disable the bypass switch (enable the ½ divider), while the GCLK frequency is higher than 80 MHz, the
GCLK_MOD is set to 1 to enable the bypass switch (disable the ½ divider).
GCLK_MUL
GCLK_MOD
SCLK
GCLK
1/2
图8-6. Frequency Multiplier Block Diagram
8.3.4 Line Transitioning Sequence
The TLC6984 defines a timing sequence of scan line transition, shown as 图 8-7. T_SW is the total transitioning
time. T_SW is broken up into four intervals: T0 is the time interval between the end of PWM time in current
segment and the beginning of channel pre-discharge, T1 is the time interval between the beginning of the
channel pre-discharge and the beginning of current line OFF, T2 is the time interval that the beginning of current
line OFF and the beginning of next line ON, T3 is the time interval of the beginning of next line ON and the
beginning of PWM time in next segment.
图8-7. Line Transitioning Sequence
The line switch time T_SW equals to T0 + T1 + T2 + T3. T_SW can be configured by the LINE_SWT (see FC1
register bit 40-37 in FC1).
表 8-4 is the relation between LINE_SWT bits and the line switch time (GCLK numbers) with different internal
GCLK frequency.
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表8-4. Line Switch Time
LINE_SW
T
GCLK
Numbers
T_SW (us, 40-
MHZ GCLK)
T_SW (us, 60-MHZ T_SW (us, 100-MHZ T_SW (us, 120-MHZ
T_SW (us, 160-
MHZ GCLK)
GCLK)
0.7515
1.002
1.503
2.004
2.505
3.006
3.507
4.008
4.509
5.01
GCLK)
0.45
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
GCLK)
0.3735
0.498
0.747
0.996
1.245
1.494
1.743
1.992
2.241
2.49
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
45
1.125
1.5
0.2835
0.378
0.567
0.756
0.945
1.134
1.323
1.512
1.701
1.89
60
90
2.25
3
120
150
180
210
240
270
300
330
360
390
420
450
480
3.75
4.5
5.25
6
6.75
7.5
8.25
9
5.511
6.012
6.513
7.014
7.515
8.016
3.3
3.6
3.9
4.2
4.5
4.8
2.739
2.988
3.237
3.486
3.735
3.984
2.079
2.268
2.457
2.646
2.835
3.024
9.75
10.5
11.25
12
8.3.5 Protections and Diagnostics
8.3.5.1 Thermal Shutdown Protection
The thermal shutdown (TSD) function turns off all IC constant-current outputs when the junction temperature (TJ)
exceeds 170°C (typical). The function resumes normal operation when TJ falls below 155°C (typical).
8.3.5.2 IREF Resistor Short Protection
The IREF resistor short protection (ISP) function prevents unwanted large currents from flowing through the
constant-current output when the IREF resistor is shorted accidently. The TLC6984 device turns off all output
channels when the IREF pin voltage is lower than 0.19 V (typical). When the IREF pin voltage goes higher than
0.325 V (typical), the TLC6984 device resumes normal operation.
8.3.5.3 LED Open Load Detection and Removal
8.3.5.3.1 LED Open Detection
The LED open detection (LOD) function detects faults caused by an open circuit in any LED, or a short from
OUTn to VLED with low impedance. This function was realized by comparing the OUTn voltage to the LOD
detection threshold voltage level set by LODVTH_R/LODVTH_G/LODVTH_B (See FC3 for more details). If the
OUTn voltage is higher than the programmed voltage, the corresponding output LOD bit is set to 1 to indicate an
open LED. Otherwise, the output of that LOD bit is 0. LOD data output by the detection circuit are valid only
during the OUTn turning on period.
图8-8 shows the equivalent circuit of LED open detection.
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图8-8. LED Open Detection Circuit
The LED open detection function records the position of the open LED, which contains the scan line number and
relevant channel number. The scan line order is stored LOD_LINE_WARN register (see FC16, FC17 for more
details), and the channel number is latched into the internal 48-bit LOD data register (see FC20 for more details)
at the end of each segment. 图8-9 shows the bit arrangement of the LOD data register.
图8-9. Bit Arrangement in LOD Data Register
8.3.5.3.2 Read LED Open Information
The LOD readback function must be enabled before read LED open information. This function is enabled by
LOD_LSD_RB (see FC3 for more details).
图 8-10 shows the steps to read LED open information. Wait at least one sub-period time between Step2 and
Step3 command.
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图8-10. Steps to Read LED Open Information
8.3.5.3.3 LED Open Caterpillar Removal
图 8-11 shows the caterpillar issue caused by open LED. Suppose the LED0-1 is an open LED. When line0 is
chosen and the OUT1 is turned on, the OUT1 voltage is forced to approach to VLED because of the broken path
of the current source. However, the voltage of the un-chosen lines are below the Vclamp which is much lower
than VLED, causing all LEDs which connect to the channel OUT1, light unwanted.
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图8-11. LED Open Caterpillar
The TLC6984 implements circuits that can eliminate the caterpillar issue caused by open LEDs. The LED open
caterpillar removal function is configured by LOD_RM_EN (see FC0 for more details). When LOD_RM_EN is set
to 1b, the caterpillar removal function is enabled. The corresponding channel OUTn is turned off when scanning
to line with open LED, The caterpillar issue is eliminated until device resets or LOD_RM_EN is set to 0b.
The internal caterpillar elimination circuit can handle a maximum of three lines that have open LEDs fault
condition. If there are open LEDs located in three or fewer lines, the TLC6984 is able to handle the open LEDs
all in these lines. If there are open LEDs in more than three lines, the caterpillar issue is solved for the lines
where the first three open LEDs were detected, but the open LEDs in the fourth and subsequent lines still cause
the caterpillar issue.
8.3.5.4 LED Short and Weak Short Circuitry Detection and Removal
8.3.5.4.1 LED Short and Weak Short Detection
The LED short detection (LSD) function detects faults caused by a short circuit in any LED. This function was
realized by comparing the OUTn voltage to the LSD threshold voltage. If the OUTn voltage is lower than the
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threshold voltage, the corresponding output LSD bit is set to 1 to indicate an short LED, otherwise, the output of
that LSD bit is 0. LSD data output by the detection circuit are valid only during the OUTn turning on period.
LSD weak short can be detected by adjusting threshold voltage, which level is set by LSDVTH_R/LSDVTH_G/
LSDVTH_B (See FC3 for more details).
图8-12 shows the equivalent circuit of LED short detection.
图8-12. LED Short Detection Circuit
The LED short detection function records the position of the short LED, which contains the scan line order and
relevant channel number. The scan line order is stored LSD_LINE_WARN register (see FC18 and FC19 for
more details), and the channel number is latched into the internal 48-bit LSD data register (see FC21 for more
details) at the end of each segment. 图8-13 shows the bit arrangement of the LSD data register.
图8-13. Bit Arrangement in the LSD Data Register
8.3.5.4.2 Read LED Short Information
The LSD readback function must be enabled before reading LED Short information. This function is enabled by
LOD_LSD_RB (see FC3 for more details).
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图 8-14 shows the steps to read LED Short information. Wait at least one sub-period time between Step2 and
Step3 command.
图8-14. Steps to Read LED Short Information
8.3.5.4.3 LSD Caterpillar Removal
图 8-15 shows the LSD caterpillar issue caused by short LED. Suppose the LED0-1 is a short LED. When it
scans to the line1 and the OUT1 is turned off, the OUT1 voltage is the same with scan line0 voltage because of
the short path of the LED0-1. At this time, there is a current path from the line0 to the GND through the LED1-1
and SW1-1, which causes LED1-1 light unwanted.
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图8-15. LED Short Caterpillar
The TLC6984 device implements internal circuits that can eliminate the caterpillar issue by short LEDs. As is
shown in 图 8-15, the LED short caterpillar is caused by the voltage of the Vclamp on the line. So it can be
solved by adjusting the LSD_RM_EN (see FC3 for more details) to let the voltage drop of the LED1-1 be smaller
than LED forward voltage.
8.4 Device Functional Modes
The device functional modes are shown in 图8-16.
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图8-16. Functional Modes
• Initialization: the device enters into Initialization when Vcc goes down to UVLO voltage. In this mode, all the
registers are reset. Entry can also be from any state.
• Normal: the device enters the normal mode when Vcc is higher than UVLO threshold. The display process is
shown as below in normal mode.
• Power saving: the device automatically enters and gets out from the power save mode when it detects the
condition PSin and PSout. In this mode, all channels turn off. PSin: after the device detects that the display
data of the next frame all equal to zero, it enters to power save mode when the VSYNC comes. PSout: after
the device detects that there is non-zero display data of the next frame, it gets out from power save mode
immediately.
• IREF Resistor Short Protection: the device automatically enters and gets out from the IREF resistor short
protection mode when it detects the condition ISPin and ISPout. In this mode, all channels turn off. ISPin: the
device detects that the reference voltage is smaller than 0.195 V ISPout: the device detects that the
reference voltage is larger than 0.325 V.
• Thermal Shutdown: the device automatically enters and gets out from the thermal shutdown mode when it
detects the condition TSDin and TSDout. In this mode, all channels turn off. TSDin: the device detects that
the junction temperature exceeds 170° C TSDout: the device detects that the junction temperature is below
155° C.
8.5 Continuous Clock Series Interface
The continuous clock series interface (CCSI) provides access to the programmable functions and registers,
SRAM data of the device. The interface contains two input digital pins. the pins are the serial data input (SIN)
and serial clock (SCLK). Moreover, there is an another wire called serial data output (SOUT) as the output digital
signal of the device. The SIN is set to HIGH when device is in idle status and the SCLK must be existent and
continuous all the time considering as the clock source of internal Frequency Multiplier, the SOUT is used to
transmit the data or read the data of internal registers.
This protocol can support up to 32 devices cascaded in a data chain. The devices receive the chip index
command after power up. The chip index command configures addresses of the devices from 0x00 up to 0x1F
according to the sequence that receives the command. Then the controller can communicate with all the devices
through the broadcast way or particular device through non-broadcast way.
The broadcast is mainly used to transmit function control commands. All the devices in a data chain receive the
same data in this way. The non-broadcast is mainly used to transmit function control commands or display data,
and each device receives its own data in this way. These two ways are distinguished by the command
identification.
Dual-edge is designed to support more devices cascaded in a data chain.
8.5.1 Data Validity
The data on DIN wire must be stable at rising and falling edges of the SCLK in dual-edge transmission.
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8.5.2 CCSI Frame Format
图8-17 defines the format of the command and data transimission. There are four states in one frame.
• IDLE: SCLK is always existent and continuous, and DIN is always HIGH.
• START: DIN changes from HIGH to LOW after the IDLE states.
• DATA:
– Head_bytes: command identifier that contains one 16-bit data and one check bit. It can be WRITE
COMMAND ID or READ COMMAND ID (see Register Maps for more details).
– Data_bytes_N: The Nth data-bytes, contains 3 × 17-bit data, each 17-bit data contains one 16-bit data
and one check bit. N is the number of devices cascaded in a data chain.
• END: the device recognizes continuous 18-bit HIGH on DIN, then returns to IDLE state.
• CHECK BIT: the check bit (17th bit) value is the NOT of 16th bit value, to avoid continuous 18-bit HIGH (to
distinguish with END).
SCLK
SIN
Y...
Head_bytes
Data_bytes_N
Data_bytes_1
End_bytes
IDLE START
DATA
END
IDLE
图8-17. CCSI Frame
The IDLE state is not the necessary, that means the START state of next frame can connect to the END state of
current frame.
8.5.3 Write Command
Take m devices cascaded in a data chain for example.
8.5.3.1 Chip Index Write Command
The chip index is used to set the identification of the device cascaded in a data chain. When the first device
receives the chip index command Head_bytes1, it sets the current address to 00h and meanwhile change the
chip index command Head_bytes2, then sends to the next device. When the device receives the Head_bytes2, it
sets the address to 01h and meanwhile changes the chip index command Head_bytes3, then sends to the next
device, likewise, all the cascaded devices get their unique identifications.
SOUT
SCLK
Controller
SIN
Device_1
Device_...
Device_m
ST Head_bytes1
END
ST Head_bytes...
END
ST Head_bytesm
END
图8-18. Chip Index Write Command
8.5.3.2 VSYNC Write Command
The VSYNC is used to sync the display of each frame for the devices in a cascaded chain. The VSYNC is a
write-only command. The devices receive VSYNC command one time from the controller in each frame, and the
VSYNC command must be active for all devices at the same time.
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Because some devices receive the command earlier in the data chain, they must wait until the last device
receives the command, then all the devices are active at that time. To realize such function, each device must
know its delay time from receiving VSYNC command to enabling VSYNC. The device uses some register bits to
restore the device number in a data chain. This number minuses the device identification, and the result is the
delay time of the device.
Because the sync function has been done by the device, the controller must only send the VSYNC command to
the first device in a data chain.
SOUT
SCLK
Controller
SIN
Device_1
Device_...
Device_m
ST Head_bytes
END
ST Head_bytes
END
ST Head_bytes
END
ST Head_bytes
END
图8-19. VSYNC Write Command
8.5.3.3 MPSM Write Command
The MPSM command is used to control the intelligent power save mode of devices in the same matrix. The
device detects all zero data in a stackable module and receives MPSM command in current frame, then when
VSYNC command comes, all devices in the same matrix turn off. After the device detects that there is non-zero
display data of the next frame, it gets out from intelligent power save mode until MSPM command comes in
current frame.
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图8-20. Design Procedure for MPSM Command
8.5.3.4 Standby Clear and Enable Command
Standby clear command and standby enable command are used to control intelligent power save mode of
devices in the same daisy chain. When the device receives standby enable command, it enters to intelligent
power save mode right away and does not have to wait for other devices in a module or daisy chain. After the
device receives standby enable command, it exits from intelligent power save mode immediately and does not
wait for other devices in a module or daisy chain.
8.5.3.5 Soft_Reset Command
The Soft_Reset Command is used to reset all the function registers to the default value, except for SRAM data.
The format of this command is the same with VSYNC shown as VYSNC Write Command. The difference is the
headbytes.
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8.5.3.6 Data Write Command
The device can receive the function control with broadcast and non-broadcast way, which depends on the
configuration of the devices. If the cascaded devices have the same configuration, broadcast is used, if the
cascaded devices have the different configurations, non-broadcast is used. The MSB is always transmitted first
and the LSB transmitted last. For 48-bits RGB data, the Blue data must be transmitted first, then the Green, and
last the Red data.
For broadcast, the devices receive the same data. When devices recognize the broadcast command, they copy
the data to the internal registers. Generally, broadcast is used for write FC0-FC13 command, LOD/LSD.
图8-21. Data Write Command with Broadcast
图8-22 shows the time diagram of the data write command with broadcast.
SCLK
1
2
3
15 16 17 18 19 20 32 33 34 35 36 37 48 49 50 51 52 53 66 67 68 69 70 71 85 86
SIN
HB15 HB14
HB0
CHECK
B15 B14
CHECK
G15 G14
B0
CHECK
G0
R15 R14
CHECK
R0
SOUT
HB15 HB14
HB0
CHECK
B15 B14
CHECK
G15 G14
B0
CHECK
G0
R15 R14
CHECK
R0
图8-22. Data Write Command with Broadcast (Timing Diagram)
For non-broadcast, the devices receive the different data, the controller prepares the data as the figure shows.
One pixel data is written to the corresponding device in each command. When the first device receives the END,
it cuts off the last 51-bit (3 × 17 bit) data before the END, and the left are shifted out from SDO to the second
device. Similarly, when the second device receives the END bytes from the former device, it cuts off the last 51-
bit (3×17 bit) data before the END, and the left are shifted out to the next device. Generally, non-broadcast is
used for write SRAM command (WRTGS), Details for how to write a frame data into memory bank can be found
in Write a Frame Data into Memory Book.
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图8-23. Data Write Command with Non-Broadcast
图8-24 shows the time diagram of the data write command with non-broadcast.
SCLK
1
2
3
15 16 17 18 19 20 32 33 34 35 36 37 48 49 50 51 52 53 66 67 68 69 70 71 83 84 85 86 87 88 100 101 102 103 104 105 117 118 119 120 121 122 123 124 137
SIN
HB15 HB14
HB0
CHECK 2B15 2B14
2B0 CHECK 2G15 2G14
2G0
CHECK 2R15 2R14
2R0 CHECK 1B15 1B14
1B0 CHECK 1G15 1G14
1G0
CHECK 1R15 1R14
1R0 CHECK
SOUT
HB15 HB14
HB0
CHECK 2B15 2B14
2B0 CHECK 2G15 2G14
2G0
CHECK 2R15 2R14
2R0 CHECK
图8-24. Data Write Command with Non-Broadcast (Timing Diagram)
8.5.4 Read Command
The controller sends the read command. When the first device receives this command, it inserts its 48-bit data
before End_bytes, and meanwhile shifts out to the second device. When the second device receives this
command, it inserts its 48-bit data before End_bytes and meanwhile shifts out to the third device. The data of all
the device shifts out from the last device SOUT with this flow. It is always the MSB transmitted first and the LSB
transmitted last.
图8-25. Data Read Command
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8.6 PWM Grayscale Control
8.6.1 Grayscale Data Storage and Display
8.6.1.1 Memory Structure Overview
The TLC6984 implements a display memory unit to achieve high refresh rate and high contrast ratio in an LED
display products. The internal display memory unit is divided into two BANKs: BANK A and BANK B. During the
normal operation, one BANK is selected to display the data of current frame, another is used to restore the data
of next frame. The BANK switcher is controlled by the BANK_SEL bit, which is an internal flag register bit.
After power on, BANK_SEL is initialized to 0, and BANK A is selected to restore the data of next frame.
Meanwhile, the data in BANK B is read out for display. When one frame has elapsed, the controller sends the
vertical synchronization (VSYNC) command to start the next frame, the BANK_SEL bit value is toggled and the
selection of the two BANKs reverses. Repeat this operation until all the frame images are displayed.
With this method, the TLC6984 device can display the current frame image at a very high refresh rate. See 图
8-26 for more details about the BANK-selection exchange operation.
图8-26. Bank Selection Exchange Operation
8.6.1.2 Details of Memory Bank
Each memory BANK contains the frame-image grayscale data of all the 64 lines. Each line comprises 16 48-bit-
width memory units. Each memory unit contains the grayscale data of the corresponding R/G/B channels.
Depending on the number of scan lines set in SCAN_NUM (FC0 bit 21 to bit 16), the total number of memory
units that must be written in one BANK is: 48 × the number of scan lines. For example, if the number of scan
lines is set to 64, then 3072 (64 × 48 = 3072) memory units must be written during each frame period.
图8-27 shows the detailed memory structure of the TLC6984 device.
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图8-27. TLC6984 Memory-unit Structure
8.6.1.3 Write a Frame Data into Memory Bank
After power on, the TLC6984 internal flag BANK_SEL, and counters LINE_COUNT, CHANNEL_COUNT, are all
initialized to 0. Thus, the memory unit of channel R0/G0/B0, locating in line 0 of BANK A, is selected to restore
the data transimitted the first time after VSYNC command.
When the first WRTGS command is received, all the data in the common shift register is latched into the memory
unit of channel R0/G0/B0, locating in line 0 of BANK A. Then CHANNEL_COUNT increases by 1 and
LINE_COUNT stays the same. Thus, the memory unit of channel R1/G1/B1, locating in line 0 of BANK A, is
selected to restore the data transimitted the second time after VSYNC command.
When the second WRTGS command is received, all the data in the common shift register is latched into the
memory unit of channel R1/G1/B1, locating in line 0 of BANK A. Then CHANNEL_COUNT increases by 1 and
LINE_COUNT stays the same. Thus, the memory unit of channel R2/G2/B2, locating in line 0 of BANK A, is
selected to restore the data transimitted the third time after VSYNC command.
Repeat the grayscale-data-write operation until the 16th WRTGS command is received. Then
CHANNEL_COUNT is reset to 0 and LINE_COUNT increases by 1. Thus, the memory unit of channel
R0/G0/B0, locating in line 1 of BANK A, is selected to restore the data transimitted the 17th time after VSYNC
command.
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Repeat this operation for each line until the LINE_COUNT exceeds the number of scan lines set in the
SCAN_NUM (See FC0 register bit21-16 ) and all scan lines have been updated with new GS data, which means
one frame of GS data is restored into the memory BANK. Then the LINE_COUNT is reset to 0.
8.6.2 PWM Control for Display
To increase the refresh rate in time-multiplexing display system, an DS-PWM (Dynamic Spectrum- Pulse Width
Modulation) algorithm is proposed in this device. One frame is divided into many segments shown as below.
Note that one frame is divided into n sub-periods, n is set by SUBP_NUM (FC0 register bit24-22), and each sub-
period is divided into 32 segments for 32 scan lines. Each segment contains GS GCLKs time for grayscale data
display and T_SW GCLKs time for switching lines. GS is configured by the SEG_LENGTH (FC1 register bit9-0 in
表 8-8) , and T_SW is the line switch time, which is configured by the LINE_SWT (see FC1 register bit 40-37 in
表8-8).
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Frame (display period)
SP1
Sub-period
SP0
SPn-1
ꢀꢀ
ꢀꢀ
Segment
SP0_L0
SP0_L1
SP0_L31
SP1_L0
SP1_L1
SP1_L31
SPn-1_L0
SPn-1_L1
SPn-1_L31
ꢀ
ꢀ
ꢀ
Grayscale data display (GS × GCLK)
Line switch (T_SW × GCLK)
Note that, SP0: Sub-period 0, L0: Scan line 0
图8-28. DS-PWM Algorithm with 32 Scan Lines
The DS-PWM can not only increase the refresh rate meanwhile keep the same frame rate, but also decrease the
brightness loss in low grayscale, which can smoothly increase the sub-period number when the grayscale data
increases.
To achieve ultra-low luminance, the LED driver must have the ability to output a very short current pulse (1
GCLK time). However, because of the parasitic capacitor of the LEDs, such pulse can not turn on the LEDs. And
the larger GCLK frequency is, the harder to turn on LEDs.
The DS-PWM algorithm has a parameter called sub-period threshold, which is used to calculate when to change
sub-period number according to the giving grayscale data. Sub-period threshold defines the LED minimum turn-
on time, so as to conquer the current loss caused by LED parasitic capacitor. Sub-period threshold is configured
by the SUBP_TH_R/G/B (FC1 register bit24-10 in 表8-8).
With DS-PWM algorithm, the brightness has smoothly increased with the gradient grayscale data.
8.7 Register Maps
表8-5. Register Maps
WRITE COMMAND READ COMMAND
REGISTER NAME
TYPE
DESCRIPTION
ID
ID
FC0
FC1
R/ W
R/ W
R/ W
R/ W
R/ W
R/ W
R/ W
AA00h
AA01h
AA02h
AA03h
AA04h
AA0Eh
AA0Fh
AA60h
AA61h
AA62h
AA63h
AA64h
AA6Eh
AA6Fh
Common configuration
Common configuration
Common configuration
Common configuration
Common configuration
Locate the line for LOD
Locate the line for LSD
FC2
FC3
FC4
FC14
FC15
Read the lines' warning of LOD from 64th ~ 49th
line
FC16
FC17
FC18
R
R
R
AAA0h
AAA1h
AAA2h
Read the lines' warning of LOD from 48th~1st line
Read the lines' warning of LSD from 64th ~ 49th
line
FC19
FC20
R
R
AAA3h
AAA4h
Read the lines' warning of LSD from 48th~1st line
Read the channel's warning of LOD
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表8-5. Register Maps (continued)
WRITE COMMAND READ COMMAND
REGISTER NAME
TYPE
DESCRIPTION
ID
ID
FC21
Chip Index
VSYNC
R
R/ W
W
AAA5h
AA70h
Read the channel's warning of LSD
Read/Write chip index
AA10h
AAF0h
AA90h
AAB0h
AAB1h
AA80h
AA30h
Write VSYNC command
MPSM
W
Write matrix PSM command
SBY_CLR
SBY_EN
Soft_Reset
SRAM
W
Write standby clear command
Write standby enable command
Reset the all the registers expect the SRAM
Write or read the SRAM data
W
W
W
表8-6. Access Type Codes
Access Type
Code
Description
Read Type
R
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
8.7.1 FC0
FC0 is shown in 图8-29 and described in 表8-7.
图8-29. FC0 Register
47
46
45
44
43
42
41
25
9
40
39
38
22
6
37
36
20
4
35
34
33
17
1
32
16
0
LSD_R RESERVED
M_EN
GRP_DLY_B
GRP_DLY_G
GRP_DLY_R
RESERVED
R/
W-0b
R/W-01b
R/W-000b
R/W-000b
R/W-000b
21
R/
W-0b
R/W-00b
31
30
29
28
27
26
24
23
19
18
FREQ_MUL
R/W-0111b
14
FREQ_
MOD
RESERVED
SUBP_NUM
R/W-000b
7
SCAN_NUM
R/
W-0b
R/W-000b
R/W-000000b
15
13
12
11
10
8
5
3
2
LODR
M_EN
PSP_MOD
PS_EN
RESERVED
PDC_E
N
RESERVED
CHIP_NUM
R/
R/W-00b
R/
R/
R/
R/
R/
R/
R/
R/
R/W-00111b
W-0b
W-0b
W-0b
W-0b
W-0b
W-1b
W-0b
W-0b
W-0b
表8-7. FC0 Register Field Descriptions
Bit
Field
Type
Reset
Description
4-0
CHIP_NUM
R/W
00111b
Set the device number
00000b: 1 device
...
01111b: 16 devices
...
11111b: 32 devices
7-5
RESERVED
R/W
000b
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表8-7. FC0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
8
PDC_EN
R/W
1b
Enable or disable pre-discharge function
0b: disable
1b: enable
11-9
12
RESERVED
PS_EN
R/W
R/W
000b
0b
Enable or disable the power saving mode
0b: disable
1b: enable
14-13
PSP_MOD
R/W
00b
Set the powering saving plus mode
00b: disable
01b: enable, when GSn(including the extending) ≤1/4
segment_length, power saving during the off cycle.
10b: enable, when GSn(including the extending) ≤1/2
segment_length, power saving during the off cycle.
11b: enable, when GSn(including the extending) ≤7/8
segment_length, power saving during the off cycle.
15
LODRM_EN
SCAN_NUM
R/W
R/W
0b
Enable or disable the LED open load removal function
0b: disable
1b: enable
21-16
000000b
Set the scan line number
000000b: 1 line
...
001111b: 16 lines
...
011111b: 32 lines
...
111111b: 64 lines
24-22
SUBP_NUM
R/W
000b
Set the subperiod number
000b: 16
001b: 32
010b: 48
011b: 64
100b: 80
101b: 96
110b: 112
111b: 128
27-25
28
RESERVED
FREQ_MOD
R/W
R/W
000b
0b
Set the GCLK multiplier mode
0b: high frequency mode, 80MHz to 160MHz
1b:low frequency mode, 40MHz to 80MHz
32-29
FREQ_MUL
R/W
0111b
Set the GCLK multiplier frequency
0000b: 1 x SCLK frequency
...
0111b: 8 x SCLK frequency
...
1111b: 16 x SCLK frequency
35-33
38-36
LINE_CHRG
GRP_DLY_R
R/W
R/W
000b
000b
Set the Red group delay, forward PWM mode only
000b: no delay
001b: 1 GCLK
010b: 2 GCLK
011b: 3 GCLK
100b: 4 GCLK
101b: 5 GCLK
110b: 6 GCLK
111b: 7 GCLK
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表8-7. FC0 Register Field Descriptions (continued)
Bit
Field
GRP_DLY_G
Type
Reset
Description
41-39
R/W
000b
Set the Green group delay, forward PWM mode only
000b: no delay
001b: 1 GCLK
010b: 2 GCLK
011b: 3 GCLK
100b: 4 GCLK
101b: 5 GCLK
110b: 6 GCLK
111b: 7 GCLK
44-42
GRP_DLY_B
R/W
000b
Set the Blue group delay, forward PWM mode only
000b: no delay
001b: 1 GCLK
010b: 2 GCLK
011b: 3 GCLK
100b: 4 GCLK
101b: 5 GCLK
110b: 6 GCLK
111b: 7 GCLK
46-45
47
RESERVED
LSD_RM_EN
R/W
R/W
01b
0b
Enable or disable short LED caterpillar
0b: disable
1b: enable
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8.7.2 FC1
FC1 is shown in 图8-30 and described in 表8-8.
图8-30. FC1 Register
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
32
RESE
RVED
BLK_ADJ
LINE_SWT
LG_ENH_B
LG_EN
H_G
R-0b
31
R/W-000000b
R/W-0111b
R/W-0000b
30
29
13
28
27
26
25
9
24
8
23
7
22
21
5
20
4
19
3
18
16
0
LG_ENH_G
R/W-0000b
14
LG_ENH_R
R/W-0000b
LG_STEP_B
R/W-01001b
6
LG_STEP_G
R/W-01001b
15
12
11
10
2
1
LG_ST
EP_G
LG_STEP_R
SEG_LENGTH
R/W-01001b
R/W-0'000'000'000b
表8-8. FC1 Register Field Descriptions
Bit
Field
Type
Reset
Description
9-0
SEG_LENGTH
LG_ENH_B
R/W
0'000'000'0 Set the GCLK number in each segment
00b
127d: 128 GCLK
...
1023d: 1024 GCLK
others: 128 GCLK
14-10
19-15
24-20
28-25
32-29
36-33
R/W
R/W
R/W
R/W
R/W
R/W
01001b
Adjust the smooth of the brightness in low grayscale
00000b: level 1
...
01111b: level 16
...
11111b: level 32
LG_ENH_G
LG_ENH_B
LG_STEP_R
LG_STEP_G
LG_STEP_B
01001b
01001b
0000b
0000b
0000b
Adjust the smooth of the brightness in low grayscale
00000b: level 1
...
01111b: level 16
...
11111b: level 32
Adjust the smooth of the brightness in low grayscale
00000b: level 1
...
01111b: level 16
...
11111b: level 32
Adjust low grayscale enhancement of red channels
0000b: level 0
...
0111b: level 7
...
1111b: level 15
Adjust low grayscale enhancement of green channels
0000b: level 0
...
0111b: level 7
...
1111b: level 15
Adjust low grayscale enhancement of blue channels
0000b: level 0
...
0111b: level 7
...
1111b: level 15
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表8-8. FC1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
40-37
LINE_SWT
R/W
0111b
Set the scan line switch time.
0000b: 45 GCLK
0001b: 2x30 GCLK
...
0111b: 8x30 GCLK
...
1111b: 16x30 GCLK
46-41
BLK_ADJ
R/W
000000b
Set the black field adjustment
000000b: 0 GCLK
...
011111b: 31 GCLK
...
111111b: 63 GCLK
47
RESERVED
R
0b
Reserved bit.
8.7.3 FC2
FC2 is shown in 图8-31 and described in 表8-9.
图8-31. FC2 Register
47
46
45
29
44
43
42
41
40
39
38
22
37
36
35
34
33
32
MPSM RESE
_EN
MOD_SIZE
SUBP_ CH_B_ CH_G_ CH_R_
MAX_2 IMMU IMMU IMMU
56
RESERVED
LG_COLOR_B
RVED
NITY
NITY
NITY
R/
W-0b
R/
W-0b
R/W-111b
28
R/
W-0b
R/
W-1b
R/
W-1b
R/
W-1b
R/W-000b
21
R/W-0000b
31
30
27
11
26
25
24
23
20
4
19
3
18
17
16
0
LG_COLOR_G
R/W-0000b
LG_COLOR_R
R/W-0000b
DE_COUPLE1_B
R/W-0000b
DE_COUPLE1_G
R/W-0000b
15
14
13
12
10
9
8
7
6
5
2
1
DE_COUPLE1_R
R/W-0000b
V_PDC_B
R/W-0110b
V_PDC_G
R/W-0110b
V_PDC_R
R/W-0110b
表8-9. FC2 Register Field Descriptions
Bit
Field
Type
Reset
Description
3-0
V_PDC_R
R/W
0110b
Set the Red pre_discharge voltage (typical), the voltage value
must not be higher than (VR-1.3 V).
0000b: 0.1 V
0001b: 0.2 V
0010b: 0.3 V
0011b: 0.4 V
0100b: 0.5 V
0101b: 0.6 V
0110b: 0.7 V
0111b: 0.8 V
1000b: 0.9 V
1001b: 1.0 V
1010b: 1.1 V
1011b: 1.3 V
1100b: 1.5 V
1101b: 1.7 V
1110b: 1.9 V
1111b: 2.1 V
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表8-9. FC2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
7-4
V_PDC_G
R/W
0110b
Set the Green pre_discharge voltage (typical), the voltage value
must not be higher than (VG-1.3V).
0000b: 0.1 V
0001b: 0.2 V
0010b: 0.3 V
0011b: 0.4 V
0100b: 0.5 V
0101b: 0.6 V
0110b: 0.7 V
0111b: 0.8 V
1000b: 0.9 V
1001b: 1.0 V
1010b: 1.1 V
1011b: 1.3 V
1100b: 1.5 V
1101b: 1.7 V
1110b: 1.9 V
1111b: 2.1 V
11-8
V_PDC_B
R/W
0110b
Set the Blue pre_discharge voltage (typical), the voltage value
must not be higher than (VB-1.3V).
0000b: 0.1V
0001b: 0.2 V
0010b: 0.3 V
0011b: 0.4 V
0100b: 0.5 V
0101b: 0.6 V
0110b: 0.7 V
0111b: 0.8 V
1000b: 0.9 V
1001b: 1.0 V
1010b: 1.1 V
1011b: 1.3 V
1100b: 1.5 V
1101b: 1.7 V
1110b: 1.9 V
1111b: 2.1 V
15-12
19-16
23-20
27-24
DE_COUPLE1_R
DE_COUPLE1_G
DE_COUPLE1_B
LG_COLOR_R
R/W
R/W
R/W
R/W
0000b
0000b
0000b
0000b
Set the Red dummy rising one-shot level
0000b: level 1 (lowest)
...
0111b: level 8 (middle)
...
1111b: level 16(highest)
Set the Green dummy rising one-shot level
0000b: level 1 (lowest)
...
0111b: level 8 (middle)
...
1111b: level 16(highest)
Set the Blue dummy rising one-shot level
0000b: level 1 (lowest)
...
0111b: level 8 (middle)
...
1111b: level 16(highest)
Set the Red rising one-shot level
0000b: level 1 (lowest)
...
0111b: level 8 (middle)
...
1111b: level 16(highest)
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表8-9. FC2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
31-28
LG_COLOR_G
R/W
0000b
Set the Green rising one-shot level
0000b: level 1 (lowest)
...
0111b: level 8 (middle)
...
1111b: level 16(highest)
35-32
LG_COLOR_B
R/W
0000b
Set the Blue rising one-shot level
0000b: level 1 (lowest)
...
0111b: level 8 (middle)
...
1111b: level 16(highest)
38-36
39
RESERVED
R/W
R/W
000b
1b
CH_R_IMMUNITY
Set the immunity of the Red channels group
0b: high immunity
1b: low immunity
40
41
CH_G_IMMUNITY
CH_B_IMMUNITY
SUBP_MAX_256
MOD_SIZE
R/W
R/W
R/W
R/W
1b
Set the immunity of the Green channels group
0b: high immunity
1b: low immunity
1b
Set the immunity of the Blue channels group
0b: high immunity
1b: low immunity
42
0b
Set the maximum subperiod to 256.
0b: disable
1b: enable
45-43
111b
Set the module size.
000b: 16x16 RGB pixels
001b:32x32 RGB pixels
010b:48x48 RGB pixels with D3 reverse, and scan sequence
D1, D2, D3
48x48 RGB pixels with D3 reverse, and scan sequence D1, D3,
D2
100b:48x64 RGB pixels with D3, D4 reverse, and scan
sequence D1, D2, D3
101b:48x64 RGB pixels with D3,D4 reverse, and scan sequence
D1, D3, D2
110b:64x64 RGB pixels with D3, D4 reserve, and scan
seqeunce D1, D2, D3, D4
111b:64x64 RGB pixels with D3, D4 reverse,and scan sequence
D1, D4, D2, D3
46
47
RESERVED
MPSM_EN
R/W
R/W
0b
0b
Enable or disable matrix power saving mode.
0b: disable
1b: enable
8.7.4 FC3
FC3 is shown in 图8-32 and described in 表8-10.
图8-32. FC3 Register
47
31
15
46
45
29
13
44
28
43
LSDVTH_G
R/W-000b
27
42
26
10
41
25
9
40
39
23
7
38
22
6
37
LSD_RM
R/W-0111b
36
35
19
34
18
2
33
BC
32
16
0
LSDVTH_B
R/W-000b
30
LSDVTH_R
R/W-000b
24
R/W-011b
17
21
20
CC_B
CC_G
R/W-0111 1111b
R/W-0111 1111b
12 11
14
8
5
4
3
1
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图8-32. FC3 Register (continued)
CC_R
LOD_L RESE
SD_RB RVED
LODVTH_B
LODVTH_G
R/W-00b
LODVTH_R
R/W-00b
R/W-0111 1111b
R/
R/
R/W-00b
W-0b
W-0b
表8-10. FC3 Register Field Descriptions
Bit
Field
Type
Reset
Description
1-0
LODVTH_R
R/W
00b
Set the Red LED open load detection threshold
00b: (VLEDR-0.2) V
01b: (VLEDR-0.5) V
10b: (VLEDR-0.9) V
11b: (VLEDR-1.2) V
3-2
5-4
LODVTH_G
LODVTH_B
R/W
R/W
00b
00b
Set the Green LED open load detection threshold
00b: (VLEDG-0.2) V
01b: (VLEDG-0.5) V
10b: (VLEDG-0.9) V
11b: (VLEDG-1.2) V
Set the Blue LED open load detection threshold
00b: (VLEDB-0.2) V
01b: (VLEDB-0.5) V
10b: (VLEDB-0.9) V
11b: (VLEDB-1.2) V
6
7
RESERVED
R/W
R/W
0b
0b
LOD_LSD_RB
Enable or disable the LOD and LSD readback function
0b: disabled
01b: enabled
15-8
23-16
31-24
34-32
CC_R
CC_G
CC_B
BC
R/W
R/W
R/W
R/W
0111 1111b Set the Red color brightness level
0000 0000b: level 0 (lowest)
...
0111 1111b: level 127 (middle)
...
1111 1111b: level 255 (highest)
0111 1111b Set the Green color brightness level
0000 0000b: level 0 (lowest)
...
0111 1111b: level 127 (middle)
...
1111 1111b: level 255 (highest)
0111 1111b Set the Blue color brightness level
0000 0000b: level 0 (lowest)
...
0111 1111b: level 127 (middle)
...
1111 1111b: level 255 (highest)
011b
Set the global brightness level
000b: level 0 (lowest)
...
011b: level 3 (middle)
...
111b: level 7 (highest)
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表8-10. FC3 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
38-35
LSD_RM
R/W
0111b
Set the LED short removal level
0000b: level 1
0001b: level 2
0010b: level 3
0011b: level 4
0100b: level 5
0101b: level 6
0110b: level 7
0111b: level 8
1000b: level 9
1001b: level 10
1010b: level 11
1011b: level 12
1100b: level 13
1101b: level 14
1110b: level 15
1111b: level 16
41-39
44-42
47-45
LSDVTH_R
LSDVTH_G
LSDVTH_B
R/W
R/W
R/W
000b
000b
000b
Set the Red LED short/weak short circuitry detection threshold
(typical)
000b: 0.2 V
001b: 0.4 V
010b: 0.8 V
011b: 1.0 V
100b: 1.2 V
101b: 1.4 V
110b: 1.6 V
111b: 1.8 V
Set the Green LED short/weak short circuitry detection threshold
(typical)
000b: 0.2 V
001b: 0.4 V
010b: 0.8 V
011b: 1.2 V
100b: 1.6 V
101b: 2 V
110b: 2.4 V
111b: 2.8 V
Set the Blue LED short/weak short circuitry detection threshold
(typical)
000b: 0.2 V
001b: 0.4 V
010b: 0.8 V
011b: 1.2 V
100b: 1.6 V
101b: 2 V
110b: 2.4 V
111b: 2.8 V
8.7.5 FC4
FC4 is shown in 图8-33 and described in 表8-11.
图8-33. FC4 Register
47
31
46
45
29
44
43
27
42
41
40
24
39
38
22
37
36
35
19
34
33
32
RESERVED
DE_C
OUPL
E3_EN
DE_COUPLE3
DE_C
OUPL
E2
FIRST_LINE_DIM
CAUR CAUR CAUR
SE_B SE_G SE_R
R-000b
30
R/
W-0b
R/W-1000b
R/
W-0b
R/W-0000b
R/
W-0b
R/
W-0b
R/
W-0b
28
26
25
23
21
20
18
17
16
RESERVED
SR_ON_B
SR_ON_G
SR_ON_R
SR_OF SR_OF SR_OF FINE_ FINE_ FINE_
F_B F_G F_R
B
G
R
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图8-33. FC4 Register (continued)
R/W-0000b
14 13
R/W-01b
R/W-01b
R/W-01b
R/
W-0b
R/
W-0b
R/
W-0b
R/
W-0b
R/
W-0b
R/
W-0b
15
12
11 10
9
8
7
6
5
4
3
2
1
0
RESE SCAN_
RVED REV
RESERVED
IMAX LAST_
SOUT
R/
R/
R/W-0000 0000 1111b
R/
R/
W-0b
W-1b
W-0b
W-0b
表8-11. FC4 Register Field Descriptions
Bit
Field
Type
Reset
Description
0
LAST_SOUT
R/W
0b
Enable or disable the last device's SOUT cut-off function
0b: disabled, last chip's SOUT shift out
1b: enabled, last chip's SOUT cut off, except for READ
command
1
IMAX
R/W
0b
Set the maximum current of each channel
0b: 10mA maximum
01b: 20 mA maximum
13-2
14
RESERVED
SCAN_REV
R/W
R/W
0000 0000
1111b
1b
When 2 device stackable or 3 devices stackable, the scan lines
PCB layout is reversed. For the proper scan and SRAM read
sequence, SCAN_REV register is provided.
0b: the PCB layout sequence is L0-L15, L16-L31.
1b: the PCB layout sequence is L0-L15, L31-L16.
15
16
RESERVED
FINE_R
R/W
R/W
0b
0b
Enable the Red brightness compensation level fine range
0b: disable.
1b: enable.
17
18
FINE_G
R/W
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
01b
Enable the Green brightness compensation level fine range
0b: disable.
1b: enable.
FINE_B
Enable the Blue brightness compensation level fine range
0b: disable.
1b: enable.
19
SR_OFF_R
SR_OFF_G
SR_OFF_B
SR_ON_R
Slew rate control function when Red turns off operation
0b: slow slew rate.
1b: fast slew rate.
20
Slew rate control function when Green turns off operation
0b: slow slew rate.
1b: fast slew rate.
21
Slew rate control function when Blue turns off operation
0b: slow slew rate.
1b: fast slew rate.
23-22
Slew rate control function when Red turns on operation
00b: the slower slew rate.
01b: slow slew rate.
10b: fast slew rate.
11b: the faster slew rate.
25-24
27-26
SR_ON_G
SR_ON_B
R/W
R/W
01b
01b
Slew rate control function when Green turns on operation
00b: the slower slew rate.
01b: slow slew rate.
10b: fast slew rate.
11b: the faster slew rate.
Slew rate control function when Blue turns on operation
00b: the slower slew rate.
01b: slow slew rate.
10b: fast slew rate.
11b: the faster slew rate.
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表8-11. FC4 Register Field Descriptions (continued)
Bit
31-28
32
Field
Type
R/W
R/W
Reset
0000b
0b
Description
RESERVED
CAURSE_R
Enable the Red brightness compensation level caurse tange
0b: disabled
1b: enabled
33
34
CAURSE_G
R/W
R/W
R/W
0b
Enable the Green brightness compensation level caurse tange
0b: disabled
1b: enabled
CAURSE_B
0b
Enable the Blue brightness compensation level caurse tange
0b: disabled
1b: enabled
38-35
FIRST_LINE_DIM
0000b
Adjust the first line dim level
0000b: level 1
...
0111b: level 8
...
1111b: level 16
39
DE_COUPLE2
DE_COUPLE3
R/W
R/W
0b
Decoupling between ON and OFF channels
0b: disabled
1b: enabled
43-40
1000b
Set decoupling enhancement level
0000b: level 1
...
0111b: level 8
...
1111b: level 16
44
DE_COUPLE3_EN
RESERVED
R/W
R/W
0b
Enable decoupling enhancement
0b: disabled
1b: enabled
47-45
000b
8.7.6 FC14
FC14 is shown in FC14 Register and described in FC14 Register Field Descriptions.
图8-34. FC14 Register
47
31
15
46
30
14
45
29
13
44
28
12
43
27
11
42
26
10
41
25
9
40
39
38
22
6
37
21
5
36
20
4
35
19
3
34
18
2
33
17
1
32
16
0
RESERVED
R-0b
24
23
RESERVED
R-0b
8
7
RESERVED
R-0b
LOD_LINE_CMD
R/W-000000b
表8-12. FC14 Register Field Descriptions
Bit
Field
Type
Reset
Description
5-0
LOD_LINE_CMD
R/W
000000b
Locate the line with LED open load warnings:
000000b: Line 0
...
011111b: Line 31
...
111111b: Line 63
47-6
RESERVED
R
0b
Reserved bits
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8.7.7 FC15
FC15 is shown in FC15 Register and described in FC15 Register Field Descriptions.
图8-35. FC15 Register
47
31
15
46
30
14
45
29
13
44
28
12
43
27
11
42
26
10
41
25
9
40
39
38
22
6
37
21
5
36
20
4
35
19
3
34
18
2
33
17
1
32
16
0
RESERVED
R-0b
24
23
RESERVED
R-0b
8
7
RESERVED
R-0b
LSD_LINE_CMD
R/W-000000b
表8-13. FC15 Register Field Descriptions
Bit
Field
Type
Reset
Description
5-0
LSD_LINE_CMD
R/W
000000b
Locate the line with LED short circuitry warnings:
000000b: Line 0
...
011111b: Line 31
...
111111b: Line 63
47-6
RESERVED
R
0b
Reserved bits
8.7.8 FC16
FC16 is shown in FC16 Register and described in FC16 Register Field Descriptions.
图8-36. FC16 Register
47
31
15
46
30
14
45
29
13
44
28
12
43
27
11
42
26
10
41
25
9
40
39
38
22
6
37
21
5
36
20
4
35
19
3
34
18
2
33
17
1
32
16
0
RESERVED
R-0b
24
23
RESERVED
R-0b
8
7
LOD_LINE_WARN[63:48]
R-0b
表8-14. FC16 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
LOD_LINE_WARN[63:48]
R
0b
Read the line with LED open load warnings:
Bit 0 = 0, Line 48 has no warning; Bit 0 = 1, Line 48 has warning
...
Bit 15 = 0, Line 63 has no warning; Bit 15 = 1, Line 63 has
warning
47-16
RESERVED
R
0b
Reserved bits
8.7.9 FC17
FC17 is shown in FC17 Register and described in FC17 Register Field Descriptions.
图8-37. FC17 Register
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
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图8-37. FC17 Register (continued)
LOD_LINE_WARN[47:0]
R-0b
31
15
30
14
29
13
28
12
27
11
26
10
25
24
23
22
21
5
20
4
19
3
18
2
17
1
16
0
LOD_LINE_WARN[47:0]
R-0b
9
8
7
6
LOD_LINE_WARN[47:0]
R-0b
表8-15. FC17 Register Field Descriptions
Bit
47-0
Field
LOD_LINE_WARN[47:0]
Type
Reset
Description
R
0b
Read the line with LED open load warnings:
Bit 0 = 0, Line 0 has no warning; Bit 0 = 1, Line 0 has warning
...
Bit 47 = 0, Line 47 has no warning; Bit 47 = 1, Line 47 has
warning
8.7.10 FC18
FC18 is shown in FC18 Register and described in FC18 Register Field Descriptions.
图8-38. FC18 Register
47
31
15
46
30
14
45
29
13
44
28
12
43
27
11
42
26
10
41
25
9
40
39
38
22
6
37
21
5
36
20
4
35
19
3
34
18
2
33
17
1
32
16
0
RESERVED
R-0b
24
23
RESERVED
R-0b
8
7
LSD_LINE_WARN[63:48]
R-0b
表8-16. FC18 Register Field Descriptions
Bit
Field
Type
Reset
Description
16-0
LSD_LINE_WARN[63:48]
R
0b
Read the line with LED short circuitry warnings:
Bit 0 = 0, Line 48 has no warning; Bit 0 = 1, Line 48 has warning
...
Bit 15 = 0, Line 63 has no warning; Bit 15 = 1, Line 63 has
warning
47-16
RESERVED
R
0b
Reserved bits
8.7.11 FC19
FC19 is shown in FC19 Register and described in FC19 Register Field Descriptions.
图8-39. FC19 Register
47
31
15
46
30
14
45
29
13
44
28
12
43
27
11
42
26
10
41
40
39
38
37
21
5
36
20
4
35
19
3
34
18
2
33
17
1
32
16
0
LSD_LINE_WARN[47:0]
R-0b
25
24
23
22
LSD_LINE_WARN[47:0]
R-0b
9
8
7
6
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图8-39. FC19 Register (continued)
LSD_LINE_WARN[47:0]
R-0b
表8-17. FC19 Register Field Descriptions
Bit
Field
Type
Reset
Description
47-0
LSD_LINE_WARN[47:0]
R
0b
Read the line with LED short circuitry warnings:
Bit 0 = 0, Line 0 has no warning; Bit 0 = 1, Line 0 has warning
...
Bit 47 = 0, Line 47 has no warning; Bit 47 = 1, Line 47 has
warning
8.7.12 FC20
FC20 is shown in FC20 Register and described in FC20 Register Field Descriptions.
图8-40. FC20 Register
47
31
15
46
30
14
45
29
13
44
28
12
43
27
11
42
26
10
41
25
9
40
LOD_CH
R-0b
39
38
22
6
37
21
5
36
20
4
35
19
3
34
18
2
33
17
1
32
16
0
24
23
LOD_CH
R-0b
8
7
LOD_CH
R-0b
表8-18. FC20 Register Field Descriptions
Bit
47-0
Field
LOD_CH
Type
Reset
Description
R
0b
Locate the LED opem load channel:
Bit 0 = 0, CH 0 is normal; Bit 0 = 1, CH 0 is short circuitry
...
Bit 47 = 0, CH 47 is normal; Bit 47 = 1, CH 47 is short circuitry
8.7.13 FC21
FC21 is shown in FC21 Register and described in FC21 Register Field Descriptions.
图8-41. FC21 Register
47
31
15
46
30
14
45
29
13
44
28
12
43
27
11
42
26
10
41
25
9
40
LSD_CH
R-0b
39
38
22
6
37
21
5
36
20
4
35
19
3
34
18
2
33
17
1
32
16
0
24
23
LSD_CH
R-0b
8
7
LSD_CH
R-0b
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表8-19. FC21 Register Field Descriptions
Bit
Field
LSD_CH
Type
Reset
Description
47-0
R
0b
Locate the LED short circuitry channel:
Bit 0 = 0, CH 0 is normal; Bit 0 = 1, CH 0 is short circuitry
...
Bit 47 = 0, CH 47 is normal; Bit 47 = 1, CH 47 is short circuitry
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TLC6984 integrates 48 constant current sources and 16 scanning FETs. A single TLC6984 is capable of
driving 16 × 16 RGB LED pixels while stacking two TLC6984s can drive 32 × 32 RGB LED pixels. To achieve
low power consumption, the TLC6984 supports separated power supplies for the red, green, and blue LEDs by
its common cathode structure.
The TLC6984 implements a high speed dual-edge transmission interface (up to 25 MHz) to support high device
count daisy-chained and high refresh rate while minimizing electrical-magnetic interference (EMI). SCLK must be
continuous, no matter there are data on SIN or not, because SCLK is not only used to sample the data on SIN,
but also used as a clock source to generate GCLK by internal frequency multiplier. Based on dual-edge CCSI
protocol, all the commands/FC registers/SRAM data are written from the SIN input terminal, and all the FC
registers/ LED open and short flag can be read out from the SOUT output terminal. Moreover, the device
supports up to 160-MHz GCLK frequency and can achieve 16-bit PWM resolution, with 3840 Hz or even higher
refresh rate.
Meanwhile, the TLC6984 integrates enhanced circuits and intelligent algorithms to solve the various display
challenges in Narrow Pixel Pitch (NPP) LED display applications and mini and micro-LED products: dim at the
first scan line, upper and downside ghosting, non-uniformity in low grayscale, coupling, caterpillar caused by
open or short LEDs, which make the TLC6984 a perfect choice in such applications.
The TLC6984 also implements LED open and weak, short and short detections and removals during operations
and can also report this information out to the accompanying digital processor.
9.2 Typical Application
The TLC6984 is typically connected in series in a daisy-chain to drive the LED matrix with only a few controller
ports. 图 9-1 shows a typical application diagram with two TLC6984 devices stackable connection to drive 32 ×
32 RGB LED pixels.
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图9-1. TLC6984 With Dual Devices Stackable Connection
9.2.1 Design Requirements
Taking 4K micro-LED televation for example, the resolution of the screen is 3840 × 2160, and the screen
consists of many modules. The following sections show an example to build a LED display module with 240 ×
180 pixels.
The example uses the following values as the system design parameters.
表9-1. TLC6984 Design Parameters
DESIGN PARAMETER
VCC and VR
EXAMPLE VALUE
2.8 V
VG and VB
3.8 V
Maximum current per LED
PWM resolution
IRED = 3 mA, IGREEN = 2 mA, IBLUE = 1 mA
14 bits
Frame rate
120 Hz
Refresh rate
3840 Hz
Display module size
cascaded devices number
devices number per LED display module
240 × 180 pixels
8
96
9.2.1.1 System Structure
To build an LED display module with 240 × 180 pixels, 96 TLC6984s are required.
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240 Colume
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
180
Lines
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
30 x 30
pixels
图9-2. LED Display Module
As shown in 图 9-2, the total module can be divided into 48 32 × 32 matrix. Each matrix includes two devices
with stackable connection.
备注
To achieve the best performance, TI suggests to distribute the redundant channels and lines to each
32 × 32 matrix. For this case, two Red/Green/Blue channels and two lines are not used in each matrix.
And these unused pins can be floated. For the software, TI suggests zero data is to send to the
unused channels. There is no must send the zero data to unused lines.
9.2.1.2 SCLK Frequency
The SCLK frequency is determined by the data volume of one frame and frame rate. In this application, the data
volume V_Data is 30 × 32 × 48 bits × 4 = 184.32 Kb, the frame rate is 120 Hz. Suppose the data transmission
efficiency is 0.8, the minimum frequency of SCLK must be: fSCLK = V_Data × fframe / 0.8. So the minimum SCLK
frequency is 13.83 MHz with dual-edge transmission.
9.2.1.3 Internal GCLK Frequency
The internal GCLK frequency is configured by the Frequency Multiplier (FREQ_MUL), and is determined by the
PWM resolution. The GCLK frequency can be calculated by the below equations:
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frefresh_ rate
Nsub_ period
=
f frame_ rate
GSmax = 2K
GSmax = NGCLK _ Seg ì Nsub_ period
N
≈
∆
«
’
1
GCLK _ Seg
=
+TSW ì NScan_line ì Nsub_ period +TBlank
÷
f frame_ rate
fGCLK
◊
(3)
where
• frefresh_rate means the refresh rate
• fframe_rate means the frame rate
• K means the PWM resolution
• Nsub_period means the sub-period numbers within one frame
• NGCLK_seg means the GCLK number per segment (Line switch time excluded)
• fGCLK means GCLK frequency
• TSW means line switching time
• Nscan_line means the scan line number
• Tblank means the blank time in one frame, equals to 0 in ideal configuration
• GSmax means the maximum grayscale that the device can output in one frame
表9-2 gives the values based on the system configuration and equation.
表9-2. TLC6984 Design Parameters for GCLK Frequency Calculation
DESIGN PARAMETER
Nsub_period
Nscan_line
TSW
EXAMPLE VALUE
32
30
1.5 µs
0
Tblank
NGCLK_seg
GSmax
512
16383
71.3 MHz
fGCLK
Considering SCLK frequency and FREQ_MUL, the SCLK can be 13.9 MHz, and FREQ_MUL can be 6. So the
GCLK is 83.4 MHz.
9.2.1.4 Line Switch Time
The line switch time is digitalized with the GCLK number and can be set by the LINE_SWT (Bit 40-37 in FC1
register). In this application, it is 1.5 us × 83.4 MHz = 125 GCLKs, so the LINE_SWT equals to 0011b (120
GCLKs), the actual line switch time is 1.44 us.
9.2.1.5 Blank Time Removal
The TLC6984 has an algorithm to distribute the blank time into each subperiod to prevent the black field when
taking photos or video.
From Equation 3, 83.4-MHz GCLK frequency and 1.44-us line switch time, the calculated blank time is 1.059 ms
( 88280 GCLK ), which is too long and brings black field.
Here are detailed steps of the algorithm.
Step 1: Distribute blank time into each segment
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When the blank GCLK number is larger than Nsub_period × Nscan_line, it can be distributed into each segment.
In this application, the blank GCLK number is 88280, and Nsub_period × Nscan_line is 960, so the distributed GCLK
number in each segment is 88280/960 = 91...920. These 91GCLKs can be used to increase PWM length or
extend line switch time. If used to increase PWM length, the GCLK number in each segment is 512 + 91= 603,
so the SEG_LENGTH ( Bit9-0 in FC1 register) is 1001011010b.
Step 2: Distribute blank time into each sub-period
If the left GCLK number is larger than Nsub_period, it can be distributed into each sub-period.
In this application, the left GCLK is 697, the distributed GCLK number in each sub-period is 920/32=28...24. The
BLK_ADJ (Bit46-41 in FC1 register) is 011100b.
After distributing into each sub-period, the left GCLK number is 24, which is about 300 ns, this time is too short
to bring black field.
9.2.1.6 BC and CC
Select the reference current-setting resistor RIREF and configure a proper BC value to set the maximum current
of the RGB LEDs (see Brightness Control (BC) Function for more details). Here the maximum current is 3 mA,
BC value is 03h, according to equation 方程式1, the reference resistor value is 0.8 V/3 mA × 85.33 = 22.75 kΩ.
Configure the CC_R/CC_G/CC_B registers to set the current of Red/ Green/Blue LED current to 3 mA/2 mA/1
mA (see Color Brightness Control (CC) Function for more details).
表9-3 shows the reference current setting resistor RIREF, BC and CC_R/CC_G/CC_B register value.
表9-3. Current Setting Value
DESIGN PARAMETER
EXAMPLE VALUE
22.75 kΩ
RIREF
BC
011 b
CC_R
CC_G
CC_B
11111111 b
10101001 b
01010100 b
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9.2.2 Detailed Design Procedure
图9-3 gives a detail design procedure for LED display. After power on and digital signals are ready, the first step
for the controller is to send the chip index command to let the devices know their identifications. Then, the
controller sends the configuration data to the FC registers. After this, it sends the VSYNC at the beginning of
each frame and also sends the data to each device. The devices display the data of last frame when the VSYNC
comes and meanwhile receive the data of current frame transmitted from controller. The registers can be read at
anytime of the frame.
Begin
Power Supply, SCLK/SIN
Ready
Write Chip Index
Configure the
register during
sending data
Write FC Registers
Write SRAM
Write next
frame SRAM
Data in normal
operation
Wait for the end of current
frame
Write VSYNC
Read registers
during each
time of the
frame
Read Chip Index/FC/LOD/LSD
图9-3. Design Procedure for LED Display
9.2.2.1 Chip Index Command
The chip index is used to distribute the address of the devices in a data chain. Each device gets its unique
address by this command. Details can be found in Chip Index Write Command.
9.2.2.2 FC Registers Settings
Some bits of FC0, FC1, FC2, FC3 registers must be configured properly before the devices work normally. In
this application, the registers value can be:
表9-4. FC Registers Value
FC Registers
FC0
Register Value (BIN)
Register Value (HEX)
2000 B85D 8107h
2AE0 0094 A631 h
0B80 0000 0AA0 h
003B 54A9 FF00 h
0010 0000 0000 0000 1011 1000 0101 1101 1000 0001 0000 0111 b
0010 1010 1110 0000 0000 0000 1001 0100 1010 0110 0011 0001 b
0000 1011 1000 0000 0000 0000 0000 0000 0000 1010 1010 0000 b
0000 0000 0011 1011 0101 0100 1010 1001 1111 1111 0000 0000 b
FC1
FC2
FC3
FC6, FC7, FC8, FC9, FC10, FC11, FC12, FC13 registers are used for programmable scanning sequence
function.
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The controller can configure the FC by the data write command with broadcast mode (see Data Write Command
for more detail). The FC0, FC1 registers are updated after the VSYNC command comes, and the other FC
registers are updated right away regardless the VSYNC command.
9.2.2.3 Grayscale Data Write
The channel grayscale data is written to SRAM of the device by the data write command with non-broadcast
way. Details can be found in Data Write Command and Write a Frame Data into Memory Book.
Data Write Flow is the data write flow for this application, P (i, j) is the data of pixel locating in i+ 1 row and j + 1
column. Suppose channel R15/G15/B15 of each device is not used and not connected, the channel
R14/G14/B14 is connected to P (i, 0), the channel R13/G13/B13 is connected to P (i, 1),…, and channel
R0/G0/B0 is connected to P (i, 14). The data of unused channel must be zero noting D_Zero in below figure, and
D_Zero = 00000000000000001 00000000000000001 00000000000000001b.
i=0
j=15
ST+HB+P(i, jx7)+P(i, jx6)+Y+P(i, jx1)+P(i,0)+END
j=j-1
Write one
line data
N
Write one
frame data
j=0
Y
ST+HB+D_Zero+D_Zero+Y+D_Zero+D_Zero+END
i=i+1
N
i=30
Y
图9-4. Data Write Flow
9.2.2.4 VSYNC Command
The VSYNC is used to sync the display of each frame for the devices in a cascaded chain. Details can be found
in VSYNC Write Command.
9.2.2.5 LED Open and Short Read
FC14, FC15, FC16, FC17, FC18, FC19, FC20, FC21 are the read command for LOD/LSD information. Details
can be found in Read LED-open Information and Read LED-short Information.
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9.2.3 Application Curves
图9-5. Line and Channel Waveform in One Frame
图9-6. Line and Channel Waveform in One
(GSn=0xFFFFh)
Subperiod (GSn=0xFFFFh)
图9-8. Line and Channel Waveform in One Frame
图9-7. Line and Channel Waveform in One Frame
(GSn=0x0001h)
(GSn=0x0001h)
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10 Power Supply Recommendations
Decouple the VCC power supply voltage by placing a 0.1-μF ceramic capacitor close to VCC pin and GND
plane. Depending on panel size, several electrolytic capacitors must be placed on the board equally distributed
to get well regulated LED supply voltage VR/VG/VB. The ripple of the LED supply voltage must be less than 5%
of their nominal value. Generally, the green and blue LEDs have the similar forward voltage and they can be
supplied by the same power rail.
Furthermore, the VR > Vf(R) + 0.35 V (10-mA constant current example), the VG = VB > Vf(G/B) + 0.35 V (10-
mA constant current example), here Vf(R), Vf(G/B) are representative for the maximum forward voltage of red,
green/blue LEDs.
To simplify the power design, VCC can be connected to VR power rail.
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11 Layout
11.1 Layout Guidelines
• Place the decoupling capacitor near the VCC/VR, VG/VB pins and GND plane.
• Place the current programming resistor RIREF close to IREF pin and GND plane.
• Route the GND thermal pad as widely as possible for large GND currents. Maximum GND current is
approximately 2 A for two devices (96-CH × 20 mA = 1.92 A).
• The Thermal pad must be connected to GND plane because the pad is used as power ground pin internally.
There is a large current flow through this pad when all channels turn on. Furthermore, this pad must be
connected to a heat sink layer by thermal via to reduce device temperature. For more information about
suggested thermal via pattern and via size, see PowerPAD™ Thermally Enhanced Package application note.
• Routing between the LED Anode side and the device OUTXn pin must be as short and straight as possible to
reduce wire inductance.
• The line switch pins must be located in the middle of the matrix, which must be laid out as symmetrically as
possible.
11.2 Layout Example
To simplify the system power rails design, we suggest that VR, VCC use one power rail, and VG, VB use another
power rail. 图11-1 gives an example for power rails routing.
Connect the GND pin to thermal pad on board with the shortest wire and the thermal pad is connected to GND
plane with the vias, as many as possible to help the power dissipation.
32 RGB LEDs
VR/VCC
C
C
GND
GND
GND
GND
C
GND
C
32 Lines
VG/VB
C
C
GND
GND
T
GND
GND
C
GND
C
VR/VCC
图11-1. Power Rails Routing Suggestion
图 11-2 gives an example for line routing. Connect the line switch to the center of the line bus, so as to uniform
the current flowing from the line switch to the left side and right side LEDs in white grayscale. With this
connection, the unbalance of the parasitic inductor from the routing is the smallest and the display performance
is better, especially in low grayscale condition.
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图11-2. Line Routing Suggestion
图11-3 gives an example for channel routing with the shortest wire. With this connection, the channel to the LED
path is the shortest, which can reduce the wire inductance, and be a benefit to the performance. However, the
data transmission sequence must be adjusted to follow the pins routing map. For example, R0 connects to
column 15 (LED15 ). The first data must be column 15 (LED15) rather than column 0 (LED0).
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图11-3. Channel Routing Suggestion With Shortest Wire
图 11-4 gives an example for channel routing with pin number sequence. With this connection, the data
transmission sequence are the same with pin number sequence. For example, R0 connects to column 0
(LED0 ). The first data is column 0 (LED0). However, with this connection, the inductance for each channel can
be different, which can bring a slight difference for the worst case.
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图11-4. Channel Routing Suggestion With Channel Order Sequence
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
• Texas Instruments, PowerPAD™ Thermally Enhanced Package application note
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLC6984RRFR
TLC6984ZXLR
ACTIVE
ACTIVE
VQFN
RRF
ZXL
76
96
2000 RoHS & Green
2500 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
TLC6984
TLC6984
Samples
Samples
NFBGA
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Mar-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC6984ZXLR
NFBGA
ZXL
96
2500
330.0
16.4
6.3
6.3
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Mar-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
NFBGA ZXL 96
SPQ
Length (mm) Width (mm) Height (mm)
336.6 336.6 31.8
TLC6984ZXLR
2500
Pack Materials-Page 2
PACKAGE OUTLINE
RRF0076A
VQFN - 1 mm max height
S
C
A
L
E
1
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
A
9.1
8.9
B
PIN 1 INDEX AREA
9.1
8.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
2X 7.2
SYMM
EXPOSED
THERMAL PAD
(0.1) TYP
38
20
19
39
SYMM
77
2X 7.2
6.3 0.1
1
57
72X 0.4
0.25
0.15
76X
76
58
PIN 1 ID
0.1
C A B
0.6
0.4
76X
0.05
4224965/A 04/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RRF0076A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(6.3)
SYMM
SEE SOLDER MASK
DETAIL
58
76
76X (0.7)
76X (0.2)
1
57
72X (0.4)
(1.1) TYP
(R0.05) TYP
(1.2) TYP
(0.6) TYP
SYMM
77
(8.7)
(
0.2) TYP
VIA
39
19
38
20
(0.6)
TYP
(1.2)
TYP
(1.1)
TYP
(8.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224965/A 04/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RRF0076A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
25X ( 1)
(1.2) TYP
58
76
76X (0.7)
76X (0.2)
1
57
72X (0.4)
(R0.05) TYP
(1.2) TYP
SYMM
77
(8.7)
19
39
38
20
SYMM
(8.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 10X
EXPOSED PAD 77
63% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4224965/A 04/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
NFBGA - 1.08 mm max height
PLASTIC BALL GRID ARRAY
ZXL0096A
A
6.1
5.9
B
BALL A1 CORNER
6.1
5.9
1.08 MAX
C
SEATING PLANE
0.08 C
0.25
0.19
BALL TYP
5 TYP
SYMM
(0.5) TYP
(0.5) TYP
L
K
J
H
G
SYMM
5
TYP
F
E
D
C
0.35
0.25
96X Ø
0.15
0.05
C A B
C
B
A
0.5 TYP
1
2
3
4
5
6
7
8
9
10 11
0.5 TYP
4225828/A 03/2020
NanoFree is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
NFBGA - 1.08 mm max height
PLASTIC BALL GRID ARRAY
ZXL0096A
(0.5) TYP
1
2
3
4
5
6
7
8
9
10
11
A
B
(0.5) TYP
C
D
E
SYMM
F
G
H
J
K
L
96X (Ø 0.25)
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.05 MAX
ALL AROUND
0.05 MIN
EXPOSED
METAL
EXPOSED
METAL
ALL AROUND
(Ø 0.25)
SOLDER MASK
OPENING
(Ø 0.25)
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225828/A 03/2020
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments
Literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
NFBGA - 1.08 mm max height
PLASTIC BALL GRID ARRAY
ZXL0096A
(0.5) TYP
1
2
3
4
5
6
7
8
9
10
11
A
B
(0.5) TYP
C
D
E
SYMM
F
G
H
J
(R0.05) TYP
K
L
96X (☐ 0.25)
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 15X
4225828/A 03/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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