TPS22993_技术文档

Sample &

Buy

Support &

Community

Product

Folder

Tools &

Software

Technical

Documents

TPS22993

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

TPS22993 四通道负载开关，具有通用输入输出 (GPIO) 和 I²C 控制功能

1 特性

2 应用范围

1

•

输入电压：1.0V 至 3.6V

•

Ultrabook™

超薄个人电脑

笔记本电脑

平板电脑

服务器

•

低导通状态电阻 (V_BIAS= 7.2V)

–

V_IN= 3.3V 时，R_ON= 15mΩ

V_IN= 1.8V 时，R_ON= 15mΩ

V_IN= 1.5V 时，R_ON= 15mΩ

V_IN= 1.05V 时，R_ON= 15mΩ

一体机

•

VBIAS 电压范围：4.5V 至 17.2V

适合于 2S/3S/4S 锂离子电池拓扑结构

3 说明

–

TPS22993 是一款多通道、低 R_ON负载开关，此开关

具有用户可编程特性。此器件包含四个可在 1.0V 至

3.6V 的输入电压范围内运行的 N 通道金属氧化物半导

体场效应晶体管 (MOSFET)。此开关可由 I²C 控制，

从而使其非常适合与具有有限 GPIO 数量的处理器一

同使用。 TPS22993 器件的上升时间受到内部控制以

避免涌入电流。 TPS22993 具有五个可编程转换率选

项、四个接通延迟选项和四个快速输出放电 (QOD) 电

阻选项。

•

每通道 1.2A 最大持续电流

静态电流

–

单通道 < 9µA

全部四个通道 < 17µA

•

关断电流（全部四个通道）< 6µA

四个 1.2V 兼容 GPIO 控制输入

I²C 配置（每通道）

–

开/关控制

可编程转换率控制（5 个选项）

可编程接通延迟（4 个选项）

可编程输出放电（4 个选项）

此器件的通道可由 GPIO 或 I²C 控制。缺省运行模式

为通过 ONx 端子的 GPIO 控制。 I²C 从地址端子可接

至高电平或低电平，以分配 7 个唯一的器件地址。

•

I²C SwitchALL™ 用于多通道/多芯片控制的命令

四方扁平无引线 (QFN)-20 封装，3mm x 3mm，高

度 0.75mm

TPS22993 采用节省空间的 RLW 封装（焊球间距

0.4mm），并可在 -40°C 至 85°C 的自然通风温度范

围内运行。

器件信息

订货编号

封装

封装尺寸

3mm x 3mm

超薄四方扁平无引线

(WQFN) (20)

TPS22993PRLWR

4 简化电路原理图

VBIAS

(4.5V to 17.2V)

VIN1

VOUT1

ON1

C_L

R_L

VIN2

VOUT2

ON2

C_L

PMIC or

PMU

TPS22993

VOUT3

VIN3

ON3

C_L

VOUT4

VIN4

ON4

ADD1

C_L

R_L

ADD2

ADD3

SDA SCL

µC

VDD

(1.62 to 3.6)

1

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

English Data Sheet: SLVSCA3

TPS22993

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

www.ti.com.cn

1

2

3

4

5

6

7

特性.......................................................................... 1

应用范围................................................................... 1

说明.......................................................................... 1

简化电路原理图........................................................ 1

修订历史记录 ........................................................... 2

Terminal Configuration and Functions................ 3

Specifications......................................................... 4

7.1 Recommended Operating Conditions....................... 4

7.2 Absolute Maximum Ratings ..................................... 5

7.3 Handling Ratings....................................................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 Switching Characteristics.......................................... 8

7.7 Typical Characteristics.............................................. 9

8

9

Parametric Measurement Information ............... 14

Detailed Description ............................................ 15

9.1 Block Diagram......................................................... 15

9.2 Register Map........................................................... 16

10 Application and Implementation........................ 18

10.1 Application Information.......................................... 18

10.2 Typical Applications .............................................. 23

11 Layout................................................................... 29

11.1 Board Layout......................................................... 29

12 器件和文档支持 ..................................................... 31

12.1 Trademarks........................................................... 31

12.2 Electrostatic Discharge Caution............................ 31

12.3 Glossary................................................................ 31

13 机械封装和可订购信息 .......................................... 31

5 修订历史记录

Changes from Original (November 2013) to Revision A

Page

•

已将文档修改为完整版。 ....................................................................................................................................................... 1

2

TPS22993

www.ti.com.cn

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

Device Comparison Table

TPS22993

R_ONTYPICAL AT 3.3 V (V_BIAS= 7.2V)

RISE TIME⁽¹⁾

15 mΩ

Programmable

1.2 A

(1)

ON DELAY

QUICK OUTPUT DISCHARGE⁽¹⁾⁽²⁾

MAXIMUM OUTPUT CURRENT (per channel)

GPIO ENABLE

Active High

–40°C to 85°C

OPERATING TEMP

(1) See Application Information section.

(2) This feature discharges output of the switch to GND through an internal resistor, preventing the output from floating. See Application

information section.

6 Terminal Configuration and Functions

Bottom View

Top View

11

12

13

14

15

14

13

12

11

NC

10

9

16

17

18

ON1

ON2

ADD2

SCL

10

9

16

17

18

ON1

ON2

ON3

ON4

ADD1

ADD2

SCL

8

ON3

VDD

SDA

8

VDD

SDA

ON4

7

6

19

20

7

6

19

20

ADD1

ADD3

NC

5

4

3

2

1

2

3

4

5

20-RLW (3mm x 3mm x 0.75mm)

3

TPS22993

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

www.ti.com.cn

Terminal Functions

Terminal

I/O

DESCRIPTION

NO.

NAME

NO

CONNECT

NC

-

Attached terminal to PCB. Leave the terminals floating or tie to GND.

1

2

VOUT2

VIN2

O

I

Channel 2 output.

Channel 2 input.

Bias voltage. Power supply to the device. Recommended voltage range for this terminal is 5.2V to 14V.

See Application Information section.

3

VBIAS

I

4

5

VIN1

I

O

I

Channel 1 input.

VOUT1

ADD1

ON4

Channel 1 output.

6

Device address terminal. Tie high or low. See Application Information section.

Active high channel 4 control input. Do not leave floating.

Active high channel 3 control input. Do not leave floating.

Active high channel 2 control input. Do not leave floating.

Active high channel 1 control input. Do not leave floating.

Channel 4 output.

7

I

8

ON3

I

9

ON2

I

10

11

12

13

14

15

16

17

ON1

I

VOUT4

VIN4

O

I

Channel 4 input.

GND

-

Device ground.

VIN3

I

Channel 3 input.

VOUT3

ADD2

SCL

O

I

Channel 3 output.

Device address terminal. Tie high or low. See Application Information section.

I

Serial clock input.

I²C device supply input. Tie this terminal to the I²C SCL/SDA pull-up voltage. See Application Information

section.

18

VDD

I

19

20

SDA

I/O

I

Serial data input/output.

ADD3

Device address terminal. Tie high or low. See Application Information section.

7 Specifications

7.1 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.0

4.5

1.62

0

MAX UNIT

V_INx

Input voltage for VIN1, VIN2, VIN3, VIN4

Supply voltage for VBIAS

3.6

17.2

3.6

5

V

V_BIAS

V_DD

Supply voltage for VDD

V

V_ADDx

V_ONx

V_OUTx

C_INx

Input voltage for ADD1, ADD2, ADD3

Input voltage for ON1, ON2, ON3, ON4

Output voltage for VOUT1, VOUT2, VOUT3, VOUT4

Input capacitor on VIN1, VIN2, VIN3, VIN4

V

0

V

0

V_INx

V

(1)

1

µF

(1) Refer to application section.

4

TPS22993

www.ti.com.cn

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

7.2 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

VALUE

UNIT⁽²⁾

MIN

–0.3

MAX

V_INx

Input voltage for VIN1, VIN2, VIN3, VIN4

Supply voltage for VBIAS

4

V

V_BIAS

20

4

V_OUTx

V_DD, V_SCL

V_SDA, V_ADDx

V_ONx

I_MAX

Output voltage for VOUT1, VOUT2, VOUT3, VOUT4

,

Input voltage for VDD, SCL, SDA, ADD1, ADD2, ADD3

–0.3

4

V

Input voltage for ON1, ON2, ON3, ON4

Maximum continuous switch current per channel

Operating free-air temperature⁽³⁾

6

1.2

85

V

A

T_A

–40

125

°C

T_J

Maximum junction temperature

125

300

T_LEAD

Maximum lead temperature (10-s soldering time)

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature [TA(max)] is dependent on the maximum operating junction temperature [T_J(max)],

the maximum power dissipation of the device in the application [PD(max)], and the junction-to-ambient thermal resistance of the

part/package in the application (_θJA), as given by the following equation: T_A(max)= T_J(max)– (θ_JA× P_D(max)

)

7.3 Handling Ratings

MIN

MAX

150

UNIT

°C

V

T_stg

Storage temperature

–65

Human-Body Model (HBM)⁽²⁾

Charged-Device Model (CDM)⁽³⁾

2000

500

ESD⁽¹⁾

Electrostatic discharge protection

V

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in

to the device.

(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500V HBM allows safe

manufacturing with a standard ESD control process.

(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250V CDM allows safe

manufacturing with a standard ESD control process.

7.4 Thermal Information

TPS22993

THERMAL METRIC⁽¹⁾⁽²⁾

UNIT

RLW

(20 TERMINALS)

Θ_JA

Junction-to-ambient thermal resistance

58

24

Θ_JC(top)

Θ_JB

Junction-to-case(top) thermal resistance

Junction-to-board thermal resistance

10

°C/W

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case(bottom) thermal resistance

0.7

10

Ψ_JB

Θ_JC(bottom)

N/A

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.

5

TPS22993

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

www.ti.com.cn

7.5 Electrical Characteristics

The specification applies over the operating ambient temperature –40°C ≤ T_A≤ 85°C (Full) (unless otherwise noted). Typical

values are for T_A= 25°C. V_BIAS= 7.2V (unless otherwise noted).

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX

UNIT

POWER SUPPLIES CURRENTS AND LEAKAGES

V_BIAS= 4.5V

V_BIAS= 5.2V

V_BIAS= 7.2V

V_BIAS= 10.8V

V_BIAS= 12.6V

V_BIAS= 17.2V

V_BIAS= 4.5V

V_BIAS= 5.2V

V_BIAS= 7.2V

V_BIAS= 10.8V

V_BIAS= 12.6V

V_BIAS= 17.2V

V_DD= 1.8V

14.8

14.9

16.2

16.6

16.7

16.8

7.7

26

28

30

15

16

2

I_OUT1,2,3,4= 0 A,

V_IN1,2,3,4= 3.6 V,

V_ON1,2,3,4= 3.6 V,

V_DD= 0 V

Quiescent current for VBIAS

(all four channels)

Full

µA

I_{Q, VBIAS}

7.8

I_OUT1,2,3,4= 0A,

8.5

V_IN1= V_ON1= 3.6V,

V_IN2,3,4= V_ON2,3,4= 0V,

V_DD= 0V

Quiescent current for VBIAS

(single channel)

Full

µA

8.7

8.8

8.9

I_OUT1,2,3,4= 0A,

0.6

I_{Q, VDD}

Quiescent current for VDD

V_IN1,2,3,4= V_ON1,2,3,4= 3.6V,

f_SCL= 0Hz

Full

µA

V_DD= 3.6V

V_DD= 1.8V

V_DD= 3.6V

1.2

2

20

35

I_OUT1,2,3,4= 0A,

V_IN1,2,3,4= V_ON1,2,3,4= 3.6V,

f_SCL= 1MHz

Average dynamic current for

VDD during I²C

communication

I_{DYN, VDD}

V_BIAS= 5.2V

V_BIAS= 7.2V

V_BIAS= 10.8V

V_BIAS= 12.6V

V_BIAS= 5.2V

V_BIAS= 7.2V

V_BIAS= 10.8V

V_BIAS= 12.6V

85

75

I_OUT1,2,3,4= 0A,

V_IN1,2,3,4= V_ON1,2,3,4= 3.6V,

f_SCL=1MHz

Average dynamic current for

VBIAS (all four channels)

during I²C communication

Full

µA

I_{DYN, VBIAS}

I_OUT1,2,3,4= 0A,

Average dynamic current for

VBIAS (single channel) during

I²C communication

V_IN1= V_ON1= 3.6V,

V_IN2,3,4= V_ON2,3,4= 0V,

f_SCL=1MHz

V_ON1,2,3,4= 0V, V_OUT1,2,3,4= 0V, V_DD= 3.6V,

V_BIAS= 17.2V

Shutdown current for VBIAS

(all four channels)

I_{SD, VBIAS}

I_{SD, VDD}

Full

5.7

1.2

13

2

µA

V_ON1,2,3,4= 0V, V_OUT1,2,3,4= 0V,

V_DD= 3.6V

Shutdown current for VDD

V_INx= 3.3V

0.009

0.006

0.01

4

3

V_INx= 1.8V

V_INx= 1.5V

V_INx= 1.05V

I_{SD, VINx}

Shutdown current for VINx

V_ONx= 0V, V_OUTx= 0V, V_DD= 3.6V

Full

µA

3

2.5

0.1

0.2

I_ONx

I_ADDx

I_SCL

I_SDA

Leakage current for ONx

Leakage current for ADDx

Leakage current for SCL

Leakage current for SDA

V_ONx= 5V

Full

µA

V_ADDx= 3.6V

V_SCL= 3.6V

V_SDA= 3.6V

0.01

RESISTANCE CHARACTERISTICS

25°C

Full

15

20

22

20

22

20

22

20

22

20

22

V_IN= 3.3V

V_IN= 2.5V

V_IN= 1.8V

V_IN= 1.5V

V_IN= 1.05V

mΩ

25°C

Full

25°C

Full

R_ON

On-state resistance

V_BIAS= 7.2V, I_OUT= –200mA

25°C

Full

25°C

Full

6

TPS22993

www.ti.com.cn

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

Electrical Characteristics (continued)

The specification applies over the operating ambient temperature –40°C ≤ T_A≤ 85°C (Full) (unless otherwise noted). Typical

values are for T_A= 25°C. V_BIAS= 7.2V (unless otherwise noted).

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX

25

28

22

24

20

23

20

22

20

22

UNIT

25°C

Full

18

V_IN= 3.3V

_VIN= 2.5V

V_IN= 1.8V

V_IN= 1.5V

V_IN= 1.05V

mΩ

25°C

Full

16

15

mΩ

25°C

Full

R_ON

On-state resistance

V_BIAS= 5.2V, I_OUT= –200mA

25°C

Full

25°C

Full

V_IN= 3.3V, V_ON= 0V, I_OUT= 1mA, QOD[1:0] = 00

V_IN= 3.3V, V_ON= 0V, I_OUT= 1mA, QOD[1:0] = 01

V_IN= 3.3V, V_ON= 0V, I_OUT= 1mA, QOD[1:0] = 10

V_IN= 3.3V, V_ON= 0V, I_OUT= 1mA, QOD[1:0] = 11

25°C

110

483

949

R_PD

Output pulldown resistance

Ω

No

QOD

THRESHOLD CHARACTERISTICS

High-level input voltage for

ADDx

V_{IH, ADDx}

V_{IL, ADDx}

V_{IH, ONx}

V_{IL, ONx}

Full

0.7×V_DD

V_DD

0.3×V_DD

5

V

Low-level input voltage for

ADDx

0

1.05

0

High-level input voltage for

ONx

Low-level input voltage for

ONx

0.4

V_BIAS= 5.2V

V_BIAS= 7.2V

V_BIAS= 10.8V

V_BIAS= 12.6V

130

V_{HYS, ONx}

Hysteresis for ONx

Full

mV

I²C CHARACTERISTICS

(1)

f_SCL

Clock frequency

Full

1

MHz

ns

(1)

t_{SU, SDA}

t_{HD, SDA}

I_{OL, SDA}

Setup time for SDA

Hold time for SDA

f_SCL= 1MHz (fast mode plus)

V_OL,SDA= 0.4V

50

0

Full

ns

SDA output low current

25°C

8

mA

High-level input voltage for

SDA

V_{IH, SDA}

V_{IH, SCL}

V_{IL, SDA}

V_{IL, SCL}

Full

0.7×V_DD

V_DD

V

High-level input voltage for

SCL

0.7×V_DD

Low-level input voltage for

SDA

0

0.3×V_DD

Low-level input voltage for

SCL

(1) Parameter verified by design.

7

TPS22993

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

www.ti.com.cn

7.6 Switching Characteristics

Values below are typical values at T_A= 25°C. V_BIAS= 7.2V (unless otherwise noted).

VIN VOLTAGE

PARAMETER

TEST CONDITION

UNIT

3.3V

11

1.8V

1.5V

11

1.05V

Slew rate[4:2] = 000

Slew rate[4:2] = 001

Slew rate[4:2] = 010

Slew rate[4:2] = 011

Slew rate[4:2] = 100

11

181

302

549

1066

2

11

146

243

438

848

2

V_BIAS= 7.2V,

247

416

761

1481

2

167

279

505

980

2

R_L=10Ω, C_L=0.1µF,

QOD[1:0] = 10,

ON-delay[6:5] = 00

t_ON

t_OFF

t_R

VOUTx turn-on time

VOUTx turn-off time

VOUTx rise time

µs

V_BIAS= 7.2V, R_L=10Ω, C_L=0.1µF, QOD[1:0] = 10, ON-delay[6:5] = 00

Slew rate[4:2] = 000

2

1.1

1

0.8

147

248

459

888

2

Slew rate[4:2] = 001

307

527

970

1898

2

203

346

638

1245

2

180

307

566

1105

2

V_BIAS= 7.2V, R_L=10Ω, C_L=0.1µF,

QOD[1:0] = 10, ON-delay[6:5] = 00

Slew rate[4:2] = 010

Slew rate[4:2] = 011

Slew rate[4:2] = 100

t_F

VOUTx fall time

V_BIAS= 7.2V, R_L=10Ω, C_L=0.1µF, QOD[1:0] = 10, ON-delay[6:5] = 00

ON delay[4:2] = 00

µs

11

ON delay[4:2] = 01

ON delay[4:2] = 10

ON delay[4:2] = 11

102

324

923

104

332

946

105

334

953

106

338

965

V_BIAS= 7.2V, R_L=10Ω, C_L=0.1µF,

QOD[1:0] = 10, Slew rate[6:5] = 000

t_D

VOUTx ON delay time

8

TPS22993

www.ti.com.cn

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

7.7 Typical Characteristics

1.6

1.4

1.2

1

1.6

-40°C

25°C

85°C

-40°C

25°C

1.4

85°C

1.2

1

0.8

0.6

0.4

0.2

0

0.8

0.6

0.4

0.2

0

1.5

2

2.5

3

3.5

4

1.5

4.5

2

2.5

3

3.5

4

V_DD(V)

C001

C005

C002

C004

Figure 1. I_Q,VDDvs. V_DD

Figure 2. I_SD,VDDvs. V_DD

25

20

15

10

5

14

12

10

8

-40°C

25°C

85°C

-40°C

25°C

85°C

6

4

6.5

8.5

10.5

12.5

14.5

16.5

4.5

6.5

8.5

10.5

12.5

14.5

16.5

V_BIAS(V)

C003

Figure 3. I_Q,VBIASvs. V_BIAS(all channels)

Figure 4. I_Q,VBIASvs. V_BIAS(single channel)

0.35

0.3

8

7

6

5

4

3

2

1

0

-40°C

25°C

85°C

0.25

0.2

0.15

0.1

-40°C

25°C

85°C

0.05

0

1

1.5

2

2.5

V_IN(V)

3

3.5

6.5

8.5

10.5

12.5

14.5

16.5

V_BIAS(V)

C024

Figure 6. I_SD,VINvs. V_IN

Figure 5. I_SD,VBIASvs. V_DD

9

TPS22993

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

www.ti.com.cn

Typical Characteristics (continued)

60

50

40

30

20

10

0

20

VBIAS = 4.5V

VBIAS = 5.2V

VBIAS = 7.2V

VBIAS = 10.8V

VBIAS = 12.6V

VBIAS = 14V

VBIAS = 17.2V

18

16

14

12

10

8

6

4

-40°C

25°C

85°C

2

T_A= 25C, I_OUT= -200mA

V_BIAS= 7.2V, I_OUT= -200mA

0

1

1.5

2

2.5

V_IN(V)

3

3.5

1

1.5

2

2.5

3

3.5

V_IN(V)

C010

C009

C006

C008

Figure 8. R_ONvs. V_INvs. V_BIAS(T_A= 25°C)

Figure 7. R_ONvs. V_IN(V_BIAS= 7.2V)

3.5

3

3.5

VBIAS = 4.5V

VBIAS = 5.2V

VBIAS = 7.2V

VBIAS = 10.8V

VBIAS = 12.6V

VBIAS = 14V

VBIAS = 17.2V

VBIAS = 4.5V

VBIAS = 5.2V

3

VBIAS = 7.2V

VBIAS = 10.8V

2.5

2

2.5

VBIAS = 12.6V

VBIAS = 14V

VBIAS = 17.2V

2

1.5

1

1.5

1

0.5

0

0.5

T_A= 25°C

0.4

T_A= 25°C

1.6

0

0.8

1.2

1.6

2

1.2

0.8

0.4

0

V_ON(V)

C007

Figure 9. Output voltage vs. VOUT rising

Figure 10. Output voltage vs. VOUT falling

0.14

0.12

0.1

QOD = 00

QOD = 01

QOD = 10

T_A= 25°C

1400

1200

1000

800

600

400

200

0

0.08

0.06

0.04

0.02

0

25°C

V_IN= 3.3V

4.5

6.5

8.5

10.5

12.5

14.5

16.5

4.5

6.5

8.5

10.5

12.5

14.5

16.5

V_BIAS(V)

C023

Figure 12. R_PDvs. V_BIAS

Figure 11. V_{HYS, ONx}vs. V_BIAS

10

TPS22993

www.ti.com.cn

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

Typical Characteristics (continued)

2.5

350

300

250

200

150

100

-40°C

25°C

85°C

25°C

85°C

2

1.5

1

0.5

Slew rate [4:2] = 000, C_IN= 1µF, C_L= 0.1µF, R_L= 10ꢀ

Slew rate [4:2] = 001, C_IN= 1µF, C_L= 0.1µF, R_L= 10ꢀ

0

1

1.5

2

2.5

V_IN(V)

3

3.5

1

1.5

2

2.5

V_IN(V)

3

3.5

C015

C016

C018

C011

Figure 13. t_Rvs. V_IN(Slew rate [4:2] = 000)

Figure 14. t_Rvs. V_IN(Slew rate [4:2] = 001)

1000

900

800

700

600

500

400

300

600

500

400

300

200

100

-40°C

25°C

85°C

-40°C

25°C

85°C

Slew rate [4:2] = 011, C_IN= 1µF, C_L= 0.1µF, R_L= 10ꢀ

Slew rate [4:2] -= 010, C_IN= 1µF, C_L= 0.1µF, R_L= 10ꢀ

1.5

2

2.5

V_IN(V)

3

3.5

1

1.5

2

2.5

V_IN(V)

3

3.5

C017

Figure 15. t_Rvs. V_IN(Slew rate [4:2] = 010)

Figure 16. t_Rvs. V_IN(Slew rate [4:2] = 011)

14

12

10

8

2000

1800

1600

1400

1200

1000

800

-40°C

25°C

85°C

6

4

-40°C

2

25°C

ON delay [6:5] = 00, V_IN= 3.6V, C_IN= 1µF,

C_L= 0.1µF, R_L= 10ꢀ

85°C

16.5

Slew rate [4:2] = 100, C_IN= 1µF, C_L= 0.1µF, R_L= 10ꢀ

0

600

4.5

6.5 8.5

10.5

12.5

14.5

1.5

2

2.5

V_IN(V)

3

3.5

V_BIAS(V)

C019

Figure 18. t_Dvs. V_BIAS(ON delay [6:5] = 00)

Figure 17. t_Rvs. V_IN(Slew rate [4:2] = 100)

11

TPS22993

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

www.ti.com.cn

Typical Characteristics (continued)

102

320

310

300

290

280

270

260

250

100

98

96

94

92

90

-40°C

25°C

85°C

-40°C

25°C

85°C

ON delay [6:5] = 10, V_IN= 3.6V,

C_IN= 1µF, C_L= 0.1µF, R_L= 10ꢀ

ON delay [6:5] = 01, V_IN= 3.6V, C_IN= 1µF,

C_L= 0.1µF, R_L= 10ꢀ

88

4.5

6.5

8.5

10.5

12.5

14.5

16.5

4.5

1

6.5

8.5

10.5

12.5

14.5

16.5

V_BIAS(V)

C013

C012

C014

C021

Figure 19. t_Dvs. V_BIAS(ON delay [6:5] = 01)

Figure 20. t_Dvs. V_BIAS(ON delay [6:5] = 10)

900

800

700

600

500

400

300

-40°C

25°C

85°C

920

900

880

860

840

820

800

-40°C

25°C

ON delay [6:5] = 11, V_IN= 3.6V,

C_IN= 1µF, C_L= 0.1µF, R_L= 10ꢀ

Slew rate [4:2] = 011, C_IN= 1µF, C_L= 0.1µF, R_L= 10ꢀ

85°C

16.5

6.5

8.5

10.5

12.5

14.5

1

1.5

2

2.5

V_IN(V)

3

3.5

V_BIAS(V)

C020

Figure 21. t_Dvs. V_BIAS(ON delay [6:5] = 11)

Figure 22. t_ONvs. V_IN(V_BIAS= 7.2V)

4

3.5

3

4

3.5

3

-40°C

25°C

85°C

-40°C

25°C

85°C

2.5

2

2.5

2

1.5

1

1.5

1

0.5

0

0.5

0

Slew rate [4:2] = 011, C_IN= 1µF, C_L= 0.1µF, R_L= 10ꢀ

1.5

2

2.5

V_IN(V)

3

3.5

1

1.5

2

2.5

V_IN(V)

3

3.5

C022

Figure 23. t_Fvs. V_IN(V_BIAS= 7.2V)

Figure 24. t_OFFvs. V_IN(V_BIAS= 7.2V)

12

TPS22993

www.ti.com.cn

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

Typical Characteristics (continued)

Figure 26. Power up with different tD settings

Figure 25. +Power up with different slew rate settings

Figure 28. Power up with default settings

Figure 27. Power down with different QOD settings

Figure 29. Channel 1 powered up via GPIO control, and

control is switched over to I²C control without any glitches

on VOUT.

Figure 30. Enabling channel 1 across two TPS22993 devices

with the SwitchALL^TMcommand.

13

TPS22993

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

www.ti.com.cn

8 Parametric Measurement Information

VINx

VOUTx

C_IN= 1µF

ON

ONx

C_L

+

-

(A)

R_L

OFF

VBIAS

GND

TPS22993

GND

Single channel shown for clarity.

TEST CIRCUIT

V_ONx

50%

t_F

t_OFF

t_R

t_ON

V_OUTx

90%

V_OUTx

50%

10%

t_D

t_ON/t_OFFWAVEFORMS

(A) Rise and fall times of the control signal is 100ns.

(B) All switching measurements are done using GPIO control only.

Figure 31. Test Circuit and t_ON/t_OFFWaveforms

14

TPS22993

www.ti.com.cn

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

9 Detailed Description

9.1 Block Diagram

Power supply

and bandgap

VBIAS

VIN1

Driver

VOUT1

PD_EN

ON1

ON2

VIN2

GPIO ON

Buffer

ON3

Driver

ON4

VOUT2

PD_EN

ADD1

Address

Buffers &

Level Shifters

I2C

Digital Control

ADD2

ADD3

VIN3

Driver

VDD

VOUT3

SCL

SDA

I2C

PD_EN

SCL/SDA

Buffers &

Level Shifters

VIN4

Driver

VOUT4

PD_EN

* PD_EN = Pulldown Enable

15

TPS22993

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

www.ti.com.cn

9.2 Register Map

Configuration registers (default register values shown below)

Channel 1 configuration register (Address: 01h)

BIT

B7

B6

B5

B4

B3

B2

B1

B0

QUICK OUTPUT

DISCHARGE

DESCRIPTION

DEFAULT

X

ON-DELAY

SLEW RATE

1

X

0

1

0

Channel 2 configuration register (Address: 02h)

BIT

B7

B6

B5

B4

B3

B2

B1

B0

QUICK OUTPUT

DISCHARGE

DESCRIPTION

DEFAULT

X

ON-DELAY

SLEW RATE

1

X

0

1

0

Channel 3 configuration register (Address: 03h)

BIT

B7

B6

B5

B4

B3

B2

B1

B0

QUICK OUTPUT

DISCHARGE

DESCRIPTION

DEFAULT

X

ON-DELAY

SLEW RATE

1

X

0

1

0

Channel 4 configuration register (Address: 04h)

BIT

B7

B6

B5

B4

B3

B2

B1

B0

QUICK OUTPUT

DISCHARGE

DESCRIPTION

DEFAULT

X

ON-DELAY

SLEW RATE

1

X

0

1

0

Control register (default register values shown below)

Control register (Address: 05h)

BIT

B7

B6

B5

B4

B3

B2

B1

B0

GPIO/I²C ch GPIO/I²C ch GPIO/I²C ch GPIO/I²C ch ENABLE CH ENABLE CH ENABLE CH ENABLE CH

DESCRIPTION

DEFAULT

4

3

2

1

4

3

2

1

0

Mode registers (default register values shown below)

Mode1 (Address: 06h)

BIT

B7

X

B6

X

B5

X

B4

X

B3

B2

B1

B0

ENABLE CH ENABLE CH ENABLE CH ENABLE CH

DESCRIPTION

DEFAULT

4

3

2

1

X

0

Mode2 (Address: 07h)

BIT

B7

X

B6

X

B5

X

B4

X

B3

B2

B1

B0

ENABLE CH ENABLE CH ENABLE CH ENABLE CH

DESCRIPTION

DEFAULT

4

3

2

1

X

0

Mode3 (Address: 08h)

BIT

B7

X

B6

X

B5

X

B4

X

B3

B2

B1

B0

ENABLE CH ENABLE CH ENABLE CH ENABLE CH

DESCRIPTION

DEFAULT

4

3

2

1

X

0

16

TPS22993

www.ti.com.cn

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

Mode4 (Address: 09h)

BIT

B7

X

B6

X

B5

X

B4

X

B3

B2

B1

B0

ENABLE CH ENABLE CH ENABLE CH ENABLE CH

DESCRIPTION

DEFAULT

4

0

3

0

2

0

1

0

X

Mode5 (Address: 0Ah)

BIT

B7

X

B6

X

B5

X

B4

X

B3

B2

B1

B0

ENABLE CH ENABLE CH ENABLE CH ENABLE CH

DESCRIPTION

DEFAULT

4

3

2

1

X

0

Mode6 (Address: 0Bh)

BIT

B7

X

B6

X

B5

X

B4

X

B3

B2

B1

B0

ENABLE CH ENABLE CH ENABLE CH ENABLE CH

DESCRIPTION

DEFAULT

4

3

2

1

X

0

Mode7 (Address: 0Ch)

BIT

B7

X

B6

X

B5

X

B4

X

B3

B2

B1

B0

ENABLE CH ENABLE CH ENABLE CH ENABLE CH

DESCRIPTION

DEFAULT

4

3

2

1

X

0

Mode8 (Address: 0Dh)

BIT

B7

X

B6

X

B5

X

B4

X

B3

B2

B1

B0

ENABLE CH ENABLE CH ENABLE CH ENABLE CH

DESCRIPTION

DEFAULT

4

3

2

1

X

0

Mode9 (Address: 0Eh)

BIT

B7

X

B6

X

B5

X

B4

X

B3

B2

B1

B0

ENABLE CH ENABLE CH ENABLE CH ENABLE CH

DESCRIPTION

DEFAULT

4

3

2

1

X

0

Mode10 (Address: 0Fh)

BIT

B7

B6

X

B5

X

B4

X

B3

B2

B1

B0

ENABLE CH ENABLE CH ENABLE CH ENABLE CH

DESCRIPTION

DEFAULT

X

4

3

2

1

X

0

Mode11 (Address: 10h)

BIT

B7

B6

X

B5

X

B4

X

B3

B2

B1

B0

ENABLE CH ENABLE CH ENABLE CH ENABLE CH

DESCRIPTION

DEFAULT

X

4

3

2

1

X

0

Mode12 (Address: 11h)

BIT

B7

B6

X

B5

X

B4

X

B3

B2

B1

B0

ENABLE CH ENABLE CH ENABLE CH ENABLE CH

DESCRIPTION

DEFAULT

X

4

3

2

1

X

0

17

TPS22993

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

www.ti.com.cn

10 Application and Implementation

10.1 Application Information

10.1.1 I²C Control

When power is applied to VBIAS, the device comes up in its default mode of GPIO operation where the channel

outputs can be controlled solely via the ON terminals. At any time, if SDA and SCL are present and valid, the

device can be configured to be controlled via I²C (if in GPIO control) or GPIO (if in I²C control).

The control register (address 05h) can be configured for GPIO or I²C enable on a per channel basis.

10.1.1.1 Operating Frequency

The TPS22993 is designed to be compatible with fast-mode plus and operate up to 1MHz clock frequency for

bus communication. The device is also compatible with standard-mode (100kHz) and fast-mode (400kHz). This

device can reside on the same bus as high-speed mode (3.4MHz) devices, but the device is not designed to

respond to I²C commands for frequencies greater than 1MHz. See table below for characteristics of the fast-

mode plus, fast-mode, and standard-mode bus speeds.

Table 1. I²C Interface Timing Requirements⁽¹⁾

STANDARD

MODE

FAST MODE

PLUS (FM+)

I²C BUS

FAST MODE

I²C BUS

PARAMETER

UNIT

MIN

0

MAX

MIN

0

MAX

MIN

0

MAX

f_scl

t_sch

t_scl

t_sp

I²C clock frequency

I²C clock high time

I²C clock low time

I²C spike time

I²C serial data setup time

I²C serial data hold time

100

50

400

1000

kHz

μs

ns

μs

4

0.6

1.3

0.26

0.5

4.7

50

t_sds

t_sdh

t_icr

250

0

100

0

50

0

I2C input rise time

1000

20

300

120

t_buf

t_sts

t_sth

t_sps

I²C bus free time between Stop and Start

I²C Start or repeater Start condition setup time

I²C Start or repeater Start condition hold time

I²C Stop condition setup time

4.7

4

1.3

0.6

0.3

0.5

0.26

4

t_vd(data)Valid data time; SCL low to SDA output valid

3.45

0.9

0.45

Valid data time of ACK condition; ACK signal from SCL

low to SDA (out) low

t_vd(ack)

0.3

μs

(1) over operating free-air temperature range (unless otherwise noted)

18

TPS22993

www.ti.com.cn

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

10.1.1.2 SDA/SCL Terminal Configuration

The SDA and SCL terminals of the device operate use an open-drain configuration, and therefore, need pull up

resistors to communicate on the I²C bus. The graph below shows recommended values for max pullup resistors

(R_P) and bus capacitances (C_b) to ensure proper bus communications. The SDA and SCL terminals should be

pulled up to VDD through an appropriately sized R_Pbased on the graphs below.

10.1.1.3 Address (ADDx) Terminal Configuration

The TPS22993 can be configured with an unique I²C slave addresses by using the ADDx terminals. There are 3

ADDx terminals that can be tied high to VDD or low to GND (independent of each other) to get up to 7 different

slave addresses. The ADDx terminals should be tied to GND if the I²C functionality of the device is not to be

used. External pull-up resistors for the ADDx are optional as the ADDx inputs are high impedance. The following

table shows the ADDx terminal tie-offs with their associated slave addresses (assuming an eight bit word, where

the LSB is the read/write bit and the device address bits are the 7 MSB bits) :

Hex Address

E0/E1

ADD3

GND

VDD

ADD2

ADD1

GND

VDD

GND

VDD

GND

VDD

GND

E2/E3

GND

E4/E5

VDD

E6/E7

VDD

E8/E9

GND

EA/EB

EC/ED

GND

VDD

Invalid unique device address.

EE

This address is the SwitchALL^TMaddress.

10.1.2 GPIO Control

There are four ON terminals to enable/disable the four channels. Each ON terminal controls the state of the

switch by default upon power up. Asserting ON high enables the switch. ON is active high and has a low

threshold, making it capable of interfacing with low-voltage signals. The ON terminal is compatible with standard

GPIO logic threshold. It can be used with any microcontroller with 1.2V or higher voltage GPIO.

10.1.3 On-Delay Control

Using the I²C interface, the configuration register for each channel can be set for different ON delays for power

sequencing. The options for delay are as follows:

00 = 11µs delay (default register value)

01 = 105µs delay

10 = 330µs delay

11 = 950µs delay

19

TPS22993

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

www.ti.com.cn

10.1.4 Slew Rate Control

Using the I²C interface, the configuration register for each channel can be set for different slew rates for inrush

current control and power sequencing. The options for slew rate are as follows:

000 = 1µs/V

001 = 150µs/V

010 = 250µs/V

011 = 460µs/V (default register value)

100 = 890µs/V

101 = invalid slew rate

110 = invalid slew rate

111 = reserved

10.1.5 Quick Output Discharge (QOD) Control

Using the I²C interface, the configuration register for each channel can be set for different output discharge

resistors. The options for QOD are as follows:

00 = 110Ω

01 = 490Ω

10 = 951Ω (default register value)

11 = No QOD (high impedance)

10.1.6 Mode Registers

Using the I²C interface, the mode registers can be programmed to the desired on/off status for each channel.

The contents of these registers are copied over to the control registers when a SwitchALL™ command is issued,

allowing all channels of the device to transition to their desired output states synchronously. See the I²C Protocol

section and the Application Scenario section for more information on how to use the mode registers in

conjunction with the SwitchALL^TMcommand.

10.1.7 SwitchALL™ Command

I²C controlled channels can respond to a common slave address. This feature allows multiple load switches on

the same I²C bus to respond simultaneously. The SwitchALL™ address is EEh. During a SwitchALL™

command, the lower four bits (bits 0 through 3) of the mode register is copied to the lower four bits (bits 0

through 3) of the control register. The mode register to be invoked is referenced in the body of the SwitchALL™

command. The structure of the SwitchALL™ command is as follows (as shown in Figure 32):

<start><SwitchALL™ addr><mode addr><stop>. See the I²C Protocol section and the Application Scenario

section for more information on how to use the SwitchALL^TMcommand in conjunction with the mode registers.

SCL

SwitchALL^TMAddress

Mode Register Address

SDA ST 1

1

0

1

0

A D7 D6 D5 D4 D3 D2 D1 D0 A SP

Start

W/R

Ack

from

slave

Ack. from slave

Figure 32. Composition of SwitchALL™ Command

10.1.8 V_DDSupply For I²C Operation

Stop

The SDA and SCL terminals of the device must be pulled up to the VDD voltage of the device for proper I²C bus

communication.

20

TPS22993

www.ti.com.cn

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

10.1.9 Input Capacitor (Optional)

To limit the voltage drop on the input supply caused by transient in-rush currents when the switch turns on into a

discharged load capacitor or short-circuit, a capacitor needs to be placed between V_INand GND. A 1-µF ceramic

capacitor, C_IN, placed close to the terminals, is usually sufficient. Higher values of C_INcan be used to further

reduce the voltage drop during high-current application. When switching heavy loads, it is recommended to have

an input capacitor about 10 times higher than the output capacitor to avoid excessive voltage drop. For the

fastest slew rate setting of the device, a CIN to CL ratio of at least 100 to 1 is recommended to avoid excessive

voltage drop.

10.1.10 Output Capacitor (Optional)

Due to the integrated body diode of the NMOS switch, a C_INgreater than C_Lis highly recommended. A C_L

greater than C_INcan cause V_OUTto exceed V_INwhen the system supply is removed. This could result in current

flow through the body diode from V_OUTto V_IN. A C_INto C_Lratio of at least 10 to 1 is recommended for minimizing

V_INdip caused by inrush currents during startup. For the fastest slew rate setting of the device, a CIN to CL ratio

of at least 100 to 1 is recommended to minimize V_INdip caused by inrush currents during startup.

10.1.11 I²C Protocol

The following section will cover the standard I²C protocol used in the TPS22993. In the I²C protocol, the following

basic blocks are present in every command (except for the SwitchALL^TMcommand):

•

Start/stop bit – marks the beginning and end of each command.

Slave address – the unique address of the slave device.

Sub address – this includes the register address and the auto-increment bit.

Data byte – data being written to the register. Eight bits must always be transferred even if a single bit is

being written or read.

•

Auto-increment bit – setting this bit to ‘1’ turns on the auto-increment functionality; setting this bit to ‘0’ turns

off the auto-increment functionality.

Write/read bit – this bit signifies if the command being sent will result in reading from a register or writing to a

register. Setting this bit to ‘0’ signifies a write, and setting this bit to ‘1’ signifies a read.

Acknowledge bit – this bit signifies if the master or slave has received the preceding data byte.

10.1.11.1 Start and Stop Bit

In the I²C protocol, all commands contain a START bit and a STOP bit. A START bit, defined by high to low

transition on the SDA line while SCL is high, marks the beginning of a command. A STOP bit, defined by low to

high transition on the SDA line while SCL is high, marks the end of a command. The START and STOP bits are

generated by the master device on the I²C bus. The START bit indicates to other devices that the bus is busy,

and some time after the STOP bit the bus is assumed to be free.

10.1.11.2 Auto-increment Bit

The auto-increment feature in the I²C protocol allows users to read from and write to consecutive registers in

fewer clock cycles. Since the register addresses are consecutive, this eliminates the need to resend the register

address. The I²C core of the device automatically increments the register address pointer by one when the auto-

increment bit is set to ‘1’. When this bit is set to ‘0’, the auto-increment functionality is disabled.

10.1.11.3 Write Command

During the write command, the write/read bit is set to ‘0’, signifying that the register in question will be written to.

Figure 33 the composition of the write protocol to a single register:

SCL

Slave Address

Sub Address

Data Byte

SDA ST A6 A5 A4 A3 A2 A1 A0

0

A

0

A

D7 D6 D5 D4 D3 D2 D1 D0

A

D7 D6 D5 D4 D3 D2 D1 D0 A SP

Start

W/R

Ack. from slave

Auto-Inc.

Ack

from

slave

Data to Register N

Ack

from

slave

Data to Register N

Ack Stop

from

slave

Register Address N

Figure 33. Data Write to a Single Register

21

TPS22993

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

www.ti.com.cn

Number of clock cycles for single register write: 29

If multiple consecutive registers must be written to, a short-hand version of the write command can be used.

Using the auto-increment functionality of I²C, the device will increment the register address after each byte.

Figure 34 shows the composition of the write protocol to multiple consecutive registers:

SCL

Slave Address

Sub Address

Data Byte

SDA ST A6 A5 A4 A3 A2 A1 A0

0

A

1

0

A

D7 D6 D5 D4 D3 D2 D1 D0

A

D7 D6 D5 D4 D3 D2 D1 D0 A

Start

W/R

Ack. from slave

Auto-Inc.

Ack

from

slave

Data to Register N

Ack

from

slave

Data to Register N+1 Ack

from

slave

Register Address N

Figure 34. Data Write to Consecutive Registers

Number of clock cycles for consecutive register write: 20 + (Number of registers) x 9

The write command is always ended with a STOP bit after the desired registers have been written to. If multiple

non-consecutive registers must be written to, then the format in Figure 33 must be followed.

10.1.11.4 Read Command

During the read command, the write/read bit is set to ‘1’, signifying that the register in question will be read from.

However, a read protocol includes a “dummy” write sequence to ensure that the memory pointer in the device is

pointing to the correct register that will be read. Failure to precede the read command with a write command may

result in a read from a random register. Figure 35 shows the composition of the read protocol to a single register:

SCL

Slave Address

Sub Address

Slave Address

Data Byte

SDA ST A6 A5 A4 A3 A2 A1 A0

0

A

0

A

RS A6 A5 A4 A3 A2 A1 A0

1

A

D7 D6 D5 D4 D3 D2 D1 D0 NA SP

Start

W/R

Ack. from slave

Auto-Inc.

Ack Re-Start

from

slave

W/R

Data from Register N

Stop

Register Address

Ack. from slave

No Ack. from master (message ends)

Continued

Figure 35. Data Read to a Single Register

Number of clock cycles for single register read: 39

If multiple registers must be read from, a short-hand version of the read command can be used. Using the auto-

increment functionality of I²C, the device will increment the register address after each byte. Figure 36 shows the

composition of the read protocol to multiple consecutive registers:

SCL

Slave Address

Sub Address

Slave Address

Data Byte

SDA ST A6 A5 A4 A3 A2 A1 A0

0

A

1

0

A RS A6 A5 A4 A3 A2 A1 A0

1

A

D7 D6 D5 D4 D3 D2 D1 D0

Start

W/R

Ack. from slave

Auto-Inc.

Ack Re-Start

from

slave

W/R

Ack. from slave

Data from Register N

Register Address

Continued

Data Byte

A

D7 D6 D5 D4 D3 D2 D1 D0

Data from Register N+1

A D7 D6 D5 D4 D3 D2 D1 D0 NA SP

Data from Register N+2

Stop

Ack. from master

No Ack. from master (Message ends)

Figure 36. Data Read to Consecutive Registers

Number of clock cycles for consecutive register write: 30 + (Number of registers) x 9

22

TPS22993

www.ti.com.cn

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

The read command is always ended with a STOP bit after the desired registers have been read from. If multiple

non-consecutive registers must be read from, then the format in Figure 35 must be followed.

10.1.11.5 SwitchALL^TMCommand

The SwitchALL^TMcommand allows multiple devices in the same I²C bus to respond synchronously to the same

command from the master. Every TPS22993 device has a shared address which allows for multiple devices to

respond or execute a pre-determined action with a single command. Figure 37 shows the composition of the

SwitchALL^TMcommand:

SCL

SwitchALL^TMAddress

Mode Register Address

SDA ST 1

Start

1

0

1

0

A D7 D6 D5 D4 D3 D2 D1 D0 A SP

W/R

Ack

from

slave

Ack. from slave

Stop

Figure 37. SwitchALL^TMCommand Structure

Number of clock cycles for a SwitchALL^TMcommand: 20

10.2 Typical Applications

This section will cover applications of I²C in the TPS22993. Registers discussed here are specific to the

TPS22993.

10.2.1 Switch from GPIO Control to I²C Control (and vice versa)

The TPS22993 can be switched from GPIO control to I²C (and vice versa) mode by writing to the control register

of the device. Each device has a single control register and is located at register address 05h. The register’s

composition is as follows:

Control register (Address: 05h)

BIT

B7

B6

B5

B4

B3

B2

B1

B0

DESCRIPTION

GPIO/I²C CH GPIO/I²C CH GPIO/I²C CH GPIO/I²C CH ENABLE CH ENABLE CH ENABLE CH ENABLE CH

4

0

3

0

2

0

1

0

4

0

3

0

2

0

1

0

DEFAULT

Figure 38. Control Register Composition

The higher four bits of the control register dictates if the device is in GPIO control (bit set to ‘0’) or I²C control (bit

set to ‘1’). The transition from GPIO control to I²C control can be made with a single write command to the

control register. See Figure 33 for the composition of a single write command. It is recommended that the

channel of interest is transitioned from GPIO control to I²C control with the first write command and followed by a

second write command to enable the channel via I²C control. This will ensure a smooth transition from GPIO

control to I²C control.

10.2.2 Configuration of Configuration Registers

The TPS22993 contains four configuration registers (one for each channel) and are located at register addresses

01h through 04h. The register’s composition is as follows (single channel shown for clarity):

23

TPS22993

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

www.ti.com.cn

Channel 1 configuration register (Address: 01h)

BIT

B7

B6

B5

B4

B3

B2

B1

B0

DESCRIPTION

X

ON-DELAY

SLEW RATE

QUICK OUTPUT

DISCHARGE

DEFAULT

X

0

1

0

1

0

Figure 39. Configuration Register Composition

10.2.2.1 Single Register Configuration

A single configuration register can be written to using the write command sequence shown in Figure 33.

Multiple register writes to non-consecutive registers is treated as multiple single register writes and follows the

same write command as that of a single register write as shown in Figure 33.

10.2.2.2 Multi-register Configuration (Consecutive Registers)

Multiple consecutive configuration registers can be written to using the write command sequence shown in

Figure 34.

10.2.3 Configuration of Mode Registers

The TPS22993 contains twelve mode registers located at register addresses 06h through 11h. These mode

registers allow the user to turn-on or turn-off multiple channels in a single TPS22993 or multiple channels

spanning multiple TPS22993 devices with a single SwitchALL^TMcommand.

For example, an application may have multiple power states (e.g. sleep, active, idle, etc.) as shown in Figure 40.

SwitchALL^TMcommand with Mode2

register

SwitchALL^TMcommand with Mode1

register

Sleep

Active

Idle

Figure 40. Application Example of Power States

In each of the different power states, different combinations of channels may be on or off. Each power state may

be associated with a single mode register (Mode1, Mode2, etc.) across multiple TPS22993 as shown in Table 2.

For example, with 7 quad-channel devices, up to 28 rails can be enabled/disabled with a single SwitchALL^TM

command.

Table 2. Application Example of State of Each Channel in Multiple TPS22993 in Different Power States

Load Switch #1

Load Switch #2

Load Switch #N

Mode

Register

Power

State

Ch. 1

Off

Ch. 2

Off

Ch. 3

Off

Ch. 4

Off

Ch. 1

Off

Ch. 2

Off

Ch. 3

Off

Ch. 4

Off

Ch. 1

Off

Ch. 2

Off

Ch. 3

Off

Ch. 4

Off

Mode1

Mode2

Mode3

Sleep

Active

Idle

On

Off

On

Off

On

Off

On

Off

On

Off

On

Off

On

24

TPS22993

www.ti.com.cn

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

The contents of the lower four bits of the mode register is copied into the lower four bits of the control register

during an SwitchALL^TMcommand. The address of the mode register to be copied is specified in the SwitchALL^TM

command (see Figure 37 for the structure of the SwitchALL^TMcommand). By executing a SwitchALL^TM

command, the application will apply the different on/off combinations for the various power states with a single

command rather than having to turn on/off each channel individually by re-configuring the control register. This

reduces the latency and allows the application to control multiple channels synchronously. The example above

shows the application using three mode registers, but the TPS22993 contains twelve mode registers, allowing for

up to twelve power states.

The mode register’s composition is as follows (single mode register shown for clarity):

Mode1 (Address: 06h)

BIT

B7

B6

B5

B4

B3

B2

B1

B0

DESCRIPTION

X

ENABLE

CH 4

ENABLE

CH 3

ENABLE

CH 2

ENABLE

CH 1

DEFAULT

X

0

Figure 41. Mode Register Composition

The lower four bits of the mode registers are copied into the lower four bits of the control register during an all-

call command.

25

TPS22993

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

www.ti.com.cn

10.2.4 Turn-on/Turn-off of Channels

By default upon power up VBIAS, all the channels of the TPS22993 are controlled via the ONx terminals. Using

the I²C interface, each channel be controlled via I²C control as well. The channels of the TPS22993 can also be

switched on or off by writing to the control register of the device. Each device has a single control register and is

located at register address 05h. The register’s composition is as follows:

Control Register (Address: 05h)

BIT

B7

B6

B5

B4

B3

B2

B1

B0

GPIO/I²C CH GPIO/I²C CH GPIO/I²C CH GPIO/I²C CH ENABLE CH ENABLE CH ENABLE CH ENABLE CH

DESCRIPTION

DEFAULT

4

0

3

0

2

0

1

0

4

0

3

0

2

0

1

0

Figure 42. Control Register Composition

The lower four bits of the control register dictate if the channels of the device are off (bit set to ‘0’) or on (bit set

to ‘1’) during I²C control. The transition from off to on can be made with a single write command to the control

register. See Figure 33 for the composition of a single write command.

10.2.5 Tying Multiple Channels in Parallel

Two or more channels of the device can be tied in parallel for applications that require lower R_ONand/or more

continous current. Tying two channels in parallel will result in half of the R_ONand two times the I_MAXcapability.

Tying three channels in parallel will result in one-third of the R_ONand three times the I_MAXcapability. Tying four

channels in parallel will result in one-fourth of the R_ONand four times the I_MAXcapability. For the channels that

are tied in parallel, it is recommended that the ONx terminals be tied together for synchronous control of the

channels when in GPIO control. In I²C control, all four channels can be enabaled or disabled synchronously by

writing to the control register of the device. Figure 43 shows an application example of tying all four channels in

parallel.

VBIAS

(4.5V to 17.2V)

VIN1

VOUT1

PMIC or

PMU

ON1

C_L

R_L

VIN2

VOUT2

VOUT3

ON2

TPS22993

VIN3

ON3

VOUT4

VIN4

ON4

ADD1

GPIO >>

ADD2

ADD3

SDA SCL

µC

VDD

(1.62 to 3.6)

Figure 43. Parallel Channels

26

TPS22993

www.ti.com.cn

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

10.2.6 Cold Boot Programming of all Registers

Since the TPS22993 has a digital core with volatile memory, upon power cycle of the VBIAS terminal, the

registers will revert back to their default values (see register map for default values). Therefore, the application

must reprogram the configuration registers, control register, and mode registers if non-default values are desired.

The TPS22993 contains 17 programmable registers (4 configuration registers, 1 control register, 12 mode

registers) in total.

During cold boot when the microcontroller and the I²C bus is not yet up and running, the channels of the

TPS22993 can still be enabled via GPIO control. One method to achieve this is to tie the ONx terminal to the

respective VINx terminal for the channels that need to turn on by default during cold boot. With this method,

when VINx is applied to the TPS22993, the channel will be enabled as well. Once the I²C bus is active, the

channel can be switched over to I²C control to be disabled. See Figure 44 for an example of how the ONx

terminals can be tied to VINx for default enable during cold boot.

VBIAS

(4.5V to 17.2V)

VIN1

VOUT1

ON1

C_L

R_L

VIN2

VOUT2

VOUT3

ON2

PMIC or

PMU

TPS22993

VIN3

ON3

VOUT4

VIN4

ON4

ADD1

C_L

R_L

ADD2

ADD3

SDA SCL

µC

VDD

(1.62 to 3.6)

Figure 44. Cold Boot Programming

It is also possible to power sequence the channels of the device during a cold boot when there is no I²C bus

present for control. One method to accomplish this it to tie the VOUT of one channel to the ON terminal of the

next channel in the sequence. For example, if the desired power up sequence is VOUT3, VOUT1, VOUT2, and

VOUT4 (in that order), then the device can be configured for GPIO control as shown in Figure 45. The device will

power up with default slew rate, ON-delay, and QOD values as specified in the register map.

27

TPS22993

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

www.ti.com.cn

VBIAS

(4.5V to 17.2V)

VIN1

VOUT1

ON1

C_L

R_L

VIN2

VOUT2

VOUT3

ON2

PMIC or

PMU

TPS22993

VIN3

ON3

VOUT4

VIN4

ON4

ADD1

C_L

R_L

ADD2

ADD3

SDA SCL

µC

VDD

(1.62 to 3.6)

Figure 45. Power Sequencing Without I²C

10.2.7 Reading From the Registers

Reading any register from the TPS22993 follows the same standard I²C read protocol as outlined in the I²C

Protocol section of this datasheet.

28

TPS22993

www.ti.com.cn

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

11 Layout

11.1 Board Layout

For best performance, all traces should be as short as possible. To be most effective, the input and output

capacitors should be placed close to the device to minimize the effects that parasitic trace inductances may have

on normal operation. Using wide traces for VIN, VOUT, and GND helps minimize the parasitic electrical effects

along with minimizing the case to ambient thermal impedance.

The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. To

calculate the maximum allowable power dissipation, P_D(max)for a given output current and ambient temperature,

use the following equation:

T

_J(max)- T_A

P

=

D(max)

Q_JA

(1)

Where:

P_D(max)= maximum allowable power dissipation

T_J(max)= maximum allowable junction temperature (125°C for the TPS22993)

T_A= ambient temperature of the device

Θ_JA= junction to air thermal impedance. See Thermal Information section. This parameter is highly

dependent upon board layout.

The figure below shows an example of a layout.

Figure 46. Top View of the TPS22993 EVM

29

TPS22993

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

www.ti.com.cn

Board Layout (continued)

Figure 47. Bottom View of the TPS22993 EVM.

30

TPS22993

www.ti.com.cn

ZHCSBU6A –NOVEMBER 2013–REVISED MARCH 2014

12 器件和文档支持

12.1 Trademarks

SwitchALL is a trademark of Texas Instruments.

Ultrabook is a trademark of Intel.

12.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.3 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms and definitions.

13 机械封装和可订购信息

以下页中包括机械封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。要获得这份数据表的浏览器版本，请查阅左侧的导航栏。

31

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS22993
厂家：	TEXAS INSTRUMENTS
描述：	可通 I2C 进行控制的 4 通道、3.6V、1.2A、15mΩ 负载开关开关
文件：	总37页 (文件大小：1985K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS22993 [TI]

相关型号：

TPS22993RLWR

TPS22994

TPS22994RUKR

TPS22994RUKT

TPS22995

TPS22995H-Q1

TPS22995HQDDCRQ1

TPS22995RZFR

TPS22995RZGR

TPS22997

TPS22997RYZR

TPS22998