TPS43336QDAPRQ1 [TI]
LOW IQ, SINGLE BOOST, DUAL SYNCHRONOUS BUCK CONTROLLER; 低IQ ，单升压，双路同步降压控制器
| 型号： | TPS43336QDAPRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW IQ, SINGLE BOOST, DUAL SYNCHRONOUS BUCK CONTROLLER |
| 文件： | 总42页 (文件大小：1573K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS43335-Q1
TPS43336-Q1
www.ti.com
SLVSAV6B –JUNE 2011–REVISED JULY 2012
LOW IQ, SINGLE BOOST, DUAL SYNCHRONOUS BUCK CONTROLLER
Check for Samples: TPS43335-Q1, TPS43336-Q1
1
FEATURES
2
•
Qualified for Automotive Applications
•
•
•
Separate Enable Inputs (ENA, ENB)
•
AEC-Q100 Test Guidance With the Following
Results:
Frequency Spread Spectrum (TPS43332)
Selectable Forced Continuous Mode or
–
Device Temperature Grade 1: –40°C to
125°C Ambient Operating Temperature
Automatic Low-Power Mode at Light Loads
•
•
Sense Resistor or Inductor DCR Sensing
–
–
Device HBM ESD Classification Level H2
Device CDM ESD Classification Level C2
Out-of-Phase Switching Between Buck
Channels
•
•
•
Two Synchronous Buck Controllers
One Pre-Boost Controller
•
•
Peak Gate-Drive Current 0.7 A
Thermally Enhanced 38-Pin HTSSOP (DAP)
PowerPAD™ Package
Input Range up to 40 V, (Transients up to 60
V), Operation Down to 2 V When Boost is
Enabled
APPLICATIONS
•
Automotive Start-Stop, Infotainment,
Navigation Instrument Cluster Systems
•
Low Power Mode IQ: 30 µA (One Buck On),
35 µA (Two Bucks On)
•
Industrial and Automotive Multi-Rail DC Power
Distribution Systems and Electronic Control
Units
•
•
•
•
Low Shutdown Current Ish < 4 µA
Buck Output Range 0.9 V to 11 V
Boost Output Selectable: 7 V, 10 V, or 11 V
Programmable frequency and External
Synchronization Range 150 kHz to 600 kHz
DESCRIPTION
The TPS43335-Q1 and TPS43336-Q1 include two current-mode synchronous buck controllers and a voltage-
mode boost controller. The devices are ideally suited as a pre-regulator stage with low Iq requirements and for
applications that must survive supply drops due to cranking events. The integrated boost controller allows the
devices to operate down to 2 V at the input without seeing a drop on the buck regulator output stages. At light
loads, the buck controllers can be enabled to operate automatically in low-power mode, consuming just 30 µA of
quiescent current.
The buck controllers have independent soft-start capability and power-good indicators. External MOSFET
protection is provided by current foldback in the buck controllers and cycle-by-cycle current limitation in the boost
controller. The switching frequency can be programmed over 150 kHz to 600 kHz or synchronized to an external
clock in the same range. Additionally, the TPS43336-Q1 offers frequency-hopping spread-spectrum operation.
spacer
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
TPS43335-Q1
TPS43336-Q1
SLVSAV6B –JUNE 2011–REVISED JULY 2012
www.ti.com
VBAT
VBuckA
TPS43335-Q1/
TPS43336-Q1
VBuckB
2 V
Figure 1. Typical Application Diagram
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
TJ
OPTION
PACKAGE
ORDERABLE PART NUMBER
TPS43335QDAPRQ1
Frequency-hopping spread spectrum OFF
Frequency-hopping spread spectrum ON
–40ºC to 150ºC
DAP
TPS43336QDAPRQ1
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
2
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Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS43335-Q1 TPS43336-Q1
TPS43335-Q1
TPS43336-Q1
www.ti.com
SLVSAV6B –JUNE 2011–REVISED JULY 2012
space
ABSOLUTE MAXIMUM RATINGS(1)
MIN
–0.3
–0.3
–0.3
–0.7
–1
MAX UNIT
Voltage
Input voltage: VIN, VBAT
60
60
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
Enable inputs: ENA, ENB
Bootstrap inputs: CBA, CBB
Phase inputs: PHA, PHB
68
60
Phase inputs: PHA, PHB (for 150 ns)
Feedback inputs: FBA, FBB
Error amplifier outputs: COMPA, COMPB
High-side MOSFET driver: GA1-PHA, GB1-PHB
Low-side MOSFET drivers: GA2, GB2
Current-sense voltage: SA1, SA2, SB1, SB2
Soft start: SSA, SSB
60
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–40
13
13
Voltage
(buck function:
BuckA and BuckB)
8.8
8.8
13
13
Power-good output: PGA, PGB
Power-good delay: DLYAB
13
13
Switching-frequency timing resistor: RT
SYNC, EXTSUP
13
13
Low-side MOSFET driver: GC1
Error-amplifier output: COMPC
Enable input: ENC
8.8
13
Voltage
(boost function)
13
Current-limit sense: DS
60
Output-voltage select: DIV
8.8
60
P-channel MOSFET driver: GC2
P-channel MOSFET driver: VIN-GC2
Gate-driver supply: VREG
Voltage
(PMOS driver)
8.8
8.8
150
125
165
Junction temperature: TJ
Temperature
Operating temperature: TA
–40
Storage temperature: Tstg
–55
Human-body model (HBM) AEC-Q11
Classification Level H2
±2
kV
FBA, FBB, RT, DLYAB
VBAT, ENC, SYNC, VIN
All other pins
±400
±750
±500
±150
±200
Charged-device model (CDM) AEC-Q11
Classification Level C2
Electrostatic
discharge ratings
V
PGA, PGB
Machine model (MM)
All other pins
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to GND.
Copyright © 2011–2012, Texas Instruments Incorporated
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Product Folder Link(s): TPS43335-Q1 TPS43336-Q1
TPS43335-Q1
TPS43336-Q1
SLVSAV6B –JUNE 2011–REVISED JULY 2012
www.ti.com
THERMAL INFORMATION
TPS4333x-Q1
DAP
THERMAL METRIC(1)
UNIT
38 PINS
27.3
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
θJCtop
θJB
19.6
15.9
°C/W
ψJT
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
0.24
ψJB
6.6
θJCbot
1.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
40
UNIT
Input voltage: VIN, VBAT
Enable inputs: ENA, ENB
Boot inputs: CBA, CBB
Phase inputs: PHA, PHB
Current-sense voltage: SA1, SA2, SB1, SB2
Power-good output: PGA, PGB
SYNC, EXTSUP
4
0
40
4
–0.6
0
48
Buck function:
BuckA and BuckB
voltage
40
V
11
0
11
0
9
Enable input: ENC
0
9
Boost function
Voltage sense: DS
40
V
DIV
0
VREG
125
Operating temperature: TA
–40
°C
4
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Product Folder Link(s): TPS43335-Q1 TPS43336-Q1
TPS43335-Q1
TPS43336-Q1
www.ti.com
SLVSAV6B –JUNE 2011–REVISED JULY 2012
DC ELECTRICAL CHARACTERISTICS
VIN = 8 V to 18 V, TJ = –40°C to 150°C (unless otherwise noted)
NO.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.0
Input Supply
Boost controller enabled, after initial start-up
condition is satisfied
1.1
1.2
VBat
Supply voltage
2
6.5
4
40
40
40
3.8
4
V
Input voltage required for device
on initial start-up
VIN
V
Buck regulator operating range
after initial start-up
VIN falling. After a reset, initial start-up conditions
may apply.(1)
3.5
3.6
3.8
8.5
V
V
V
1.3
VIN UV
Buck undervoltage lockout
Boost unlock threshold
VIN rising. After a reset, initial start-up conditions
may apply.(1)
VBOOST_UNLOC
1.4
1.5
VBAT rising
8.2
8.8
K
VIN = 13 V, BuckA: LPM, BuckB: off, TA = 25°C
VIN = 13 V, BuckB: LPM, BuckA: off, TA = 25°C
VIN = 13 V, BuckA, B: LPM, TA = 25°C
VIN = 13 V, BuckA: LPM, BuckB: off, TA = 125°C
VIN = 13 V, BuckB: LPM, BuckA: off, TA = 125°C
VIN = 13 V, BuckA, B: LPM, TA = 125°C
SYNC = 5 V, TA = 25°C
30
35
40
45
40
45
50
55
µA
µA
µA
µA
LPM quiescent current:
Iq_LPM_
(2)
LPM quiescent current:
1.6
1.7
Iq_LPM
(2)
VIN = 13 V, BuckA: CCM, BuckB: off, TA = 25°C
VIN = 13 V, BuckB: CCM, BuckA: off, TA = 25°C
VIN = 13 V, BuckA, B: CCM, TA = 25°C
SYNC = 5 V, TA = 125°C
4.85
7
5.3
7.6
5.5
Quiescent current:
Iq_NRM
mA
mA
normal (PWM) mode(2)
VIN = 13 V, BuckA: CCM, BuckB: off, TA = 125°C
VIN = 13 V, BuckB: CCM, BuckA: off, TA = 125°C
VIN = 13 V, BuckA, B: CCM, TA = 125°C
BuckA, B: off, VBat = 13 V , TA = 25°C
BuckA, B: off, VBat = 13 V, TA = 125°C
5
Quiescent current:
1.8
Iq_NRM
normal (PWM) mode(2)
7.5
2.5
3
8
4
5
1.9
1.10
2.0
Ibat_sh
Ibat_sh
Shutdown current
Shutdown current
µA
µA
Input Voltage VBAT - Undervoltage Lockout
VBAT falling. After a reset, initial start-up
conditions may apply.(1)
1.8
1.9
2.5
2
V
V
2.1
VBATUV
Boost-input undervoltage
VBAT rising. After a reset, initial start-up
conditions may apply.(1)
2.4
2.6
2.2
2.3
3.0
UVLOHys
UVLOfilter
Hysteresis
Filter time
500
600
5
700
mV
µs
Input Voltage VIN - Overvoltage Lockout
VIN rising
VIN falling
45
43
1
46
44
2
47
45
3
3.1
VOVLO
Overvoltage shutdown
V
3.2
3.3
OVLOHys
OVLOfilter
Hysteresis
Filter time
V
5
µs
(1) If VBAT and VREG remain adequate, the buck can continue to operate if VIN is > 3.8 V.
(2) Quiescent current specification is non-switching current consumption without including the current in the external-feedback resistor
divider.
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TPS43335-Q1
TPS43336-Q1
SLVSAV6B –JUNE 2011–REVISED JULY 2012
www.ti.com
DC ELECTRICAL CHARACTERISTICS (continued)
VIN = 8 V to 18 V, TJ = –40°C to 150°C (unless otherwise noted)
NO.
4.0
4.1
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
Boost Controller
Vboost7-VIN
Boost VOUT = 7 V
DIV = low, VBAT = 2 V to 7 V
6.8
7.5
8
7
8
7.3
8.5
9
Boost-enable threshold
Boost-disable threshold
Boost hysteresis
Boost VOUT = 7 V, VBAT falling
Boost VOUT = 7 V, VBAT falling
Boost VOUT = 7 V, VBAT falling
DIV = open, VBAT = 2 V to 10 V
Boost VOUT = 10 V, VBAT falling
Boost VOUT = 10 V, VBAT falling
Boost VOUT = 10 V, VBAT falling
DIV = VREG, VBAT = 2 V to 11 V
Boost VOUT = 11 V, VBAT falling
Boost VOUT = 11 V, VBAT falling
Boost VOUT = 11 V, VBAT falling
4.2
4.3
4.4
4.5
4.6
Vboost7-th
8.5
0.5
10
V
0.4
9.7
10.5
11
0.6
10.4
11.5
12
Vboost10-VIN
Vboost10-th
Vboost11-VIN
Vboost11-th
Boost VOUT = 10 V
Boost-enable threshold
Boost-disable threshold
Boost hysteresis
V
11
11.5
0.5
11
V
0.4
10.7
11.5
12
0.6
11.4
12.5
13
Boost VOUT = 11 V
Boost-enable threshold
Boost-disable threshold
Boost hysteresis
V
12
12.5
0.5
V
0.4
0.6
Boost-Switch Current Limit
4.7
4.8
VDS
tDS
Current-limit sensing
Leading-edge blanking
DS input with respect to PGNDA
0.175
0.2
0.225
V
200
ns
Gate Driver for Boost Controller
IGC1 Peak Gate-driver peak current
rDS(on) Source and sink driver
Gate Driver for PMOS
4.9
1.5
A
4.10
VREG = 5.8 V, IGC1 current = 200 mA
2
20
10
Ω
4.11
4.12
4.13
rDS(on)
PMOS OFF
10
5
Ω
mA
µs
IPMOS_ON
tdelay_ON
Gate current
Turnon delay
VIN = 13.5 V, Vgs = –5 V
C = 10 nF
10
Boost-Controller Switching Frequency
4.14
4.15
fsw-Boost
DBoost
Boost switching frequency
Boost duty cycle
fSW_Buck / 2
90%
kHz
Error Amplifier (OTA) for Boost Converters
VBAT = 12 V
VBAT = 5 V
0.8
1.35
0.65
4.16
GmBOOST Forward transconductance
mS
0.35
5.0
5.1
Buck Controllers
VBuckA/B Adjustable output-voltage range
0.9
0.792
–1%
11
0.808
1%
V
V
Measure FBX pin
Measure FBX pin
0.800
0.800
Internal reference and tolerance
voltage in normal mode
5.2
5.3
Vref, NRM
0.784
–2%
0.816
2%
V
Internal reference and tolerance
voltage in low-power mode
Vref, LPM
V sense for forward-current limit in
CCM
5.4
5.5
FBx = 0.75 V (low duty cycle)
60
75
90
mV
mV
Vsense
V sense for reverse-current limit in
CCM
FBx = 1 V
FBx = 0 V
–65
17
–7.5
–23
48
5.6
5.7
VI-Foldback
tdead
V sense for output short
32.5
20
mV
ns
Shoot-through delay, blanking time
High-side minimum on-time
100
ns
5.8
5.9
DCNRM
Maximum duty cycle (digitally
controlled)
98.75%
DCLPM
Duty cycle, LPM
80%
LPM entry-threshold load current
as fraction of maximum set load
current
(3)
ILPM_Entry
1%
.
5.10
LPM exit-threshold load current as
fraction of maximum set load
current
(3)
ILPM_Exit
10%
(3) The exit threshold is specified to be always higher than the entry threshold.
6
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Product Folder Link(s): TPS43335-Q1 TPS43336-Q1
TPS43335-Q1
TPS43336-Q1
www.ti.com
SLVSAV6B –JUNE 2011–REVISED JULY 2012
DC ELECTRICAL CHARACTERISTICS (continued)
VIN = 8 V to 18 V, TJ = –40°C to 150°C (unless otherwise noted)
NO.
PARAMETER
TEST CONDITIONS
VVREG = 5.8 V, IGX1 current = 200 mA
VREG = 5.8 V, IGX2 current = 200 mA
MIN
TYP
MAX
UNIT
High-Side External NMOS Gate Drivers for Buck Controller
5.11
5.12
IGX1_peak
rDS(on)
Gate-driver peak current
Source and sink driver
0.7
A
4
4
Ω
Low-Side NMOS Gate Drivers for Buck Controller
5.13
5.14
IGX2_peak
RDS ON
Gate driver peak current
Source and sink driver
0.7
A
Ω
Error Amplifier (OTA) for Buck Converters
COMPA, COMPB = 0.8 V,
source/sink = 5 µA, test in feedback loop
5.15
GmBUCK
Transconductance
0.72
50
1
1.35
200
mS
nA
5.16
6.0
6.1
6.2
6.3
6.4
IPULLUP_FBx
Pullup current at FBx pins
FBx = 0 V
100
Digital Inputs: ENA, ENB, ENC, SYNC
VIH
Higher threshold
VIN = 13 V
VIN = 13 V
VSYNC = 5 V
VENC = 5 V
1.7
V
V
VIL
Lower threshold
0.7
2
RIH_SYNC
RIL_ENC
Pulldown resistance on SYNC
Pulldown resistance on ENC
500
500
kΩ
kΩ
Pullup current source on ENA,
ENB
6.5
IIL_ENx
VENx = 0 V,
0.5
µA
7.0
7.1
7.2
7.3
8.0
8.1
8.2
Boost Output Voltage: DIV
VIH_DIV
VIL_DIV
Voz_DIV
Higher threshold
VREG = 5.8 V
Vreg – 0.2
V
V
V
Lower threshold
0.2
Voltage on DIV if unconnected
Voltage on DIV if unconnected
Vreg / 2
Switching Parameter – Buck DC-DC Controllers
fSW_Buck
fSW_Buck
Buck switching frequency
Buck switching frequency
RT pin: GND
360
360
400
400
440
440
kHz
kHz
RT pin: 60-kΩ external resistor
Buck adjustable range with
external resistor
8.3
fSW_adj
RT pin: external resistor
150
150
600
600
kHz
kHz
8.4
8.5
9.0
fSYNC
fSS
Buck synchronization range
Spread-spectrum spreading
External clock input
TPS4333-Q1 only
5%
Internal Gate-Driver Supply
Internal regulated supply
VIN = 8 V to 18 V, EXTSUP = 0 V, SYNC = high
5.5
7.2
5.8
0.2%
7.5
6.1
1%
7.8
1%
V
V
9.1
VREG
IVREG = 0 mA to 100 mA, EXTSUP = 0 V,
SYNC = high
Load regulation
Internal regulated supply
Load regulation
EXTSUP = 8.5 V
9.2
9.3
VREG(EXTSUP)
IEXTSUP = 0 mA to 125 mA, SYNC = High
EXTSUP = 8.5 V to 13 V
0.2%
EXTSUP switch-over voltage
threshold
IVREG = 0 mA to 100 mA,
EXTSUP ramping positive
VEXTSUP-th
4.4
4.6
4.8
V
9.4
9.5
VEXTSUP-Hys
IREG-Limit
EXTSUP switch-over hysteresis
Current limit on VREG
150
100
250
400
mV
mA
EXTSUP = 0 V, normal mode as well as LPM
IREG_EXTSUP-
Current limit on VREG when using IVREG = 0 mA to 100 mA,
9.6
125
400
mA
EXTSUP
EXTSUP = 8.5 V, SYNC = High
Limit
10.0
10.1
11.0
11.1
Soft Start
ISSx
Soft-start source current
Oscillator reference voltage
SSA and SSB = 0 V
0.75
1
1.25
µA
V
Oscillator (RT)
VRT
1.2
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TPS43335-Q1
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SLVSAV6B –JUNE 2011–REVISED JULY 2012
www.ti.com
DC ELECTRICAL CHARACTERISTICS (continued)
VIN = 8 V to 18 V, TJ = –40°C to 150°C (unless otherwise noted)
NO.
12.0
12.1
12.2
12.3
12.4
12.5
12.6
12.7
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Good / Delay
PGpullup
PGth1
Pullup for A and B to Sx2
Power-good threshold
Hysteresis
50
–7%
2%
kΩ
FBx falling
–5%
–9%
PGhys
PGdrop
Voltage drop
IPGA = 5 mA
IPGA = 1 mA
450
100
1
mV
mV
µA
µs
PGleak
tdeglitch
Power-good leakage
VSx2 = VPGx = 13 V
Power-good deglitch time
2
16
External capacitor = 1 nF
VBUCKX < PGth1
12.8
12.9
tdelay
tdelay_fix
IOH
Reset delay
1
20
40
ms
µs
Fixed reset delay
No external capacitor, pin open
50
50
Activate current source (current to
charge external capacitor)
12.10
30
30
µA
Activate current sink (current to
discharge external capacitor)
12.11
13.0
13.1
13.2
IIL
40
50
µA
Overtemperature Protection
Junction-temperature shutdown
threshold
Tshutdown
Thys
150
165
15
°C
°C
Junction-temperature hysteresis
8
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Product Folder Link(s): TPS43335-Q1 TPS43336-Q1
TPS43335-Q1
TPS43336-Q1
www.ti.com
SLVSAV6B –JUNE 2011–REVISED JULY 2012
DEVICE INFORMATION
DAP PACKAGE
(TOP VIEW)
1
2
3
4
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VBAT
DS
VIN
EXTSUP
DIV
GC1
GC2
VREG
CBB
5
6
7
8
CBA
GA1
GB1
PHA
PHB
GA2
GB2
9
PGNDA
SA1
PGNDB
SB1
10
11
SA2
SB2
12
13
14
15
FBA
FBB
COMPA
SSA
COMPB
SSB
PGA
ENA
PGB
16
17
18
AGND
RT
ENB
COMPC
ENC
DLYAB
SYNC
19
20
PIN FUNCTIONS
NAME
NO.
I/O
DESCRIPTION
AGND
23
O
Analog ground reference
A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck
controller BuckA. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the
high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.
CBA
5
I
A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck
controller BuckB. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the
high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.
CBB
34
13
26
I
Error amplifier output of BuckA and compensation node for voltage-loop stability. The voltage at this node sets the
target for the peak current through the inductor of BuckA. This voltage is clamped on the upper and lower ends to
provide current-limit protection for the external MOSFETs.
COMPA
COMPB
O
O
Error amplifier output of BuckB and compensation node for voltage-loop stability. The voltage at this node sets the
target for the peak current through the inductor of BuckB. This voltage is clamped on the upper and lower ends to
provide current-limit protection for the external MOSFETs.
COMPC
DIV
18
36
O
I
Error-amplifier output and loop-compensation node of the boost regulator
The status of this pin defines the output voltage of the boost regulator. A high input regulates the boost converter
at 11 V, a low input sets the value at 7 V, and a floating pin sets 10 V.
The capacitor at the DLYAB pin sets the power-good delay interval used to de-glitch the outputs of the power-
good comparators. When this pin is left open, the power-good delay is set to an internal default value of 20 µs
typical.
DLYAB
DS
21
2
O
I
This input monitors the voltage on the external boost-converter low-side MOSFET for overcurrent protection.
Alternatively, it can be connected to a sense resistor between the source of the low-side MOSFET and ground via
a filter network for better noise immunity.
Enable input for BuckA (active-high with an internal pullup current source). An input voltage higher than 1.5 V
enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and
ENB are low, the device is shut down and consumes less than 4 µA of current.
ENA
16
I
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PIN FUNCTIONS (continued)
NAME
ENB
NO.
I/O
DESCRIPTION
Enable input for BuckB (active-high with an internal pullup current source). An input voltage higher than 1.5 V
enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and
ENB are low, the device is shut down and consumes less than 4 µA of current.
17
I
This input enables and disables the boost regulator. An input voltage higher than 1.5 V enables the controller.
Voltages lower than 0.7 V disable the controller. Because this pin provides and internal pulldown resistor (500 kΩ)
it must be pulled high to enable the boost function. When enabled, the controller starts switching as soon as VBAT
falls below the boost threshold, depending upon the programmed output voltage.
ENC
19
I
EXTSUP can be used to supply the VREG regulator from one of the TPS43330/2 buck regulator rails to reduce
power dissipation in cases where VIN is expected to be high. When EXTSUP is open or lower than 4.6 V, the
regulator is powered from VIN.
EXTSUP
FBA
37
12
27
I
I
I
Feedback voltage pin for BuckA. The buck controller regulates the feedback voltage to the internal reference of
0.8 V. A suitable resistor divider network between the buck output and the feedback pin sets the desired output
voltage.
Feedback voltage pin for BuckB. The buck controller regulates the feedback voltage to the internal reference of
0.8 V. A suitable resistor-divider network between the buck output and the feedback pin sets the desired output
voltage.
FBB
External high-side N-channel MOSFET for buck regulator BuckA can be driven from this output. The output
provides high peak currents to drive capacitive loads. The gate drive is referred to a floating ground reference
provided by PHA and has a voltage swing provided by CBA.
GA1
GA2
GB1
6
8
O
O
O
External low-side N-channel MOSFET for buck regulator BuckA can be driven from this output. The output
provides high peak currents to drive capacitive loads. The voltage swing on this pin is provided by VREG.
External high-side N-channel MOSFET for buck regulator BuckB can be driven from this output. The output
provides high peak currents to drive capacitive loads. The gate drive is referred to a floating ground reference
provided by PHB and has a voltage swing provided by CBB.
33
External low-side N-channel MOSFETs for buck regulator BuckB can be driven from this output. The output
provides high peak currents to drive capacitive loads. The voltage swing on this pin is provided by VREG.
GB2
GC1
31
3
O
O
An external low-side N-channel MOSFET for the boost regulator can be driven from this output. This output
provides high peak currents to drive capacitive loads. The voltage swing on this pin is provided by VREG.
A floating output drive to control the external P-channel MOSFET is available at this pin. This MOSFET can be
used to bypass the boost rectifier diode or a reverse protection diode when the boost is not switching or if boost is
disabled, and thus reduce power losses.
GC2
PGA
PGB
4
O
O
O
Open-drain power-good indicator pin for BuckA. An internal power-good comparator monitors the voltage at the
feedback pin and pulls this output low when the output voltage falls below 93% of the set value, or if either Vin or
Vbat drops below its respective undervoltage threshold.
15
24
Open-drain power-good indicator pin for BuckB. An internal power-good comparator monitors the voltage at the
feedback pin and pulls this output low when the output voltage falls below 93% of the set value, or if either Vin or
Vbat drops below its respective undervoltage threshold.
PGNDA
PGNDB
9
O
O
Power ground connection to the source of the low-side N-channel MOSFETs of BuckA.
Power ground connection to the source of the low-side N-channel MOSFETs of BuckB
30
Switching terminal of buck regulator BuckA, providing a floating ground reference for the high-side MOSFET gate-
driver circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desired.
PHA
PHB
7
O
O
Switching terminal of buck regulator BuckB, providing a floating ground reference for the high-side MOSFET gate-
driver circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desired.
32
The operating switching frequency of the buck and boost controllers is set by connecting a resistor to ground on
this pin. A short circuit to ground on this pin defaults operation to 400 kHz for the buck controllers and 200 kHz for
the boost controller.
RT
22
O
SA1
SA2
SB1
SB2
10
11
29
28
I
I
I
I
High-impedance differential voltage inputs from the current-sense element (sense resistor or inductor DCR) for
each buck controller. The current-sense element should be chosen to set the maximum current through the
inductor based on the current-limit threshold (subject to tolerances) and considering the typical characteristics
across duty cycle and VIN. (SA1 positive node, SA2 negative node).
High-impedance differential voltage inputs from the current-sense element (sense resistor or inductor DCR) for
each buck controller. The current-sense element should be chosen to set the maximum current through the
inductor based on the current-limit threshold (subject to tolerances) and considering the typical characteristics
across duty cycle and VIN. (SB1 positive node, SB2 negative node).
Soft-start or tracking input for buck controller BuckA. The buck controller regulates the FBA voltage to the lower of
0.8 V or the SSA pin voltage. An internal pullup current source of 1 µA is present at the pin, and an appropriate
capacitor connected here can be used to set the soft-start ramp interval. A resistor divider connected to another
supply can also be used to provide a tracking input to this pin.
SSA
14
O
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SLVSAV6B –JUNE 2011–REVISED JULY 2012
PIN FUNCTIONS (continued)
NAME
NO.
I/O
DESCRIPTION
Soft-start or tracking input for buck controller BuckB. The buck controller regulates the FBB voltage to the lower of
0.8 V or the SSB pin voltage. An internal pullup current source of 1 µA is present at the pin, and an appropriate
capacitor connected here can be used to set the soft-start ramp interval. A resistor-divider connected to another
supply can also be used to provide a tracking input to this pin.
SSB
25
O
If an external clock is present on this pin, the device detects it and the internal PLL locks onto the external clock.
This overrides the internal oscillator frequency. The device can synchronize to frequencies from 150 kHz to 600
kHz. A high logic level on this pin ensures forced continuous-mode operation of the buck controllers and inhibits
transition to low-power mode. An open or low allows discontinuous mode operation and entry into low-power
mode at light loads. On the TPS43332, a high level enables frequency-hopping spread spectrum, whereas an
open or a low level disables it.
SYNC
20
I
Battery input sense for the boost controller. If the boost controller is enabled and the voltage at VBAT falls below
the boost threshold, the device activates the boost controller and regulates the voltage at VIN to the programmed
boost output voltage.
VBAT
VIN
1
I
I
Main Input pin. This is the buck controller input pin as well as the output of the boost regulator. Additionally, it
powers the internal control circuits of the device.
38
An external capacitor on this pin is required to provide a regulated supply for the gate drivers of the buck and
boost controllers. A capacitance in the order of 4.7 µF is recommended. The regulator can be used such that it is
either powered from VIN or EXTSUP. This pin has current-limit protection and should not be used to drive any
other loads.
VREG
35
O
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5
6
7
8
9
Duplicate for second
Buck controller channel
CBA
GA1
Internal ref
(Band gap)
38
VIN
Gate Driver
Supply
37
EXTSUP
PWM logic
PHA
VREG
VREG 35
GA2
Internal
Oscillator
RT
22
PGNDA
Current sense
Amp
Slope Comp
+
SYNC &
LPM
10
11
12
PWM
comp
SA1
SA2
FBA
+
-
+
20
SYNC
-
OTA
-
gm
+
0.8V
+
SSA
Source/
Sink
Logic
4
13
15
GC2
COMPA
PGA
SA2
FBA
–
+
EN
VREF
Filter timer
1mA
VIN
14
16
SSA
ENA
ENA
VREF
40 mA
500 nA
21
DLYAB
40 mA
VREF
1mA
VIN
25
17
34
33
32
31
30
29
28
27
26
SSB
ENB
CBB
GB1
PHB
GB2
500 nA
ENB
COMPC
VBAT
18
1
OTA
Second Buck Controller
Channel
-
gm
+
PGNDB
SB1
36
2
DIV
DS
Vref
OCP
-
-
+
0.2V
SB2
+
VIN
PWM
comp
VREG
FBB
3
GC1
PWM
Logic
COMPB
PGNDA
19
23
ENC
24
PGB
AGND
Figure 2. Functional Block Diagram
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SLVSAV6B –JUNE 2011–REVISED JULY 2012
TYPICAL CHARACTERISTICS
EFFICIENCY ACROSS OUTPUT CURRENTS (BUCKS)
VIN = 12V, VOUT = 5V, SWITCHING FREQUENCY = 400kHz
INDUCTOR = 4.7µH, RSENSE = 10mW
10000
100
EFFICIENCY,
SYNC = LOW
90
80
70
60
50
40
30
20
10
0
1000
100
10
POWER LOSS,
SYNC = HIGH
POWER LOSS,
SYNC = LOW
1
EFFICIENCY,
SYNC = HIGH
0.1
0.0001
0.001
0.01
0.1
1
10
OUTPUT CURRENT (A)
Figure 3.
Figure 4.
SOFT-START OUTPUTS (BUCK)
VOUTA
VOUTB
1V/DIV
2ms/DIV
Figure 5.
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
BUCK LOAD STEP: LOW POWER MODE EXIT
(90 mA TO 4 A AT 2.5 A/µs)
VIN = 12 V, VOUT = 5 V, SWITCHING FREQUENCY = 400 kHz
INDUCTOR = 4.7 µH, RSENSE = 10 mW
100 mV/DIV
VOUT AC-COUPLED
2 A/DIV
IIND
50 µs/DIV
Figure 8.
Figure 7.
EFFICIENCY ACROSS OUTPUT CURRENTS (BOOST)
VIN (BOOST OUTPUT) = 10V, SWITCHING FREQUENCY = 200kHz,
INDUCTOR = 1.0µH, RSENSE = 7.5mW
LOAD STEP RESPONSE (BOOST)
(0 TO 5A AT 2.5A/µs)
VBAT (BOOST INPUT) = 5V, VIN (BOOST OUTPUT) = 10V,
SWITCHING FREQUENCY = 200kHz, INDUCTOR = 1.0µH,
RSENSE = 7.5mW, CIN = 440µF, COUT = 660µF
100
90
VBAT = 8V
80
500mV/DIV
70
VIN (BOOST OUTPUT) AC-COUPLED
VBAT = 5V
60
VBAT = 3V
50
40
30
20
10
0
5A/DIV
IIND
0.01
1
10
2ms/DIV
OUTPUT CURRENT (A)
Figure 9.
Figure 10.
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SLVSAV6B –JUNE 2011–REVISED JULY 2012
TYPICAL CHARACTERISTICS (continued)
CRANKING PULSE BOOST RESPONSE
(12V to 4V IN 1ms AT BOOST DIRECT OUTPUT 25W)
CRANKING PULSE BOOST RESPONSE
(12V to 3V IN 1ms AT BUCK OUTPUTS 7.5W/11.5W)
VIN (BOOST OUTPUT) = 10V, BUCKA = 5V/1.5A, BUCKB = 3.3V/3.5A,
SWITCHING FREQUENCY = 200kHz, INDUCTOR = 1.0µH,
RSENSE = 7.5mOHM, CIN = 440µF, COUT = 660µF
VIN (BOOST OUTPUT) = 10V, BUCKA = 5V/1.5A, BUCKB = 3.3V/3.5A,
SWITCHING FREQUENCY = 200kHz, INDUCTOR = 1.0µH,
RSENSE = 7.5mOHM, CIN = 440µF, COUT = 660µF
VBAT (BOOST INPUT)
VBAT (BOOST INPUT)
5V/DIV
5V/DIV
0V
200mV/DIV
200mV/DIV
0V
VIN (BOOST OUTPUT)
VOUT BUCKA AC-COUPLED
VOUT BUCKB AC-COUPLED
5V/DIV
0V
10A/DIV
10A/DIV
0A
IIND
IIND
0A
20ms/DIV
20ms/DIV
Figure 11.
Figure 12.
INDUCTOR CURRENTS (BOOST)
VBAT (BOOST INPUT) = 5V, VIN (BOOST OUTPUT) = 10V,
SWITCHING FREQUENCY = 200kHz, INDUCTOR = 1.0µH,
RSENSE = 7.5mW, CIN = 440µF, COUT = 660µF
3A LOAD
5A/DIV
100mA LOAD
5A/DIV
2µs/DIV
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
BUCKx PEAK CURRENT LIMIT vs. COMPx VOLTAGE
NO-LOAD QUIESCENT CURRENT
ACROSS TEMPERATURE
75
62.5
50
60
50
40
30
20
10
0
37.5
25
BOTH BUCKS ON
12.5
0
SYNC = LOW
ONE BUCK ON
-12.5
-25
NEITHER BUCK ON
SYNC = HIGH
0.8 0.95
-37.5
0.65
1.1
1.25
1.4
1.55
-40 -15 10
35
60
85 110 135 160
COMPx VOLTAGE (V)
Temperature (°C)
Figure 14.
Figure 15.
FOLDBACK CURRENT LIMIT (BUCK)
CURRENT SENSE PINS INPUT CURRENT (BUCK)
0.9
80
70
60
50
40
30
20
10
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
150°C
25°C
-0.1
-0.2
-0.3
0
1
2
3
4
5
6
7
8
9
10 11 12
0
0.2
0.4
0.6
0.8
OUTPUT VOLTAGE (V)
FBx VOLTAGE (V)
Figure 16.
Figure 17.
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SLVSAV6B –JUNE 2011–REVISED JULY 2012
TYPICAL CHARACTERISTICS (continued)
REGULATED FBx VOLTAGE vs TEMPERATURE (BUCK)
CURRENT LIMIT VS DUTY CYCLE (BUCK)
805
804
803
802
801
800
799
798
797
796
795
80
70
60
50
40
30
20
10
0
VIN = 8V
VIN = 12V
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
-40 -15 10
35
60
85 110 135 160
TEMPERATURE (°C)
Figure 18.
Figure 19.
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DETAILED DESCRIPTION
BUCK CONTROLLERS: NORMAL MODE PWM OPERATION
Frequency Selection and External Synchronization
The buck controllers operate using constant-frequency peak-current-mode control for optimal transient behavior
and ease of component choices. The switching frequency is programmable between 150 kHz and 600 kHz,
depending upon the resistor value at the RT pin. A short circuit to ground at this pin sets the default switching
frequency to 400 kHz. The frequency can also be set by a resistor at RT, according to the formula:
X
f
=
(X=24kΩ×MHz)
SW
RT
9
10
f
=24×
SW
RT
For example,
600 kHz requires 40 kΩ
150 kHz requires 160 kΩ
It is also possible to synchronize to an external clock at the SYNC pin in the same frequency range of 150 kHz to
600 kHz. The device detects clock pulses at this pin, and an internal PLL locks on to the external clock within the
specified range. The device can also detect a loss of clock at this pin, and when this condition is detected, the
device sets the switching frequency to the internal oscillator. The two buck controllers operate at identical
switching frequencies, 180 degrees out-of-phase.
Enable Inputs
The buck controllers are enabled using independent enable inputs from the ENA and ENB pins. These are high-
voltage pins, with a threshold of 1.5 V for high level, and can be connected directly to the battery for self-bias.
The low threshold is 0.7 V. Both these pins have internal pullup currents of 0.5 µA (typical). As a result, an open
circuit on these pins enables the respective buck controllers. When both buck controllers are disabled, the device
is shut down and consumes a current less than 4 µA.
Feedback Inputs
The output voltage is set by choosing the right resistor feedback divider network connected to the FBx (feedback)
pins. Choose this network such that the regulated voltage at the FBx pin equals 0.8 V. The FBx pins have a 100-
nA pullup current source as a protection feature in case the pins open up as a result of physical damage.
Soft-Start Inputs
In order to avoid large inrush currents, both buck controllers have an independent programmable soft-start timer.
The voltage at the SSx pins acts as the soft-start reference voltage. A 1-µA pullup current is available at the SSx
pins, and by choosing a suitable capacitor, a ramp of the desired soft-start speed can be generated. After start-
up, the pullup current ensures that SSx is higher than the internal reference of 0.8 V; 0.8 V then becomes the
reference for the buck controllers. The soft-start ramp time is defined by:
I
×Δt
SS
C
=
(Farads)
SS
ΔV
where,
ISS = 1 µA (typical)
∆V = 0.8 V
CSS is the required capacitor for ∆t, the desired soft-start time.
Alternatively, the soft-start pins can be used as tracking inputs. In this case, they should be connected to the
supply to be tracked via a suitable resistor-divider network.
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Current-Mode Operation
Peak-current-mode control regulates the peak current through the inductor such that the output voltage is
maintained to its set value. The error between the feedback voltage at FBx and the internal reference produces a
signal at the output of the error amplifier (COMPx) which serves as the target for the peak inductor current. The
current through the inductor is sensed as a differential voltage at Sx1–Sx2 and compared with this target during
each cycle. A fall or rise in load current produces a rise or fall in voltage at FBx, causing COMPx to fall or rise
respectively, thus increasing or decreasing the current through the inductor until the average current matches the
load. In this way, the output voltage is maintained in regulation.
The top N-channel MOSFET is turned on at the beginning of each clock cycle and kept on until the inductor
current reaches its peak value. Once this MOSFET is turned off, and after a small delay (shoot-through delay)
the lower N-channel MOSFET is turned on until the start of the next clock cycle. In dropout operation, the high-
side MOSFET stays on continuously. In every fourth clock cycle, the duty cycle is limited to 95% in order to
charge the bootstrap capacitor at CBx. This allows a maximum duty cycle of 98.75% for the buck regulators.
During dropout, the buck regulator switches at one-fourth of its normal frequency.
Current Sensing and Current Limit With Foldback
The maximum value of COMPx is clamped such that the maximum current through the inductor is limited to a
specified value. When the output of the buck regulator (and hence the feedback value at FBx) falls to a low value
due to a short circuit or overcurrent condition, the clamped voltage at the COMPx successively decreases, thus
providing current foldback protection. This protects the high-side external MOSFET from excess current (forward-
direction current limit).
Similarly, if due to a fault condition the output is shorted to a high voltage and the low-side MOSFET turns fully
on, the COMPx node drops low. It is clamped on the lower end as well, in order to limit the maximum current in
the low-side MOSFET (reverse-direction current limit).
The current through the inductor is sensed by an external resistor. The sense resistor should be chosen such
that the maximum forward peak current in the inductor generates a voltage of 75 mV across the sense pins. This
value is specified at low duty cycles only. At typical duty-cycle conditions around 40% (assuming 5 V output and
12 V input), 50 mV is a more reasonable value, considering tolerances and mismatches. The typical
characteristics provide a guide for using the correct current-limit sense voltage.
The current-sense pins Sx1 and Sx2 are high-impedance pins with low leakage across the entire output range.
This allows DCR current sensing using the dc resistance of the inductor for higher efficiency. DCR sensing is
shown in Figure 20. Here, the series resistance (DCR) of the inductor is used as the sense element. The filter
components should be placed close to the device for noise immunity. Remember that while the DCR sensing
gives high efficiency, it is inaccurate due to the temperature sensitivity and a wide variation of the parasitic
inductor series resistance. Hence, it may often be advantageous to use the more-accurate sense resistor for
current sensing.
Inductor L
TPS43335-Q1/
TPS43336-Q1
VBUCK X
DCR
R1
C1
Sx2
VC
Sx1
Figure 20. DCR Sensing Configuration
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Slope Compensation
Optimal slope compensation which is adaptive to changes in input voltage and duty cycle allows stable operation
at all conditions. For optimal performance of this circuit, the following condition must be satisfied in the choice of
inductor and sense resistor:
L×f
SW
=200
R
S
where
L is the buck regulator inductor in henries.
RS is the sense resistor in ohms.
fsw is the buck regulator switching frequency in hertz.
Power-Good Outputs and Filter Delays
Each buck controller has an independent power-good comparator monitoring the feedback voltage at the FBx
pins and indicating whether the output voltage has fallen below a specified power-good threshold. This threshold
has a typical value of 93% of the regulated output voltage. The power-good indicator is available as an open-
drain output at the PGx pins. An internal 50-kΩ pullup resistor to Sx2 is available, or an external resistor can be
used. When a buck controller is shut down, the power-good indicator is pulled down internally. Connecting the
pullup resistor to a rail other than the output of that particular buck channel causes a constant current flow
through the resistor when the buck controller is powered down.
In order to avoid triggering the power-good indicators due to noise or fast transients on the output voltage, an
internal delay circuit for de-glitching is used. Similarly, when the output voltage returns to its set value after a long
negative transient, the power-good indicator is asserted high (the open-drain pin released) after the same delay.
This can be used to delay the reset to the circuits being powered from the buck regulator rail. The delay of this
circuit can be programmed by using a suitable capacitor at the DLYAB pin according to the equation:
tDELAY
1 msec
=
CDLYAB
1 nF
When the DLYAB pin is open, the delay is set to a default value of 20 µs typical. The power-good delay timing is
common to both the buck rails, but the power-good comparators and indicators function independently.
Light-Load PFM Mode
An external clock or a high level on the SYNC pin results in forced continuous-mode operation of the bucks.
When the SYNC pin is low or open, the buck controllers are allowed to operate in discontinuous mode at light
loads by turning off the low-side MOSFET whenever a zero-crossing in the inductor current is detected.
In discontinuous mode, as the load decreases, the duration of the clock period when both the high-side and low-
side MOSFETs are turned off increases (deep discontinuous mode). In case the duration exceeds 60% of the
clock period and VBAT > 8 V, the buck controller switches to a low-power operation mode. The design ensures
that this typically occurs at 1% of the set full-load current if the inductor and the sense resistor have been chosen
appropriately as recommended in the slope compensation section.
In low-power PFM mode, the buck monitors the FBx voltage and compares it with the 0.8-V internal reference.
Whenever the FBx value falls below the reference, the high-side MOSFET is turned on for a pulse duration
inversely proportional to the difference VIN – Sx2. At the end of this on-time, the high-side MOSFET is turned off
and the current in the inductor decays until it becomes zero. The low-side MOSFET is not turned on. The next
pulse occurs the next time FBx falls below the reference value. This results in a constant volt-second ton
hysteretic operation with a total device quiescent current consumption of 30 µA when a single buck channel is
active and 35 µA when both channels are active.
As the load increases, the pulses become more and more frequent and move closer to each other until the
current in the inductor becomes continuous. At this point, the buck controller returns to normal fixed-frequency
current-mode control. Another criterion to exit the low-power mode is when VIN falls low enough to require higher
than 80% duty cycle of the high-side MOSFET.
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The TPS43335-Q1and TPS43336-Q1 can support the full-current load during low-power mode until the transition
to normal mode takes place. The design ensures the low-power mode exit occurs at 10% (typical) of full-load
current if the inductor and sense resistor have been chosen as recommended. Moreover, there is always a
hysteresis between the entry and exit thresholds to avoid oscillating between the two modes.
In the event that both buck controllers are active, low-power mode is only possible when both buck controllers
have light loads that are low enough for low-power mode entry. When the boost controller is enabled, low-power
mode is possible only if VBAT is high enough to prevent the boost from switching and if DIV is open or set to
GND. If DIV is high (VREG), low-power mode is inhibited.
Boost Controller
The boost controller has a fixed-frequency voltage-mode architecture and includes cycle-by-cycle current-limit
protection for the external N-channel MOSFET. The switching frequency is derived from and set to one-half of
the buck-controller switching frequency. The output voltage of the boost controller at the VIN pin is set by an
internal resistor-divider network and is programmable to 7 V, 10 V or 11 V, based on the low, open, or high
status, respectively, of the DIV pin. A change of the DIV setting is not recognized while the device is in low-
power mode.
The boost controller is enabled by the active-high ENC pin and is active when the input voltage at the VBAT pin
has crossed the unlock threshold of 8.5 V at least once. After that, the boost controller is armed and starts
switching as soon as VIN falls below the value set by the DIV pin and regulates the VIN voltage. Thus, the boost
regulator maintains a stable input voltage for the buck regulators during transient events such as a cranking
pulse at VBAT.
Whenever the voltage at the DS pin exceeds 200 mV, the boost external MOSFET is turned off by pulling the
CG1 pin low. By connecting the DS pin to the drain of the MOSFET or to a sense resistor between the MOSFET
source and ground, cycle-by-cycle overcurrent protection for the MOSFET can be achieved. The on-resistance of
the MOSFET or the value of the sense resistor must be chosen in such a way that the on-state voltage at the DS
does not exceed 200 mV at the maximum-load and minimum-input-voltage conditions. When a sense resistor is
used , a filter network is recommended to be connected between the DS pin and the sense resistor for better
noise immunity.
The boost output (VIN) can also be used to supply other circuits in the system. However, they should be high-
voltage tolerant. The boost output is regulated to the programmed value only when VIN is low, and so VIN can
reach battery levels.
Vbat
VIN
DS
TPS43335-Q1/
TPS43336-Q1
GC1
Figure 21. External Drain-Source Voltage Sensing
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Vbat
VIN
TPS43335-Q1/
TPS43336-Q1
GC1
DS
RIFLT
CIFLT
RISEN
Figure 22. External Current Shunt Resistor
Frequency-Hopping Spread Spectrum (TPS43336-Q1 only)
The TPS43332 features a frequency-hopping pseudo-random spectrum-spreading architecture. On this device,
whenever the SYNC pin is high, the internal oscillator frequency is varied from one cycle to the next within a
band of ±5% around the value programmed by the resistor at the RT pin. The implementation uses a linear-
feedback shift register that changes the frequency of the internal oscillator based on a digital code. The shift
register is long enough to make the hops pseudo-random in nature and is designed in such a way that the
frequency shifts only by one step at each cycle to avoid large jumps in the buck and boost switching frequencies.
Table 1. Frequency-Hopping Control
Sync
Terminal
Frequency Spread Spectrum (FSS)
Not active
Comments
Device in forced continuous mode, internal PLL locks into external clock
between 150 kHz and 600 kHz.
External clock
Device can enter discontinuous mode. Automatic LPM entry and exit,
depending on load conditions
Low or open
High
Not active
TPS43330: FSS not active
TPS43332: FSS active
Device in forced continuous mode
Table 2. Mode of Operation
ENABLE AND INHIBIT PINS
ENA ENB ENC SYNC
DRIVER STATUS
DEVICE STATUS
QUIESCENT CURRENT
BUCK CONTROLLERS
BOOST CONTROLLER
Disabled
Low
Low
Low
X
Shutdown
Shutdown
Approximately 4 µA
Approximately 30 µA (light loads)
mA range
Low
High
Low
High
Low
High
X
Buck B: LPM enabled
Buck B: LPM inhibited
Buck A: LPM enabled
Buck A: LPM inhibited
Buck A/B: LPM enabled
Buck A/B: LPM inhibited
Shutdown
Low
High
Low
Buck B running
Buck A running
Disabled
Disabled
Approximately 30 µA (light loads)
mA range
High
Low
Low
Approximately 35 µA (light loads)
mA range
BuckA and BuckB
running
High
Low
High
Low
Low
Disabled
Disabled
High
Shutdown
Approximately 4 µA
Approximately 50 µA (no boost,
light loads)
Low
High
Low
High
Low
High
Buck B: LPM enabled
Buck B: LPM inhibited
Buck A: LPM enabled
Buck A: LPM inhibited
Buck A/B: LPM enabled
Buck A/B: LPM inhibited
Boost running for VIN < set
boost output
Low
High
High
High
Low
High
High
High
High
Buck B running
mA range
Approximately 50 µA (no boost,
light loads)
Boost running for VIN < set
boost output
Buck A running
mA range
Approximately 60 µA (no boost,
light loads)
BuckA and BuckB
running
Boost running for VIN < set
boost output
mA range
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Gate-Driver Supply (VREG, EXTSUP)
The gate drivers of the buck and boost controllers are supplied from an internal linear regulator whose output
(5.8 V typical) is available at the VREG pin and should be decoupled using at least a 3.3-µF ceramic capacitor.
This pin has internal current-limit protection and should not be used to power any other circuits.
The VREG linear regulator is powered from VIN by default when the EXTSUP voltage is lower than 4.6 V
(typical). In case VIN expected to go to high levels, there can be excessive power dissipation in this regulator,
especially at high switching frequencies and when using large external MOSFETs. In this case, it is
advantageous to power this regulator from the EXTSUP pin, which can be connected to a supply lower than VIN
but high enough to provide the gate drive. When EXTSUP is connected to a voltage greater than 4.6 V, the linear
regulator automatically switches to EXTSUP as its input to provide this advantage. Efficiency improvements are
possible when one of the switching regulator rails from the TPS43335-Q1 or TPS43336-Q1 or any other voltage
available in the system is used to power EXTSUP. The maximum voltage that should be applied to EXTSUP is
13 V.
VIN
EXTSUP
LDO
EXTSUP
LDO
VIN
typ 5.8 V
typ 7.5 V
typ 4.6 V
VREG
Figure 23. Internal Gate-Driver Supply
Using a large value for EXTSUP is advantageous, as it provides a large gate drive and hence better on-
resistance of the external MOSFETs. A 0.1-µF ceramic capacitor is recommended for decoupling the EXTSUP
pin when not being used.
During low-power mode, the EXTSUP functionality is not available. The internal regulator operates as a shunt
regulator powered from VIN and has a typical value of 7.5 V. Current-limit protection for VREG is available in
low-power mode as well.
External P-Channel Drive (GC2) and Reverse Battery Protection
The TPS43335-Q1 and TPS43336-Q1 include a gate driver for an external P-channel MOSFET which can be
connected across the rectifier diode of the boost regulator. This is useful to reduce power losses when the boost
controller is not switching. The gate driver provides a swing of 6 V typical below the VIN voltage in order to drive
a P-channel MOSFET. When VBAT falls below the boost-enable threshold, the gate driver turns off the P-
channel MOSFET and the diode is no longer bypassed.
The gate driver can also be used to bypass any additional protection diodes connected in series, as shown in
Figure 24. Figure 25 also shows a different scheme of reverse battery protection, which may require only a
smaller-sized diode to protect the N-channel MOSFET, as it conducts only for a part of the switching cycle.
Because it is not always in the series path, the system efficiency can be improved.
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R10
GC2
VIN
TPS43335-Q1/
TPS43336-Q1
D3
Q7
Q6
L3
Fuse (S1)
Vbat
D1
D2
C17
C15
C16
C14
DS
GC1
COMPC
C13
R9
VBAT
Figure 24. Reverse Battery Protection Option 1 for Buck Boost Configuration
GC2
VBAT
VIN
Fuse
TPS43335-Q1/
TPS43336-Q1
DS
GC1
COMPC
VBAT
Figure 25. Reverse Battery Protection Option 2 for Buck Boost Configuration
Undervoltage Lockout and Overvoltage Protection
The TPS43335-Q1 and TPS43336-Q1 start up at a VIN voltage of 6.5 V (minimum), required for the internal
supply (VREG). Once it has started up, the device operates down to a VIN voltage of 3.6 V; below this voltage
level, the undervoltage lockout disables the device. Note: if Vin drops, VREG drops as well; hence, the gate-drive
voltage is reduced, whereas the digital logic is fully functional. Note as well, even if ENC is high, the boost
requires the unlock-voltage of typically 8.5 V to be exceeded once, before it can be activated (see the Boost
Controller section herein). A voltage of 46 V at VIN triggers the overvoltage comparator, which shuts down the
device. In order to prevent transient spikes from shutting down the device, the under- and overvoltage protection
have filter times of 5 µs (typical).
When the voltages return to the normal operating region, the enabled switching regulators start including a new
soft-start ramp for the buck regulators.
When the boost controller is enabled, a voltage less than 1.9 V (typical) on VBAT triggers an undervoltage
lockout and pulls the boost gate driver (GC1) low (this action has a filter delay of 5 µs, typical). As a result, VIN
falls at a rate dependent on its capacitor and load, eventually triggering VIN undervoltage. A short falling
transient at VBAT even lower than 2 V can thus be survived, if VBAT returns above 2.5 V before VIN is
discharged to the undervoltage threshold.
Thermal Protection
The TPS43335-Q1 or TPS43336-Q1 protects itself from overheating using an internal thermal shutdown circuit. If
the die temperature exceeds the thermal shutdown threshold of 165ºC due to excessive power dissipation (for
example, due to fault conditions such as a short circuit at the gate drivers or VREG), the controllers are turned
off and restarted when the temperature has fallen by 15ºC.
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APPLICATION INFORMATION
The following example illustrates the design process and component selection for the TPS43330. The design
goal parameters are given in Table 3.
Table 3. Application Example
PARAMETER
VBUCK A
VBUCK B
BOOST
VIN 6 V to 30 V
12 V - typical
VIN 6 V to 30 V
12 V - typical
VBAT - 5 V (cranking
pulse input) to 30 V
Input voltage
Output voltage, VO
5 V
3 A
3.3 V
2 A
10 V
2.5 A
Maximum output current, IO
Load step output tolerance, ∆VO
Current output load step, ∆IO
Converter switching frequency, fSW
±0.2 V
±0.12 V
0.1 A to 2 A
400 kHz
±0.5 V
0.1 A to 3 A
400 kHz
0.1 A to 2.5 A
200 kHz
This is a starting point and theoretical representation of the values to be used for the application, further
optimization of the components derived may be required to improve the performance of the device.
Boost Component Selection
A boost converter operating in continuous-conduction mode (CCM) has a right-half-plane (RHP) zero in its
transfer function. The RHP zero is inversely related to the load current and inductor value and directly related to
the input voltage. The RHP zero limits the maximum bandwidth achievable for the boost regulator. If the
bandwidth is too close to the RHP zero frequency, the regulator may become unstable.
Thus, for high-power systems with low input voltages, a low inductor value is chosen. This increases the
amplitude of the ripple currents in the N-channel MOSFET, the inductor, and the capacitors for the boost
regulator. They must be designed with the ripple-to-RHP zero trade-off in mind and considering the power
dissipation effects in the components due to parasitic series resistance.
A boost converter that operates in the discontinuous mode does not contain the RHP zero in its transfer function.
However, this needs an even lower inductor value and has high ripple currents. Also, ensure that the regulator
never enters the continuous-conduction mode; otherwise, it may become unstable.
VIN
C O
7V
OTA-gmEA
COMPx
R ESR
-
10V
C 1
+
VREF
C 2
R3
12V
Figure 26. Boost Compensation Components
This design is done assuming continuous-conduction mode. During light load conditions, the boost converter
operates in discontinuous mode without affecting stability. Hence, the assumptions here cover the worst case for
stability.
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Boost Maximum Input Current IIN_MAX
The maximum input current is drawn at the minimum input voltage and maximum load. The efficiency for VBAT =
5 V at 2.5 A is 80%, based on the typical characteristics plot.
POUT
25 W
0.8
P
=
=
= 31.3 W
INmax
Efficiency
Hence,
31.3 W
5 V
IINmax (at VBAT = 5 V) =
= 6.3 A
Boost Inductor Selection, L
Allow input ripple current of 40% of IIN max at VBAT = 5 V.
V
BAT *TON
V
BAT
5V
L =
=
=
= 4.9 mH
I
IN max
I
IN max* 2 *fSW
2.52A * 2 * 200kHz
Choose a lower value of 4 µH in order to ensure a high RHP-zero frequency while making a compromise that
expects a high current ripple. Also, this can make the boost converter operate in discontinuous conduction mode,
where it is easier to compensate.
The inductor saturation current must be higher than the peak inductor current and some percentage higher than
the maximum current-limit value set by the external sensing resistive element.
This rating should be determined at the minimum input voltage, maximum output current, and maximum core
temperature for the application.
Inductor Ripple Current, IRIPPLE
Based on an inductor value of 4 µH, the ripple current is approximately 3.1 A.
Peak Current in Low-Side FET, IPEAK
IRIPPLE
3.1 A
IPEAK = IINmax
+
= 6.3 A +
= 7.85 A
2
2
Based on this peak current value, the external current-sense resistor RSENSE is calculated.
0.2 V
RSENSE
=
= 25 mW
7.85 A
Select 20 mΩ, allowing for tolerance.
The filter component values RIFLT and CIFLT for current sense are 1.5 kΩ and 1 nF, respectively. This allows for
good noise immunity.
Right Half-Plane Zero RHP Frequency, fRHP
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Output Capacitor, CO
To ensure stability, output capacitor CO is chosen such that
fRHP
fLC
£
10
VBATmin
10
£
2p´IINmax ´L
2p´ L ´ CO
2
2
æ
CO ³ ç
ö
÷ ´L =
10´IINmax
æ
ç
è
ö
÷
ø
10´ 6.3 A
´ 4 mH
ç
÷
ø
VBATmin
5 V
è
COmin ³ 635 mF
Select CO = 660 µF to 680 µF.
This capacitor is usually aluminum electrolytic with ESR in the tens of milliohms. This is good for loop stability,
because it provides a phase boost due to the ESR. The output filter components, L and C, create a double pole
(180-degree phase shift) at a frequency fLC and the ESR of the output capacitor RESR creates a zero for the
modulator at frequency fESR. These frequencies can be determined by the following:
1
fESR
=
Hz, assume RESR = 40 mW
2p´CO ´RESR
1
fESR
=
= 6 kHz
2p´ 660 mF´0.04 W
1
1
fLC
=
=
2p´ L´CO 2p´ 4 mH´ 660 mF
= 3.1 kHz
This satisfies fLC ≤ 0.1 fRHP
.
Bandwidth of Boost Converter, fC
Use the following guidelines to set the frequency poles, zeroes, and crossover values for the trade-off between
stability and transient response:
fLC < fESR< fC< fRHP Zero
fC < fRHP Zero / 3
fC < fSW / 6
fLC < fC / 3
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Output Ripple Voltage Due to Load Transients, ∆VO
Assume a bandwidth of fC = 10 kHz.
DIO
DVO = RESR ´ DIO
+
4´ CO ´ fC
2.5 A
= 0.04 W´ 2.5 A +
= 0.19 V
4´ 660 mF´10 kHz
Because the boost converter is active only during brief events such as a cranking pulse, and the buck converters
are high-voltage tolerant, a higher excursion on the boost output may be tolerable in some cases. In such cases,
smaller component choices for the boost output may be used.
Selection of Components for Type II Compensation
The required loop gain for unity-gain bandwidth (UGB) is
æ
ö
fC
fC
æ
ö
G = 40 logç
÷ - 20 log
ç
÷
ç
÷
ç
è
÷
ø
fLC
f ESR
è
ø
æ 10 kHz ö
÷
æ 10 kHz ö
ç
è
G = 40 log
- 20 log
= 15.9 dB
÷
ç
3.1kHz
6 kHz
ø
è
ø
The boost-converter error amplifier (OTA) has a Gm that is proportional to the VBAT voltage. This allows a
constant loop response across the input-voltage range and makes it easier to compensate by removing the
dependency on VBAT
.
10G/20
85´10-6 A / V2 ´ VO
R3 =
C1=
C2 =
= 7.2 kW
10
10
=
2p´ fC ´R3 2p´10 kHz ´ 7.2 kW
= 22 nF
C1
22 nF
=
= 223 pF
f
200 kHz
2
æ
ç
è
ö
÷
ø
æ
ç
è
ö
÷
ø
SW
2p´ 7.2 kW ´ 22 nF´
-1
2p´R3´ C1´
-1
2
Input Capacitor, CIN
The input ripple required is lower than 50 mV.
IRIPPLE
DVC1
=
= 10 mV
8´ fSW ´CIN
IRIPPLE
CIN
=
= 194-μF
8´ fSW ´ DVC1
DVESR = IRIPPLE ´RESR = 40 mV
Therefore, our recommendation is 220 µF with 10-mΩ ESR.
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Output Schottky Diode D1 Selection
A Schottky diode with low forward conducting voltage VF over temperature and fast switching characteristics is
required to maximize efficiency. The reverse breakdown voltage should be higher than the maximum input
voltage, and the component should have low reverse leakage current. Additionally, the peak forward current
should be higher than the peak inductor current. The power dissipation in the Schottky diode is given by:
PD = ID(PEAK) ´ VF ´(1-D)
VINMIN
5 V
D = 1-
= 1-
= 0.53
Vout + VF
10 V + 0.6 V
PD = 7.85 A ´0.6 V ´(1- 0.53) = 2.2 W
Because this is activated for the low-input-voltage profile related to the crank pulse, the duration is less than
25 ms.
Low-Side MOSFET (BOT_SW3)
V ´I
æ
ö
I
Pk
PBOOSTFET = (IPk )2 ´rDS(on)(1+ TC)´D +
´(t + t )´ f
ç
÷
r
f
SW
ç
÷
2
è
ø
V ´I
æ
ç
è
ö
Pk
÷
I
P
= (7.85 A)2 ´ 0.02 W ´ (1+ 0.4)´ 0.53 +
´(20 ns + 20 ns)´ 200 kHz = 1.07 W
BOOSTFET
2
ø
The times tr and tf denote the rising and falling times of the switching node and are related to the gate-driver
strength of the TPS43330/2 and gate Miller capacitance of the MOSFET. The first term denotes the conduction
losses which are minimized when the on-resistance of the MOSFET is low. The second term denotes the
transition losses which arise due to the full application of the input voltage across the drain-source of the
MOSFET as it turns on or off. They are higher at high output currents and low input voltages (due to the large
input peak current) and when the switching time is low.
Note: The on-resistance, rDS(on), has a positive temperature coefficient, which produces the (TC = d × ΔT) term
that signifies the temperature dependence. (Temperature coefficient d is available as a normalized value from
MOSFET data sheets and can be assumed to be 0.005 / °C as a starting value.)
BuckA Component Selection
Minimum On-Time, tON min
VO
5 V
tON min
=
=
= 416 ns
VIN max ´ fSW 30 V ´ 400 kHz
This is higher than the minimum duty cycle specified (100 ns typical). Hence, the minimum duty cycle is
achievable at this frequency.
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Current-Sense Resistor RSENSE
Based on the typical characteristics for the VSENSE limit with VIN versus duty cycle, the sense limit is
approximately 65 mV (at VIN = 12 V and duty cycle of 5 V / 12 V = 0.416). Allowing for tolerances and ripple
currents, choose VSENSE maximum of 50 mV.
Select 15 mΩ.
Inductor Selection L
As explained in the description of the buck controllers, for optimal slope compensation and loop response, the
inductor should be chosen such that:
KFLR = coil-selection constant = 200
Choose a standard value of 8.2 µH. For the buck converter, the inductor saturation currents and core should be
chosen to sustain the maximum currents.
Inductor Ripple Current IRIPPLE
At the nominal input voltage of 12 V, this gives a ripple current of 30% of IO max ≈ 1 A.
Output Capacitor CO
Select an output capacitance CO of 100 µF with low ESR in the range of 10 mΩ. This gives ∆VO(Ripple) ≈ 15 mV
and a ∆V drop of ≈ 180 mV during a load step, which does not trigger the power-good comparator and is within
the required limits.
Bandwidth of Buck Converter fC
Use the following guidelines to set frequency poles, zeroes, and crossover values for the trade-off between
stability and transient response.
•
•
•
Crossover frequency fC between fSW / 6 and fSW / 10. Assume fC = 50 kHz.
Select the zero fz ≈ fC / 10
Make the second pole fP2 ≈ fSW / 2
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SLVSAV6B –JUNE 2011–REVISED JULY 2012
Selection of Components for Type II Compensation
VO
RESR
R1
R2
VSENSE
RL
COMP
Type 2A
GmBUCK
CO
Vref
R3
C1
R0
C2
Figure 27. Buck Compensation Components
2p´ fC ´ VO ´ CO
2p´ 50 kHz ´ 5 V ´100μF
R3 =
=
= 23.57 kW
GmBUCK ´KCFB ´ VREF
GmBUCK ´KCFB ´ VREF
where VO = 5 V, CO = 100 µF, GmBUCK = 1 mS, VREF = 0.8 V, KCFB = 0.125 / RSENSE = 8.33 S (0.125 is an
internal constant)
Use the standard value of R3 = 24 kΩ.
10
10
C1=
=
2p´R3 ´ fC 2p´ 24 kW ´ 50 kHz
= 1.33 nF
Use standard value of 1.5 nF.
The resulting bandwidth of buck converter fC
GmBUCK ´R3 ´KCFB
VREF
fC =
´
2p´ CO
VO
1mS ´ 24 kW ´ 8.33 S ´ 0.8 V
2p´100 μF ´ 5 V
fC =
= 50.9 kHz
This is close to the target bandwidth of 50 kHz.
The resulting zero frequency fZ1
This is close to the fC / 10 guideline of 5 kHz.
The second pole frequency fP2
This is close to the fSW / 2 guideline of 200 kHz. Hence, all requirements for a good loop response are satisfied.
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Resistor Divider Selection for Setting VO Voltage
VREF
0.8 V
b =
=
= 0.16
VO
5 V
Choose the divider current through R1 and R2 to be 50 µA. Then
And
Therefore, R2 = 16 kΩ and R1 = 84 kΩ.
BuckB Component Selection
Using the same method as for VBUCKA, the following parameters and components are realized.
VO
3.3 V
tON min
=
=
IN max ´ fSW 30 V ´ 400 kHz
= 275 ns
V
This is higher than the min duty cycle specified (100 ns typical).
∆Iripple current ≈ 0.4 A (approx. 20% of IO max
)
Select an output capacitance CO of 100 µF with low ESR in the range of 10 mΩ. This gives ∆VO (ripple) ≈ 7.5 mV
and ∆V drop of ≈ 120 mV during a load step.
Assume fC = 50 kHz.
2p´ fC ´ VO ´ CO
R3 =
GmBUCK ´KCFB ´ VREF
2p´ 50 kHz ´ 3.3 V ´100 mF
=
= 31kW
1mS ´ 4.16 S ´ 0.8 V
Use standard value of R3 = 30 kΩ.
10
10
C1=
=
2p´R3 ´ fC 2p´ 30 kW ´ 50 kHz
= 1.1nF
C1
f
C2 =
æ
ö
÷
ø
SW
2p´R3 ´ C1´
-1
ç
è
2
1.1nF
=
= 27 pF
400 kHz
2
æ
ö
÷
ø
2p´ 30 kW ´1.1nF´
-1
ç
è
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SLVSAV6B –JUNE 2011–REVISED JULY 2012
GmBUCK ´R3 ´KCFB VREF
´
fC =
2p´ CO
VO
1mS ´ 30 kW ´ 4.16 S ´ 0.8 V
2p´100 μF ´ 3.3 V
=
= 48 kHz
This is close to the target bandwidth of 50 kHz.
The resulting zero frequency fZ1
1
1
fZ1
=
=
2p´R3 ´ C1 2p´ 30 kW ´1.1nF
= 4.8 kHz
This is close to the fC guideline of 5 kHz.
The second pole frequency fP2
1
1
fP2
=
=
2p´R3 ´ C2 2p´ 30 kW ´ 27 pF
= 196 kHz
This is close to the fSW / 2 guideline of 200 kHz.
Hence, all requirements for a good loop response are satisfied.
Resistor Divider Selection for Setting VO Voltage
VREF
0.8 V
b =
=
= 0.242
VO
3.3 V
Choose the divider current through R1 and R2 to be 50 µA. Then
And
Therefore, R2 = 16 kΩ and R1 = 50 kΩ.
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BuckX High-Side and Low-Side N-Channel MOSFETs
The gate-drive supply for these MOSFETs is supplied by an internal supply, which is 5.8 V typical under normal
operating conditions. The output is a totem pole, allowing full voltage drive of VREG to the gate with peak output
current of 1.2 A. The high-side MOSFET is referenced to a floating node at the phase terminal (PHx), and the
low-side MOSFET is referenced to the power-ground (PGND) terminal. For a particular application, these
MOSFETs should be selected with consideration for the following parameters: rDS(on), gate charge Qg, drain-to-
source breakdown voltage BVDSS, maximum dc current IDC(max), and thermal resistance for the package.
The times tr and tf denote the rising and falling times of the switching node and are related to the gate-driver
strength of the TPS43335-Q1 and TPS43336-Q1, and the gate Miller capacitance of the MOSFET. The first term
denotes the conduction losses, which are minimized when the on-resistance of the MOSFET is low. The second
term denotes the transition losses, which arise due to the full application of the input voltage across the drain-
source of the MOSFET as it turns on or off. They are lower at low currents and when the switching time is low.
V ´I
æ
ç
è
O ö
÷
ø
= (IO )2 ´rDS(on)(1+ TC)´D +
´(tr + tf )´ fSW
I
P
BuckTOPFET
2
P
= (IO )2 ´rDS(on)(1+ TC)´(1-D) + VF ´IO ´(2´ td )´ fSW
buckLOWERFET
In addition, during the dead time td when both the MOSFETs are off, the body diode of the low-side MOSFET
conducts, increasing the losses. This is denoted by the second term in the above equation. Using external
Schottky diodes in parallel with the low-side MOSFETs of the buck converters helps to reduce this loss.
Note: rDS(on) has a positive temperature coefficient, which is accounted for in the TC term for rDS(on). TC = d ×
ΔT[°C]. The temperature coefficient d is available as a normalized value from MOSFET data sheets and can be
assumed to be 0.005 / ºC as a starting value.
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SLVSAV6B –JUNE 2011–REVISED JULY 2012
Schematics
The following section summarizes the previously calculated example and gives schematic and component
proposals.
Table 4. Application Example 1
PARAMETER
VBUCK A
VBUCK B
BOOST
VIN 6 V to 30 V
12 V - typical
VIN 6 V to 30 V
12 V - typical
VBAT - 5 V (cranking
pulse input) to 30 V
Input voltage
Output voltage, VO
5 V
3 A
3.3 V
2 A
10 V
2.5 A
Maximum output current, IO
Load step output tolerance, ∆VO
Current output load step, ∆IO
Converter switching frequency, fSW
±0.2 V
±0.12 V
0.1 A to 2 A
400 kHz
±0.5 V
0.1 A to 3 A
400 kHz
0.1 A to 2.5 A
200 kHz
2.5V to 40V
VBAT
L1
D1
BOOST 10V, 25W
3.9µH
680µF
COUT1
10µF
CIN
220µF
TOP-SW3
1kΩ
VBAT
DS
VIN
EXTSUP
DIV
0.1µF
BOT-SW3
0.02Ω
1.5kΩ
1nF
GC1
GC2
VREG
CBB
3.3µF
0.1µF
CBA
TOP-SW2
L3
TOP-SW1
0.1µF
VBUCKA - 5V, 15W
0.015Ω
VBUCKB – 3.3V, 6.6W
L2
0.03Ω
GA1
GB1
8.2µH
15µH
100µF
COUTA
100µF
COUTB
PHA
PHB
BOT-SW2
BOT-SW1
GA2
GB2
PGNDA
SA1
PGNDB
SB1
TPS43335-Q1
or
TPS43336-Q1
84kΩ
16kΩ
50kΩ
16kΩ
SA2
SB2
FBA
FBB
COMPA
SSA
COMPB
SSB
33pF
27pF
1.5nF
1.1nF
30kΩ
10nF
24kΩ
10nF
PGA
ENA
PGB
5kΩ
5kΩ
AGND
RT
ENB
COMPC
ENC
DLYAB
SYNC
220pF
22nF
1nF
7.2kΩ
Figure 28. Simplified Application Schematic, Example 1
Table 5. Application Example 1 – Component Proposals
Name
Component Proposal
Value
L1
L2
L3
D1
MSS1278T-392NL (Coilcraft)
4 µH
8.2 µH
15 µH
MSS1278T-822ML (Coilcraft)
MSS1278T-153ML (Coilcraft)
SK103 (Micro Commercial Components)
IRF7416 (International Rectifier)
TOP_SW3
TOP_SW1, TOP_SW2 Si4840DY-T1-E3 (Vishay)
BOT_SW1, BOT_SW2 Si4840DY-T1-E3 (Vishay)
BOT_SW3
COUT1
IRFR3504ZTRPBF (International Rectifier)
EEVFK1J681M (Panasonic)
ECASD91A107M010K00 (Murata)
EEEFK1V331P (Panasonic)
680 µF
100 µF
220 µF
COUTA, COUTB
CIN
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Table 6. Application Example 2
PARAMETER
VBUCK A
VBUCK B
BOOST
VIN 5 V to 30 V
12 V - typical
VIN 6 V to 30 V
12 V - typical
VBAT - 5 V (cranking
pulse input) to 30 V
Input voltage
Output voltage, VO
5 V
3 A
2.5 V
1 A
10 V
2 A
Maximum output current, IO
Load step output tolerance, ∆VO
Current output load step, ∆IO
Converter switching frequency, fSW
±0.2 V
±0.12 V
0.1 A to 1 A
400 kHz
±0.5 V
0.1 A to 3 A
400 kHz
0.1 A to 2 A
200 kHz
5V to 30V
VBAT
L1
D1
BOOST 10V, 20W
3.9µH
CIN
330µF
470µF
COUT1
TOP-SW3
1kΩ
VBAT
DS
VIN
EXTSUP
DIV
0.1µF
BOT-SW3
0.03Ω
1.5kΩ
470pF
GC1
GC2
VREG
CBB
3.3µF
0.1µF
CBA
TOP-SW2
L3
0.1µF
TOP-SW1
VBUCKA - 5V, 15W
0.015Ω
VBUCKB – 2.5V, 2.5W
L2
0.045Ω
GA1
GB1
10uH
22uH
PHA
PHB
150µF
COUTA
100µF
COUTB
BOT-SW2
BOT-SW1
GA2
GB2
PGNDA
PGNDB
SB1
TPS43335-Q1
or
TPS43336-Q1
34kΩ
16kΩ
84kΩ
16kΩ
SA1
SA2
SB2
FBA
FBB
COMPA
SSA
COMPB
SSB
20pF
1nF
1nF
47pF
5kΩ
36kΩ
10nf
39kΩ
10nF
PGA
PGB
5k
ENA
AGND
RT
ENB
COMPC
ENC
DLYAB
SYNC
220pF
1nF
18nF
8.2kΩ
Figure 29. Simplified Application Schematic, Example 2
Table 7. Application Example 2 – Component Proposals
Name
Component Proposal
Value
L1
L2
L3
D1
MSS1278T-392NL (Coilcraft)
3.9 µH
8.2 µH
22 µH
MSS1278T-822ML (Coilcraft)
MSS1278T-223ML (Coilcraft)
SK103 (Micro Commercial Components)
IRF7416 (International Rectifier)
TOP_SW3
TOP_SW1, TOP_SW2 Si4840DY-T1-E3 (Vishay)
BOT_SW1, BOT_SW2 Si4840DY-T1-E3 (Vishay)
BOT_SW3
COUT1
COUTA
COUTB
CIN
IRFR3504ZTRPBF (International Rectifier)
EEVFK1V471Q (Panasonic)
470 µF
150 µF
100 µF
330 µF
ECASD91A157M010K00 (Murata)
ECASD40J107M015K00 (Murata)
EEEFK1V331P (Panasonic)
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SLVSAV6B –JUNE 2011–REVISED JULY 2012
Power Dissipation Derating Profile, 38-Pin HTTSOP PowerPAD Package
Figure 30. Power Dissipation Derating Profile Based on High-K JEDEC PCB
PCB Layout Guidelines
Grounding and PCB Circuit Layout Considerations
Boost converter
1. The path formed from the input capacitor to the inductor and BOT_SW3 with the low side-current sense-
resistor should have short leads and PC trace lengths. The same applies for the trace from the inductor to
Schottky diode D1 to the COUT1 capacitor. The negative terminal of the input capacitor and the negative
terminal of the sense resistor must be connected together with short trace lengths.
2. The overcurrent-sensing shunt resistor may require noise filtering, and this capacitor should be close to the
IC pin.
Buck Converter
1. Connect the drain of TOP_SW1 and TOP_SW2 together with the positive terminal of input capacitor COUT1.
The trace length between these terminals should be short.
2. Connect a local decoupling capacitor between the drain of TOP_SWx and the source of BOT_SWx.
3. The Kelvin-current sensing for the shunt resistor should have traces with minimum spacing, routed in parallel
with each other. Any filtering capacitors for noise should be placed near the IC pins.
4. The resistor divider for sensing the output voltage is connected between the positive terminal of its respective
output capacitor and COUTA or COUTB and the IC signal ground. These components and the traces should
not be routed near any switching nodes or high-current traces.
Other Considerations
1. PGNDx and AGND should be shorted to the thermal pad. Use a star ground configuration if connecting to a
non-ground plane system. Use tie-ins for the EXTSUP capacitor, compensation-network ground, and
voltage-sense feedback ground networks to this star ground.
2. Connect a compensation network between the compensation pins and IC signal ground. Connect the
oscillator resistor (frequency setting) between the RT pin and IC signal ground. These sensitive circuits
should NOT be located near the dv/dt nodes; these include the gate-drive outputs, phase pins, and boost
circuits (bootstrap).
3. Reduce the surface area of the high-current-carrying loops to a minimum, by ensuring optimal component
placement. Ensure the bypass capacitors are located as close as possible to their respective power and
ground pins.
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PCB Layout
POWER
INPUT
Power L ines
Connection to GND P lane ofPCB through vias
Connection to top /bottom ofPCB through vias
Vo ltage Ra ilOutputs
VBOOST
VBAT
DS
V IN
EXTSUP
D IV
GC1
GC2
CBA
VREG
CBB
GA1
PHA
GB1
PHB
GA2
PGNDA
SA1
GB2
PGNDB
SB1
SA2
SB2
FBA
FBB
COMPA
SSA
COMPB
SSB
PGA
ENA
PGB
AGND
RT
ENB
COMPC
ENC
DLYAB
SYNC
Exposed Pad
connected to GND
P lane
M icrocontro ller
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PACKAGE OPTION ADDENDUM
www.ti.com
24-May-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS43335QDAPRQ1
TPS43336QDAPRQ1
ACTIVE
ACTIVE
HTSSOP
HTSSOP
DAP
DAP
38
38
2000
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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TI
TPS43340QPHPRQ1
LOW IQ, 30 μA, HIGH VIN QUAD-OUTPUT POWER SUPPLYWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS43350-Q1
LOW IQ, DUAL SYNCHRONOUS BUCK CONTROLLERWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS43350-Q1_15
LOW IQ, DUAL SYNCHRONOUS BUCK CONTROLLERWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS43350QDAPRQ1
LOW IQ, DUAL SYNCHRONOUS BUCK CONTROLLERWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS43351-Q1
LOW IQ, DUAL SYNCHRONOUS BUCK CONTROLLERWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS43351QDAPQ1
IC 0.4 A DUAL SWITCHING CONTROLLER, 600 kHz SWITCHING FREQ-MAX, PDSO38, PLASTIC, HTSSOP-38, Switching Regulator or ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
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