V62/05622-01XE [TI]

3 V TO 6 V INPUT, 6 A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFTâ¢); 3 V至6 V输入， 6 A输出同步降压型PWM具有集成FET SWITCHER （ SWIFTâ ?? ¢ ）


型号：	V62/05622-01XE
厂家：	TEXAS INSTRUMENTS
描述：	3 V TO 6 V INPUT, 6 A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFTâ¢) 3 V至6 V输入， 6 A输出同步降压型PWM具有集成FET SWITCHER （ SWIFTâ ?? ¢ ）输出元件输入元件
文件：	总24页 (文件大小：829K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Typical Size

6,4 mm X 9,7 mm

TPS54610-EP

www.ti.com

SGLS294A–FEBRUARY 2005–REVISED AUGUST 2007

3 V TO 6 V INPUT, 6 A OUTPUT SYNCHRONOUS BUCK PWM

SWITCHER WITH INTEGRATED FETs (SWIFT™)

FEATURES

APPLICATIONS

•

Low-Voltage, High-Density Distributed Power

Systems

•

Controlled Baseline

–

One Assembly/Test Site, One Fabrication

Site

•

Point-of-Load Regulation for High-

Performance DSPs, FPGAs, ASICs, and

Microprocessors

Broadband, Networking, and Optical

Communications Infrastructure

•

Extended Temperature Performance of –55°C

to 125°C

•

Enhanced Diminishing Manufacturing Sources

(DMS) Support

Portable Computing/Notebook PCs

•

Enhanced Product-Change Notification

(1)

DESCRIPTION/ORDERING INFORMATION

Qualification Pedigree

30 mΩ, 12 A Peak MOSFET Switches for High

Efficiency at 6 A Continuous Output Source or

Sink Current

As a member of the SWIFT™ family of dc/dc

regulators, the TPS54610 low-input voltage

high-output current synchronous buck PWM

converter integrates all required active components.

Included on the substrate with the listed features are

a true, high-performance, voltage error amplifier that

enables maximum performance and flexibility in

choosing the output filter L and C components, an

under-voltage-lockout circuit to prevent start-up until

the input voltage reaches 3 V, an internally or

externally set slow-start circuit to limit inrush currents,

and a power good output useful for processor/logic

reset, fault signaling, and supply sequencing.

•

Adjustable Output Voltage Down to 0.9 V With

1% Accuracy

Wide PWM Frequency: Fixed 350 kHz, 550 kHz

or Adjustable 280 kHz to 700 kHz

•

Synchronizable to 700 kHz

Load Protected by Peak Current Limit and

Thermal Shutdown

•

Integrated Solution Reduces Board Area and

Component Count

The TPS54610 is available in a thermally enhanced

28-pin TSSOP (PWP) PowerPAD™ package, which

eliminates bulky heatsinks. Texas Instruments

provides evaluation modules and the SWIFT™

designer software tool to aid in quickly achieving

high-performance power supply designs to meet

aggressive equipment development cycles.

(1) Component qualification in accordance with JEDEC and

industry standards to ensure reliable operation over an

extended temperature range. This includes, but is not limited

to, Highly Accelerated Stress Test (HAST) or biased 85/85,

temperature cycle, autoclave or unbiased HAST,

electromigration, bond intermetallic life, and mold compound

life. Such qualification testing should not be viewed as

justifying use of this component beyond specified

performance and environmental limits.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SWIFT, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS54610-EP

www.ti.com

SGLS294A–FEBRUARY 2005–REVISED AUGUST 2007

SIMPLIFIED SCHEMATIC

EFFICIENCY AT 350 kHz

100

Input

Output

VIN

TPS54610

BOOT

PGND

VSENSE

VBIAS

AGND COMP

V = 5 V,

= 3.3 V

Load Current − A

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION⁽¹⁾

(2)

T_J

OUTPUT VOLTAGE

PACKAGE

PART NUMBER

–55°C to 125°C

Adjustable down to 0.9 V

Plastic HTSSOP (PWP)

TPS54610MPWPREP

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

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SGLS294A–FEBRUARY 2005–REVISED AUGUST 2007

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

TPS54610M

–0.3 V to 7 V

–0.3 V to 6 V

–0.3 V to 4 V

–0.3 V to 17 V

–0.3 V to 7 V

–0.6 V to 10 V

Internally Limited

6 mA

VIN, SS/ENA, FSEL

V_I

Input voltage range

VSENSE

BOOT

VBIAS, COMP, PWRGD

V_O

Output voltage range

Source current

I_O

COMP, VBIAS

12 A

I_S

Sink current

COMP

6 mA

SS/ENA, PWRGD

AGND to PGND

10 mA

Voltage differential

ꢀ 0.3 V

T_J

Operating virtual junction temperature range

Storage temperature

–55°C to 150°C

–65°C to 150°C

300°C

T_stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

MIN

NOM

MAX

UNIT

V_I

Input voltage

T_J

Operating junction temperature

–55

125

°C

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SGLS294A–FEBRUARY 2005–REVISED AUGUST 2007

DISSIPATION RATINGS^{(1) (2)}

THERMAL IMPEDANCE

JUNCTION-TO-AMBIENT

T_A= 25°C

POWER RATING

T_A= 70°C

POWER RATING

T_A= 85°C

POWER RATING

PACKAGE

28-pin PWP with solder

18.2°C/W

5.49 W⁽³⁾

3.02 W

1.36 W

2.20 W

28-pin PWP without solder

40.5°C/W

2.48 W

0.99 W

(1) For more information on the PWP package, see the Texas Instruments technical brief SLMA002.

(2) Test board conditions:

a. 3 inch x 3 inch, 4 layers, thickness: 0.062 inch

b. 1.5 oz. copper traces located on the top of the PCB

c. 1.5 oz. copper ground plane on the bottom of the PCB

d. 0.5 oz. copper ground planes on the two internal layers

e. 12 thermal vias (see Recommended Land Pattern in the Application Information section of this data sheet.

(3) Maximum power dissipation may be limited by overcurrent protection.

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

SUPPLY VOLTAGE, VINL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input voltage range, V_IN

f_s= 350 kHz, FSEL ≤ 0.8 V, RT open, PH pin

open

9.8

I_(Q)

Quiescent current

f_s= 550 kHz, FSEL ≥ 2.5 V, RT open, PH pin

open

Shutdown, SS/ENA = 0 V

1.4

UNDER VOLTAGE LOCK OUT

Start threshold voltage, UVLO

Stop threshold voltage, UVLO

Hysteresis voltage, UVLO

Rising and falling edge deglitch, UVLO⁽¹⁾

BIAS VOLTAGE

2.95

2.8

2.7

0.12

0.16

2.5

µs

Output voltage, VBIAS

Output current, VBIAS⁽²⁾

I_(VBIAS)= 0

2.7

2.8

2.95

100

ꢀ A

CUMULATIVE REFERENCE

(1)

V_ref

Accuracy

0.882 0.891

0.9

REGULATION

I_L= 3 A, f_s= 350 kHz, T_J= 85°C

0.07

0.03

Line regulation^{(1) (3)}

Load regulation^{(1) (3)}

OSCILLATOR

%/V

%/A

I_L= 3 A, f_s= 550 kHz, T_J= 85°C

I_L= 0 A to 6 A, f_s= 350 kHz, T_J= 85°C

I_L= 0 A to 6 A, f_s= 550 kHz, T_J= 85°C

FSEL ≤ 0.8 V, RT open

270

415

245

285

655

2.5

350

550

280

312

700

425

662

315

360

773

Internally set—free-running frequency

kHz

FSEL ≥ 2.5 V, RT open

Externally set—free-running frequency

range

RT = 180 kΩ (1% resistor to AGND)⁽¹⁾

RT = 160 kΩ (1% resistor to AGND)⁽¹⁾

RT = 68 kΩ (1% resistor to AGND)⁽¹⁾

High-level threshold, FSEL

Low-level threshold, FSEL

0.8

Pulse duration, external synchronization,

FSEL⁽¹⁾

Frequency range, FSEL⁽¹⁾

330

700

kHz

(1) Specified by design

(2) Static resistive loads only

(3) Specified by the circuit used in Figure 10.

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SGLS294A–FEBRUARY 2005–REVISED AUGUST 2007

ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Ramp valley⁽¹⁾

Ramp amplitude (peak-to-peak)⁽¹⁾

Minimum controllable on time⁽¹⁾

Maximum duty cycle⁽¹⁾

TEST CONDITIONS

MIN

TYP

0.75

MAX

UNIT

200

90%

ERROR AMPLIFIER

Error amplifier open loop voltage gain

Error amplifier unity gain bandwidth

1 kΩ COMP to AGND⁽¹⁾

Parallel 10 kΩ, 160 pF COMP to AGND⁽¹⁾

110

MHz

Error amplifier common mode input

voltage range

VBIAS

Input bias current, VSENSE⁽⁴⁾

VSENSE = V_ref

Output voltage slew rate (symmetric),

COMP⁽¹⁾

1.4

V/µs

PWM COMPARATOR

PWM comparator propagation delay time,

PWM comparator input to PH pin

(excluding deadtime)

10-mV overdrive⁽¹⁾

SLOW-START/ENABLE

Enable threshold voltage, SS/ENA

Enable hysteresis voltage, SS/ENA⁽⁵⁾

Falling edge deglitch, SS/ENA⁽⁵⁾

Internal slow-start time⁽⁶⁾

0.82

1.2

0.03

2.5

1.4

µs

µA

2.5

1.1

3.35

4.5

Charge current, SS/ENA

SS/ENA = 0 V

Discharge current, SS/ENA

SS/ENA = 1.2 V, V_I= 2.7 V

2.3

POWER GOOD

Power good threshold voltage

Power good hysteresis voltage⁽⁵⁾

Power good falling edge deglitch⁽⁵⁾

Output saturation voltage, PWRGD

Leakage current, PWRGD

VSENSE falling

%V_ref

µs

I(sink) = 2.5 mA

V_I= 5.5 V

0.18

100

0.31

CURRENT LIMIT

Current limit trip point

V_I= 3 V⁽⁵⁾

V_I= 6 V⁽⁵⁾

Current limit leading edge blanking time⁽⁵⁾

Current limit total response time⁽⁵⁾

100

200

THERMAL SHUTDOWN

Thermal shutdown trip point⁽⁵⁾

Thermal shutdown hysteresis⁽⁵⁾

135

150

165

°C

OUTPUT POWER MOSFETs

V_I= 6 V⁽⁶⁾

V_I= 3 V⁽⁶⁾

r_DS(on)Power MOSFET switches

mΩ

(4) Matched MOSFETs low-side r_DS(on)production tested, high-side r_DS(on)specified by design.

(5) Specified by design

(6) Matched MOSFETs low-side r_DS(on)production tested, high-side r_DS(on)specified by design.

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SGLS294A–FEBRUARY 2005–REVISED AUGUST 2007

PWP PACKAGE

(TOP VIEW)

AGND

VSENSE

COMP

PWRGD

BOOT

FSEL

SS/ENA

VBIAS

VIN

THERMAL

PAD

VIN

PGND

TERMINAL FUNCTIONS

TERMINAL

DESCRIPTION

NAME

NO.

Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and

FSEL pin. Connect PowerPAD to AGND.

AGND

Bootstrap output. 0.022-μF to 0.1-μF low-ESR capacitor connected from BOOT to PH generates floating drive for the

high-side FET driver.

BOOT

COMP

Error amplifier output. Connect frequency compensation network from COMP to VSENSE.

Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas

PGND

15–19 to the input and output supply returns, and negative terminals of the input and output capacitors. A single point

connection to AGND is recommended.

6–14 Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.

Power good open drain output. High when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low

when SS/ENA is low or the internal shutdown signal is active.

PWRGD

Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency. When using the

FSEL pin, set the RT value for a frequency at or slightly lower than the external oscillator frequency.

Slow-start/enable input/output. Dual function pin, which provides logic input to enable/disable device operation and

capacitor input to externally set the start-up time.

SS/ENA

Synchronization input. Dual function pin, which provides logic input to synchronize to an external oscillator or pin select

FSEL

between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be

connected to the RT pin.

Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a

high-quality, low-ESR 0.1-μF to 1-μF ceramic capacitor.

VBIAS

Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to

device package with a high-quality, low-ESR 10-μF ceramic capacitor.

VIN

20–24

VSENSE

Error amplifier inverting input. Connect to output voltage through compensation network/output divider.

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SGLS294A–FEBRUARY 2005–REVISED AUGUST 2007

VBIAS

AGND

VBIAS

VIN

Enable

Comparator

SS/ENA

REG

Falling

Edge

Deglitch

SHUTDOWN

VIN

ILIM

Comparator

1.2 V

Hysteresis: 0.03 V

3 V − 6 V

Thermal

Shutdown

150°C

Leading

Edge

2.5 µs

Blanking

VIN UVLO

Comparator

Falling

and

100 ns

VIN

BOOT

Rising

Edge

2.95 V

Deglitch

Hysteresis: 0.16 V

30 mΩ

2.5 µs

SS_DIS

SHUTDOWN

OUT

Internal/External

Slow-Start

(Internal Slow-start Time = 3.35 ms

−

Adaptive Dead-Time

and

Control Logic

Error

Amplifier

PWM

Comparator

Reference

VIN

VREF = 0.891 V

30 mΩ

OSC

PGND

Powergood

Comparator

PWRGD

VSENSE

0.90 V

Falling

Edge

ref

Deglitch

TPS54610

Hysteresis: 0.03 Vref

SHUTDOWN

35 µs

FSEL

VSENSE

COMP

ADDITIONAL 6-A SWIFT™ DEVICES, (See SGLS293)

DEVICE

OUTPUT VOLTAGE

DEVICE

OUTPUT VOLTAGE

DEVICE

OUTPUT VOLTAGE

TPS54611M⁽¹⁾

TPS54612M⁽¹⁾

TPS5413M

0.9 V

1.2 V

1.5 V

TPS54614M⁽¹⁾

TPS54615M

TPS54616M⁽¹⁾

1.8 V

2.5 V

3.3 V

TPS54680M⁽¹⁾

Sequencing/Adj.

(1) Product Preview

RELATED DC/DC PRODUCTS

•

TPS40055M—dc/dc controller

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SGLS294A–FEBRUARY 2005–REVISED AUGUST 2007

TYPICAL CHARACTERISTICS

DRAIN-SOURCE

INTERNALLY SET

ON-STATE RESISTANCE

OSCILLATOR FREQUENCY

JUNCTION TEMPERATURE

750

650

550

VIN = 3.3 V

VIN = 5 V

= 6 A

FSEL ≥ 2.5 V

FSEL ≤ 0.8 V

450

350

250

−40

125

−40

125

−40

125

− Junction Temperature − °C

Figure 1.

Figure 2.

Figure 3.

DRAIN-SOURCE

DEVICE POWER LOSSES

AT T_J= 125°C

ON-STATE RESISTANCE

VOLTAGE REFERENCE

JUNCTION TEMPERATURE

LOAD CURRENT

0.895

0.893

0.891

0.889

800

700

600

= 125°C

4.5

= 700 kHz

RT = 68 k

RT = 100 k

RT = 180 k

V = 3.3 V

3.5

2.5

500

400

300

200

1.5

V = 5 V

0.887

0.885

0.5

−40

125

−40

125

− Junction Temperature − °C

− Load Current − A

Figure 4.

Figure 5.

Figure 6.

OUTPUT VOLTAGE REGULATION

INTERNAL SLOW-START TIME

JUNCTION TEMPERATURE

ERROR AMPLIFIER

OPEN LOOP RESPONSE

INPUT VOLTAGE

3.80

0.895

0.893

0.891

0.889

140

= 10 kΩ,

= 160 pF,

= 25°C

= 85°C,

= 3 A

−20

−40

−60

−80

120

100

3.65

3.50

Phase

Gain

= 550 kHz

3.35

−100

−120

−140

−160

−180

−200

3.20

3.05

0.887

0.885

2.90

2.75

−20

10 100 1 k 10 k 100 k 1 M 10 M

−40

125

3.5

4.5

5.5

f − Frequency − Hz

− Junction Temperature − °C

V − Input Voltage − V

Figure 7.

Figure 8.

Figure 9.

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SGLS294A–FEBRUARY 2005–REVISED AUGUST 2007

APPLICATION INFORMATION

Figure 10 shows the schematic diagram for a typical TPS54610 application. The TPS54610 (U1) can provide

greater than 6 A of output current at a nominal output voltage of 3.3 V. For proper thermal performance, the

exposed thermal PowerPAD under the integrated circuit package must be soldered to the printed-circuit board.

220 µF

10 V

TPS54610PWP

10 µF

VIN

10 kΩ

FSEL

4.7 µH

SS/ENA

VBIAS

PWRGD

COMP

470 µF

4 V

C10

470 µF

4 V

C11

100 pF

0.047 µF

PWRGD

0.1 µF

BOOT

PGND

VSENSE

0.047 µF

PGND

AGND

5600 pF

120 pF

POWERPAD

9.09 kΩ

1.74 kΩ

8200 pF

3.74 kΩ

10 kΩ

Figure 10. Application Circuit

COMPONENT SELECTION

The values for the components used in this design example were selected using the SWIFT designer software

tool. SWIFT designer provides a complete design environment for developing dc-dc converters using the

TPS54610.

INPUT FILTER

The input to the circuit is a nominal 5 VDC. The input filter C2 is a 220-μF POSCAP capacitor, with a maximum

allowable ripple current of 3 A. C8 provides high-frequency decoupling of the TPS54610 from the input supply

and must be located as close as possible to the device. Ripple current is carried in both C2 and C8, and the

return path to PGND must avoid the current circulating in the output capacitors C9 and C10.

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SGLS294A–FEBRUARY 2005–REVISED AUGUST 2007

FEEDBACK CIRCUIT

The resistor divider network of R3 and R4 sets the output voltage for the circuit at 3.3 V. R4, along with R1, R5,

C3, C5, and C6 form the loop compensation network for the circuit. For this design, a Type 3 topology is used.

OPERATING FREQUENCY

In the application circuit, the 350 kHz operation is selected by leaving RT and FSEL open. Connecting a 180 kΩ

to 68 kΩ resistor between RT (pin 28) and analog ground can be used to set the switching frequency to 280 kHz

to 700 kHz. To calculate the RT resistor, use Equation 1:

500 kHz

Switching Frequency

R +

100 kW

(1)

OUTPUT FILTER

The output filter is composed of a 4.7 μH inductor and two 470 μF capacitors. The inductor is a low dc resistance

(12 mΩ) type, Coiltronics UP3B-4R7. The capacitors used are 4-V POSCAP types with a maximum ESR of

0.040 Ω. The feedback loop is compensated so that the unity gain frequency is approximately 25 kHz.

PCB LAYOUT

Figure 11 shows a generalized PCB layout guide for the TPS54610.

The VIN pins are connected together on the printed-circuit board (PCB) and bypassed with a low-ESR

ceramic-bypass capacitor. Care should be taken to minimize the loop area formed by the bypass capacitor

connections, the VIN pins, and the TPS54610 ground pins. The minimum recommended bypass capacitance is

10 mF ceramic capacitor with a X5R or X7R dielectric and the optimum placement is closest to the VIN pins and

the PGND pins.

The TPS54610 has two internal grounds (analog and power). Inside the TPS54610, the analog ground ties to all

of the noise-sensitive signals, while the power ground ties to the noisier power signals. Noise injected between

the two grounds can degrade the performance of the TPS54610, particularly at higher output currents. However,

ground noise on an analog ground plane also can cause problems with some of the control and bias signals. For

these reasons, separate analog and power ground traces are recommended. There is an area of ground on the

top layer directly under the IC, with an exposed area for connection to the PowerPAD. Use vias to connect this

ground area to any internal ground planes. Additional vias are also used at the ground side of the input and

output filter capacitors. The AGND and PGND pins are tied to the PCB ground by connecting them to the ground

area under the device as shown. The only components that tie directly to the power ground plane are the input

capacitors, the output capacitors, the input voltage decoupling capacitor, and the PGND pins of the TPS54610.

Use a separate wide trace for the analog ground signal path. The analog ground is used for the voltage set point

divider, timing resistor RT, slow-start capacitor and bias capacitor grounds. Connect this trace directly to AGND

(Pin 1).

The PH pins are tied together and routed to the output inductor. Because the PH connection is the switching

node, the inductor is located close to the PH pins. The area of the PCB conductor is minimized to prevent

excessive capacitive coupling. Connect the boot capacitor between the phase node and the BOOT pin as shown.

Keep the boot capacitor close to the IC and minimize the conductor trace lengths.

Connect the output filter capacitor(s) as shown between the VOUT trace and PGND. It is important to keep the

loop formed by the PH pins, LOUT, COUT and PGND as small as practical.

Place the compensation components from the VOUT trace to the VSENSE and COMP pins. Do not place these

components too close to the PH trace. Due to the size of the IC package and the device pin-out, they must be

routed close, but maintain as much separation as possible while still keeping the layout compact.

Connect the bias capacitor from the VBIAS pin to analog ground using the isolated analog ground trace. If a

slow-start capacitor or RT resistor is used, or if the FSEL pin is used to select 350-kHz operating frequency,

connect them to this trace.

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SGLS294A–FEBRUARY 2005–REVISED AUGUST 2007

LAYOUT CONSIDERATIONS FOR THERMAL PERFORMANCE

For operation at full-rated load current, the analog ground plane must provide an adequate heat dissipating area.

A 3 inch by 3 inch plane of 1-ounce copper is recommended, though not mandatory, depending on ambient

temperature and airflow. Most applications have larger areas of internal ground plane available and the

PowerPAD must be connected to the largest area available. Additional areas on the top or bottom layers also

help dissipate heat and any area available must be used when 6 A or greater operation is desired. Connection

from the exposed area of the PowerPAD to the analog ground plane layer must be made using 0.013 inch

diameter vias to avoid solder wicking through the vias. Eight vias must be in the PowerPAD area with four

additional vias located under the device package. The size of the vias under the package, but not in the exposed

thermal pad area, can be increased to 0.018. Additional vias beyond the 12 recommended that enhance thermal

performance must be included in areas not under the device package.

Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside

Powerpad Area 4 x 0.018 Diameter Under Device as Shown.

Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground

Area Is Extended.

Ø0.0130

8 PL

4 PL Ø0.0180

Connect Pin 1 to Analog Ground Plane

in This Area for Optimum Performance

0.0150

0.06

0.0339

0.0650

0.0500

0.3820 0.3478

0.2090

0.0256

0.0500

0.0650

0.0339

Minimum Recommended Exposed

Copper Area for Powerpad. 5-mm

Stencils May Require 10 Percent

0.1700

Larger Area

0.1340

0.0630

Minimum Recommended Top

Side Analog Ground Area

0.0400

Figure 11. Recommended Land Pattern for 28-Pin PWP PowerPAD

PERFORMANCE GRAPHS

Safe operating area is applicable to the test board conditions in the Dissipation Ratings.

EFFICIENCY

OUTPUT CURRENT

EFFICIENCY

OUTPUT CURRENT

LOAD REGULATION

OUTPUT CURRENT

100

1.004

1.003

V = 5 V,

= 3.3 V,

= 25°C,

1.002

1.001

= 550 kHz

= 3.3 V

= 2.5 V

= 1.8 V

V = 1.8 V

= 1.2 V

0.999

V = 3.3 V,

f = 550 kHz,

L = 4.7 µH,

V = 5 V,

f = 550 kHz,

L = 4.7 µH,

0.998

0.997

0.996

= 25°C

− Output Current − A

Figure 12.

Figure 13.

Figure 14.

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SGLS294A–FEBRUARY 2005–REVISED AUGUST 2007

PERFORMANCE GRAPHS (continued)

LINE REGULATION

INPUT VOLTAGE

AMBIENT TEMPERATURE

LOOP RESPONSE

LOAD CURRENT

1.002

125

115

105

180

135

V = 5 V,

= 125°C

= 3.3 V,

1.0015

= 700 kHz

= 6 A,

= 25°C,

= 6 A

= 25°C,

= 550 kHz

1.001

1.0005

V = 5 V

= 550 kHz

= 3 A

Safe Operating

(NO TAG)

Area

Phase

V = 3.3 V

0.9995

No Load

Gain

0.999

0.9985

0.998

−20

4.5

5.5

100

1 k

10 k

100 k

1 M

f − Frequency − Hz

− Output Current − A

V − Input Voltage − V

Figure 15.

Figure 16.

LOAD TRANSIENT RESPONSE

Figure 17.

OUTPUT RIPPLE VOLTAGE

SLOW-START TIMING

V = 5 V,

0.047 µF

Slow-start Cap

V = 5 V,

= 3.3 V,

6A, 350 kHz

V = 5 V,

1A to 5A,

4.0 ms/div

Time − 1 µs/div

100 µs/div

Figure 18.

Figure 19.

Figure 20.

Figure 21 shows the schematic diagram for a reduced size, high frequency application using the TPS54610. The

TPS54610 (U1) can provide up to 6 A of output current at a nominal output voltage of 1.8 V. A small size 0.56

µH inductor is used and the switching frequency is set to 680 kHz by R1. The compensation network is optimized

for fast transient response as shown in Figure 21. For good thermal performance, the PowerPAD underneath the

integrated circuit TPS54610 needs to be soldered well to the printed-circuit board. Application information is

available in SLVA107, Designing for Small-Size, High-Frequency Applications With Swift™ Family of

Synchronous Buck Regulators application note.

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SGLS294A–FEBRUARY 2005–REVISED AUGUST 2007

PERFORMANCE GRAPHS (continued)

10 µF

TPS54610PWP

VIN

71.5 kΩ

VIN

FSEL

SS/ENA

VBIAS

PWRGD

COMP

0.047 µF

1 µF

10 kΩ

0.56 µH

470 pF

BOOT

PGND

470 pF

150 µF

C10

1 pF

VSENSE

0.047 µF

1.47 kΩ

2.4 Ω

PGND

39 Ω

AGND

C11

3300 pF

1.5 kΩ

POWERPAD

C12

0.012 µF

Figure 21. Small Size, High Frequency Design

10 µs/div

Figure 22. TRANSIENT RESPONSE, 1.5-A to 4.5-A STEP

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SGLS294A–FEBRUARY 2005–REVISED AUGUST 2007

DETAILED DESCRIPTION

UNDERVOLTAGE LOCK OUT (UVLO)

The TPS54610 incorporates an under voltage lockout circuit to keep the device disabled when the input voltage

(VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO

threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins. The device

operates until VIN falls below the nominal UVLO stop threshold of 2.8 V. Hysteresis in the UVLO comparator and

a 2.5 μs rising and falling edge deglitch circuit reduce the likelihood of shutting the device down due to noise on

VIN.

SLOW-START/ENABLE (SS/ENA)

The slow-start/enable pin provides two functions. First, the pin acts as an enable (shutdown) control by keeping

the device turned off until the voltage exceeds the start threshold voltage of approximately 1.2 V. When SS/ENA

exceeds the enable threshold, device start-up begins. The reference voltage fed to the error amplifier is linearly

ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the converter output voltage reaches regulation in

approximately 3.35 ms. Voltage hysteresis and a 2.5-μs falling edge deglitch circuit reduce the likelihood of

triggering the enable due to noise.

The second function of the SS/ENA pin provides an external means of extending the slow-start time with a

low-value capacitor connected between SS/ENA and AGND.

Adding a capacitor to the SS/ENA pin has two effects on start-up. First, a delay occurs between release of the

SS/ENA pin and start-up of the output. The delay is proportional to the slow-start capacitor value and lasts until

the SS/ENA pin reaches the enable threshold. The start-up delay is approximately:

1.2 V

t + C

(SS)

5 mA

(2)

Second, as the output becomes active, a brief ramp-up at the internal slow-start rate may be observed before the

externally set slow-start rate takes control and the output rises at a rate proportional to the slow-start capacitor.

The slow-start time set by the capacitor is approximately:

0.7 V

+ C

(SS)

5 mA

(3)

The actual slow-start time is likely to be less than the above approximation due to the brief ramp-up at the

internal rate.

VBIAS REGULATOR (VBIAS)

The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in

junction temperature and input voltage. A high-quality, low-ESR, ceramic bypass capacitor is required on the

VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over

temperature. The bypass capacitor must be placed close to the VBIAS pin and returned to AGND.

External loading on VBIAS is allowed, with the caution that internal circuits require a minimum VBIAS of 2.7 V,

and external loads on VBIAS with ac or digital switching noise may degrade performance. The VBIAS pin may be

useful as a reference voltage for external circuits.

VOLTAGE REFERENCE

The voltage reference system produces a precise V_refsignal by scaling the output of a temperature stable

bandgap circuit. During manufacture, the bandgap and scaling circuits are trimmed to produce 0.891 V at the

output of the error amplifier, with the amplifier connected as a voltage follower. The trim procedure adds to the

high precision regulation of the TPS54610, since it cancels offset errors in the scale and error amplifier circuits.

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SGLS294A–FEBRUARY 2005–REVISED AUGUST 2007

DETAILED DESCRIPTION (continued)

OSCILLATOR AND PWM RAMP

The oscillator frequency can be set to internally fixed values of 350 kHz or 550 kHz using the FSEL pin as a

static digital input. If a different frequency of operation is required for the application, the oscillator frequency can

be externally adjusted from 280 kHz to 700 kHz by connecting a resistor between the RT pin and AGND and

floating the FSEL pin. The switching frequency is approximated by the following equation, where R is the

resistance from RT to AGND:

100 kW

Switching Frequency +

500 [kHz]

(4)

External synchronization of the PWM ramp is possible over the frequency range of 330 kHz to 700 kHz by driving

a synchronization signal into FSEL and connecting a resistor from RT to AGND. Choose a resistor between the

RT and AGND that sets the free running frequency to 80% of the synchronization signal. The following table

summarizes the frequency selection configurations:

SWITCHING FREQUENCY

350 kHz, internally set

FSEL PIN

Float or AGND

RT PIN

Float

550 kHz, internally set

≥ 2.5 V

Float

Externally set 280 kHz to 700 kHz

Externally synchronized frequency⁽¹⁾

Float

R = 180 kΩ to 68 kΩ

Synchronization signal

R = RT value for 80% of external synchronization frequency

(1) To ensure proper operation when the RC filter is used between the external clock and the FSEL pin, the recommended values are

R ≤ 1 kΩ and C ≤ 120 pF.

ERROR AMPLIFIER

The high-performance, wide-bandwidth, voltage error amplifier sets the TPS54610 apart from most dc/dc

converters. The user is given the flexibility to use a wide range of output L and C filter components to suit the

particular application needs. Type 2 or type 3 compensation can be employed using external compensation

components.

PWM CONTROL

Signals from the error amplifier output, oscillator, and current limit circuit are processed by the PWM control logic.

As shown in the internal block diagram, the control logic includes the PWM comparator, OR gate, PWM latch,

and portions of the adaptive dead-time and control logic block. During steady-state operation below the current

limit threshold, the PWM comparator output and oscillator pulse train alternately reset and set the PWM latch.

Once the PWM latch is reset, the low-side FET remains on for a minimum duration set by the oscillator pulse

width. During this period, the PWM ramp discharges rapidly to its valley voltage. When the ramp begins to

charge back up, the low-side FET turns off and high-side FET turns on. As the PWM ramp voltage exceeds the

error amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and

turning on the low-side FET. The low-side FET remains on until the next oscillator pulse discharges the PWM

ramp.

During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the

PWM peak voltage. If the error amplifier is high, the PWM latch is never reset, and the high-side FET remains on

until the oscillator pulse signals the control logic to turn the high-side FET off and the low-side FET on. The

device operates at its maxi- mum duty cycle until the output voltage rises to the regulation set-point, setting

VSENSE to approximately the same voltage as VREF. If the error amplifier output is low, the PWM latch is

continually reset and the high-side FET does not turn on. The low-side FET remains on until the VSENSE

voltage decreases to a range that allows the PWM comparator to change states. The TPS54610 is capable of

sinking current continuously until the output reaches the regulation set-point.

If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds

the error amplifier output. The high-side FET turns off and low-side FET turns on to decrease the energy in the

output inductor and consequently the output current. This process is repeated each cycle in which the current

limit comparator is tripped.

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SGLS294A–FEBRUARY 2005–REVISED AUGUST 2007

DEAD-TIME CONTROL AND MOSFET DRIVERS

Adaptive dead-time control prevents shoot-through current from flowing in both N-channel power MOSFETs

during the switching transitions by actively controlling the turnon times of the MOSFET drivers. The high-side

driver does not turn on until the voltage at the gate of the low-side FET is below 2 V. While the low-side driver

does not turn on until the voltage at the gate of the high-side MOSFET is below 2 V.

The high-side and low-side drivers are designed with 300 mA source and sink capability to quickly drive the

power MOSFETs gates. The low-side driver is error plied from VIN, while the high-side drive is supplied from the

BOOT pin. A bootstrap circuit uses an external BOOT capacitor and an internal 2.5 Ω bootstrap switch

connected between the VIN and BOOT pins. The integrated bootstrap switch improves drive efficiency and

reduces external component count.

OVERCURRENT PROTECTION

The cycle-by-cycle current limiting is achieved by sensing the current flowing through the high-side MOSFET and

comparing this signal to a preset overcurrent threshold. The high-side MOSFET is turned off within 200 ns of

reaching the current limit threshold. A 100 ns leading edge blanking circuit prevents current limit false tripping.

Current limit detection occurs only when current flows from VIN to PH when sourcing current to the output filter.

Load protection during current sink operation is provided by thermal shutdown.

THERMAL SHUTDOWN

The device uses the thermal shutdown to turn off the power MOSFETs and disable the controller if the junction

temperature exceeds 150°C. The device is released from shutdown automatically when the junction temperature

decreases to 10°C below the thermal shutdown trip point and starts up under control of the slow-start circuit.

Thermal shutdown provides protection when an over-load condition is sustained for several milliseconds. With a

persistent fault condition, the device cycles continuously; starting up by control of the soft-start circuit, heating up

due to the fault condition, and then shutting down upon reaching the thermal shutdown trip point. This sequence

repeats until the fault condition is removed.

POWER-GOOD (PWRGD)

The power good circuit monitors for under voltage conditions on VSENSE. If the voltage on VSENSE is 10%

below the reference voltage, the open-drain PWRGD output is pulled low. PWRGD is also pulled low if VIN is

less than the UVLO threshold or SS/ENA is low, or a thermal shutdown occurs. When VIN ≥ UVLO threshold,

SS/ENA ≥ enable threshold, and VSENSE > 90% of V_ref, the open drain output of the PWRGD pin is high. A

hysteresis voltage equal to 3% of V_refand a 35-μs falling edge deglitch circuit prevent tripping of the power good

comparator due to high-frequency noise.

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PACKAGE OPTION ADDENDUM

www.ti.com

4-Dec-2010

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

TPS54610MPWPREP

TPS54610MPWPREPG4

V62/05622-01XE

ACTIVE

HTSSOP

PWP

2000

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

Contact TI Distributor

or Sales Office

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

Contact TI Distributor

or Sales Office

Green (RoHS

& no Sb/Br)

Contact TI Distributor

or Sales Office

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS54610-EP :

Catalog: TPS54610

•

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

4-Dec-2010

Automotive: TPS54610-Q1

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS54610MPWPREP HTSSOP PWP

2000

330.0

16.4

6.9

10.2

1.8

12.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

HTSSOP PWP 28

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 38.0

TPS54610MPWPREP

2000

Pack Materials-Page 2

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