V62/05621-01XE [TI]
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP; 单上升沿触发的D型触发器
| 型号： | V62/05621-01XE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP |
| 文件： | 总11页 (文件大小：373K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVC1G79-EP
www.ti.com....................................................................................................................................................... SCES646A–AUGUST 2005–REVISED APRIL 2009
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
1
FEATURES
•
•
•
•
•
•
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 5 ns at 3.3 V
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C)
Temperature Range(1)
Low Power Consumption, 10-µA Max ICC
±24-mA Output Drive at 3.3 V
Ioff Supports Partial-Power-Down Mode
Operation
•
•
•
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
•
•
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
DCK PACKAGE
(TOP VIEW)
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
D
CLK
GND
VCC
1
2
3
5
1000-V Charged-Device Model (C101)
4
Q
See mechanical drawings for dimensions.
(1) Additional temperature ranges are available - contact factory
DESCRIPTION/ORDERING INFORMATION
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the
positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the
rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting
the level at the output.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(2)
CR_
–55°C to 115°C SOT (SC-70) – DCK
Reel of 3000
SN74LVC1G79WDCKREP
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DCK: The actual top-side marking has one additional character that designates the assembly/test site.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVC1G79-EP
SCES646A–AUGUST 2005–REVISED APRIL 2009....................................................................................................................................................... www.ti.com
FUNCTION TABLE
INPUTS
CLK
OUTPUT
Q
D
H
L
↑
↑
L
H
L
X
Q0
LOGIC DIAGRAM (POSITIVE LOGIC)
2
C
CLK
C
C
4
TG
Q
C
C
C
C
1
D
TG
TG
TG
C
C
C
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2)(3)
6.5
6.5
6.5
V
V
VO
VO
IIK
V
–0.5 VCC + 0.5
V
Input clamp current
VI < 0
–50
–50
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
Package thermal impedance(4)
Storage temperature range
±50
±100
θJA
DCK package
252 °C/W
150 °C
Tstg
–65
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
2
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Copyright © 2005–2009, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC1G79-EP
SN74LVC1G79-EP
www.ti.com....................................................................................................................................................... SCES646A–AUGUST 2005–REVISED APRIL 2009
Recommended Operating Conditions(1)
MIN
1.65
MAX UNIT
Operating
VCC
Supply voltage
V
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
1.5
0.65 × VCC
1.7
VIH
High-level input voltage
V
2
0.7 × VCC
0.35 × VCC
0.7
VIL
Low-level input voltage
V
0.8
0.3 × VCC
5.5
VCC
–4
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
–8
IOH
High-level output current
Low-level output current
–16
–24
–32
4
mA
mA
VCC = 3 V
VCC = 4.5 V
VCC = 1.65 V
VCC = 2.3 V
8
IOL
16
VCC = 3 V
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
20
Δt/Δv
Input transition rise or fall rate
Operating free-air temperature
10
ns/V
°C
5
TA
–55
115
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Copyright © 2005–2009, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Link(s): SN74LVC1G79-EP
SN74LVC1G79-EP
SCES646A–AUGUST 2005–REVISED APRIL 2009....................................................................................................................................................... www.ti.com
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 5.5 V
1.65 V
MIN TYP(1)
VCC – 0.1
MAX UNIT
IOH = –100 µA
IOH = –4 mA
1.2
1.9
2.4
2.3
3.8
IOH = –8 mA
2.3 V
VOH
V
IOH = –16 mA
IOH = –24 mA
IOH = –32 mA
IOL = 100 µA
IOL = 4 mA
3 V
4.5 V
1.65 V to 5.5 V
1.65 V
0.1
0.45
IOL = 8 mA
2.3 V
0.3
V
VOL
IOL = 16 mA
0.4
3 V
IOL = 24 mA
0.55
0.55
IOL = 32 mA
4.5 V
0 to 5.5 V
0
II
CLK or D inputs
VI = 5.5 V or GND
VI or VO = 5.5 V
VI = 5.5 V or GND,
±10
±10
10
µA
µA
µA
µA
pF
Ioff
ICC
ΔICC
Ci
IO = 0
1.65 V to 5.5 V
3 V to 5.5 V
3.3 V
One input at VCC – 0.6 V, Other inputs at VCC or GND
VI = VCC or GND
500
4
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
160
MIN
MAX
160
MIN
MAX
160
MIN
MAX
fclock
tw
Clock frequency
160 MHz
ns
Pulse duration, CLK high or low
2.5
2.2
2.6
0.3
2.5
1.4
1.4
0.4
2.5
1.3
1.3
0.5
2.5
1.2
1.2
0.5
Data high
Data low
tsu
th
Setup time before CLK↑
ns
ns
Hold time, data after CLK↑
Switching Characteristics
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX
MIN MAX
MIN MAX
MIN MAX
fmax
tpd
160
160
160
160
MHz
ns
CLK
Q
3.9
10.1
2
7
1.7
5
1
4.5
Operating Characteristics
TA = 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
TYP
TYP
Cpd
Power dissipation capacitance
f = 10 MHz
26
26
27
30
pF
4
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Copyright © 2005–2009, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC1G79-EP
SN74LVC1G79-EP
www.ti.com....................................................................................................................................................... SCES646A–AUGUST 2005–REVISED APRIL 2009
PARAMETER MEASUREMENT INFORMATION
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
/t
S1
GND
t
t
Open
PLH PHL
C
L
t
/t
V
LOAD
GND
R
L
PLZ PZL
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
t /t
r f
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
V
V
3 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
/2
/2
2 × V
2 × V
6 V
2 × V
CC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
CC
CC
CC
V
CC
CC
CC
1.5 V
/2
V
CC
V
CC
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
V
V
OH
V
V
/2
LOAD
V
V
V
M
M
Output
V
V
M
S1 at V
LOAD
V
+ V
∆
OL
OL
(see Note B)
OL
t
PHL
PLH
t
t
PHZ
PZH
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
− V
∆
V
M
OH
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
Copyright © 2005–2009, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Link(s): SN74LVC1G79-EP
PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2009
PACKAGING INFORMATION
Orderable Device
SN74LVC1G79WDCKREP
V62/05621-01XE
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SC70
DCK
5
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SC70
DCK
5
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC1G79-EP :
Catalog: SN74LVC1G79
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Jul-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC1G79WDCKRE
P
SC70
DCK
5
3000
180.0
8.4
2.25
2.4
1.22
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Jul-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SC70 DCK
SPQ
Length (mm) Width (mm) Height (mm)
202.0 201.0 28.0
SN74LVC1G79WDCKREP
5
3000
Pack Materials-Page 2
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