V62/08621-01XE [TI]
DUAL, 250-mA OUTPUT, ULTRA-LOW NOISE, HIGH PSRR, LOW-DROPOUT LINEAR REGULATOR; 双通道， 250 mA输出，超低噪声，高PSRR ，低压差线性稳压器
| 型号： | V62/08621-01XE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL, 250-mA OUTPUT, ULTRA-LOW NOISE, HIGH PSRR, LOW-DROPOUT LINEAR REGULATOR |
| 文件： | 总19页 (文件大小：679K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS71202-EP
A ctu al S ize
(3 m m x 3 m m)
www.ti.com
SGLS395A –OCTOBER 2008–REVISED SEPTEMBER 2010
DUAL, 250-mA OUTPUT, ULTRA-LOW NOISE, HIGH PSRR, LOW-DROPOUT
LINEAR REGULATOR
Check for Samples: TPS71202-EP
1
FEATURES
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
•
•
•
Dual 250-mA High-Performance RF LDOs
Adjustable Output Voltage (1.2 V to 5.5 V)
High PSRR: 65 dB at 10 kHz
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C)
Temperature Range(1)
Ultra-Low Noise: 32 mVrms
Fast Start-Up Time: 60 ms
Stable with 2.2-mF Ceramic Capacitor
Excellent Load/Line Transient Response
Very Low Dropout Voltage: 125 mV at 250 mA
Independent Enable Pins
•
•
•
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
DESCRIPTION
Thermal Shutdown and Independent Current
Limit
The TPS71202 low-dropout (LDO) voltage regulator
is tailored to noise-sensitive and RF applications. It
features dual 250-mA LDOs with ultra-low noise, high
power-supply rejection ratio (PSRR), and fast
transient and start-up response. Each regulator
output is stable with low-cost 2.2-mF ceramic output
capacitors and features very low dropout voltages
(125 mV typical at 250 mA). The regulator achieves
fast start-up times (approximately 60 ms with a
0.001-mF bypass capacitor) while consuming very low
quiescent current (300 mA typical with both outputs
enabled). When the device is placed in standby
mode, the supply current is reduced to less than
0.3 mA typical. The regulator exhibits approximately
32 mVrms of output voltage noise with VOUT = 2.8 V
•
Available in Thermally-Enhanced SON
Package: 3 mm × 3 mm × 1 mm
APPLICATIONS
•
•
•
•
•
Cellular and Cordless Phones
Wireless PDA/Handheld Products
PCMCIA/Wireless LAN Applications
Digital Camera/Camcorder/Internet Audio
DSP/FPGA/ASIC/Controllers and Processors
and
a 0.01-mF noise reduction (NR) capacitor.
Applications with analog components that are
noise-sensitive, such as portable RF electronics,
benefit from high PSRR, low noise, and fast line and
load transient features. The TPS71202 is offered in a
thin 3-mm × 3-mm SON package and is fully
specified from –55°C to 125°C (TJ).
(1) Custom temperature ranges available
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2010, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are
tested unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
TPS71202-EP
SGLS395A –OCTOBER 2008–REVISED SEPTEMBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PSRR (RIPPLE REJECTION) vs FREQUENCY
80
70
IOUT = 250 mA
DRC PACKAGE
3-mm y 3-mm SON
60
(TOP VIEW)
50
40
30
20
10
0
IN
NC
1
2
3
4
5
10 EN1
IOUT = 1 mA
9
8
7
6
FB1
EN2
FB2
NR
OUT1
OUT2
GND
VOUT = 2.8 V
µ
COUT = 2.2
CNR = 0.01
F
F
µ
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
ORDERING INFORMATION(1)
TJ
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
–55°C to 125°C
SON-10 – DRC
Reel of 250
TPS71202MDRCTEP
CVQ
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range unless otherwise noted(1)
VIN
Input voltage range
IN
–0.3 V to 6 V
VEN1
VEN2
,
Input voltage range
EN1, EN2
OUT
–0.3 V to VIN + 0.3 V
VOUT
Output voltage range
–0.3 V to 6 V
Internally limited
Indefinite
Peak output current
Output short-circuit duration
Continuous total power dissipation
Junction temperature range
Storage temperature range
See Thermal Information table
–55°C to 150°C
–65°C to 150°C
2000 V
TJ
Human-Body Model (HBM)
ESD
Electrostatic discharge rating
Charged-Device Model (CDM)
500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
2
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SGLS395A –OCTOBER 2008–REVISED SEPTEMBER 2010
THERMAL INFORMATION
TPS71202-EP
UNITS
THERMAL METRIC(1)(2)
DRC (10 PINS)
qJA
Junction-to-ambient thermal resistance
49.6
70.0
qJCtop
qJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
17.8
°C/W
0.6
yJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
yJB
15.2
5.2
qJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
ELECTRICAL CHARACTERISTICS
over operating temperature range (TJ = –55°C to +125°C), VIN = highest (VOUT(nom) + 1 V) or 2.7 V (whichever is greater),
IOUT = 1 mA, VEN1, 2 = 1.2 V, COUT = 10 mF, CNR = 0.01 mF, and adjustable LDOs are tested at VOUT = 3.0 V (unless otherwise
noted). Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIN
Input voltage range(1)
2.7
5.5
V
V
VFB
Internal reference (adjustable LDOs)
1.200
1.225 1.250
5.5 – VDO
+1.5
Output voltage range
(adjustable LDOs)
VFB
V
Nominal
TJ = +25°C, IOUT = 0 mA
VOUT + 1.0 V ≤ VIN ≤ 5.5 V,
–1.5
VOUT
Over VIN
IOUT, and
temperatur 0 mA ≤ IOUT ≤ 250 mA
,
Accuracy(1)
%
–3
1
+3
e
ΔVOUT%/ΔVIN Line regulation(1)
VOUT + 1.0 V ≤ VIN ≤ 5.5 V
0 mA ≤ IOUT ≤ 250 mA
0.05
0.8
%/V
ΔVOUT%/ΔIOU
Load regulation
%/mA
T
Dropout voltage
VDO
IOUT1 = IOUT2 = 250 mA
VOUT = 0.9 × VOUT(nom)
125
600
190
315
800
250
mV
mA
(VIN = VOUT(nom) – 0.1V)
ICL
Output current limit
400
One LDO
IOUT = 1 mA (enabled channel)
enabled
IGND
Ground pin current
mA
Both LDOs
IOUT1 = IOUT2 = 1 mA to 250 mA
enabled
300
600
ISHDN
IFB
Shutdown current(2)
FB pin current
VEN ≤ 0.4 V, 0 V ≤ VIN ≤ 5.5 V
0.3
0.1
2.0
mA
mA
1.50
No CNR, IOUT = 250 mA
80.0 × VOUT
Output noise voltage,
BW = 10 Hz to 100 kHz
Vn
mVrms
CNR = 0.01 mF, IOUT = 250 mA
f = 100 Hz, IOUT = 250 mA
11.8 × VOUT
65
65
60
Power-supply rejection ratio
(ripple rejection)
PSRR
dB
f = 10 kHz, IOUT = 250 mA
tSTR
VIH
VIL
Startup time
VOUT = 2.85 V, RL = 30Ω, CNR = 0.001 mF
ms
V
Enable threshold high (EN1, EN2)
Enable threshold low (EN1, EN2)
Enable pin current (EN1, EN2)
1.2
VIN
0.4
1
0
V
IEN
VIN = VEN = 5.5 V
–1
mA
Shutdown
Reset
Temp increasing
Temp decreasing
+160
+140
TSD
Thermal shutdown temperature
°C
Undervoltage lockout threshold
Undervoltage lockout hysteresis
VIN rising
VIN falling
2.25
2.65
V
UVLO
100
mV
(1) Minimum VIN = (VOUT + VDO) or 2.7 V, whichever is greater.
(2) For the adjustable version, this applies only after VIN is applied; then VEN transitions from high to low.
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FUNCTIONAL BLOCK DIAGRAM —
FIXED VERSION
FUNCTIONAL BLOCK DIAGRAM —
ADJUSTABLE VERSION
IN
OUT1
IN
OUT1
Current
Limit
Current
Limit
µ
30
A
90 kΩ
FB1
EN1
EN1
Thermal
Shutdown
Thermal
Shutdown
OUT2
OUT2
µ
30
A
Current
Limit
Current
Limit
UVLO
UVLO
90 kΩ
FB2
NR
EN2
EN2
Ω
250 k
Ω
250 k
NR
VREF
VREF
5 pF
5 pF
TPS712xx
Fixed/Fixed
1.225 V
1.225 V
TPS712xx
Adj/Adj
Quickstart
Quickstart
Table 1. TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
DRC
IN
1
Unregulated input supply. A small 0.1-mF capacitor should be connected from IN to GND.
GND
5, Pad
Ground
Output of the regulator. A small 2.2-mF ceramic capacitor is required from this pin to ground to assure
stability.
OUT1
OUT2
EN1
3
4
Same as OUT1 but for LDO2.
Driving the enable pin (EN) high turns on LDO1. Driving this pin low puts LDO1 into shutdown mode,
reducing operating current. The enable pin should be connected to IN if not used.
10
EN2
FB1
FB2
NR
8
9
7
6
2
Same as EN1 but controls LDO2.
Feedback for channel 1
Feedback for channel 2
Noise reduction pin; connect an external bypass capacitor to reduce LDO output noise.
No connection.
NC
4
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SGLS395A –OCTOBER 2008–REVISED SEPTEMBER 2010
TYPICAL CHARACTERISTICS
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 1 mA,VEN = 1.2 V, COUT = 2.2 mF, and CNR = 0.01 mF
(unless otherwise noted)
OUTPUT VOLTAGE vs INPUT VOLTAGE
OUTPUT VOLTAGE vs OUTPUT CURRENT
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
_
_
+25
+25 C
C
−
_
40
C
−
−
−
−
−
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
0.2
0.4
0.6
0.8
1.0
_
+125
C
−
_
40
C
_
+125
C
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0
50
100
150
200
250
VIN (V)
IOUT (mA)
Figure 1.
Figure 2.
DROPOUT VOLTAGE vs INPUT VOLTAGE
(ADJUSTABLE VERSION)
OUTPUT VOLTAGE vs TEMPERATURE
200
180
160
140
120
100
80
1.0
0.5
0
_
TJ = +125
C
IOUT = 10 mA
_
TJ = +25 C
IOUT = 125 mA
−
−
−
0.5
1.0
1.5
60
IOUT = 250 mA
−
_
TJ
= 40 C
40
20
0
−
−
−
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9
VIN (V)
40 25 10
5
20 35 50 65 80 95 110 125
_
Junction Temperature ( C)
Figure 3.
Figure 4.
TPS71256
TPS71256
DROPOUT VOLTAGE vs OUTPUT CURRENT
DROPOUT VOLTAGE vs JUNCTION TEMPERATURE
200
150
100
50
250
_
TJ = +125
C
200
150
100
50
IOUT = 250 mA
−
_
TJ
= 40 C
_
TJ = +25 C
0
0
0
50
100
150
200
250
−
−
−
40 25 10
5
20 35 50 65 80 95 110 125
IOUT (mA)
Junction Temperature (°C)
Figure 5.
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 1 mA,VEN = 1.2 V, COUT = 2.2 mF, and CNR = 0.01 mF
(unless otherwise noted)
GROUND PIN CURRENT vs INPUT VOLTAGE
GROUND PIN CURRENT vs IOUT
400
375
350
325
300
275
250
225
200
400
375
350
325
300
275
250
225
200
_
+125
C
_
+125
C
_
+25
C
−
_
40
C
_
+25
C
−
_
40 C
2.7
3.2
3.7
4.2
4.7
5.2
5.7
0
50
100
150
200
250
VIN (V)
IOUT (mA)
Figure 7.
Figure 8.
GROUND PIN CURRENT vs JUNCTION TEMPERATURE
(DISABLED)
GROUND PIN CURRENT vs JUNCTION TEMPERATURE
500
400
VEN1 = VEN2 = 0.4V
VEN1 = VEN2 = 1.2V
450
375
VIN = 3.8 V
VIN = 3.8 V
400
350
300
250
200
150
100
50
350
325
300
275
250
225
200
0
−
−
−
40 25 10
5
20 35 50 65 80 95 110 125
−
−
−
40 25 10
5
20 35 50 65 80 95 110 125
_
Junction Temperature ( C)
_
Junction Temperature ( C)
Figure 9.
Figure 10.
TPS71256
CURRENT LIMIT vs JUNCTION TEMPERATURE
LINE TRANSIENT RESPONSE
800
µ
COUT1 = COUT2 = 10
F
VIN = 3.8 V
750
700
650
600
550
500
450
400
3.8 V
3.2 V
VIN
IOUT = 250 mA
IOUT = 1 mA
VOUT1
10 mV/div
10 mV/div
VOUT2
µ
100 s/div
−
−
−
40 25 10
5
20 35 50 65 80 95 110 125
_
Junction Temperature ( C)
Figure 11.
Figure 12.
6
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 1 mA,VEN = 1.2 V, COUT = 2.2 mF, and CNR = 0.01 mF
(unless otherwise noted)
TPS71256
LOAD TRANSIENT RESPONSE
AND VOUT2 CROSSTALK
TPS71256
CHANNEL-TO-CHANNEL ISOLATION vs FREQUENCY
60
50
40
30
20
µ
COUT2 = 10
F
2 mV/div
VOUT2
µ
COUT1 = 10
F
100 mV/div
VOUT1
250 mA
µ
COUT1 = COUT2 = 10
F
10 mA
200 mA/div
IOUT1
10
0
IOUT1 = 0 mA to 500 mA Sinusoidal Load
IOUT2 = 25 mA
µ
20 s/div
0.1
1
10
100
1k
Frequency (Hz)
Figure 13.
TPS71256
Figure 14.
TURN-ON/TURN-OFF RESPONSE
AND VOUT2 CROSSTALK
TPS71229
POWER-UP/POWER-DOWN
IOUT1 = IOUT2 = 250 mA
µ
CNR = 0.01
F
IOUT1 = IOUT2 = 250 mA
µ
COUT1 = COUT 2 = 10
F
20 mV/div
VOUT2
VIN
µ
CNR = 0.001
F
VOUT1
VOUT2
VOUT1
VEN1
1 V/div
µ
50 s/div
50 ms/div
Figure 15.
Figure 16.
NOISE SPECTRAL DENSITY
TOTAL NOISE vs CNR
COUT = 2.2 mF
250
200
150
100
50
350
300
250
200
150
100
50
µ
COUT = 2.2
F
µ
F
VOUT = 2.8 V
CNR = 0.1
IOUT = 250 mA
VOUT = 2.8 V
IOUT = 250 mA
µ
COUT = 2.2
F
IOUT = 0 mA
µ
COUT = 10
F
IOUT = 250 mA
IOUT = 1 mA
µ
COUT = 10
F
IOUT = 0 mA
0
0
1
10
100
1k
10k
100k
100
1k
10k
100k
CNR (pF)
Frequency (Hz)
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 1 mA,VEN = 1.2 V, COUT = 2.2 mF, and CNR = 0.01 mF
(unless otherwise noted)
NOISE SPECTRAL DENSITY
COUT = 10 mF
NOISE SPECTRAL DENSITY vs CNR
350
300
250
200
150
100
50
2.0
1.75
1.5
µ
CNR = 0.1
F
µ
COUT = 10
F
VOUT = 2.8 V
IOUT = 250 mA
VOUT = 2.8 V
1.25
1.0
µ
0.001
F
IOUT = 10 mA
µ
F
0.047
IOUT = 250 mA
µ
F
0.75
0.5
0.01
µ
0.1
F
0.25
0
100
0
1k
10k
100k
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 19.
Figure 20.
PSRR (RIPPLE REJECTION) vs FREQUENCY
PSRR (RIPPLE REJECTION) vs FREQUENCY
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
IOUT = 1 mA
IOUT = 250 mA
IOUT = 1 mA
IOUT = 250 mA
VOUT = 2.8 V
VOUT = 2.8 V
µ
COUT = 10 F
µ
COUT = 2.2
CNR = 0.01
F
F
µ
µ
F
CNR = 0.01
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 21.
Figure 22.
PSRR (RIPPLE REJECTION) vs VIN – VOUT
80
70
60
50
40
30
20
10
0
f = 1 kHz
f = 10 kHz
f = 100 kHz
VOUT = 2.8 V
IOUT = 250 mA
µ
µ
COUT = 10
CNR = 0.01
F
F
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
−
VIN VOUT (V)
Figure 23.
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APPLICATION INFORMATION
The TPS71202 dual low-dropout (LDO) regulator has
been optimized for use in noise-sensitive
battery-operated equipment. The device features
extremely low dropout, high PSRR, ultra-low output
noise, and low quiescent current (190 mA typical per
channel). When both outputs are disabled, the supply
currents are reduced to less than 2 mA.
OUTPUT NOISE
The internal voltage reference is a key source of
noise in an LDO regulator. The TPS71202 has an NR
pin that is connected to the voltage reference through
a 250-kΩ internal resistor. The 250-kΩ internal
resistor, in conjunction with an external ceramic
bypass capacitor connected to the NR pin, creates a
low-pass filter to reduce the voltage reference noise
and, therefore, the noise at the regulator output. To
achieve a fast startup, the 250-kΩ internal resistor is
shorted for 400 ms after the device is enabled.
INPUT AND OUTPUT CAPACITOR
REQUIREMENTS
A 0.1-mF or larger ceramic input bypass capacitor,
connected between IN and GND and located close to
the TPS71202, is required for stability. It improves
transient response, noise rejection, and ripple
rejection. A higher-value input capacitor may be
necessary if large, fast rise-time load transients are
anticipated and the device is located several inches
from the power source.
Because the primary noise source is the internal
voltage reference, the output noise is greater for
higher output voltage versions. For the case where
no noise reduction capacitor is used, the typical noise
(mVrms) over 10 Hz to 100 kHz is 80 times the output
voltage. If a 0.01-mF capacitor is used from the NR
pin to ground, the noise (mVrms) drops to 11.8 times
the output voltage.
The TPS71202 requires an output capacitor
connected between the outputs and GND to stabilize
the
internal
control
loops.
The
minimum
STARTUP CHARACTERISITCS
recommended output capacitor is 2.2 mF. If an output
voltage of 1.8 V or less is chosen, the minimum
recommended output capacitor is 4.7 mF. Any
ceramic capacitor that meets the minimum output
capacitor requirements is suitable. Capacitors with
higher ESR may be used, provided the ESR is less
than 1 Ω.
To minimize startup overshoot, the TPS71202 initially
targets an output voltage that is approximately 80%
of the final value. To avoid a delayed startup time,
noise reduction capacitors of 0.01 mF or less are
recommended. Larger noise reduction capacitors
cause the output to hold at 80% until the voltage on
the noise reduction capacitor exceeds 80% of the
bandgap voltage. The typical startup time with a
0.001-mF noise reduction capacitor is 60 ms. Once
one of the output voltages is present, the startup time
of the other output is not affected by the noise
reduction capacitor.
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PROGRAMMING THE TPS71202
ADJUSTABLE LDO REGULATOR
For voltages ≤ 1.8 V, the value of this capacitor
should be 100 pF. For voltages > 1.8 V, the
approximate value of this capacitor can be calculated
The output voltage of the TPS71202 dual adjustable
regulator is programmed using an external resistor
divider, as shown in Figure 24. The output voltage is
calculated using Equation 1:
as Equation 3:
5
(
)
(
)
3 10 R1 ) R2
(
)
pF
C1 +
(
)
R1 R2
(3)
R1
R2
blank
ǒ Ǔ
VOUT + VREF 1 )
(1)
The suggested value of this capacitor for several
resistor ratios is shown in Figure 24. If this capacitor
is not used (such as in a unity-gain configuration) or if
an output voltage ≤ 1.8 V is chosen, then the
minimum recommended output capacitor is 4.7 mF
instead of 2.2 mF.
where VREF
voltage).
=
1.225
V
(the internal reference
Resistors R2 and R4 should be chosen for
approximately a 40-mA divider current. Lower value
resistors can be used for improved noise
performance but consume more power. Higher values
should be avoided because leakage current at FB
increases the output voltage error. The recommended
design procedure is to choose R2 = 30.1 kΩ to set
the divider current at 40 mA, and then calculate R1
using Equation 2:
DROPOUT VOLTAGE
The TPS712xx uses a PMOS pass transistor to
achieve extremely low dropout. When (VIN - VOUT) is
less than the dropout voltage (VDO), the PMOS pass
device is in its linear region of operation and the
input-to-output resistance is the RDS, ON of the PMOS
pass element. Dropout voltages at lower currents can
be approximated by calculating the effective RDS, ON
of the pass element and multiplying that resistance by
the load current. RDS, ON of the pass element can be
obtained by dividing the dropout voltage by the rated
output current.
R1 + ǒVOUT Ǔ
* 1 R2
VREF
(2)
To improve the stability and noise performance of the
adjustable version, a small compensation capacitor
can be placed between OUT and FB.
TPS71202
VIN
VOUT1
IN
OUT1
Output Voltage Programming Guide
µ
µ
2.2
2.2
F
F
R1
R2
C1
C2
V
R1/R3
R2/R4
C1/C2
OUT
FB1
EN1
EN2
1.225 V
1.5 V
Short
Open
Open
100 pF
22 pF
15 pF
15 pF
15 pF
7.15 kΩ
31.6 kΩ
43.2 kΩ
49.9 kΩ
86.6 kΩ
30.1 kΩ
30.1 kΩ
30.1 kΩ
30.1 kΩ
30.1 kΩ
µ
0.1
F
VOUT2
2.5 V
OUT2
FB2
R3
R4
3.0 V
NR
GND
3.3 V
µ
0.01
F
4.75 V
Figure 24. Adjustable LDO Regulator Programming
10
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS71202-EP
TPS71202-EP
www.ti.com
SGLS395A –OCTOBER 2008–REVISED SEPTEMBER 2010
TRANSIENT RESPONSE
enabled. Depending on power dissipation, thermal
resistance, and ambient temperature, the thermal
protection circuit may cycle on and off. This limits the
dissipation of the regulator, protecting it from damage
due to overheating.
As with any regulator, increasing the size of the
output capacitor reduces overshoot/undershoot
magnitude but increase duration of the transient
response. In the adjustable version, the addition of a
capacitor, CFB, from the output to the feedback pin
also improves stability and transient response. The
transient response of the TPS71202 is enhanced with
an active pulldown that engages when the output is
overvoltaged. The active pulldown decreases the
output recovery time when the load is removed.
Figure 13 in the Typical Characteristics section shows
the output transient response.
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction
temperature should be limited to 125°C maximum. To
estimate the margin of safety in a complete design
(including
heatsink),
increase
the
ambient
temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
35°C above the maximum expected ambient
SHUTDOWN
condition of your application. This produces
worst-case junction temperature of 125°C at the
highest expected ambient temperature and
worst-case load.
a
Both enable pins are active high and are compatible
with standard TTL-CMOS levels. The device is only
completely disabled when both EN1 and EN2 are
logic low. In this state, the LDO is completely off and
the ground pin current drops to approximately 100
nA. With one output disabled, the ground pin current
is slightly greater than half the nominal value. When
shutdown capability is not required, the enable pins
should be connected to the input supply.
The internal protection circuitry of the TPS71202 is
designed to protect against overload conditions. It is
not intended to replace proper heatsinking.
Continuously running the TPS71202 into thermal
shutdown degrades device reliability.
POWER DISSIPATION
INTERNAL CURRENT LIMIT
The ability to remove heat from the die is different for
The TPS71202 internal current limit helps protect the
regulator during fault conditions. During current limit,
the output sources a fixed amount of current that is
largely independent of the output voltage.
each
package
type,
presenting
different
considerations in the PCB layout. The PCB area
around the device that is free of other components
moves the heat from the device to the ambient air.
Performance data for a JEDEC high-K board is
shown in the Dissipation Ratings table. Using heavier
copper increases the effectiveness in removing heat
from the device. The addition of plated through-holes
to heat-dissipating layers also improves the heat-sink
effectiveness.
The TPS71202 PMOS-pass transistors have a built-in
back diode that conducts reverse current when the
input voltage drops below the output voltage (that is,
during power-down). Current is conducted from the
output to the input and is not internally limited. If
extended reverse voltage operation is anticipated,
external limiting may be appropriate.
Power dissipation depends on input voltage and load
conditions. Power dissipation (PD) is equal to the
product of the output current times the voltage drop
across the output pass element (VIN to VOUT):
THERMAL PROTECTION
Thermal protection disables both outputs when the
junction temperature of either channel rises to
approximately 160°C, allowing the device to cool.
PD + (VIN * VOUT) IOUT
(4)
When
the
junction
temperature
cools
to
Power dissipation can be minimized by using the
lowest possible input voltage necessary to ensure the
required output voltage.
approximately 140°C, the output circuitry is again
Copyright © 2008–2010, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Link(s): TPS71202-EP
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jul-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS71202MDRCTEP
V62/08621-01XE
ACTIVE
ACTIVE
SON
SON
DRC
DRC
10
10
250
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Contact TI Distributor
or Sales Office
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Contact TI Distributor
or Sales Office
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS71202-EP :
Catalog: TPS71202
•
NOTE: Qualified Version Definitions:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jul-2010
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Dec-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS71202MDRCTEP
SON
DRC
10
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Dec-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SON DRC 10
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
TPS71202MDRCTEP
250
Pack Materials-Page 2
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