V62/09647-01XA [TI]
增强型产品低功耗 C5507 定点 DSP | PGE | 144 | -55 to 85;
| 型号： | V62/09647-01XA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 增强型产品低功耗 C5507 定点 DSP | PGE | 144 | -55 to 85 控制器 微控制器 微控制器和处理器 外围集成电路 数字信号处理器 装置 |
| 文件： | 总108页 (文件大小：1934K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SM320VC5507-EP
Fixed-Point Digital Signal Processor
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SPRS613
September 2009
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
Contents
1
2
Features ............................................................................................................................. 9
1.1
SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS ......................................... 9
Introduction ...................................................................................................................... 10
2.1
2.2
2.3
Description ................................................................................................................. 10
Pin Assignments ........................................................................................................... 11
Signal Descriptions ........................................................................................................ 13
3
Functional Overview .......................................................................................................... 23
3.1
Functional Block Diagram ................................................................................................ 23
Memory ..................................................................................................................... 24
3.2
3.2.1
On-Chip Dual-Access RAM (DARAM) ....................................................................... 24
On-Chip Single-Access RAM (SARAM) ..................................................................... 24
3.2.2
3.2.3
3.2.4
On-Chip Read-Only Memory (ROM) ......................................................................... 24
Memory Maps ................................................................................................... 25
3.2.4.1 PGE Package Memory Map ...................................................................... 25
Boot Configuration .............................................................................................. 26
3.2.5
3.3
3.4
Peripherals ................................................................................................................. 26
Direct Memory Access (DMA) Controller ............................................................................... 27
3.4.1
DMA Channel Control Register (DMA_CCR) ............................................................... 27
3.5
3.6
I2C Interface ................................................................................................................ 28
Configurable External Buses ............................................................................................. 28
3.6.1
3.6.2
3.6.3
External Bus Selection Register (EBSR) .................................................................... 29
Parallel Port ..................................................................................................... 30
Parallel Port Signal Routing ................................................................................... 31
3.7
General-Purpose Input/Output (GPIO) Ports .......................................................................... 33
3.7.1
3.7.2
3.7.3
Dedicated General-Purpose I/O .............................................................................. 33
Address Bus General-Purpose I/O ........................................................................... 34
EHPI General-Purpose I/O .................................................................................... 36
3.8
3.9
System Register ........................................................................................................... 37
USB Clock Generation .................................................................................................... 38
3.10 Memory-Mapped Registers .............................................................................................. 40
3.11 Peripheral Register Description .......................................................................................... 42
3.12 Interrupts .................................................................................................................... 52
3.12.1 IFR and IER Registers ......................................................................................... 53
3.12.2 Interrupt Timing ................................................................................................. 55
3.12.3 Waking Up From IDLE Condition ............................................................................. 55
3.12.3.1 Waking Up From IDLE With Oscillator Disabled ............................................... 55
3.12.4 Idling Clock Domain When External Parallel Bus Operating in EHPI Mode ............................ 55
4
Support ............................................................................................................................ 56
4.1
Notices Concerning JTAG (IEEE 1149.1) Boundary Scan Test Capability ........................................ 56
4.1.1
Initialization Requirements for Boundary Scan Test ....................................................... 56
Boundary Scan Description Language (BSDL) Model ..................................................... 56
4.1.2
4.2
4.3
Documentation Support ................................................................................................... 56
TMS320VC5507 Device Nomenclature ................................................................................ 57
5
Electrical Specifications ..................................................................................................... 58
5.1
ABSOLUTE MAXIMUM RATINGS ...................................................................................... 58
RECOMMENDED OPERATING CONDITIONS ....................................................................... 59
5.2
2
Contents
Copyright © 2009, Texas Instruments Incorporated
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
5.2.1
5.2.2
5.2.3
Recommended Operating Conditions for CVDD = 1.2 V (108 MHz) ..................................... 59
Recommended Operating Conditions for CVDD = 1.35 V (144 MHz) .................................... 60
Recommended Operating Conditions for CVDD = 1.6 V (200 MHz) ..................................... 61
5.3
ELECTRICAL CHARACTERISTICS .................................................................................... 62
5.3.1
5.3.2
5.3.3
Electrical Characteristics Over Recommended Operating Case Temperature Range for CVDD =
1.2 V (108 MHz) (Unless Otherwise Noted) ................................................................ 62
Electrical Characteristics Over Recommended Operating Case Temperature Range for CVDD
=
1.35 V (144 MHz) (Unless Otherwise Noted) ............................................................... 63
Electrical Characteristics Over Recommended Operating Case Temperature Range for CVDD
=
1.6 V (200 MHz) (Unless Otherwise Noted) ................................................................ 64
5.4
ESD Performance ......................................................................................................... 65
5.5
5.6
Timing Parameter Symbology ........................................................................................... 65
Clock Options .............................................................................................................. 66
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
Internal System Oscillator With External Crystal ........................................................... 66
Layout Considerations ......................................................................................... 66
Clock Generation in Bypass Mode (DPLL Disabled) ...................................................... 67
Clock Generation in Lock Mode (DPLL Synthesis Enabled) .............................................. 68
Real-Time Clock Oscillator With External Crystal .......................................................... 69
5.7
5.8
Memory Interface Timings ................................................................................................ 70
5.7.1
Asynchronous Memory Timings .............................................................................. 70
Synchronous DRAM (SDRAM) Timings ..................................................................... 72
5.7.2
Reset Timings .............................................................................................................. 79
5.8.1
5.8.2
5.8.3
Power-Up Reset (On-Chip Oscillator Active) ............................................................... 79
Power-Up Reset (On-Chip Oscillator Inactive) ............................................................. 80
Warm Reset ..................................................................................................... 80
5.9
External Interrupt Timings ................................................................................................ 81
5.10 Wake-Up From IDLE ...................................................................................................... 82
5.11 XF Timings ................................................................................................................. 82
5.12 General-Purpose Input/Output (GPIOx) Timings ...................................................................... 83
5.13 TIN/TOUT Timings (Timer0 Only) ....................................................................................... 84
5.14 Multichannel Buffered Serial Port (McBSP) Timings ................................................................. 85
5.14.1 McBSP0 Timings ............................................................................................... 85
5.14.2 McBSP1 and McBSP2 Timings ............................................................................... 86
5.14.3 McBSP as SPI Master or Slave Timings .................................................................... 89
5.14.4 McBSP General-Purpose I/O Timings ....................................................................... 94
5.15 Enhanced Host-Port Interface (EHPI) Timings ........................................................................ 95
5.16 I2C Timings ................................................................................................................ 101
5.17 Universal Serial Bus (USB) Timings ................................................................................... 103
5.18 ADC Timings .............................................................................................................. 104
Mechanical Data .............................................................................................................. 105
6
6.1
Package Thermal Resistance Characteristics ....................................................................... 105
Packaging Information ................................................................................................... 105
6.2
Copyright © 2009, Texas Instruments Incorporated
Contents
3
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
List of Figures
2-1
144-Pin PGE Low-Profile Quad Flatpack (Top View) ....................................................................... 11
Block Diagram of the SM320VC5507 ......................................................................................... 24
SM320VC5507 Memory Map................................................................................................... 25
DMA_CCR Bit Locations ........................................................................................................ 27
External Bus Selection Register................................................................................................ 29
Parallel Port Signal Routing..................................................................................................... 33
Parallel Port (EMIF) Signal Interface .......................................................................................... 33
I/O Direction Register (IODIR) Bit Layout..................................................................................... 34
I/O Data Register (IODATA) Bit Layout ....................................................................................... 34
Address/GPIO Enable Register (AGPIOEN) Bit Layout..................................................................... 35
Address/GPIO Direction Register (AGPIODIR) Bit Layout ................................................................. 35
Address/GPIO Data Register (AGPIODATA) Bit Layout.................................................................... 35
EHPI GPIO Enable Register (EHPIGPIOEN) Bit Layout.................................................................... 36
EHPI GPIO Direction Register (EHPIGPIODIR) Bit Layout ................................................................ 36
EHPI GPIO Data Register (EHPIGPIODATA) Bit Layout................................................................... 37
System Register Bit Locations.................................................................................................. 37
USB Clock Generation........................................................................................................... 38
USB PLL Selection and Status Register Bit Layout ......................................................................... 38
USB APLL Clock Mode Register Bit Layout .................................................................................. 39
IFR0 and IER0 Bit Locations.................................................................................................... 53
IFR1 and IER1 Bit Locations.................................................................................................... 54
Device Nomenclature for the TMS320VC5507............................................................................... 57
3.3-V Test Load Circuit .......................................................................................................... 65
Internal System Oscillator With External Crystal............................................................................. 66
Bypass Mode Clock Timings.................................................................................................... 68
External Multiply-by-N Clock Timings.......................................................................................... 69
Real-Time Clock Oscillator With External Crystal............................................................................ 70
Asynchronous Memory Read Timings......................................................................................... 72
Asynchronous Memory Write Timings......................................................................................... 72
Three SDRAM Read Commands .............................................................................................. 74
Three SDRAM WRT Commands............................................................................................... 75
SDRAM ACTV Command....................................................................................................... 76
SDRAM DCAB Command ...................................................................................................... 77
SDRAM REFR Command....................................................................................................... 78
SDRAM MRS Command ........................................................................................................ 79
SDRAM Self-Refresh Command ............................................................................................... 79
Power-Up Reset (On-Chip Oscillator Active) Timings....................................................................... 80
Power-Up Reset (On-Chip Oscillator Inactive) Timings..................................................................... 80
Reset Timings .................................................................................................................... 81
External Interrupt Timings....................................................................................................... 82
Wake-Up From IDLE Timings .................................................................................................. 82
XF Timings ........................................................................................................................ 82
General-Purpose Input/Output (IOx) Signal Timings ........................................................................ 83
TIN/TOUT Timings When Configured as Inputs ............................................................................. 84
TIN/TOUT Timings When Configured as Outputs ........................................................................... 84
McBSP Receive Timings ........................................................................................................ 89
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
4-1
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
5-23
5-24
4
List of Figures
Copyright © 2009, Texas Instruments Incorporated
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
5-25
5-26
5-27
5-28
5-29
5-30
5-31
5-32
5-33
5-34
5-35
5-36
5-37
5-38
5-39
5-40
McBSP Transmit Timings ....................................................................................................... 89
McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 ................................................... 90
McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 ................................................... 92
McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 ................................................... 93
McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 ................................................... 94
McBSP General-Purpose I/O Timings......................................................................................... 94
HINT Timings ..................................................................................................................... 96
EHPI Nonmultiplexed Read/Write Timings.................................................................................... 97
EHPI Multiplexed Memory (HPID) Read/Write Timings Without Autoincrement......................................... 98
EHPI Multiplexed Memory (HPID) Read Timings With Autoincrement.................................................... 99
EHPI Multiplexed Memory (HPID) Write Timings With Autoincrement .................................................. 100
EHPI Multiplexed Register Read/Write Timings ............................................................................ 100
I2C Receive Timings............................................................................................................ 102
I2C Transmit Timings ........................................................................................................... 103
USB Timings .................................................................................................................... 104
Full-Speed Loads ............................................................................................................... 104
Copyright © 2009, Texas Instruments Incorporated
List of Figures
5
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
List of Tables
2-1
Pin Assignments for the PGE Package ....................................................................................... 12
Signal Descriptions............................................................................................................... 13
DARAM Blocks ................................................................................................................... 24
SARAM Blocks ................................................................................................................... 24
Boot Configuration Summary ................................................................................................... 26
Synchronization Control Function .............................................................................................. 28
External Bus Selection Register Bit Field Description....................................................................... 29
SM320VC5507 Parallel Port Signal Routing.................................................................................. 31
I/O Direction Register (IODIR) Bit Functions ................................................................................. 34
I/O Data Register (IODATA) Bit Functions.................................................................................... 34
Address/GPIO Enable Register (AGPIOEN) Bit Functions ................................................................. 35
Address/GPIO Direction Register (AGPIODIR) Bit Functions.............................................................. 35
Address/GPIO Data Register (AGPIODATA) Bit Functions ................................................................ 35
EHPI GPIO Enable Register (EHPIGPIOEN) Bit Functions ................................................................ 36
EHPI GPIO Direction Register (EHPIGPIODIR) Bit Functions............................................................. 36
EHPI GPIO Data Register (EHPIGPIODATA) Bit Functions ............................................................... 37
System Register Bit Fields ...................................................................................................... 37
USB PLL Selection and Status Register Bit Functions...................................................................... 38
USB APLL Clock Mode Register Bit Functions .............................................................................. 39
M and D Values Based on MODE, DIV, and K............................................................................... 39
CPU Memory-Mapped Registers............................................................................................... 40
Idle Control, Status, and System Registers................................................................................... 42
External Memory Interface Registers.......................................................................................... 42
DMA Configuration Registers................................................................................................... 43
Real-Time Clock Registers...................................................................................................... 45
Clock Generator .................................................................................................................. 46
Timers.............................................................................................................................. 46
Multichannel Serial Port #0 ..................................................................................................... 46
Multichannel Serial Port #1 ..................................................................................................... 47
Multichannel Serial Port #2 ..................................................................................................... 48
GPIO ............................................................................................................................... 49
Device Revision ID............................................................................................................... 49
I2C Module Registers ........................................................................................................... 49
Watchdog Timer Registers...................................................................................................... 50
USB Module Registers .......................................................................................................... 50
Analog-to-Digital Controller (ADC) Registers................................................................................. 52
External Bus Selection Register................................................................................................ 52
Interrupt Table .................................................................................................................... 52
IFR0 and IER0 Register Bit Fields ............................................................................................. 53
IFR1 and IER1 Register Bit Fields ............................................................................................. 54
Recommended Crystal Parameters............................................................................................ 66
CLKIN Timing Requirements ................................................................................................... 67
CLKOUT Switching Characteristics............................................................................................ 67
CLKIN Timing Requirements ................................................................................................... 68
Multiply-By-N Clock Option Switching Characteristics ...................................................................... 69
Recommended RTC Crystal Parameters ..................................................................................... 70
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27
3-28
3-29
3-30
3-31
3-32
3-33
3-34
3-35
3-36
3-37
3-38
5-1
5-2
5-3
5-4
5-5
5-6
6
List of Tables
Copyright © 2009, Texas Instruments Incorporated
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
5-7
Asynchronous Memory Cycle Timing Requirements ........................................................................ 70
Asynchronous Memory Cycle Switching Characteristics.................................................................... 70
Synchronous DRAM Cycle Timing Requirements ........................................................................... 72
Synchronous DRAM Cycle Switching Characteristics....................................................................... 72
Power-Up Reset (On-Chip Oscillator Active) Timing Requirements....................................................... 79
Power-Up Reset (On-Chip Oscillator Inactive) Timing Requirements..................................................... 80
Power-Up Reset (On-Chip Oscillator Inactive) Switching Characteristics ................................................ 80
Reset Timing Requirements .................................................................................................... 80
Reset Switching Characteristics ............................................................................................... 81
External Interrupt Timing Requirements ...................................................................................... 81
Wake-Up From IDLE Switching Characteristics ............................................................................. 82
XF Switching Characteristics ................................................................................................... 82
GPIO Pins Configured as Inputs Timing Requirements..................................................................... 83
GPIO Pins Configured as Outputs Switching Characteristics .............................................................. 83
TIN/TOUT Pins Configured as Inputs Timing Requirements .............................................................. 84
TIN/TOUT Pins Configured as Outputs Switching Characteristics ........................................................ 84
McBSP0 Timing Requirements ................................................................................................ 85
McBSP0 Switching Characteristics ........................................................................................... 85
McBSP1 and McBSP2 Timing Requirements ............................................................................... 86
McBSP0 Switching Characteristics ........................................................................................... 87
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) ................................. 89
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) ............................ 90
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) ................................. 91
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) ............................ 91
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) ................................. 92
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) ............................ 92
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) ................................. 93
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) ............................ 93
McBSP General-Purpose I/O Timing Requirements......................................................................... 94
McBSP General-Purpose I/O Switching Characteristics .................................................................... 94
EHPI Timing Requirements ..................................................................................................... 95
EHPI Switching Characteristics ................................................................................................ 95
I2C Signals (SDA and SCL) Timing Requirements......................................................................... 101
I2C Signals (SDA and SCL) Timing Requirements......................................................................... 102
Universal Serial Bus (USB) Characteristics ................................................................................. 103
ADC Characteristics ............................................................................................................ 104
Thermal Resistance Characteristics (Ambient) ............................................................................. 105
Thermal Resistance Characteristics (Case)................................................................................. 105
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
5-23
5-24
5-25
5-26
5-27
5-28
5-29
5-30
5-31
5-32
5-33
5-34
5-35
5-36
5-37
5-38
5-39
5-40
5-41
5-42
6-1
6-2
Copyright © 2009, Texas Instruments Incorporated
List of Tables
7
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
8
List of Tables
Copyright © 2009, Texas Instruments Incorporated
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
Fixed-Point Digital Signal Processor
Check for Samples: SM320VC5507-EP
1
Features
1
• High-Performance, Low-Power, Fixed-Point
SMS320C5507 Digital Signal Processor
• On-Chip Peripherals
– Two 20-Bit Timers
– Watchdog Timer
– 9.26-, 6.95-, 5-ns Instruction Cycle Time
– 108-, 144-, 200-MHz Clock Rate
– One/Two Instruction(s) Executed per Cycle
– Six-Channel Direct Memory Access (DMA)
Controller
– Dual Multipliers (Up to 400 Million
– Three Multichannel Buffered Serial Ports
(McBSPs)
Multiply-Accumulates per Second (MMACS))
– Two Arithmetic/Logic Units (ALUs)
– Three Internal Data/Operand Read Buses
and Two Internal Data/Operand Write Buses
– Programmable Phase-Locked Loop Clock
Generator
– Seven (LQFP) or Eight (BGA) General-
Purpose I/O (GPIO) Pins and a General-
Purpose Output Pin (XF)
– USB Full-Speed (12 Mbps) Slave Port
Supporting Bulk, Interrupt and Isochronous
Transfers
– Inter-Integrated Circuit (I2C) Multi-Master and
Slave Interface
• 64K x 16-Bit On-Chip RAM, Composed of:
– 64K Bytes of Dual-Access RAM (DARAM) 8
Blocks of 4K x 16-Bit
– 64K Bytes of Single-Access RAM (SARAM) 8
Blocks of 4K x 16-Bit
• 64K Bytes of One-Wait-State On-Chip ROM
(32K x 16-Bit)
• 8M x 16-Bit Maximum Addressable External
Memory Space (Synchronous DRAM)
• 16-Bit External Parallel Bus Memory
Supporting Either:
– Real-Time Clock (RTC) With Crystal Input,
Separate Clock Domain, Separate Power
Supply
– 4-Channel (BGA) or 2-Channel (LQFP) 10-Bit
Successive Approximation A/D
– External Memory Interface (EMIF) With GPIO
Capabilities and Glueless Interface to:
• IEEE Std 1149.1(1) (JTAG) Boundary Scan Logic
• Packages:
•
•
•
Asynchronous Static RAM (SRAM)
Asynchronous EPROM
Synchronous DRAM (SDRAM)
– 144-Terminal Low-Profile Quad Flatpack
(LQFP) (PGE Suffix)
• 1.2-V Core (108 MHz), 2.7-V – 3.6-V I/Os
• 1.35-V Core (144 MHz), 2.7-V – 3.6-V I/Os
• 1.6-V Core (200 MHz), 2.7-V – 3.6-V I/Os
– 16-Bit Parallel Enhanced Host-Port Interface
(EHPI) With GPIO Capabilities
• Programmable Low-Power Control of Six
Device Functional Domains
(1) IEEE Standard 1149.1-1990 Standard-Test-Access Port and
Boundary Scan Architecture.
• On-Chip Scan-Based Emulation Logic
1.1 SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C) Temperature Range(2)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
(2) Additional temperature ranges are available - contact factory
1
C55x, eXpressDSP, Code Composer Studio, DSP/BIOS, RTDX, XDS510, TMS320, TMS320C5000, TMS320C55x, TMS320C55x are
trademarks of Texas Instruments.
Copyright © 2009, Texas Instruments Incorporated
Features
9
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
2
Introduction
This section describes the main features of the SM320VC5507, lists the pin assignments, and describes
the function of each pin. This data manual also provides a detailed description section, electrical
specifications, parameter measurement information, and mechanical data about the available packaging.
NOTE
This data manual is designed to be used in conjunction with theTMS320C55x DSP
Functional Overview (literature number SPRU312), the TMS320C55x DSP CPU
Reference Guide (literature number SPRU371), and the TMS320C55x DSP Peripherals
Overview Reference Guide (literature number SPRU317).
2
2.1 Description
The SM320VC5507 fixed-point digital signal processor (DSP) is based on the SMS320C55x DSP
generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power
through increased parallelism and total focus on reduction in power dissipation. The CPU supports an
internal bus structure that is composed of one program bus, three data read buses, two data write buses,
and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform
up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up
to two data transfers per cycle independent of the CPU activity.
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit
multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional
16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel
activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit
(DU) of the C55x CPU.
The C55x DSP generation supports a variable byte width instruction set for improved code density. The
Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues
instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and
DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline
flushes on execution of conditional instructions.
The 128K bytes of on-chip memory on 5507 is sufficient for many hand-held appliances, portable GPS
systems, wireless speaker phones, portable PDAs, and gaming devices. Many of these appliances
typically require 64K bytes or more on-chip memory but less than 128K bytes of memory, and need to
operate in standby mode for more than 60% to 70% of time. For the applications which require more than
128K bytes of on-chip memory but less than 256K bytes of on-chip memory, Texas Instruments (TI) offers
the TMS320VC5509A device, which is based on the TMS320C55x DSP core.
The general-purpose input and output functions and the10-bit A/D provide sufficient pins for status,
interrupts, and bit I/O for LCDs, keyboards, and media interfaces. The parallel interface operates in two
modes, either as a slave to a microcontroller using the HPI port or as a parallel media interface using the
asynchronous EMIF. Serial media is supported through three McBSPs.
The 5507 peripheral set includes an external memory interface (EMIF) that provides glueless access to
asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such
as synchronous DRAM. Additional peripherals include Universal Serial Bus (USB), real-time clock,
watchdog timer, and I2C multi-master and slave interface. Three full-duplex multichannel buffered serial
ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and
multichannel communication with up to 128 separately enabled channels. The enhanced host-port
interface (HPI) is a 16-bit parallel interface used to provide host processor access to 32K bytes of internal
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
memory on the 5507. The HPI can be configured in either multiplexed or non-multiplexed mode to provide
glueless interface to a wide variety of host processors. The DMA controller provides data movement for
six independent channel contexts without CPU intervention, providing DMA throughput of up to two 16-bit
words per cycle. Two general-purpose timers, up to eight dedicated general-purpose I/O (GPIO) pins, and
digital phase-locked loop (DPLL) clock generation are also included.
The 5507 is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™
Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the
industry’s largest third-party network. The Code Composer Studio IDE features code generation tools
including a C Compiler and Visual Linker, simulator, RTDX™, XDS510™ emulation device drivers, and
evaluation modules. The 5507 is also supported by the C55x DSP Library which features more than 50
foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and
board support libraries.
2.2 Pin Assignments
The SM320VC5507PGE 144-pin low-profile quad flatpack (LQFP) pin assignments are shown in
Figure 2-1 and is used in conjunction with Table 2-1 to locate signal names and pin numbers.
DVDD is the power supply for the I/O pins while CVDD is the power supply for the core. VSS is the ground
for both the I/O pins and the core. RCVDD and RDVDD are RTC module core and I/O supply, respectively.
USBVDD is the USB module I/O (DP, DN, and PU) supply. ADVDD is the power supply for the digital
portion of the ADC. AVDD is the power supply for the analog part of the ADC. ADVSS is the ground pin for
the digital portion of the ADC. AVSS is the ground pin for the analog part of the ADC. USBPLLVDD and
USBPLLVSS are the dedicated supply and ground pins for the USB PLL, respectively.
108
73
109
72
144
37
1
36
Figure 2-1. 144-Pin PGE Low-Profile Quad Flatpack (Top View)
Copyright © 2009, Texas Instruments Incorporated
Introduction
11
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
Table 2-1. Pin Assignments for the PGE Package
PIN NO.
1
SIGNAL NAME
VSS
PIN NO.
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
SIGNAL NAME
VSS
A13
A12
A11
CVDD
A10
A9
PIN NO.
73
SIGNAL NAME
VSS
PIN NO.
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
SIGNAL NAME
RDVDD
RCVDD
RTCINX2
RTCINX1
VSS
2
PU
74
D12
3
DP
75
D13
4
DN
76
D14
5
USBVDD
GPIO7
VSS
77
D15
6
78
CVDD
EMU0
EMU1/OFF
TDO
VSS
7
79
VSS
8
DVDD
GPIO2
GPIO1
VSS
A8
80
DX2
9
VSS
A7
81
FSX2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
82
TDI
CVDD
A6
83
CVDD
TRST
TCK
CLKX2
DR2
GPIO0
X2/CLKIN
X1
A5
84
DVDD
A4
85
FSR2
VSS
86
TMS
CLKOUT
C0
A3
87
CVDD
DVDD
SDA
CLKR2
DX1
A2
88
C1
CVDD
A1
89
FSX1
CVDD
C2
90
SCL
DVDD
A0
91
RESET
USBPLLVSS
INT0
CLKX1
DR1
C3
DVDD
D0
92
C4
93
FSR1
CLKR1
DX0
C5
D1
94
INT1
C6
D2
95
USBPLLVDD
INT2
DVDD
C7
VSS
D3
96
CVDD
97
INT3
FSX0
C8
D4
98
DVDD
INT4
CLKX0
DR0
C9
D5
99
C11
VSS
D6
100
101
102
103
104
105
106
107
108
VSS
FSR0
CLKR0
VSS
CVDD
CVDD
C14
XF
D7
VSS
D8
ADVSS
ADVDD
AIN0
DVDD
C12
CVDD
D9
TIN/TOUT0
GPIO6
GPIO4
GPIO3
VSS
VSS
C10
D10
D11
DVDD
AIN1
C13
AVDD
AVSS
VSS
12
Introduction
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
2.3 Signal Descriptions
Table 2-2 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2 for pin
locations.
Table 2-2. Signal Descriptions
TERMINAL
NAME
MULTIPLEXED
SIGNAL NAME
RESET
CONDITION
(1)
(2)
I/O/Z
FUNCTION
BK
PARALLEL BUS
A subset of the parallel address bus A13−A0 of
the C55x DSP core bonded to external pins.
These pins serve in one of three functions: HPI
address bus (HPI.HA[13:0]), EMIF address bus
(EMIF.A[13:0]), or general-purpose I/O
(GPIO.A[13:0]). The initial state of these pins
depends on the GPIO0 pin. See Section 3.6.1 for
more information.
A[13:0]
I/O/Z
The address bus has a bus holder feature that
eliminates passive component requirement and
the power dissipation associated with them. The
bus holders keep the address bus at the previous
logic level when the bus goes into a
high-impedance state.
GPIO0 = 1:
HPI address bus. HPI.HA[13:0] is selected when
the Parallel Port Mode bit field of the External Bus
Selection Register is 10. This setting enables the
HPI in non-multiplexed mode.
HPI.HA[13:0] provides DSP internal memory
access to host. In non-multiplexed mode, these
signals are driven by an external host as address
lines.
x
Output,
EMIF.A[13:0]
HPI.HA[13:0]
EMIF.A[13:0]
GPIO.A[13:0]
I
x
BK
x
GPIO0 = 0:
x
Input,
EMIF address bus. EMIF.A[13:0] is selected when
the Parallel Port Mode bit field of the External Bus
Selection Register is 01. This setting enables the
full EMIF mode and the EMIF drives the parallel
port address bus. The internal A[14] address is
exclusive-ORed with internal A[0] address and the
result is routed to the A[0] pin.
HPI.HA[13:0]
O/Z
General-purpose I/O address bus. GPIO.A[13:0] is
selected when the Parallel Port Mode bit field of
the External Bus Selection Register is 11. This
setting enables the HPI in multiplexed mode with
the Parallel Port GPIO register controlling the
parallel port address bus. GPIO is also selected
when the Parallel Port Mode bit field is 00,
enabling the Data EMIF mode.
I/O/Z
(1) I = Input, O = Output, S = Supply, Hi-Z = High-impedance
(2) BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,
PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer
Copyright © 2009, Texas Instruments Incorporated
Introduction
13
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
Table 2-2. Signal Descriptions (continued)
TERMINAL
NAME
MULTIPLEXED
SIGNAL NAME
RESET
CONDITION
(1)
(2)
I/O/Z
FUNCTION
BK
A subset of the parallel bidirectional data bus
D31−D0 of the C55x DSP core. These pins serve
in one of two functions: EMIF data bus
(EMIF.D[15:0]) or HPI data bus (HPI.HD[15:0]).
The initial state of these pins depends on the
GPIO0 pin. See Section 3.6.1 for more
information.
The data bus includes bus keepers to reduce the
static power dissipation caused by floating,
unused pins. This eliminates the need for external
bias resistors on unused pins. When the data bus
is not being driven by the CPU, the bus keepers
keep the pins at the logic level that was most
recently driven. (The data bus keepers are
enabled at reset, and can be enabled/disabled
under software control.)
GPIO0 = 1:
x
D[15:0]
I/O/Z
Input,
EMIF.D[15:0]
x
BK
x
GPIO0 = 0:
x
Input,
HPI.HD[15:0]
EMIF data bus. EMIF.D[15:0] is selected when the
Parallel Port Mode bit field of the External Bus
Selection Register is 00 or 01.
EMIF.D[15:0]
HPI.HD[15:0]
I/O/Z
I/O/Z
HPI data bus. HPI.HD[15:0] is selected when the
Parallel Port Mode bit field of the External Bus
Selection Register is 10 or 11.
EMIF asynchronous memory read enable or
general-purpose IO8. This pin serves in one of
two functions: EMIF asynchronous memory read
enable (EMIF.ARE) or general-purpose IO8
(GPIO8). The initial state of this pin depends on
the GPIO0 pin. See Section 3.6.1 for more
information.
GPIO0 = 1:
C0
I/O/Z
x
Output,
EMIF.ARE
x
BK
Active-low EMIF asynchronous memory read
enable. EMIF.ARE is selected when the Parallel
Port Mode bit field of the External Bus Selection
Register is 00 or 01.
x
GPIO0 = 0:
x
Input,
GPIO8
EMIF.ARE
GPIO8
O/Z
General-purpose IO8. GPIO8 is selected when the
Parallel Port Mode bit field of the External Bus
Selection Register is set to 10 or 11.
I/O/Z
EMIF asynchronous memory output enable or HPI
interrupt output. This pin serves in one of two
functions: EMIF asynchronous memory output
enable (EMIF.AOE) or HPI interrupt output
(HPI.HINT). The initial state of this pin depends on
the GPIO0 pin. See Section 3.6.1 for more
information.
GPIO0 = 1:
C1
O/Z
x
Output,
EMIF.AOE
x
BK
Active-low asynchronous memory output enable.
EMIF.AOE is selected when the Parallel Port
Mode bit field of the External Bus Selection
Register is 00 or 01.
x
GPIO0 = 0:
x
Input,
HPI.HINT
EMIF.AOE
HPI.HINT
O/Z
O/Z
Active-low HPI interrupt output. HPI.HINT is
selected when the Parallel Port Mode bit field of
the External Bus Selection Register is 10 or 11.
14
Introduction
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
Table 2-2. Signal Descriptions (continued)
TERMINAL
NAME
MULTIPLEXED
SIGNAL NAME
RESET
CONDITION
(1)
(2)
I/O/Z
FUNCTION
BK
EMIF asynchronous memory write enable or HPI
read/write. This pin serves in one of two functions:
EMIF asynchronous memory write enable
(EMIF.AWE) or HPI read/write (HPI.HR/W). The
initial state of this pin depends on the GPIO0 pin.
See Section 3.6.1 for more information.
GPIO0 = 1:
C2
I/O/Z
x
Output,
EMIF.AWE
x
Active-low EMIF asynchronous memory write
enable. EMIF.AWE is selected when the Parallel
Port Mode bit field of the External Bus Selection
Register is 00 or 01.
BK
x
EMIF.AWE
HPI.HR/W
O/Z
I
GPIO0 = 0:
x
Input,
HPI.HR/W
HPI read/write. HPI.HR/W is selected when the
Parallel Port Mode bit field of the External Bus
Selection Register is 10 or 11. HPI.HR/W controls
the direction of the HPI transfer.
EMIF data ready input or HPI ready output. This
pin serves in one of two functions: EMIF data
ready input (EMIF.ARDY) or HPI ready output
(HPI.HRDY). The initial state of this pin depends
on the GPIO0 pin. See Section 3.6.1 for more
information.
GPIO0 = 1:
C3
I/O/Z
x
Input,
EMIF.ARDY
EMIF data ready input. Used to insert wait states
for slow memories. EMIF.ARDY is selected when
the Parallel Port Mode bit field of the External Bus
Selection Register is 00 or 01. When this pin is
used as ARDY, an external 2.2 kΩ
x
x
H
EMIF.ARDY
HPI.HRDY
I
GPIO0 = 0:
x
Output,
HPI.HRDY
HPI ready output. HPI.HRDY is selected when the
Parallel Port Mode bit field of the External Bus
Selection Register is 10 or 11.
O
EMIF chip select for memory space CE0 or
general-purpose IO9. This pin serves in one of
two functions: EMIF chip select for memory space
CE0 (EMIF.CE0) or general-purpose IO9 (GPIO9).
The initial state of this pin depends on the GPIO0
pin. See Section 3.6.1 for more information.
GPIO0 = 1:
C4
I/O/Z
x
Output,
EMIF.CE0
x
Active-low EMIF chip select for memory space
CE0. EMIF.CE0 is selected when the Parallel Port
Mode bit field of the External Bus Selection
Register is set to 00 or 01.
BK
x
EMIF.CE0
GPIO9
O/Z
GPIO0 = 0:
x
Input,
GPIO9
General-purpose IO9. GPIO9 is selected when the
Parallel Port Mode bit field of the External Bus
Selection Register is set to 10 or 11.
I/O/Z
EMIF chip select for memory space CE1 or
general-purpose IO10. This pin serves in one of
two functions: EMIF chip-select for memory space
CE1 (EMIF.CE1) or general-purpose IO10
(GPIO10). The initial state of this pin depends on
the GPIO0 pin. See Section 3.6.1 for more
information.
GPIO0 = 1:
C5
I/O/Z
x
Output,
EMIF.CE1
x
BK
Active-low EMIF chip select for memory space
CE1. EMIF.CE1 is selected when the Parallel Port
Mode bit field of the External Bus Selection
Register is set to 00 or 01.
x
GPIO0 = 0:
x
Input,
GPIO10
EMIF.CE1
GPIO10
O/Z
General-purpose IO10. GPIO10 is selected when
the Parallel Port Mode bit field of the External Bus
Selection Register is set to 10 or 11.
I/O/Z
Copyright © 2009, Texas Instruments Incorporated
Introduction
15
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
Table 2-2. Signal Descriptions (continued)
TERMINAL
NAME
MULTIPLEXED
SIGNAL NAME
RESET
CONDITION
(1)
(2)
I/O/Z
FUNCTION
BK
EMIF chip select for memory space CE2 or HPI
control input 0. This pin serves in one of two
functions: EMIF chip-select for memory space
CE2 (EMIF.CE2) or HPI control input 0
(HPI.HCNTL0). The initial state of this pin
depends on the GPIO0 pin. See Section 3.6.1 for
more information.
C6
I/O/Z
GPIO0 = 1:
x
Output,
EMIF.CE2
Active-low EMIF chip select for memory space
CE2. EMIF.CE2 is selected when the Parallel Port
Mode bit field of the External Bus Selection
Register is set to 00 or 01.
x
BK
x
GPIO0 = 0:
x
EMIF.CE2
O/Z
Input,
HPI.HCNTL0
HPI control input 0. This pin, in conjunction with
HPI.HCNTL1, selects a host access to one of the
three HPI registers. HPI.HCNTL0 is selected when
the Parallel Port Mode bit field of the External Bus
Selection Register is set to 10 or 11.
HPI.HCNTL0
I
EMIF chip select for memory space CE3,
general-purpose IO11, or HPI control input 1. This
pin serves in one of three functions: EMIF
chip-select for memory space CE3 (EMIF.CE3),
general-purpose IO11 (GPIO11), or HPI control
input 1 (HPI.HCNTL1). The initial state of this pin
depends on the GPIO0 pin. See Section 3.6.1 for
more information.
C7
I/O/Z
GPIO0 = 1:
x
Output,
EMIF.CE3
Active-low EMIF chip select for memory space
CE3. EMIF.CE3 is selected when the Parallel Port
Mode bit field is of the External Bus Selection
Register set to 00 or 01.
x
BK
EMIF.CE3
GPIO11
O/Z
x
GPIO0 = 0:
x
Input,
HPI.HCNTL1
General-purpose IO11. GPIO11 is selected when
the Parallel Port Mode bit field is set to 10.
I/O/Z
HPI control input 1. This pin, in conjunction with
HPI.HCNTL0, selects a host access to one of the
three HPI registers. The HPI.HCNTL1 mode is
selected when the Parallel Port Mode bit field is
set to 11.
HPI.HCNTL1
I
EMIF byte enable 0 control or HPI byte
identification. This pin serves in one of two
functions: EMIF byte enable 0 control (EMIF.BE0)
or HPI byte identification (HPI.HBE0). The initial
state of this pin depends on the GPIO0 pin. See
Section 3.6.1 for more information.
GPIO0 = 1:
C8
I/O/Z
x
Output,
EMIF.BE0
x
Active-low EMIF byte enable 0 control. EMIF.BE0
is selected when the Parallel Port Mode bit field of
the External Bus Selection Register is set to 00 or
01.
BK
x
EMIF.BE0
HPI.HBE0
O/Z
I
GPIO0 = 0:
x
Input,
HPI.HBE0
HPI byte identification. This pin, in conjunction
with HPI.HBE1, identifies the first or second byte
of the transfer. HPI.HBE0 is selected when the
Parallel Port Mode bit field is set to 10 or 11.
16
Introduction
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
Table 2-2. Signal Descriptions (continued)
TERMINAL
NAME
MULTIPLEXED
SIGNAL NAME
RESET
CONDITION
(1)
(2)
I/O/Z
FUNCTION
BK
EMIF byte enable 1 control or HPI byte
identification. This pin serves in one of two
functions: EMIF byte enable 1 control (EMIF.BE1)
or HPI byte identification (HPI.HBE1). The initial
state of this pin depends on the GPIO0 pin. See
Section 3.6.1 for more information.
GPIO0 = 1:
C9
I/O/Z
x
Output,
EMIF.BE1
x
Active-low EMIF byte enable 1 control. EMIF.BE1
is selected when the Parallel Port Mode bit field of
the External Bus Selection Register is set to 00 or
01.
BK
x
EMIF.BE1
HPI.HBE1
O/Z
I
GPIO0 = 0:
x
Input,
HPI.HBE1
HPI byte identification. This pin, in conjunction
with HPI.HBE0, identifies the first or second byte
of the transfer. HPI.HBE1 is selected when the
Parallel Port Mode bit field is set to 10 or 11.
EMIF SDRAM row strobe, HPI address strobe, or
general-purpose IO12. This pin serves in one of
three functions: EMIF SDRAM row strobe
(EMIF.SDRAS), HPI address strobe (HPI.HAS), or
general-purpose IO12 (GPIO12). The initial state
of this pin depends on the GPIO0 pin. See
Section 3.6.1 for more information.
C10
I/O/Z
O/Z
GPIO0 = 1:
x
Output,
EMIF.SDRAS
Active-low EMIF SDRAM row strobe.
EMIF.SDRAS is selected when the Parallel Port
Mode bit field of the External Bus Selection
Register is set to 00 or 01.
x
BK
EMIF.SDRAS
x
GPIO0 = 0:
x
Input,
HPI.HAS
Active-low HPI address strobe. This signal latches
the address in the HPIA register in the HPI
Multiplexed mode. HPI.HAS is selected when the
Parallel Port Mode bit field is set to 11.
HPI.HAS
GPIO12
I
General-purpose IO12. GPIO12 is selected when
the Parallel Port Mode bit field is set to 10.
I/O/Z
EMIF SDRAM column strobe or HPI chip select
input. This pin serves in one of two functions:
EMIF SDRAM column strobe (EMIF.SDCAS) or
HPI chip select input (HPI.HCS). The initial state
of this pin depends on the GPIO0 pin. See
Section 3.6.1 for more information.
GPIO0 = 1:
C11
I/O/Z
x
Output,
EMIF.SDCAS
Active-low EMIF SDRAM column strobe.
EMIF.SDCAS is selected when the Parallel Port
Mode bit field of the External Bus Selection
Register is set to 00 or 01.
x
BK
x
GPIO0 = 0:
x
Input,
HPI.HCS
EMIF.SDCAS
HPI.HCS
O/Z
I
HPI Chip Select Input. HPI.HCS is the select input
for the HPI and must be driven low during
accesses. HPI.HCS is selected when the Parallel
Port Mode bit field is set to 10 or 11.
EMIF SDRAM write enable or HPI Data Strobe 1
input. This pin serves in one of two functions:
EMIF SDRAM write enable (EMIF.SDWE) or HPI
data strobe 1 (HPI.HDS1). The initial state of this
pin depends on the GPIO0 pin. See Section 3.6.1
for more information.
GPIO0 = 1:
C12
I/O/Z
x
Output,
EMIF.SDWE
EMIF SDRAM write enable. EMIF. SDWE is
selected when the Parallel Port Mode bit field of
the External Bus Selection Register is set to 00 or
01.
x
x
BK
EMIF.SDWE
HPI.HDS1
O/Z
I
GPIO0 = 0:
x
Input,
HPI.HDS1
HPI Data Strobe 1 Input. HPI.HDS1 is driven by
the host read or write strobes to control the
transfer. HPI.HDS1 is selected when the Parallel
Port Mode bit field is set to 10 or 11.
Copyright © 2009, Texas Instruments Incorporated
Introduction
17
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
Table 2-2. Signal Descriptions (continued)
TERMINAL
NAME
MULTIPLEXED
SIGNAL NAME
RESET
CONDITION
(1)
(2)
I/O/Z
FUNCTION
BK
SDRAM A10 address line or general-purpose
IO13. This pin serves in one of two functions:
SDRAM A10 address line (EMIF.SDA10) or
general-purpose IO13 (GPIO13). The initial state
of this pin depends on the GPIO0 pin. See
Section 3.6.1 for more information.
C13
I/O/Z
GPIO0 = 1:
x
Output,
SDRAM A10 address line. Address
EMIF.SDA10
line/autoprecharge disable for SDRAM memory.
Serves as a row address bit (logically equivalent
to A12) during ACTV commands and also disables
the autoprecharging function of SDRAM during
read or write operations. EMIF.SDA10 is selected
when the Parallel Port Mode bit field of the
External Bus Selection Register is set to 00 or 01.
x
BK
x
GPIO0 = 0:
x
Input,
GPIO13
EMIF.SDA10
GPIO13
O/Z
General-purpose IO13. GPIO13 is selected when
the Parallel Port Mode bit field is set to 10 or 11.
I/O/Z
I/O/Z
Memory interface clock for SDRAM, HPI Data
Strobe 2 input, or general-purpose IO14. This pin
serves in one of two functions: memory interface
clock for SDRAM (EMIF.CLKMEM) or HPI data
strobe 2 (HPI.HDS2). The initial state of this pin
depends on the GPIO0 pin. See Section 3.6.1 for
more information.
GPIO0 = 1:
C14
x
Output,
EMIF.CLKMEM
x
x
Memory interface clock for SDRAM.
EMIF.CLKMEM is selected when the Parallel Port
Mode bit field of the External Bus Selection
Register is set to 00 or 01.
BK
EMIF.CLKMEM
HPI.HDS2
O/Z
I
GPIO0 = 0:
x
Input,
HPI Data Strobe 2 Input. HPI.HDS2 is driven by
the host read or write strobes to control the
transfer. HPI.HDS2 is selected when the Parallel
Port Mode bit field is set to 10 or 11.
HPI.HDS2
INTERRUPT AND RESET PINS
Active-low external user interrupt inputs. INT[4:0]
are maskable and are prioritized by the interrupt
enable register (IER) and the interrupt mode bit.
INT[4:0]
I
I
H, FS
H, FS
Input
Input
Active-low reset. RESET causes the digital signal
processor (DSP) to terminate execution and
forces the program counter to FF8000h. When
RESET is brought to a high level, execution
begins at location FF8000h of program memory.
RESET affects various registers and status bits.
Use an external pullup resistor on this pin.
RESET
BIT I/O SIGNALS
7-bit Input/Output lines that can be individually
configured as inputs or outputs, and also
individually set or reset when configured as
outputs. At reset, these pins are configured as
inputs. After reset, the on-chip bootloader samples
GPIO[3:0] to determine the boot mode selected.
GPIO[7:6, 4:0]
I/O/Z
O/Z
Input
BK
(GPIO5
only)
H
SDRAM CKE signal. The GPIO4 pin can be
configured to serve as SDRAM CKE pin by setting
the following bits in the External Bus Selection
Register: CKE SEL = 1 and CKE EN = 1. In
default mode, this pin serves as GPIO4.
(except
GPIO5)
EMIF.CKE
(GPIO4)
Input
(GPIO4)
18
Introduction
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
Table 2-2. Signal Descriptions (continued)
TERMINAL
NAME
MULTIPLEXED
SIGNAL NAME
RESET
CONDITION
(1)
(2)
I/O/Z
FUNCTION
BK
External flag. XF is set high by the BSET XF
instruction, set low by BCLR XF instruction or by
loading ST1. XF is used for signaling other
processors in multiprocessor configurations or
used as a general-purpose output pin. XF goes
into the high-impedance state when OFF is low,
and is set high following reset.
XF
O/Z
Output
SDRAM CKE signal. The XF pin can be
configured to serve as SDRAM CKE pin by setting
the following bits in the External Bus Selection
Register: CKE SEL = 0 and CKE EN = 1. In
default mode, this pin serves as XF.
Output
(XF)
EMIF.CKE
O/Z
O/Z
OSCILLATOR/CLOCK SIGNALS
DSP clock output signal. CLKOUT cycles at the
machine-cycle rate of the CPU. CLKOUT goes
into high-impedance state when OFF is low.
CLKOUT
Output
System clock/oscillator input. If the internal
oscillator is not being used, X2/CLKIN functions as
the clock input.
NOTE:
The USB module requires a 48-MHz clock.
Since this input clock is used by both the CPU
PLL and the USB module PLL, it must be a
factor of 48 MHz in order for the
programmable PLL to produce the required
Oscillator
Input
X2/CLKIN
I/O
48-MHz
USB
module
clock.
In CLKGEN domain idle (OSC IDLE) mode,
this pin becomes output and is driven low to
stop external crystals (if used) from oscillating
or an external clock source from driving the
DSP’s internal logic.
Output pin from the internal system oscillator for
the crystal. If the internal oscillator is not used, X1
should be left unconnected. X1 does not go into
the high-impedance state when OFF is low.
Oscillator
Output
X1
O
TIMER SIGNALS
Timer0 Input/Output. When output, TIN/TOUT0
signals a pulse or a change of state when the
on-chip timer counts down past zero. When input,
TIN/TOUT0 provides the clock source for the
internal timer module. At reset, this pin is
configured as an input.
TIN/TOUT0
I/O/Z
H
Input
NOTE:
Only the Timer0 signal is brought out. The
Timer1 signal is terminated internally and is
not available for external use.
REAL-TIME CLOCK
RTCINX1
RCINX2
I
Real-Time Clock Oscillator input
Real-Time Clock Oscillator output
Input
O
Output
I2C
I2C (bidirectional) data. At reset, this pin is in
high-impedance mode.
I2C (bidirectional) clock. At reset, this pin is in
high-impedance mode.
SDA
SCL
I/O/Z
I/O/Z
H
H
Hi-Z
Hi-Z
MULTICHANNEL BUFFERED SERIAL PORTS SIGNALS
McBSP0 receive clock. CLKR0 serves as the
CLKR0
I/O/Z
serial shift clock for the serial port receiver. At
reset, this pin is in high-impedance mode.
H
Hi-Z
Copyright © 2009, Texas Instruments Incorporated
Introduction
19
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
Table 2-2. Signal Descriptions (continued)
TERMINAL
NAME
MULTIPLEXED
SIGNAL NAME
RESET
CONDITION
(1)
(2)
I/O/Z
FUNCTION
BK
DR0
I
McBSP0 receive data
FS
Input
McBSP0 receive frame synchronization. The
FSR0 pulse initiates the data receive process over
DR0. At reset, this pin is in high-impedance mode.
FSR0
CLKX0
DX0
I/O/Z
Hi-Z
Input
Hi-Z
McBSP0 transmit clock. CLKX0 serves as the
serial shift clock for the serial port transmitter. The
CLKX0 pin is configured as input after reset.
I/O/Z
O/Z
H
McBSP0 transmit data. DX0 is placed in the
high-impedance state when not transmitting, when
RESET is asserted, or when OFF is low.
McBSP0 transmit frame synchronization. The
FSX0 pulse initiates the data transmit process
over DX0. Configured as an input following reset.
FSX0
I/O/Z
Input
McBSP1 receive clock. CLKR1 serves as the
serial shift clock for the serial port receiver.
CLKR1
DR1
I/O/Z
I/Z
H
Input
Input
McBSP1 serial data receive
McBSP1 receive frame synchronization. The
FSR1 pulse initiates the data receive process over
DR1.
FSR1
DX1
I/Z
O/Z
Input
Hi-Z
McBSP1 serial data transmit. DX1 is placed in the
high-impedance state when not transmitting, when
RESET is asserted, or when OFF is low.
BK
McBSP1 transmit clock. CLKX1 serves as the
serial shift clock for the serial port transmitter. The
CLKX1 pin is configured as input after reset.
CLKX1
I/O/Z
H
H
Input
McBSP2 receive clock. CLKR2 serves as the
serial shift clock for the serial port receiver.
CLKR2
DR2
I/O/Z
I
Input
Input
McBSP2 serial data receive
McBSP2 receive frame synchronization. The
FSR2 pulse initiates the data receive process over
DR2.
FSR2
DX2
I
Input
Hi-Z
McBSP2 serial data transmit. DX2 is placed in the
high-impedance state when not transmitting, when
RESET is asserted, or when OFF is low.
O/Z
BK
H
McBSP2 transmit clock. CLKX2 serves as the
serial shift clock for the serial port transmitter. The
CLKX2 pin is configured as input after reset.
CLKX2
FSX2
I/O/Z
I/O/Z
Input
Input
McBSP2 frame synchronization. The FSX2 pulse
initiates the data transmit process over DX2. FSX2
is configured as an input following reset.
USB
Differential (positive) receive/transmit. At reset,
this pin is configured as input.
DP
I/O/Z
I/O/Z
Input
Input
Differential (negative) receive/transmit. At reset,
this pin is configured as input.
DN
Pullup output. This pin is used to pull up the
detection resistor required by the USB
specification. The pin is internally connected to
USBVDD via a software controllable switch
(CONN bit of the USBCTL register).
PU
O/Z
Hi-Z
A/D
AIN0
AIN1
I
I
Analog Input Channel 0
Analog Input Channel 1
Input
Input
20
Introduction
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
Table 2-2. Signal Descriptions (continued)
TERMINAL
NAME
MULTIPLEXED
SIGNAL NAME
RESET
CONDITION
(1)
(2)
I/O/Z
FUNCTION
BK
TEST/EMULATION PINS
IEEE standard 1149.1 test clock. TCK is normally
a free-running clock signal with a 50% duty cycle.
The changes on test access port (TAP) of input
signals TMS and TDI are clocked into the TAP
controller, instruction register, or selected test data
register on the rising edge of TCK. Changes at the
TAP output signal (TDO) occur on the falling edge
of TCK.
PU
H
TCK
I
Input
IEEE standard 1149.1 test data input. Pin with
internal pullup device. TDI is clocked into the
selected register (instruction or data) on a rising
edge of TCK.
TDI
I
O/Z
I
PU
Input
Hi-Z
IEEE standard 1149.1 test data output. The
contents of the selected register (instruction or
data) are shifted out of TDO on the falling edge of
TCK. TDO is in the high-impedance state except
when the scanning of data is in progress.
TDO
TMS
IEEE standard 1149.1 test mode select. Pin with
internal pullup device. This serial control input is
clocked into the TAP controller on the rising edge
of TCK.
PU
Input
IEEE standard 1149.1 test reset. TRST, when
high, gives the IEEE standard 1149.1 scan system
control of the operations of the device. If TRST is
not connected or driven low, the device operates
in its functional mode, and the IEEE standard
1149.1 signals are ignored. This pin has an
internal pulldown.
PD
FS
TRST
EMU0
I
Input
Input
Emulator 0 pin. When TRST is driven low, EMU0
must be high for activation of the OFF condition.
When TRST is driven high, EMU0 is used as an
interrupt to or from the emulator system and is
defined as I/O by way of the IEEE standard
1149.1 scan system.
I/O/Z
PU
Emulator 1 pin/disable all outputs. When TRST is
driven high, EMU1/OFF is used as an interrupt to
or from the emulator system and is defined as I/O
by way of IEEE standard 1149.1 scan system.
When TRST is driven low, EMU1/OFF is
configured as OFF. The EMU1/OFF signal, when
active-low, puts all output drivers into the
EMU1/OFF
I/O/Z
PU
Input
high-impedance state. Note that OFF is used
exclusively for testing and emulation purposes
(not for multiprocessing applications). Therefore,
for the OFF condition, the following apply: TRST =
low, EMU0 = high, EMU1/OFF = low.
SUPPLY PINS
Digital Power, + VDD. Dedicated power supply for
the core CPU.
CVDD
S
S
S
S
S
S
Digital Power, + VDD. Dedicated power supply for
the I/O pins.
DVDD
Digital Power, + VDD. Dedicated power supply for
the I/O of the USB module (DP, DN , and PU).
USBVDD
RDVDD
RCVDD
AVDD
Digital Power, + VDD. Dedicated power supply for
the I/O pins of the RTC module.
Digital Power, + VDD. Dedicated power supply for
the RTC module.
Analog Power, + VDD. Dedicated power supply
for the 10-bit A/D.
Copyright © 2009, Texas Instruments Incorporated
Introduction
21
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
Table 2-2. Signal Descriptions (continued)
TERMINAL
NAME
MULTIPLEXED
SIGNAL NAME
RESET
CONDITION
(1)
(2)
I/O/Z
S
FUNCTION
BK
Analog Digital Power, + VDD. Dedicated power
supply for the digital portion of the 10-bit A/D.
ADVDD
Digital Power, + VDD. Dedicated power supply pin
for the USB PLL.
USBPLLVDD
VSS
S
Digital Ground. Dedicated ground for the I/O and
core pins.
S
Analog Ground. Dedicated ground for the 10-bit
A/D.
AVSS
S
Analog Digital Ground. Dedicated ground for the
digital portion of the10-bit A/D.
ADVSS
S
Digital Ground. Dedicated ground for the USB
PLL.
USBPLLVSS
S
MISCELLANEOUS
NC
No connection
22
Introduction
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
3
Functional Overview
3.1 Functional Block Diagram
The following functional overview is based on the block diagram in Figure 3-1.
*
*
*
*
Figure 3-1. Block Diagram of the SM320VC5507
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Functional Overview
23
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
3.2 Memory
The 5507 supports a unified memory map (program and data accesses are made to the same physical
space). The total on-chip memory is 192K bytes (64K 16-bit words of RAM and 32K 16-bit words of ROM).
3.2.1 On-Chip Dual-Access RAM (DARAM)
The DARAM is located in the byte address range 000000h−00FFFFh and is composed of eight blocks of
8K bytes each (see Table 3-1). Each DARAM block can perform two accesses per cycle (two reads, two
writes, or a read and a write). DARAM can be accessed by the internal program, data, or DMA buses. The
HPI can only access the first four (32K bytes) DARAM blocks.
Table 3-1. DARAM Blocks
BYTE ADDRESS RANGE
000000h − 001FFFh
002000h − 003FFFh
004000h − 005FFFh
006000h − 007FFFh
008000h − 009FFFh
00A000h − 00BFFFh
00C000h − 00DFFFh
00E000h − 00FFFFh
MEMORY BLOCK
DARAM 0 (HPI accessible)(1)
DARAM 1 (HPI accessible)
DARAM 2 (HPI accessible)
DARAM 3 (HPI accessible)
DARAM 4
DARAM 5
DARAM 6
DARAM 7
(1) First 192 bytes are reserved for Memory-Mapped Registers (MMRs).
3.2.2 On-Chip Single-Access RAM (SARAM)
The SARAM is located at the byte address range 010000h−01FFFFh and is composed of 8 blocks of 8K
bytes each (see Table 3-2). Each SARAM block can perform one access per cycle (one read or one
write). SARAM can be accessed by the internal program, data, or DMA buses.
Table 3-2. SARAM Blocks
BYTE ADDRESS RANGE
010000h − 011FFFh
012000h − 013FFFh
014000h − 015FFFh
016000h − 017FFFh
018000h − 019FFFh
01A000h − 01BFFFh
01C000h − 01DFFFh
01E000h − 01FFFFh
MEMORY BLOCK
SARAM 0
SARAM 1
SARAM 2
SARAM 3
SARAM 4
SARAM 5
SARAM 6
SARAM 7
3.2.3 On-Chip Read-Only Memory (ROM)
The one-wait-state ROM is located at the byte address range FF0000h−FFFFFFh, for a total of 64K bytes
of ROM. The ROM address space can be mapped by software to the external memory or to the internal
ROM.
The standard 5507 device includes a bootloader program resident in the ROM. When the MPNMC bit field
of the ST3 status register is set through software, the on-chip ROM is disabled and not present in the
memory map, and byte address range FF0000h−FFFFFFh is directed to external memory space. A
hardware reset always clears the MPNMC bit, so it is not possible to disable the ROM at reset. However,
the software reset instruction does not affect the MPNMC bit. The on-chip ROM can be accessed by the
program, data, or DMA buses. The first 16-bit word access to ROM requires three cycles. Subsequent
accesses require two cycles per 16-bit word.
24
Functional Overview
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
3.2.4 Memory Maps
3.2.4.1 PGE Package Memory Map
The PGE package features 14 address bits representing 32K-/16K-byte linear address for asynchronous
memories per CE space. Due to address row/column multiplexing, address reach for SDRAM devices is
4M bytes for each CE space. The largest SDRAM device that can be used with the 5507 in a PGE
package is 128M-bit SDRAM.
-
∗
-
--
#
-
∗
-
-
-
∗
∗
-
-
-
-
-
-
-
-
∗
Figure 3-2. SM320VC5507 Memory Map
Copyright © 2009, Texas Instruments Incorporated
Functional Overview
25
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
3.2.5 Boot Configuration
The on-chip bootloader provides a method to transfer application code and tables from an external source
to the on-chip RAM memory at power up. These options include:
•
•
•
•
•
•
•
Enhanced host-port interface (HPI) in multiplexed or nonmultiplexed mode
External asynchronous memory boot (via the EMIF) from 8-bit-wide or 16-bit-wide memory
Serial port boot (from McBSP0) with 8-bit or 16-bit data length
Serial EPROM boot (from McBSP0) supporting EPROMs with 16-bit or 24-bit address
USB boot
I2C EEPROM
Direct execution from external 16-bit-wide asynchronous memory
External pins select the boot configuration. The values of GPIO[3:0] are sampled, following reset, upon
execution of the on-chip bootloader code. It is not possible to disable the bootloader at reset because the
5507 always starts execution from the on-chip ROM following a hardware reset. A summary of boot
configurations is shown in Table 3-3. For more information on using the bootloader, see the Using the
TMS320VC5503/VC5507/VC5509/VC5509A Bootloader application report (literature number SPRA375).
Table 3-3. Boot Configuration Summary
GPIO0
GPIO3
GPIO2
GPIO1
BOOT MODE PROCESS
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Reserved
Serial (SPI) EPROM Boot (24-bit address) via McBSP0
USB
I2C EEPROM (7-bit address)
Reserved
HPI – multiplexed mode
HPI – nonmultiplexed mode
Reserved
Execute from 16-bit-wide asynchronous memory (on CE1 space)
Serial (SPI) EPROM Boot (16-bit address) via McBSP0
8-bit asynchronous memory (on CE1 space)
16-bit asynchronous memory (on CE1 space)
Reserved
Reserved
Standard serial boot via McBSP0 (16-bit data)
Standard serial boot via McBSP0 (8-bit data)
3.3 Peripherals
The 5507 supports the following peripherals:
•
A configurable parallel external interface supporting either:
–
–
16-bit external memory interface (EMIF) for asynchronous memory and/or SDRAM
16-bit enhanced host-port interface (HPI)
•
•
•
•
•
•
A six-channel direct memory access (DMA) controller
A programmable phase-locked loop clock generator
Two 20-bit timers
Watchdog timer
Three multichannel buffered serial ports (McBSPs)
Eight configurable general-purpose I/O pins
x
26
Functional Overview
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
•
USB full-speed slave interface supporting:
–
–
–
Bulk
Interrupt
Isochronous
•
•
•
I2C multi-master and slave interface (I2C compatible except, no fail-safe I/O buffers)
Real-time clock with crystal input, separate clock domain and supply pins
4-channel 10-bit Successive Approximation A/D
For detailed information on the C55x DSP peripherals, see the following documents:
•
•
TMS320C55x DSP Functional Overview (literature number SPRU312)
TMS320C55x DSP Peripherals Overview Reference Guide (literature number SPRU317)
3.4 Direct Memory Access (DMA) Controller
The 5507 DMA provides the following features:
•
Four standard ports, one for each of the following data resources: DARAM, SARAM, peripherals and
external memory
•
•
•
•
Six channels, which allow the DMA controller to track the context of six independent DMA channels
Programmable low/high priority for each DMA channel
One interrupt for each DMA channel
Event synchronization. DMA transfers in each channel can be dependent on the occurrence of
selected events.
•
•
Programmable address modification for source and destination addresses
Dedicated idle domain allows the DMA controller to be placed in a low-power (idle) state under
software control.
•
Dedicated DMA channel used by the HPI to access internal memory (DARAM)
The 5507 DMA controller allows transfers to be synchronized to selected events. The 5507 supports 15
separate sync events and each channel can be tied to separate sync events independent of the other
channels. Sync events are selected by programming the SYNC field in the channel-specific DMA channel
control register (DMA_CCR).
3.4.1 DMA Channel Control Register (DMA_CCR)
The channel control register (DMA_CCR) bit layouts are shown in Figure 3-3.
15
14
13
12
11
10
Reserved
R, 0
9
8
DST AMODE
R/W, 00
SRC AMODE
R/W, 00
END PROG
R/W, 0
REPEAT
R/W, 0
AUTO INIT
R/W, 0
7
6
5
4
0
EN
PRIO
FS
SYNC
R/W, 0
R/W, 0
R/W, 0
R/W, 00000
LEGEND: R = Read, W = Write, n = value after reset
Figure 3-3. DMA_CCR Bit Locations
The SYNC[4:0] bits specify the event that can initiate the DMA transfer for the corresponding DMA
channel. The five bits allow several configurations as listed in Table 3-4. The bits are set to zero upon
reset. For those synchronization modes with more than one peripheral listed, the Serial Port Mode bit field
of the External Bus Selection Register dictates which peripheral event is actually connected to the DMA
input.
Copyright © 2009, Texas Instruments Incorporated
Functional Overview
27
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
Table 3-4. Synchronization Control Function
SYNC FIELD IN
DMA_CCR
SYNCHRONIZATION MODE
00000b
00001b
00010b
00011b
00100b
00101b
00110b
00111b
01000b
01001b
01010b
01011b
01100b
01101b
01110b
01111b
10000b
10001b
10010b
10011b
10100b
Other values
No event synchronized
McBSP 0 receive event (REVT0)
McBSP 0 transmit event (XEVT0)
Reserved. These bits should always be written with 0.
Reserved. These bits should always be written with 0.
McBSP1 receive event (REVT1)
McBSP1 transmit event (XEVT1)
Reserved. These bits should always be written with 0.
Reserved. These bits should always be written with 0.
McBSP2 receive event (REVT2)
McBSP2 transmit event (XEVT2)
Reserved. These bits should always be written with 0.
Reserved. These bits should always be written with 0.
Timer 0 interrupt event
Timer 1 interrupt event
External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
External interrupt 4 / I2C receive event (REVTI2C)(1)
I2C transmit event (XEVTI2C)
Reserved (do not use these values)
(1) The I2C receive event (REVTI2C) and external interrupt 4 (INT4) share a synchronization input to the DMA. When the SYNC field of the
DMA_CCR is set to 10011b, the logical OR of these two sources is used for DMA synchronization.
3.5 I2C Interface
The SM320VC5507 includes an I2C serial port. The I2C port supports:
•
•
•
•
•
Compatibility with Philips I2C Specification Revision 2.1 (January 2000)
Operation at 100 Kbps or 400 Kbps
7-bit addressing mode
Master (transmit/receive) and slave (transmit/receive) modes of operation
Events: DMA, interrupt, or polling
The I2C module clock must be in the range from 7 MHz to 12 MHz. This is necessary for proper operation
of the I2C module. With the I2C module clock in this range, the noise filters on the SDA and SCL pins
suppress noise that has a duration of 50 ns or shorter. The I2C module clock is derived from the DSP
clock divided by a programmable prescaler.
NOTE
I/O buffers are not fail-safe. The SDA and SCL pins could potentially draw current if the
device is powered down and SDA and SCL are driven by other devices connected to the
I2C bus.
3.6 Configurable External Buses
The 5507 offers combinations of configurations for its external parallel port. This allows the system
designer to choose the appropriate media interface for its application without the need of a large-pin-count
package. The External Bus Selection Register controls the routing of the parallel port signals.
28
Functional Overview
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
3.6.1 External Bus Selection Register (EBSR)
The External Bus Selection Register determines the mapping of the 21 address signals, 16 data signals,
and 15 control signals of the external parallel port. The External Bus Selection Register is
memory-mapped at port address 0x6C00. Once the bit fields of this register are changed, the routing of
the signals takes place on the next CPU clock cycle.
The reset value of the parallel port mode bit field is determined by the state of the GPIO0 pin at reset. If
GPIO0 is high at reset, the full EMIF mode is enabled and the parallel port mode bit field is set to 01. If
GPIO0 is low at reset, the HPI multiplexed mode is enabled and the parallel port mode bit field is set to
11. After reset, the parallel port should be selected to function in either EMIF mode or HPI mode. Dynamic
switching of the parallel port, once configured, is not recommended.
15
14
OSC Disable
R/W, 0
13
HIDL
R/W, 0
5
12
BKE
11
10
HOLD
R/W, 0
2
9
HOLDA
R/W, 1
1
8
CKE SEL
R/W, 0
0
CLKOUT
Disable
SR STAT
R/W, 0
R/W, 0
7
R/W, 0
6
Reserved
(see NOTE)
Parallel Port
Mode
CKE EN
SR CMD
R/W, 01 if GPIO0 = 1
11 if GPIO0 = 0
R/W, 0
R/W, 0
R, 0000
LEGEND: R = Read, W = Write, n = value after reset
NOTE: These bits are Reserved and must be kept as 0000 during any writes to EBSR.
Figure 3-4. External Bus Selection Register
Table 3-5. External Bus Selection Register Bit Field Description
BITS
DESCRIPTION
CLKOUT disable
CLKOUT disable = 0:
CLKOUT disable = 1:
15
CLKOUT enabled
CLKOUT disabled
Oscillator disable. Works with IDLE instruction to put the clock generation domain into IDLE mode.
14
13
OSC disable = 0:
OSC disable = 1:
Oscillator enabled
Oscillator disabled
Host mode idle bit (applicable only if the parallel bus is configured as EHPI)
x
When the parallel bus is set to EHPI mode, the clock domain is not allowed to go to idle, so a host processor can
access the DSP internal memory. The HIDL bit works around this restriction and allows the DSP to idle the clock
domain and the EHPI. When the clock domain is in idle, a host processor will not be able to access the DSP memory.
HIDL = 0:
HIDL = 1:
Host access to DSP enabled. Idling EHPI and clock domain is not allowed.
Idles the HPI and the clock domain upon execution of the IDLE instruction when the
parallel port mode is set to 10 or 11 selecting HPI mode. In addition, bit 4 of the Idle
Control Register must be set to 1 prior to the execution of the IDLE instruction.
Bus keeper enable(1)
BKE = 0:
12
11
Bus keeper, pullups/pulldowns enabled
Bus keeper, pullups/pulldowns disabled
BKE = 1:
SDRAM self-refresh status bit
SR STAT = 0:
SDRAM self-refresh signal is not asserted.
SDRAM self-refresh signal is asserted.
SR STAT = 1:
(1) Function available when the port or pins configured as input.
Copyright © 2009, Texas Instruments Incorporated
Functional Overview
29
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
Table 3-5. External Bus Selection Register Bit Field Description (continued)
BITS
DESCRIPTION
EMIF hold
HOLD = 0:
DSP drives the external memory bus
10
HOLD = 1:
Request the external memory bus to be placed in high-impedance so that another
device can drive the memory bus
EMIF hold acknowledge
HOLDA = 0:
DSP indicates that a hold request on the external memory bus has occured, the EMIF
completed any pending external bus activity, and placed the external memory bus
signals in high-impedance state (address bus, data bus, CE[3:0], AOE, AWE, ARE,
SDRAS, SDCAS, SDWE, SDA10, CLKMEM). Once this bit is cleared, an external
device can drive the bus.
9
HOLDA = 1:
SDRAM CKE pin selection bit
CKE SEL = 0:
No hold acknowledge
8
7
Use XF for SDRAM CKE signal
CKE SEL = 1:
Use GPIO.4 for SDRAM CKE signal
SDRAM CKE enable bit
CKE EN = 0:
XF or GPIO.4 operates in normal mode
CKE EN = 1:
Based on the CKE SEL bit, either XF or GPIO.4 drives the SDRAM CKE pin
SDRAM self-refresh command
SR CMD = 0:
6
EMIF will not issue a SDRAM self-refresh command
EMIF will issue a SDRAM self-refresh command
SR CMD = 1:
5-2
Reserved. Must be kept as 0000 during any writes to EBSR.
Parallel port mode. EMIF/HPI/GPIO Mode. Determines the mode of the parallel port.
Parallel Port Mode = 00:
Data EMIF mode. The 16 EMIF data signals and 13 EMIF control signals are routed to
the corresponding external parallel bus data and control signals. The 16 address bus
signals can be used as general-purpose I/O only.
Parallel Port Mode = 01:
Full EMIF mode. The 21 address signals, 16 data signals, and 15 control signals are
routed to the corresponding external parallel bus address, data, and control signals.
Non-multiplexed HPI mode. The HPI is enabled an its 14 address signals, 16 data
signals, and 7 control signals are routed to the corresponding address, data, control
signals of the external parallel bus. Moreover, 8 control signals of the external parallel
bus are used as general-purpose I/O.
1-0
Parallel Port Mode = 10:
Parallel Port Mode = 11:
Multiplexed HPI mode. The HPI is enabled and its 16 data signals and 10 control
signals are routed to the external parallel bus. In addition, 3 control signals of the
external parallel bus are used as general-purpose I/O. The 16 external parallel port
address bus signals are used as general-purpose I/O.
3.6.2 Parallel Port
The parallel port of the 5507 consists of 21 address signals, 16 data signals, and 15 control signals. Its 14
bits for address allow it to access 2M bytes of external memory when using the asynchronous SRAM
interface. On the other hand, the SDRAM interface can access the whole external memory space of 16M
bytes. The parallel bus supports four different modes:
•
Full EMIF mode: the EMIF with its 21 address signals, 16 data signals, and 15 control signals routed
to the corresponding external parallel bus address, data, and control signals.
•
Data EMIF mode: the EMIF with its 16 data signals, and 15 control signals routed to the
corresponding external parallel bus data and control signals. The 16 address bus signals can be used
as general-purpose I/O signals only.
•
•
Non-multiplexed HPI mode: the HPI is enabled with its 14 address signals, 16 data signals, and 8
control signals routed to the corresponding address, data, and control signals of the external parallel
bus. Moreover, 7 control signals of the external parallel bus are used as general-purpose I/O.
Multiplexed HPI mode: the HPI is enabled with its 16 data signals and 10 control signals routed to the
external parallel bus. In addition, 5 control signals of the external parallel bus are used as
general-purpose I/O. The external parallel port’s 16 address signals are used as general-purpose I/O.
30
Functional Overview
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
Table 3-6. SM320VC5507 Parallel Port Signal Routing
(1)
(1)
(1)
(1)
PIN SIGNAL
DATA EMIF (00)
FULL EMIF (01)
NON-MULTIPLEX HPI (10)
MULTIPLEX HPI (11)
ADDRESS BUS
A’[0]
N/A
EMIF.A[0]
N/A
N/A
HPI.HA[0]
HPI.HA[13:1]
N/A
N/A
A[0]
GPIO.A[0]
GPIO.A[13:1]
GPIO.A[15:14]
N/A
GPIO.A[0]
GPIO.A[13:1]
GPIO.A[15:14]
N/A
A[13:1]
EMIF.A[13:1]
EMIF.A[15:14]
EMIF.A[20:16]
A[15:14]
A[20:16](2)
N/A
DATA BUS
D[15:0]
EMIF.D[15:0]
EMIF.D[15:0]
HPI.HD[15:0]
HPI.HD[15:0]
CONTROL BUS
C0
C1
EMIF.ARE
EMIF.AOE
EMIF.ARE
EMIF.AOE
EMIF.AWE
EMIF.ARDY
EMIF.CE0
GPIO8
HPI.HINT
HPI.HR/W
HPI.HRDY
GPIO9
GPIO8
HPI.HINT
HPI.HR/W
HPI.HRDY
GPIO9
C2
EMIF.AWE
EMIF.ARDY
EMIF.CE0
C3
C4
C5
EMIF.CE1
EMIF.CE1
GPIO10
GPIO10
C6
EMIF.CE2
EMIF.CE2
HPI.HCNTL0
GPIO11
HPI.HCNTL0
HPI.HCNTL1
HPI.HBE0
HPI.HBE1
HPI.HAS
C7
EMIF.CE3
EMIF.CE3
C8
EMIF.BE0
EMIF.BE0
HPI.HBE0
HPI.HBE1
GPIO12
C9
EMIF.BE1
EMIF.BE1
C10
C11
C12
C13
C14
EMIF.SDRAS
EMIF.SDCAS
EMIF.SDWE
EMIF.SDA10
EMIF.CLKMEM
EMIF.SDRAS
EMIF.SDCAS
EMIF.SDWE
EMIF.SDA10
HPI.HCS
HPI.HDS1
GPIO13
HPI.HCS
HPI.HDS1
GPIO13
EMIF.CLKMEM
HPI.HDS2
HPI.HDS2
(1) Represents the Parallel Port Mode bits of the External Bus Selection Register.
(2) A[20:16] of the BGA package always functions as EMIF address pins and they cannot be reconfigured for any other function.
3.6.3 Parallel Port Signal Routing
The 5507 allows access to 16-bit-wide (read and write) or 8-bit-wide (read only) asynchronous memory
and 16-bit-wide SDRAM. For 16-bit-wide memories, EMIF.A[0] is kept low and is not used. To provide as
many address pins as possible, the 5507 routes the parallel port signals as shown in Figure 3-5.
Figure 3-5 shows the addition of the A′[0] signal in the BGA package. This pin is used for asynchronous
memory interface only, while the A[0] pin is used with HPI or GPIO. Figure 3-6 summarizes the use of the
parallel port signals for memory interfacing.
Copyright © 2009, Texas Instruments Incorporated
Functional Overview
31
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
EMIF.A[0]
A’[0]
A[0]
GPIO.A[0]
HPI.HA[0]
EMIF.A[13:1]
HPI.HA[13:1]
GPIO.A[13:1]
A[13:1]
EMIF.A[14]
GPIO.A[14]
A[14]
EMIF.A[15]
GPIO.A[15]
A[15]
EMIF.A[20:16]
A[20:16]
Figure 3-5. Parallel Port Signal Routing
32
Functional Overview
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
16-Bit-Wide Asynchronous Memory
16-Bit-Wide SDRAM
CEx
CLKMEM
SDRAS
SDCAS
SDWE
BE[1:0]
A[14]
CS
CEx
WE
RE
CS
WE
RE
OE
CLK
RAS
CAS
16-Bit
Asynchronous
Memory
OE
5507
BGA
WE
BE[1:0]
A[20:14]
A[13:1]
D[15:0]
BE[1:0]
A[19:13]
A[12:0]
D[15:0]
DQM[H:L]
BA[1]
BA[0]
A[11]
A[10]
A[9:0]
D[15:0]
A[13]
A[12]
SDA10
A[10:1]
D[15:0]
8-Bit-Wide Asynchronous Memory
CEx
WE
RE
CS
WE
RE
OE
OE
8-Bit
Asynchronous
Memory
5507
BE[1:0]
BGA
BE[1:0]
A[20:14]
A[13:1]
A[0]
A[20:14]
A[13:1]
A’[0]
D[7:0]
D[7:0]
Figure 3-6. Parallel Port (EMIF) Signal Interface
3.7 General-Purpose Input/Output (GPIO) Ports
3.7.1 Dedicated General-Purpose I/O
The 5507 provides eight dedicated general-purpose input/output pins, GPIO0−GPIO7. Each pin can be
indepedently configured as an input or an output using the I/O Direction Register (IODIR). The I/O Data
Register (IODATA) is used to monitor the logic state of pins configured as inputs and control the logic
state of pins configured as outputs. See Table 3-29 for address information. The description of the IODIR
is shown in Figure 3-7 and Table 3-7. The description of IODATA is shown in Figure 3-8 and Table 3-8.
To configure a GPIO pin as an input, clear the direction bit that corresponds to the pin in IODIR to 0. To
read the logic state of the input pin, read the corresponding bit in IODATA.
To configure a GPIO pin as an output, set the direction bit that corresponds to the pin in IODIR to 1. To
control the logic state of the output pin, write to the corresponding bit in IODATA.
15
8
7
6
5
4
3
2
1
0
Reserved
IO7DIR
R/W-0
IO6DIR
R/W-0
IO5DIR
R/W-0
IO4DIR
R/W-0
IO3DIR
R/W-0
IO2DIR
R/W-0
IO1DIR
R/W-0
IO0DIR
R/W-0
R-00000000
LEGEND: R = Read, W = Write, n = value after reset
Figure 3-7. I/O Direction Register (IODIR) Bit Layout
Copyright © 2009, Texas Instruments Incorporated
Functional Overview
33
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
Table 3-7. I/O Direction Register (IODIR) Bit Functions
RESET
VALUE
BIT NO. BIT NAME
FUNCTION
15−8
7−0
Reserved
IOxDIR
0
These bits are reserved and are unaffected by writes.
IOx Direction Control Bit. Controls whether IOx operates as an input or an output.
0
IOxDIR = 0;
IOxDIR = 1;
IOx is configured as an input.
IOx is configured as an output.
15
8
7
6
5
4
3
2
1
0
Reserved
R-00000000
IO7D
IO6D
IO5D
R/W-pin
IO4D
IO3D
IO2D
R/W-pin
IO1D
R/W-pin
IO0D
R/W-pin
R/W-pin
R/W-pin
R/W-pin
R/W-pin
LEGEND: R = Read, W = Write, pin = value present on the pin (IO7-IO0 default to inputs after reset)
Figure 3-8. I/O Data Register (IODATA) Bit Layout
Table 3-8. I/O Data Register (IODATA) Bit Functions
RESET
VALUE
BIT NO. BIT NAME
FUNCTION
15−8
Reserved
0
These bits are reserved and are unaffected by writes.
IOx Data Bit.
IOxD = 0;
IOxD = 1;
The signal on the IOx pin is low.
The signal on the IOx pin is high.
7−0
IOxD
pin(1)
If IOx is configured as an output (IOxDIR = 1 in IODIR):
IOxD = 0;
IOxD = 1;
Drive the signal on the IOx pin low.
Drive the signal on the IOx pin high.
(1) pin = value present on the pin (IO7−IO0 default to inputs after reset)
3.7.2 Address Bus General-Purpose I/O
The 16 address signals, EMIF.A[15−0], can also be individually enabled as GPIO when the Parallel Port
Mode bit field of the External Bus Selection Register is set for Data EMIF (00) or Multiplexed EHPI mode
(11). These pins are controlled by three registers: the enable register, AGPIOEN, determines if the pins
serve as GPIO or address (see Figure 3-9); the direction register, AGPIODIR, determines if the GPIO
enabled pin is an input or output (see Figure 3-10); and the data register, AGPIODATA, determines the
logic states of the pins in general-purpose I/O mode (see Figure 3-11).
15
14
13
12
11
10
9
8
AIOEN15
AIOEN14
AIOEN13
R/W, 0
AIOEN12
R/W, 0
AIOEN11
R/W, 0
AIOEN10
R/W, 0
AIOEN9
R/W, 0
AIOEN8
R/W, 0
R/W, 0
R/W, 0
7
6
5
4
3
2
1
0
AIOEN7
R/W, 0
AIOEN6
R/W, 0
AIOEN5
R/W, 0
AIOEN4
R/W, 0
AIOEN3
R/W, 0
AIOEN2
R/W, 0
AIOEN1
R/W, 0
AIOEN0
R/W, 0
LEGEND: R = Read, W = Write, n = value after reset
Figure 3-9. Address/GPIO Enable Register (AGPIOEN) Bit Layout
34
Functional Overview
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
Table 3-9. Address/GPIO Enable Register (AGPIOEN) Bit Functions
RESET
VALUE
BIT NO. BIT NAME
FUNCTION
Enable or disable GPIO function of Address Bus of EMIF.
15−0
AIOENx
0
AIOENx = 0;
AIOENx = 1;
GPIO function of Ax line is disabled; i.e., Ax has address function.
GPIO function of Ax line is enabled; i.e., Ax has GPIO function.
15
14
13
12
11
10
9
8
AIODIR13
R/W, 0
AIODIR12
R/W, 0
AIODIR11
R/W, 0
AIODIR10
R/W, 0
AIODIR9
R/W, 0
AIODIR8
R/W, 0
AIODIR15
AIODIR14
R/W, 0
R/W, 0
7
6
5
4
3
2
1
0
AIODIR7
R/W, 0
AIODIR6
R/W, 0
AIODIR5
R/W, 0
AIODIR4
R/W, 0
AIODIR3
R/W, 0
AIODIR2
R/W, 0
AIODIR1
R/W, 0
AIODIR0
R/W, 0
LEGEND: R = Read, W = Write, n = value after reset
Figure 3-10. Address/GPIO Direction Register (AGPIODIR) Bit Layout
Table 3-10. Address/GPIO Direction Register (AGPIODIR) Bit Functions
RESET
VALUE
BIT NO. BIT NAME
FUNCTION
Data direction bits that configure the Address Bus configured as I/O pins as either input or output pins.
15−0
AIODIRx
0
AIODIRx = 0;
AIODIRx = 1;
Configure corresponding pin as an input.
Configure corresponding pin as an output.
15
14
13
12
11
10
9
8
AIOD15
AIOD14
R/W, 0
AIOD13
R/W, 0
AIOD12
R/W, 0
AIOD11
R/W, 0
AIOD10
R/W, 0
AIOD9
R/W, 0
AIOD8
R/W, 0
R/W, 0
7
6
5
4
3
2
1
0
AIOD7
R/W, 0
AIOD6
R/W, 0
AIOD5
R/W, 0
AIOD4
R/W, 0
AIOD3
R/W, 0
AIOD2
R/W, 0
AIOD1
R/W, 0
AIOD0
R/W, 0
LEGEND: R = Read, W = Write, n = value after reset
Figure 3-11. Address/GPIO Data Register (AGPIODATA) Bit Layout
Table 3-11. Address/GPIO Data Register (AGPIODATA) Bit Functions
RESET
VALUE
BIT NO. BIT NAME
FUNCTION
Data bits that are used to control the level of the Address Bus configured as I/O output pins, and to
monitor the level of the Address Bus configured as I/O input pins.
If AIODIRn = 0, then:
AIODx = 0;
AIODx = 1;
Corresponding I/O pin is read as a low.
Corresponding I/O pin is read as a high.
15−0
AIODx
0
If AIODIRn = 1, then:
AIODx = 0;
Set corresponding I/O pin to low.
Set corresponding I/O pin to high.
AIODx = 1;
Copyright © 2009, Texas Instruments Incorporated
Functional Overview
35
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
3.7.3 EHPI General-Purpose I/O
Six control lines of the External Parallel Bus can also be set as general-purpose I/O when the Parallel Port
Mode bit field of the External Bus Selection Register is set to Nonmultiplexed EHPI (10) or Multiplexed
EHPI mode (11). These pins are controlled by three registers: the enable register, EHPIGPIOEN,
determines if the pins serve as GPIO or address (see Figure 3-12); the direction register, EHPIGPIODIR,
determines if the GPIO enabled pin is an input or output (see Figure 3-13); and the data register,
EHPIGPIODATA, determines the logic states of the pins in GPIO mode (see Figure 3-14).
15
6
5
4
3
2
1
0
Reserved
GPIOEN13
R/W, 0
GPIOEN12
R/W, 0
GPIOEN11
R/W, 0
GPIOEN10
R/W, 0
GPIOEN9
R/W, 0
GPIOEN8
R/W, 0
R, 0000 0000 00
LEGEND: R = Read, W = Write, n = value after reset
Figure 3-12. EHPI GPIO Enable Register (EHPIGPIOEN) Bit Layout
Table 3-12. EHPI GPIO Enable Register (EHPIGPIOEN) Bit Functions
RESET
VALUE
BIT NO. BIT NAME
FUNCTION
15−6
5−0
Reserved
0
0
Reserved
Enable or disable GPIO function of EHPI Control Bus.
GPIOEN13−
GPIOEN8
GPIOENx = 0;
GPIOENx = 1;
GPIO function of GPIOx line is disabled.
GPIO function of GPIOx line is enabled.
15
6
5
4
3
2
1
0
Reserved
GPIODIR13
R/W, 0
GPIODIR12
R/W, 0
GPIODIR11
R/W, 0
GPIODIR10
R/W, 0
GPIODIR9
R/W, 0
GPIODIR8
R/W, 0
R, 0000 0000 00
LEGEND: R = Read, W = Write, n = value after reset
Figure 3-13. EHPI GPIO Direction Register (EHPIGPIODIR) Bit Layout
Table 3-13. EHPI GPIO Direction Register (EHPIGPIODIR) Bit Functions
RESET
VALUE
BIT NO. BIT NAME
FUNCTION
15−6
Reserved
0
Reserved
Data direction bits that configure the EHPI Control Bus configured as I/O pins as either input or output
pins.
GPIODIR13
−
GPIODIR8
5−0
0
GPIODIRx = 0;
GPIODIRx = 1;
Configure corresponding pin as an input.
Configure corresponding pin as an output.
15
6
5
4
3
2
1
0
Reserved
GPIOD13
R/W, 0
GPIOD12
R/W, 0
GPIOD11
R/W, 0
GPIOD10
R/W, 0
GPIOD9
R/W, 0
GPIOD8
R/W, 0
R, 0000 0000 00
LEGEND: R = Read, W = Write, n = value after reset
Figure 3-14. EHPI GPIO Data Register (EHPIGPIODATA) Bit Layout
36
Functional Overview
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
Table 3-14. EHPI GPIO Data Register (EHPIGPIODATA) Bit Functions
RESET
VALUE
BIT NO. BIT NAME
FUNCTION
15−6
Reserved
0
Reserved
Data bits that are used to control the level of the EHPI Control Bus configured as I/O output pins, and
to monitor the level of the EHPI Control Bus configured as I/O input pins.
If GPIODIRn = 0, then:
GPIODx = 0;
GPIODx = 1;
Corresponding I/O pin is read as a low.
Corresponding I/O pin is read as a high.
GPIOD13−
GPIOD8
5−0
0
If GPIODIRn = 1, then:
GPIODx = 0;
Set corresponding I/O pin to low.
Set corresponding I/O pin to high.
GPIODx = 1;
3.8 System Register
The system register (SYSR) provides control over certain device-specific functions. The register is located
at port address 07FDh.
15
8
Reserved
7
3
2
0
Reserved
CLKDIV
R/W
LEGEND: R = Read, W = Write, n = value after reset
Figure 3-15. System Register Bit Locations
Table 3-15. System Register Bit Fields
BIT
FUNCTION
NUMBER
NAME
15−3
Reserved
These bits are reserved and are unaffected by writes.
CLKOUT Divide Factor. Allows the clock present on the CLKOUT pin to be a
divided-down version of the internal CPU clock. This field does not affect the programming
of the PLL.
CLKDIV 000 = CLKOUT represents the CPU clock divided by 1
CLKDIV 001 = CLKOUT represents the CPU clock divided by 2
CLKDIV 010 = CLKOUT represents the CPU clock divided by 4
CLKDIV 011 = CLKOUT represents the CPU clock divided by 6
CLKDIV 100 = CLKOUT represents the CPU clock divided by 8
CLKDIV 101 = CLKOUT represents the CPU clock divided by 10
CLKDIV 110 = CLKOUT represents the CPU clock divided by 12
CLKDIV 111 = CLKOUT represents the CPU clock divided by 14
2-0
CLKDIV
Copyright © 2009, Texas Instruments Incorporated
Functional Overview
37
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
3.9 USB Clock Generation
The USB module can be clocked from either an Analog Phase-Locked Loop (APLL) or a Digital
Phase-Locked Loop (DPLL). The APLL is the recommended USB clock source due to better noise
tolerance and less long-term jitter than the DPLL. To maintain the backward compatibility, the DPLL is the
power-up default clock source for the USB module.
USB
1
APLL
USB Module Clock
CLKIN
(48.0 MHz)
USB
0
DPLL
PLLSEL
Figure 3-16. USB Clock Generation
15
3
2
1
APLLSTAT
R, 0
0
Reserved
DPLLSTAT
R, 1
PLLSEL
R/W, 0
R, 0000 0000 0000 0
LEGEND: R = Read, W = Write, n = value after reset
Figure 3-17. USB PLL Selection and Status Register Bit Layout
Table 3-16. USB PLL Selection and Status Register Bit Functions
RESET
VALUE
BIT NO. BIT NAME
FUNCTION
15−3
Reserved
0
1
Reserved bits. Always write 0.
Status bit indicating if the DPLL is the source for the USB module clock.
2
DPLLSTAT
DPLLSTAT = 0;
DPLLSTAT = 1;
The DPLL is not the USB module clock source.
The DPLL is the USB module clock source.
Status bit indicating if the APLL is the source for the USB module clock.
1
0
APLLSTAT
PLLSEL
0
0
APLLSTAT = 0;
APLLSTAT = 1;
The APLL is not the USB module clock source.
The APLL is the USB module clock source.
USB module clock source selection bit.
PLLSEL = 0;
PLLSEL = 1;
DPLL is selected as USB module clock source.
APLL is selected as USB module clock source.
15
12
11
10
3
2
ON
1
0
MULT
DIV
COUNT
MODE
R/W, 0
STAT
R, 0
R/W, 0000
R/W, 0
R, 0000 0000
R/W, 0
LEGEND: R = Read, W = Write, n = value after reset
Figure 3-18. USB APLL Clock Mode Register Bit Layout
38
Functional Overview
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
Table 3-17. USB APLL Clock Mode Register Bit Functions
RESET
VALUE
BIT NO. BIT NAME
FUNCTION
PLL Multiply Factor K. Multiply Factor K, combined with DIV and MODE, determines the final PLL
output clock frequency.
15−12
MULT
DIV
0
K = MULT[3:0] + 1
PLL Divide Factor (D) selection bit for PLL multiply mode operation. DIV, combined with K and MODE,
determines the final PLL output clock frequency. When the PLL is operating in multiply mode:
11
0
0
DIV = 0;
DIV = 1;
PLL Divide Factor D = 1
PLL Divide Factor D = 2 if K is odd
PLL Divide Factor D = 4 if K is even
Status bit indicating if the APLL is the source for the USB module clock.8-bit counter for PLL lock
timer. When the MODE bit is set to 1, the COUNT field starts decrementing by 1 at the rate of
CLKIN/16. When COUNT decrements to 0, the STAT bit is set to 1 and the PLL enabled clock is
sourced to the USB module.
10-3
COUNT
PLL Voltage Controlled Oscillator (VCO) enable bit. This bit works in conjunction with MODE to enable
or disable the VCO.
ON
MODE
VCO
OFF
ON
0
0
X
1
2
ON
0
1
X
ON
X = Don’t care
PLL mode selection bit
MODE = 0;
PLL operating in divide mode (VCO bypassed). When the PLL is
operating in DIV mode, the PLL Divide Factor (D) is determined by the
factor K.
1
0
MODE
STAT
0
0
D = 2 if K = 1 to 15
D = 4 if K = 16
PLL operating in multiply mode (VCO on). The PLL multiply and divide
factors are determined by DIV and K.
MODE = 1;
PLL lock status bit
STAT = 0;
PLL operating in DIV mode (VCO bypassed)
PLL operating in multiply mode (VCO on)
STAT = 1;
DIV, combined with MODE and K, defines the final PLL multiplication ratio M/D as indicated below. The
USB APLL clock frequency can be simply expressed by Equation 1.
FUSB APLL CLK = FCLKIN x (M/D)
The multiplication factor M and the dividing factor D are defined in Table 3-18.
Table 3-18. M and D Values Based on MODE, DIV, and K
MODE
DIV
X
K
1 to 15
16
M
1
D
2
4
1
1
2
4
0
0
1
1
1
1
X
1
0
1 to 15
16
K
0
1
1
Odd
Even
K
1
K-1
Copyright © 2009, Texas Instruments Incorporated
Functional Overview
39
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
The USB clock generation and the PLL switching scheme are discussed in detail in the
TMS320VC5507/5509 DSP Universal Serial Bus (USB) Module Reference Guide (literature number
SPRU596) and in the Using the USB APLL on the TMS320VC5507/5509A Application Report (literature
number SPRA997).
3.10 Memory-Mapped Registers
The 5507 has 78 memory-mapped CPU registers that are mapped in data memory space address 0h to
4Fh. Table 3-19 provides a list of the CPU memory-mapped registers (MMRs) available.
Table 3-19. CPU Memory-Mapped Registers
WORD ADDRESS
REGISTER
DESCRIPTION
Interrupt enable register 0
BIT FIELD
(HEX)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
IER0
IFR0
ST0_55
ST1_55
ST3_55
−
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[31−16]
[39−32]
[15−0]
[31−16]
[39−32]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[7−0]
Interrupt flag register 0
Status register 0 for C55x
Status register 1 for C55x
Status register 3 for C55x
Reserved
ST0
Status register ST0
Status register ST1
Accumulator 0
ST1
AC0L
AC0H
AC0G
AC1L
AC1H
AC1G
T3
Accumulator 1
Temporary register
TRN0
AR0
Transition register
Auxiliary register 0
AR1
Auxiliary register 1
AR2
Auxiliary register 2
AR3
Auxiliary register 3
AR4
Auxiliary register 4
AR5
Auxiliary register 5
AR6
Auxiliary register 6
AR7
Auxiliary register 7
SP
Stack pointer register
Circular buffer size register
Block repeat counter
Block repeat start address
Block repeat end address
Processor mode status register
Program counter extension register
Reserved
BK03
BRC0
RSA0L
REA0L
PMST
XPC
–
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
T0
Temporary data register 0
Temporary data register 1
Temporary data register 2
Temporary data register 3
Accumulator 2
T1
T2
T3
AC2L
40
Functional Overview
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
Table 3-19. CPU Memory-Mapped Registers (continued)
WORD ADDRESS
REGISTER
DESCRIPTION
BIT FIELD
(HEX)
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
AC2H
AC2G
CDP
[31−16]
[39−32]
[15−0]
[15−0]
[31−16]
[39−32]
[6−0]
Coefficient data pointer
Accumulator 3
AC3L
AC3H
AC3G
DPH
Extended data page pointer
MDP05
MDP67
DP
Reserved
[6−0]
Reserved
[6−0]
Memory data page start address
Peripheral data page start address
Circular buffer size register for AR[4−7]
Circular buffer size register for CDP
Circular buffer start address register for AR[0−1]
Circular buffer start address register for AR[2−3]
Circular buffer start address register for AR[4−5]
Circular buffer start address register for AR[6−7]
Circular buffer coefficient start address register
Data page pointer storage location for 128-word data table
Transition register 1
[15−0]
[8−0]
PDP
BK47
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[23−16]
[15−0]
[23−16]
[15−0]
[23−16]
[15−0]
[23−16]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[6−0]
BKC
BSA01
BSA23
BSA45
BSA67
BSAC
BIOS
TRN1
BRC1
BRS1
CSR
Block repeat counter 1
Block repeat save 1
Computed single repeat
RSA0H
RSA0L
REA0H
REA0L
RSA1H
RSA1L
REA1H
REA1L
RPTC
IER1
Repeat start address 0
Repeat end address 0
Repeat start address 1
Repeat end address 1
Repeat counter
Interrupt enable register 1
Interrupt flag register 1
Debug IER0
IFR1
DBIER0
DBIER1
IVPD
Debug IER1
Interrupt vector pointer DSP
Interrupt vector pointer HOST
Status register 2 for C55x
System stack pointer
IVPH
ST2_55
SSP
SP
User stack pointer
SPH
Extended data page pointer for the SP and the SSP
Main data page pointer for the CDP
CDPH
[6−0]
Copyright © 2009, Texas Instruments Incorporated
Functional Overview
41
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
3.11 Peripheral Register Description
Each 5507 device has a set of memory-mapped registers associated with peripherals as listed in
Table 3-20 through Table 3-35. Some registers use less than 16 bits. When reading these registers,
unused bits are always read as 0.
NOTE
The CPU access latency to the peripheral memory-mapped registers is 6 CPU cycles.
Following peripheral register update(s), the CPU must wait at least 6 CPU cycles before
attempting to use that peripheral. When more than one peripheral register is updated in a
sequence, the CPU only needs to wait following the final register write. For example, if the
EMIF is being reconfigured, the CPU must wait until the very last EMIF register update
takes effect before trying to access the external memory. The users should consult the
respective peripheral user’s guide to determine if a peripheral requires additional time to
initialize itself to the new configuration after the register updates take effect.
Before reading or writing to the USB register, the USB module has to be brought out of reset by setting bit
2 of the USB Idle Control and Status Register.
Table 3-20. Idle Control, Status, and System Registers
(1)
WORD ADDRESS
0x0001
REGISTER NAME
ICR[7:0]
DESCRIPTION
RESET VALUE
Idle control register
Idle status register
System register
xxxx xxxx 0000 0100
xxxx xxxx 0000 0000
0000 0000 0000 0000
0x0002
ISTR[7:0]
0x07FD
SYSR[15:0]
(1) Hardware reset; x denotes a “don’t care'.
Table 3-21. External Memory Interface Registers
(1)
WORD ADDRESS
0x0800
0x0801
0x0802
0x0803
0x0804
0x0805
0x0806
0x0807
0x0808
0x0809
0x080A
0x080B
0x080C
0x080D
0x080E
0x080F
0x0810
0x0811
0x0812
0x0813
0x0814
REGISTER NAME
DESCRIPTION
EMIF global control register
RESET VALUE
EGCR[15:0]
EMI_RST
xxxx xxxx 0010 xx00
xxxx xxxx xxxx xxxx
xx00 0000 0000 0000
x010 1111 1111 1111
0100 1111 1111 1111
xxxx xxxx 0000 0000
x010 1111 1111 1111
0100 1111 1111 1111
xxxx xxxx 0000 0000
x010 1111 1111 1111
0101 1111 1111 1111
xxxx xxxx 0000 0000
x010 1111 1111 1111
0101 1111 1111 1111
xxxx xxxx 0000 0000
1111 1001 0100 1000
xxxx 0000 1000 0000
xxxx 0000 1000 0000
xxxx xxxx xxxx xxxx
xxxx xx11 1111 1111
0000 0000 0000 0111
EMIF global reset register
EMI_BE[13:0]
CE0_1[14:0]
CE0_2[15:0]
CE0_3[7:0]
CE1_1[14:0]
CE1_2[15:0]
CE1_3[7:0]
CE2_1[14:0]
CE2_2[15:0]
CE2_3[7:0]
CE3_1[14:0]
CE3_2[15:0]
CE3_3[7:0]
SDC1[15:0]
SDPER[11:0]
SDCNT[11:0]
INIT
EMIF bus error status register
EMIF CE0 space control register 1
EMIF CE0 space control register 2
EMIF CE0 space control register 3
EMIF CE1 space control register 1
EMIF CE1 space control register 2
EMIF CE1 space control register 3
EMIF CE2 space control register 1
EMIF CE2 space control register 2
EMIF CE2 space control register 3
EMIF CE3 space control register 1
EMIF CE3 space control register 2
EMIF CE3 space control register 3
EMIF SDRAM control register 1
EMIF SDRAM period register
EMIF SDRAM counter register
EMIF SDRAM init register
SDC2[9:0]
EMIF SDRAM control register 2
EMIF SDRAM control register 3
SDC3
(1) Hardware reset; x denotes a “don’t care.”
42
Functional Overview
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
Table 3-22. DMA Configuration Registers
PORT ADDRESS
(1)
REGISTER NAME
DESCRIPTION
RESET VALUE
(WORD)
GLOBAL REGISTER
0x0E00
DMA_GCR[2:0]
DMA_GSCR
DMA_GTCR
DMA global control register
xxxx xxxx xxxx x000
0x0E02
DMA software compatibility register
DMA timeout control register
0x0E03
CHANNEL #0 REGISTERS
0x0C00
DMA_CSDP0
DMA_CCR0[15:0]
DMA_CICR0[5:0]
DMA_CSR0[6:0]
DMA_CSSA_L0
DMA_CSSA_U0
DMA channel 0 source destination parameters register
DMA channel 0 control register
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx xx00 0011
xxxx xxxx xx00 0000
Undefined
0x0C01
0x0C02
DMA channel 0 interrupt control register
0x0C03
DMA channel 0 status register
0x0C04
DMA channel 0 source start address register (lower bits)
DMA channel 0 source start address register (upper bits)
0x0C05
Undefined
DMA channel 0 source destination address register
(lower bits)
0x0C06
0x0C07
DMA_CDSA_L0
DMA_CDSA_U0
Undefined
Undefined
DMA channel 0 Source destination address register (upper
bits)
0x0C08
0x0C09
DMA_CEN0
DMA_CFN0
DMA_CSFI0
DMA_CSEI0
DMA_CSAC0
DMA_CDAC0
DMA_CDEI0
DMA_CDFI0
DMA channel 0 element number register
DMA channel 0 frame number register
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0x0C0A
DMA channel 0 source frame index register
DMA channel 0 source element index register
DMA channel 0 source address counter
DMA channel 0 destination address counter
DMA channel 0 destination element index register
DMA channel 0 destination frame index register
0x0C0B
0x0C0C
0x0C0D
0x0C0E
0x0C0F
CHANNEL #1 REGISTERS
0x0C20
DMA_CSDP1
DMA_CCR1[15:0]
DMA_CICR1[5:0]
DMA_CSR1[6:0]
DMA_CSSA_L1
DMA_CSSA_U1
DMA channel 1 source destination parameters register
DMA channel 1 control register
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx xx00 0011
xxxx xxxx xx00 0000
Undefined
0x0C21
0x0C22
DMA channel 1 interrupt control register
0x0C23
DMA channel 1 status register
0x0C24
DMA channel 1 source start address register (lower bits)
DMA channel 1 source start address register (upper bits)
0x0C25
Undefined
DMA channel 1 source destination address register
(lower bits)
0x0C26
0x0C27
DMA_CDSA_L1
DMA_CDSA_U1
Undefined
Undefined
DMA channel 1 source destination address register (upper
bits)
0x0C28
0x0C29
DMA_CEN1
DMA_CFN1
DMA_CSFI1
DMA_CSEI1
DMA_CSAC1
DMA_CDAC1
DMA_CDEI1
DMA_CDFI1
DMA channel 1 element number register
DMA channel 1 frame number register
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0x0C2A
DMA channel 1 source frame index register
DMA channel 1 source element index register
DMA channel 1 source address counter
DMA channel 1 destination address counter
DMA channel 1 destination element index register
DMA channel 1 destination frame index register
0x0C2B
0x0C2C
0x0C2D
0x0C2E
0x0C2F
CHANNEL #2 REGISTERS
0x0C40
DMA_CSDP2
DMA_CCR2[15:0]
DMA_CICR2[5:0]
DMA channel 2 source destination parameters register
DMA channel 2 control register
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx xx00 0011
0x0C41
0x0C42
DMA channel 2 interrupt control register
(1) Hardware reset: x denotes a “don’t care.”
Copyright © 2009, Texas Instruments Incorporated
Functional Overview
43
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
Table 3-22. DMA Configuration Registers (continued)
PORT ADDRESS
(WORD)
(1)
REGISTER NAME
DESCRIPTION
RESET VALUE
0x0C43
0x0C44
0x0C45
DMA_CSR2[6:0]
DMA_CSSA_L2
DMA_CSSA_U2
DMA channel 2 status register
xxxx xxxx xx00 0000
Undefined
DMA channel 2 source start address register (lower bits)
DMA channel 2 source start address register (upper bits)
Undefined
DMA channel 2 source destination address register
(lower bits)
0x0C46
0x0C47
DMA_CDSA_L2
DMA_CDSA_U2
Undefined
Undefined
DMA channel 2 source destination address register
(upper bits)
0x0C48
0x0C49
DMA_CEN2
DMA_CFN2
DMA_CSFI2
DMA_CSEI2
DMA_CSAC2
DMA_CDAC2
DMA_CDEI2
DMA_CDFI2
DMA channel 2 element number register
DMA channel 2 frame number register
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0x0C4A
DMA channel 2 source frame index register
DMA channel 2 source element index register
DMA channel 2 source address counter
DMA channel 2 destination address counter
DMA channel 2 destination element index register
DMA channel 2 destination frame index register
0x0C4B
0x0C4C
0x0C4D
0x0C4E
0x0C4F
CHANNEL #3 REGISTERS
0x0C60
DMA_CSDP3
DMA_CCR3[15:0]
DMA_CICR3[5:0]
DMA_CSR3[6:0]
DMA_CSSA_L3
DMA_CSSA_U3
DMA channel 3 source destination parameters register
DMA channel 3 control register
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx xx00 0011
xxxx xxxx xx00 0000
Undefined
0x0C61
0x0C62
DMA channel 3 interrupt control register
0x0C63
DMA channel 3 status register
0x0C64
DMA channel 3 source start address register (lower bits)
DMA channel 3 source start address register (upper bits)
0x0C65
Undefined
DMA channel 3 source destination address register
(lower bits)
0x0C66
0x0C67
DMA_CDSA_L3
DMA_CDSA_U3
Undefined
Undefined
DMA channel 3 source destination address register
(upper bits)
0x0C68
0x0C69
DMA_CEN3
DMA_CFN3
DMA_CSFI3
DMA_CSEI3
DMA_CSAC3
DMA_CDAC3
DMA_CDEI3
DMA_CDFI3
DMA channel 3 element number register
DMA channel 3 frame number register
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0x0C6A
DMA channel 3 source frame index register
DMA channel 3 source element index register
DMA channel 3 source address counter
DMA channel 3 destination address counter
DMA channel 3 destination element index register
DMA channel 3 destination frame index register
0x0C6B
0x0C6C
0x0C6D
0x0C6E
0x0C6F
CHANNEL #4 REGISTERS
0x0C80
DMA_CSDP4
DMA_CCR4[15:0]
DMA_CICR4[5:0]
DMA_CSR4[6:0]
DMA_CSSA_L4
DMA_CSSA_U4
DMA channel 4 source destination parameters register
DMA channel 4 control register
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx xx00 0011
xxxx xxxx xx00 0000
Undefined
0x0C81
0x0C82
DMA channel 4 interrupt control register
0x0C83
DMA channel 4 status register
0x0C84
DMA channel 4 source start address register (lower bits)
DMA channel 4 source start address register (upper bits)
0x0C85
Undefined
DMA channel 4 Source destination address register
(lower bits)
0x0C86
0x0C87
DMA_CDSA_L4
DMA_CDSA_U4
Undefined
Undefined
DMA channel 4 source destination address register
(upper bits)
0x0C88
0x0C89
0x0C8A
DMA_CEN4
DMA_CFN4
DMA_CSFI4
DMA channel 4 element number register
DMA channel 4 frame number register
DMA channel 4 source frame index register
Undefined
Undefined
Undefined
44
Functional Overview
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
Table 3-22. DMA Configuration Registers (continued)
PORT ADDRESS
(1)
REGISTER NAME
DESCRIPTION
RESET VALUE
(WORD)
0x0C8B
DMA_CSEI4
DMA_CSAC4
DMA_CDAC4
DMA_CDEI4
DMA_CDFI4
DMA channel 4 source element index register
DMA channel 4 source address counter
Undefined
Undefined
Undefined
Undefined
Undefined
0x0C8C
0x0C8D
DMA channel 4 destination address counter
DMA channel 4 destination element index register
DMA channel 4 destination frame index register
0x0C8E
0x0C8F
CHANNEL #5 REGISTERS
0x0CA0
DMA_CSDP5
DMA_CCR5[15:0]
DMA_CICR5[5:0]
DMA_CSR5[6:0]
DMA_CSSA_L5
DMA_CSSA_U5
DMA channel 5 source destination parameters register
DMA channel 5 control register
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx xx00 0011
xxxx xxxx xx00 0000
Undefined
0x0CA1
0x0CA2
DMA channel 5 interrupt control register
0x0CA3
DMA channel 5 status register
0x0CA4
DMA channel 5 source start address register (lower bits)
DMA channel 5 source start address register (upper bits)
0x0CA5
Undefined
DMA channel 5 source destination address register
(lower bits)
0x0CA6
0x0CA7
DMA_CDSA_L5
DMA_CDSA_U5
Undefined
Undefined
DMA channel 5 source destination address register
(upper bits)
0x0CA8
0x0CA9
0x0CAA
0x0CAB
0x0CAC
0x0CAD
0x0CAE
0x0CAF
DMA_CEN5
DMA_CFN5
DMA_CSFI5
DMA_CSEI5
DMA_CSAC5
DMA_CDAC5
DMA_CDEI5
DMA_CDFI5
DMA channel 5 element number register
DMA channel 5 frame number register
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
DMA channel 5 source frame index register
DMA channel 5 source element index register
DMA channel 5 source address counter
DMA channel 5 destination address counter
DMA channel 5 destination element index register
DMA channel 5 destination frame index register
Table 3-23. Real-Time Clock Registers
(1)
WORD ADDRESS
0x1800
REGISTER NAME
DESCRIPTION
RESET VALUE
RTCSEC
RTCSECA
RTCMIN
Seconds register
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0x1801
Seconds alarm register
Minutes register
0x1802
0x1803
RTCMINA
RTCHOUR
RTCHOURA
RTCDAYW
RTCDAYM
RTCMONTH
RTCYEAR
RTCPINTR
RTCINTEN
RTCINTFL
Minutes alarm register
Hours register
0x1804
0x1805
Hours alarm register
Day of the week register
Day of the month (date) register
Month register
0x1806
0x1807
0x1808
0x1809
Year register
0x180A
Periodic interrupt selection register
Interrupt enable register
Interrupt flag register
Reserved
0x180B
0x180C
0x180D−0x1BFF
(1) Hardware reset; x denotes a “don’t care.”
Copyright © 2009, Texas Instruments Incorporated
Functional Overview
45
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
Table 3-24. Clock Generator
(1)
WORD ADDRESS
REGISTER NAME
DESCRIPTION
RESET VALUE
0010 0000 0000 0010 DIV1
mode
0x1C00
CLKMD[14:0]
Clock mode register
If non-USB boot mode:
0010 0000 0000 0110 DIV2
mode
0x1E00
USBDPLL[14:0](2)
USB DPLL control register
If USB boot mode:
0010 0010 0001 0011 PLL
MULT4 mode
0x1E80
0x1F00
USBPLLSEL[2:0]
USBAPLL[15:0]
USB PLL selection register
USB APLL control register
0000 0000 0000 0100
0000 0000 0000 0000
(1) Hardware reset; x denotes a “don’t care.”
(2) DPLL is the power-up default USB clock source.
Table 3-25. Timers
(1)
WORD ADDRESS
0x1000
REGISTER NAME
TIM0[15:0]
DESCRIPTION
Timer count register, timer #0
Period register, timer #0
RESET VALUE
1111 1111 1111 1111
1111 1111 1111 1111
0000 0000 0001 0000
xxxx 0000 xxxx 0000
1111 1111 1111 1111
1111 1111 1111 1111
0000 0000 0001 0000
xxxx 0000 xxxx 0000
0x1001
PRD0[15:0]
TCR0[15:0]
PRSC0[15:0]
TIM1[15:0]
0x1002
Timer control register, timer #0
Timer prescaler register, timer #0
Timer count register, timer #1
Period register, timer #1
0x1003
0x2400
0x2401
PRD1[15:0]
TCR1[15:0]
PRSC1[15:0]
0x2402
Timer control register, timer #1
Timer prescaler register, timer #1
0x2403
(1) Hardware reset; x denotes a “don’t care.”
Table 3-26. Multichannel Serial Port #0
PORT ADDRESS
(1)
REGISTER NAME
DESCRIPTION
RESET VALUE
(WORD)
0x2800
0x2801
0x2802
0x2803
0x2804
0x2805
0x2806
0x2807
0x2808
0x2809
0x280A
0x280B
0x280C
0x280D
DRR2_0[15:0]
DRR1_0[15:0]
DXR2_0[15:0]
DXR1_0[15:0]
SPCR2_0[15:0]
SPCR1_0[15:0]
RCR2_0[15:0]
RCR1_0[15:0]
XCR2_0[15:0]
XCR1_0[15:0]
SRGR2_0[15:0]
SRGR1_0[15:0]
MCR2_0[15:0]
MCR1_0[15:0]
Data receive register 2, McBSP #0
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0020 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
0000 0000 0000 0000
Data receive register 1, McBSP #0
Data transmit register 2, McBSP #0
Data transmit register 1, McBSP #0
Serial port control register 2, McBSP #0
Serial port control register 1, McBSP #0
Receive control register 2, McBSP #0
Receive control register 1, McBSP #0
Transmit control register 2, McBSP #0
Transmit control register 1, McBSP #0
Sample rate generator register 2, McBSP #0
Sample rate generator register 1, McBSP #0
Multichannel control register 2, McBSP #0
Multichannel control register 1, McBSP #0
Receive channel enable register partition A,
McBSP #0
0x280E
0x280F
0x2810
RCERA_0[15:0]
RCERB_0[15:0]
XCERA_0[15:0]
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Receive channel enable register partition B,
McBSP #0
Transmit channel enable register partition A,
McBSP #0
(1) Hardware reset; x denotes a “don’t care.”
46 Functional Overview
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
Table 3-26. Multichannel Serial Port #0 (continued)
Transmit channel enable register partition B,
0x2811
XCERB_0[15:0]
McBSP #0
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0x2812
0x2813
PCR0[15:0]
Pin control register, McBSP #0
Receive channel enable register partition C,
McBSP #0
RCERC_0[15:0]
Receive channel enable register partition D,
McBSP #0
0x2814
0x2815
0x2816
0x2817
0x2818
0x2819
0x281A
0x281B
0x281C
0x281D
0x281E
RCERD_0[15:0]
XCERC_0[15:0]
XCERD_0[15:0]
RCERE_0[15:0]
RCERF_0[15:0]
XCERE_0[15:0]
XCERF_0[15:0]
RCERG_0[15:0]
RCERH_0[15:0]
XCERG_0[15:0]
XCERH_0[15:0]
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Transmit channel enable register partition C,
McBSP #0
Transmit channel enable register partition D,
McBSP #0
Receive channel enable register partition E,
McBSP #0
Receive channel enable register partition F,
McBSP #0
Transmit channel enable register partition E,
McBSP #0
Transmit channel enable register partition F,
McBSP #0
Receive channel enable register partition G,
McBSP #0
Receive channel enable register partition H,
McBSP #0
Transmit channel enable register partition G,
McBSP #0
Transmit channel enable register partition H,
McBSP #0
Table 3-27. Multichannel Serial Port #1
PORT ADDRESS
(WORD)
REGISTER NAME
DESCRIPTION
RESET VALUE(1)
0x2C00
0x2C01
0x2C02
0x2C03
0x2C04
0x2C05
0x2C06
0x2C07
0x2C08
0x2C09
0x2C0A
0x2C0B
0x2C0C
0x2C0D
DRR2_1[15:0]
DRR1_1[15:0]
DXR2_1[15:0]
DXR1_1[15:0]
SPCR2_1[15:0]
SPCR1_1[15:0]
RCR2_1[15:0]
RCR1_1[15:0]
XCR2_1[15:0]
XCR1_1[15:0]
SRGR2_1[15:0]
SRGR1_1[15:0]
MCR2_1[15:0]
MCR1_1[15:0]
Data receive register 2, McBSP #1
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0020 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
0000 0000 0000 0000
Data receive register 1, McBSP #1
Data transmit register 2, McBSP #1
Data transmit register 1, McBSP #1
Serial port control register 2, McBSP #1
Serial port control register 1, McBSP #1
Receive control register 2, McBSP #1
Receive control register 1, McBSP #1
Transmit control register 2, McBSP #1
Transmit control register 1, McBSP #1
Sample rate generator register 2, McBSP #1
Sample rate generator register 1, McBSP #1
Multichannel control register 2, McBSP #1
Multichannel control register 1, McBSP #1
Receive channel enable register partition A,
McBSP #1
0x2C0E
0x2C0F
0x2C10
RCERA_1[15:0]
RCERB_1[15:0]
XCERA_1[15:0]
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Receive channel enable register partition B,
McBSP #1
Transmit channel enable register partition A,
McBSP #1
(1) Hardware reset; x denotes a “don’t care.”
Copyright © 2009, Texas Instruments Incorporated
Functional Overview
47
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
Table 3-27. Multichannel Serial Port #1 (continued)
Transmit channel enable register partition B,
0x2C11
0x2C12
0x2C13
XCERB_1[15:0]
McBSP #1
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
PCR1[15:0]
Pin control register, McBSP #1
Receive channel enable register partition C,
McBSP #1
RCERC_1[15:0]
Receive channel enable register partition D,
McBSP #1
0x2C14
0x2C15
0x2C16
0x2C17
0x2C18
0x2C19
0x2C1A
0x2C1B
0x2C1C
0x2C1D
0x2C1E
RCERD_1[15:0]
XCERC_1[15:0]
XCERD_1[15:0]
RCERE_1[15:0]
RCERF_1[15:0]
XCERE_1[15:0]
XCERF_1[15:0]
RCERG_1[15:0]
RCERH_1[15:0]
XCERG_1[15:0]
XCERH_1[15:0]
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Transmit channel enable register partition C,
McBSP #1
Transmit channel enable register partition D,
McBSP #1
Receive channel enable register partition E,
McBSP #1
Receive channel enable register partition F,
McBSP #1
Transmit channel enable register partition E,
McBSP #1
Transmit channel enable register partition F,
McBSP #1
Receive channel enable register partition G,
McBSP #1
Receive channel enable register partition H,
McBSP #1
Transmit channel enable register partition G,
McBSP #1
Transmit channel enable register partition H,
McBSP #1
Table 3-28. Multichannel Serial Port #2
PORT ADDRESS
(WORD)
REGISTER NAME
DESCRIPTION
RESET VALUE(1)
0x3000
0x3001
0x3002
0x3003
0x3004
0x3005
0x3006
0x3007
0x3008
0x3009
0x300A
0x300B
0x300C
0x300D
DRR2_2[15:0]
DRR1_2[15:0]
DXR2_2[15:0]
DXR1_2[15:0]
SPCR2_2[15:0]
SPCR1_2[15:0]
RCR2_2[15:0]
RCR1_2[15:0]
XCR2_2[15:0]
XCR1_2[15:0]
SRGR2_2[15:0]
SRGR1_2[15:0]
MCR2_2[15:0]
MCR1_2[15:0]
Data receive register 2, McBSP #2
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0020 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
0000 0000 0000 0000
Data receive register 1, McBSP #2
Data transmit register 2, McBSP #2
Data transmit register 1, McBSP #2
Serial port control register 2, McBSP #2
Serial port control register 1, McBSP #2
Receive control register 2, McBSP #2
Receive control register 1, McBSP #2
Transmit control register 2, McBSP #2
Transmit control register 1, McBSP #2
Sample rate generator register 2, McBSP #2
Sample rate generator register 1, McBSP #2
Multichannel control register 2, McBSP #2
Multichannel control register 1, McBSP #2
Receive channel enable register partition A,
McBSP #2
0x300E
0x300F
0x3010
RCERA_2[15:0]
RCERB_2[15:0]
XCERA_2[15:0]
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Receive channel enable register partition B,
McBSP #2
Transmit channel enable register partition A,
McBSP #2
(1) Hardware reset; x denotes a “don’t care.”
48 Functional Overview
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
Table 3-28. Multichannel Serial Port #2 (continued)
Transmit channel enable register partition B,
0x3011
XCERB_2[15:0]
McBSP #2
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0x3012
0x3013
PCR2[15:0]
Pin control register, McBSP #2
Receive channel enable register partition C,
McBSP #2
RCERC_2[15:0]
Receive channel enable register partition D,
McBSP #2
0x3014
0x3015
0x3016
0x3017
0x3018
0x3019
0x301A
0x301B
0x301C
0x301D
0x301E
RCERD_2[15:0]
XCERC_2[15:0]
XCERD_2[15:0]
RCERE_2[15:0]
RCERF_2[15:0]
XCERE_2[15:0]
XCERF_2[15:0]
RCERG_2[15:0]
RCERH_2[15:0]
XCERG_2[15:0]
XCERH_2[15:0]
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Transmit channel enable register partition C,
McBSP #2
Transmit channel enable register partition D,
McBSP #2
Receive channel enable register partition E,
McBSP #2
Receive channel enable register partition F,
McBSP #2
Transmit channel enable register partition E,
McBSP #2
Transmit channel enable register partition F,
McBSP #2
Receive channel enable register partition G,
McBSP #2
Receive channel enable register partition H,
McBSP #2
Transmit channel enable register partition G,
McBSP #2
Transmit channel enable register partition H,
McBSP #2
Table 3-29. GPIO
WORD ADDRESS
0x3400
REGISTER NAME
PIN
DESCRIPTION
General–purpose I/O direction register
General–purpose I/O data register
Address/GPIO enable register
Address/GPIO direction register
Address/GPIO data register
EHPI/GPIO enable register
RESET VALUE(1)
0000 0000 0000 0000
0000 0000 xxxx xxxx
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx xxxx xxxx
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 00xx xxxx
IODIR[7:0]
IODATA[7:0]
GPIO[7:0]
GPIO[7:0]
A[15:0]
0x3401
0x4400
AGPIOEN[15:0]
AGPIODIR[15:0]
AGPIODATA[15:0]
EHPIGPIOEN[5:0]
EHPIGPIODIR[5:0]
EHPIGPIODATA[5:0]
0x4401
A[15:0]
0x4402
A[15:0]
0x4403
GPIO[13:8]
GPIO[13:8]
GPIO[13:8]
0x4404
EHPI/GPIO direction register
EHPI/GPIO data register
0x4405
(1) Hardware reset; x denotes a “don’t care.”
Table 3-30. Device Revision ID
(1)
WORD ADDRESS
REGISTER NAME
Rev ID[4:1]
DESCRIPTION
VALUE
Rev. 1.0:
xxxx xxxx xxx0 001x
0x3803
Silicon revision identification
(1) x denotes a “don’t care.”
Table 3-31. I2C Module Registers(1)
WORD ADDRESS
REGISTER NAME
DESCRIPTION
RESET VALUE(2)
(1) I2C protocol compatible, no fail-safe buffer.
(2) Hardware reset; x denotes a “don’t care.”
Copyright © 2009, Texas Instruments Incorporated
Functional Overview
49
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
(1)
Table 3-31. I2C Module Registers
(continued)
0x3C00
0x3C01
0x3C02
0x3C03
0x3C04
0x3C05
0x3C06
0x3C07
0x3C08
0x3C09
0x3C0A
0x3C0B
0x3C0C
0x3C0D
0x3C0E
0x3C0F
-
I2COAR[9:0](3)
I2C own address register
I2C interrupt enable register
I2C status register
I2C clock divider low register
I2C clock divider high register
I2C data count
I2C data receive register
I2C slave address register
I2C data transmit register
I2C mode register
0000 0000 0000 0000
0000 0000 0000 0000
0000 0001 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0011 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
I2CIER
I2CSTR
I2CCLKL[15:0]
I2CCLKH[15:0]
I2CCNT[15:0]
I2CDRR[7:0]
I2CSAR[9:0]
I2CDXR[7:0]
I2CMDR[14:0]
I2CISRC
-
I2C interrupt source register
Reserved
I2CPSC
I2C prescaler register
Reserved
0000 0000 0000 0000
0000 0000 0000 0000
-
-
Reserved
I2C mode register 2
I2C receive shift register (not accessible to the CPU)
I2C transmit shift register (not accessible to the CPU)
I2CMDR2
I2CRSR
-
I2CXSR
(3) This register must be set by the user. The user may program the I2C’s own address to any value, as long as the value does not conflict
with the I2C addresses of other components connected to the I2C bus.
Table 3-32. Watchdog Timer Registers
(1)
WORD ADDRESS
0x4000
REGISTER NAME
WDTIM[15:0]
DESCRIPTION
WD timer counter register
RESET VALUE
1111 1111 1111 1111
1111 1111 1111 1111
0000 0011 1100 1111
0001 0000 0000 0000
0x4001
WDPRD[15:0]
WDTCR[13:0]
WDTCR2[15:0]
WD timer period register
WD timer control register
WD timer control register 2
0x4002
0x4003
(1) Hardware reset; x denotes a “don’t care.”
Table 3-33. USB Module Registers
WORD ADDRESS
DMA CONTEXTS
REGISTER NAME
DESCRIPTION
RESET VALUE(1) (2)
0x5800
0x5808
0x5810
0x5818
0x5820
0x5828
0x5830
0x5838
0x5840
0x5848
0x5850
0x5858
0x5860
Reserved
DMAC_O1
DMAC_O2
DMAC_O3
DMAC_O4
DMAC_O5
DMAC_O6
DMAC_O7
Reserved
DMAC_I1
DMAC_I2
DMAC_I3
DMAC_I4
Output endpoint 1 DMA context register
Output endpoint 2 DMA context register
Output endpoint 3 DMA context register
Output endpoint 4 DMA context register
Output endpoint 5 DMA context register
Output endpoint 6 DMA context register
Output endpoint 7 DMA context register
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Input endpoint 1 DMA context register
Input endpoint 2 DMA context register
Input endpoint 3 DMA context register
Input endpoint 4 DMA context register
Undefined
Undefined
Undefined
Undefined
(1) Hardware reset; x denotes a “don’t care.”
(2) The USB module must be brought out of reset by setting bit 2 of the USB Idle Control and Status Register before any USB module
register read or write attempt.
50
Functional Overview
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
Table 3-33. USB Module Registers (continued)
0x5868
DMAC_I5
Input endpoint 5 DMA context register
Input endpoint 6 DMA context register
Input endpoint 7 DMA context register
Undefined
Undefined
Undefined
0x5870
0x5878
DMAC_I6
DMAC_I7
DATA BUFFER
0x5880
Data Buffers
OEB_0
Contains X/Y data buffers for endpoints 1 – 7
Output endpoint 0 buffer
Undefined
Undefined
Undefined
Undefined
0x6680
0x66C0
IEB_0
Input endpoint 0 buffer
0x6700
SUP_0
Setup packet for endpoint 0
ENDPOINT DESCRIPTOR BLOCKS
0x6708
0x6710
0x6718
0x6720
0x6728
0x6730
0x6738
OEDB_1
OEDB_2
OEDB_3
OEDB_4
OEDB_5
OEDB_6
OEDB_7
Output endpoint 1 descriptor register block
Output endpoint 2 descriptor register block
Output endpoint 3 descriptor register block
Output endpoint 4 descriptor register block
Output endpoint 5 descriptor register block
Output endpoint 6 descriptor register block
Output endpoint 7 descriptor register block
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0x6740
0x6748
0x6750
0x6758
0x6760
0x6768
0x6770
0x6778
Reserved
IEDB_1
IEDB_2
IEDB_3
IEDB_4
IEDB_5
IEDB_6
IEDB_7
Input endpoint 1 descriptor register block
Input endpoint 2 descriptor register block
Input endpoint 3 descriptor register block
Input endpoint 4 descriptor register block
Input endpoint 5 descriptor register block
Input endpoint 6 descriptor register block
Input endpoint 7 descriptor register block
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
CONTROL AND STATUS REGISTERS
IEPCNF_0
0x6780
0x6781
0x6782
0x6783
0x6784 - 0x6790
0x6791
0x6792
0x6793
0x6794
0x6795
0x6796
0x6797
0x6798
0x6799
0x679A
0x679B
0x679C
0x67A0
0x67A1
0x67A2
0x67F8
0x67F9
0x67FA
Input endpoint 0 configuration
Input endpoint 0 byte count
Output endpoint 0 configuration
Output endpoint 0 byte count
xxxx xxxx 0000 0000
xxxx xxxx 1000 0000
xxxx xxxx 0000 0000
xxxx xxxx 0000 0000
IEPBCNT_0
OEPCNF_0
OEPBCNT_0
Reserved
GLOBCTL
VECINT
Global control register
xxxx xxxx 0000 0000
xxxx xxxx 0000 0000
xxxx xxxx 0000 0000
xxxx xxxx 0000 0000
xxxx xxxx 0000 0000
xxxx xxxx 0000 0000
xxxx xxxx 0000 0000
xxxx xxxx 0000 0000
xxxx xxxx 0000 0000
xxxx xxxx 0000 0000
xxxx xxxx 0000 0000
xxxx xxxx 0000 0000
xxxx xxxx xxxx x000
xxxx xxxx x000 0000
xxxx xxxx xxxx x001
xxxx xxxx 0000 0000
xxxx xxxx xxxx x000
xxxx xxxx 0000 0000
Vector interrupt register
IEPINT
Input endpoint interrupt register
Output endpoint interrupt register
Input DMA reload interrupt register
Output DMA reload interrupt register
Input DMA go interrupt register
Output DMA go interrupt register
Input DMA interrupt mask register
Output DMA interrupt mask register
Input EDB interrupt mask register
Output EDB interrupt mask register
Host DMA control register
OEPINT
IDMARINT
ODMARINT
IDMAGINT
ODMAGINT
IDMAMSK
ODMAMSK
IEDBMSK
OEDBMSK
HOSTCTL
HOSTEP
Host DMA endpoint register
Host DMA status
HOST
FNUML
Frame number low register
Frame number high
FNUMH
PSOFTMR
PreSOF interrupt timer register
Copyright © 2009, Texas Instruments Incorporated
Functional Overview
51
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
Table 3-33. USB Module Registers (continued)
0x67FC
0x67FD
0x67FE
0x67FF
0x7000
USBCTL
USB control register
xxxx xxxx 0101 0000
USBMSK
USBSTA
USB interrupt mask register
USB status register
xxxx xxxx 0000 0000
xxxx xxxx 0000 0000
xxxx xxxx x000 0000
xxxx xxxx xxxx x000
FUNADR
Function address register
USB idle control and status register
USBIDLECTL
Table 3-34. Analog-to-Digital Controller (ADC) Registers
(1)
WORD ADDRESS
0x6800
REGISTER NAME
ADCCTL[15:11]
ADCDATA[15:0]
ADCCLKDIV[15:0]
ADCCLKCTL[8:0]
DESCRIPTION
RESET VALUE
ADC control register
ADC data register
0111 0000 0000 0000
0111 0000 0000 0000
0000 0000 0000 1111
0000 0000 0000 0111
0x6801
0x6802
ADC function clock divider register
ADC clock control register
0x6803
(1) Hardware reset; x denotes a “don’t care.”
Table 3-35. External Bus Selection Register
WORD ADDRESS
REGISTER NAME
DESCRIPTION
RESET VALUE(1)
0x6C00
EBSR[15:0]
External bus selection register
0000 0000 0000 0011(2)
(1) Hardware reset; x denotes a “don’t care.”
(2) The reset value is 0000 0000 0000 0001 if GPIO0 = 1; the value is 0000 0000 0000 0011 if GPIO0 = 0.
3.12 Interrupts
Vector-relative locations and priorities for all internal and external interrupts are shown in Table 3-36.
Table 3-36. Interrupt Table
SOFTWARE
(TRAP)
RELATIVE
LOCATION
(1)
NAME
PRIORITY
FUNCTION
EQUIVALENT
(HEX BYTES)
RESET
NMI(2)
SINT0
SINT1
SINT24
SINT2
SINT16
SINT3
SINT4
SINT5
SINT17
SINT6
SINT7
SINT8
SINT18
SINT9
SINT10
SINT11
0
0
1
Reset (hardware and software)
Nonmaskable interrupt
Bus error interrupt
8
BERR
C0
10
80
18
20
28
88
30
38
40
90
48
50
58
2
INT0
3
External interrupt #0
INT1
4
External interrupt #1
INT2
5
External interrupt #2
TINT0
6
Timer #0 interrupt
RINT0
XINT0
7
McBSP #0 receive interrupt
McBSP #0 transmit interrupt
McBSP #1 receive interrupt
McBSP #1 transmit interrupt
USB interrupt
8
RINT1
XINT1
9
10
11
12
13
14
15
USB
DMAC0
DMAC1
DSPINT
INT3/WDTINT
DMA channel #0 interrupt
DMA channel #1 interrupt
Interrupt from host
External interrupt #3 or watchdog timer interrupt
(1) Absolute addresses of the interrupt vector locations are determined by the contents of the IVPD and IVPH registers. Interrupt vectors for
interrupts 0−15 and 24−31 are relative to IVPD. Interrupt vectors for interrupts 16−23 are relative to IVPH.
(2) The NMI pin is internally tied high. However, NMI interrupt vector can be used for SINT1 and Watchdog Timer Interrupt.
52
Functional Overview
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
Table 3-36. Interrupt Table (continued)
INT4/RTC(3)
SINT19
SINT12
SINT13
SINT20
SINT21
SINT14
SINT15
SINT22
SINT23
SINT25
SINT26
SINT27
SINT28
SINT29
SINT30
SINT31
98
60
68
A0
A8
70
78
B0
B8
C8
D0
D8
E0
E8
F0
F8
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
External interrupt #4 or RTC interrupt
RINT2
XINT2
DMAC2
DMAC3
DMAC4
DMAC5
TINT1
IIC
McBSP #2 receive interrupt
McBSP #2 transmit interrupt
DMA Channel #2 interrupt
DMA Channel #3 interrupt
DMA Channel #4 interrupt
DMA Channel #5 interrupt
Timer #1 interrupt
I2C interrupt
DLOG
RTOS
-
Data log interrupt
Real–time operating system interrupt
Software interrupt #27
Software interrupt #28
Software interrupt #29
Software interrupt #30
Software interrupt #31
-
-
-
-
(3) It is recommended that either the INT4 or RTC interrupt be used. If both INT4 and RTC interrupts are used, one interrupt event can
potentially hold off the other interrupt. For example, if INT4 is asserted first and held low, the RTC interrupt will not be recognized until
the INT4 pin is back to high-logic state again. The INT4 pin must be pulled high if only the RTC interrupt is used.
3.12.1 IFR and IER Registers
The IFR0 (Interrupt Flag Register 0) and IER0 (Interrupt Enable Register 0) bit layouts are shown in
Figure 3-19.
15
14
13
12
11
10
9
8
INT3/
DMAC5
R/W
DMAC4
R/W
XINT2
R/W
RINT2
R/W
DSPINT
R/W
DMAC1
R/W
USB
R/W
WDTINT
R/W
7
6
5
4
3
2
1
0
XINT1
R/W
RINT1
R/W
RINT0
R/W
TINT0
R/W
INT2
R/W
INT0
R/W
Reserved
LEGEND: R = Read, W = Write, n = value after reset
Figure 3-19. IFR0 and IER0 Bit Locations
Table 3-37. IFR0 and IER0 Register Bit Fields
BIT
FUNCTION
NUMBER
NAME
DMAC5
DMAC4
XINT2
15
14
13
12
DMA channel 5 interrupt flag/mask bit
DMA channel 4 interrupt flag/mask bit
This bit is used as the McBSP2 transmit interrupt flag/mask bit.
McBSP2 receive interrupt flag/mask bit.
RINT2
This bit is used as either the external user interrupt 3 flag/mask bit, or the watchdog timer interrupt
flag/mask bit.(1)
11
INT3/WDTINT
10
9
DSPINT
DMAC1
USB
HPI host–to–DSP interrupt flag/mask.
DMA channel 1 interrupt flag/mask bit
USB interrupt flag/mask bit.
8
(1) It is possible to have active interrupts simultaneously from both the external INT3 source and the watchdog timer. When an interrupt is
detected in this bit, the watchdog timer status register should be polled to determine if the watchdog timer is the interrupt source.
Copyright © 2009, Texas Instruments Incorporated
Functional Overview
53
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
Table 3-37. IFR0 and IER0 Register Bit Fields (continued)
7
6
XINT1
RINT1
This bit is used as the McBSP1 transmit interrupt flag/mask bit.
McBSP1 receive interrupt flag/mask bit.
McBSP0 receive interrupt flag bit
5
RINT0
TINT0
INT2
INT0
-
4
Timer 0 interrupt flag bit
3
External interrupt 2 flag bit
2
External interrupt 0 flag bit
1-0
Reserved for future expansion. These bits should always be written with 0.
The IFR1 (Interrupt Flag Register 1) and IER1 (Interrupt Enable Register 1) bit layouts are shown in
Figure 3-20.
NOTE
It is possible to have active interrupts simultaneously from both the external interrupt 4
(INT4) and the real-time clock (RTC). When an interrupt is detected in this bit, the
real-time clock status register should be polled to determine if the real-time clock is the
source of the interrupt.
Reserved
RTOS
R/W-0
DLOG
R/W-0
BERR
R/W-0
*
R/W-00000
7
6
5
4
3
2
1
0
I2C
TINT1
R/W-0
DMAC3
R/W-0
DMAC2
R/W-0
INT4/RTC
R/W-0
DMAC0
R/W-0
XINT0
R/W-0
INT1
R/W-0
R/W-0
LEGEND: R = Read, W = Write, n = value after reset
*
Always write zeros.
Figure 3-20. IFR1 and IER1 Bit Locations
Table 3-38. IFR1 and IER1 Register Bit Fields
BIT
FUNCTION
NUMBER
NAME
-
15-11
Reserved for future expansion. These bits should always be written with 0.
Real–time operating system interrupt flag/mask bit
Data log interrupt flag/mask bit
10
9
RTOS
DLOG
BERR
I2C
8
Bus error interrupt flag/mask bit
I2C interrupt flag/mask bit
7
6
TINT1
DMAC3
DMAC2
Timer 1 interrupt flag/mask bit
5
DMA channel 3 interrupt flag/mask bit
DMA channel 2 interrupt flag/mask bit
4
This bit can be used as either the external user interrupt 4 flag/mask bit, or the real–time clock
interrupt flag/mask bit.
3
INT4/RTC
2
1
0
DMAC0
XINT0
INT1
DMA channel 0 interrupt flag/mask bit
McBSP transmit 0 interrupt flag/mask bit
External user interrupt 1 flag/mask bit
54
Functional Overview
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
3.12.2 Interrupt Timing
The external interrupts (INT[4:0]) are synchronized to the CPU by way of a two-flip-flop synchronizer. The
interrupt inputs are sampled on falling edges of the CPU clock. A sequence of 1-1-0-0-0 on consecutive
cycles on the interrupt pin is required for an interrupt to be detected. Therefore, the minimum low pulse
duration on the external interrupts on the 5507 is three CPU clock periods.
3.12.3 Waking Up From IDLE Condition
One of the following four events can wake up the CPU from IDLE:
•
•
•
•
Hardware Reset
External Interrupt
RTC Interrupt
USB Event (Reset or Resume)
3.12.3.1 Waking Up From IDLE With Oscillator Disabled
With an external interrupt, a RTC interrupt, or an USB resume/reset, the clock generation circuit wakes up
the oscillator and enables the USB PLL to determine the oscillator stable time. In the case of the interrupt
being disabled by clearing the associated bit in the Interrupt Enable Register (IERx), the CPU is not
“woken up”. If the interrupt due to the wake-up event is enabled, the interrupt is sent to the CPU only after
the oscillator is stabilized and the USB PLL is locked. If the external interrupt serves as the wake-up
event, the interrupt line must stay low for a minimum of 3 CPU cycles after the oscillator is stabilized to
wake up the CPU. Otherwise, only the clock domain will wake up and another external interrupt will be
needed to wake up the CPU.
Once out of IDLE, any system not using the USB should put the USB module in idle mode to reduce
power consumption.
For more details on the SM320VC5507 oscillator-disable process, see the Disabling the Internal Oscillator
on the TMS320VC5507/5509/5509A DSP application report (literature number SPRA078).
3.12.4 Idling Clock Domain When External Parallel Bus Operating in EHPI Mode
The clock domain cannot be idled when the External Parallel Bus is operating in EHPI mode to ensure
host access to the DSP memory. To work around this restriction, use the HIDL bit of the External Bus
Selection Register (EBSR) with the CLKGENI bit of the Idle Control Register (ICR) to idle the clock
domain.
Copyright © 2009, Texas Instruments Incorporated
Functional Overview
55
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
4
Support
4.1 Notices Concerning JTAG (IEEE 1149.1) Boundary Scan Test Capability
4.1.1 Initialization Requirements for Boundary Scan Test
The SM320VC5507 uses the JTAG port for boundary scan tests, emulation capability and factory test
purposes. To use boundary scan test, the EMU0 and EMU1/OFF pins must be held LOW through a rising
edge of the TRST signal prior to the first scan. This operation selects the appropriate TAP control for
boundary scan. If at any time during a boundary scan test a rising edge of TRST occurs when EMU0 or
EMU1/OFF are not low, a factory test mode may be selected preventing boundary scan test from being
completed. For this reason, it is recommended that EMU0 and EMU1/OFF be pulled or driven low at all
times during boundary scan test.
4.1.2 Boundary Scan Description Language (BSDL) Model
BSDL models are available on the web in the TMS320VC5507 product folder under the “simulation
models” section.
4.2 Documentation Support
Extensive documentation supports all TMS320™ DSP family of devices from product announcement
through applications development. The following types of documentation are available to support the
design and use of the TMS320C5000™ platform of DSPs:
•
•
•
•
•
TMS320C55x ™ DSP Functional Overview (literature number SPRU312)
Device-specific data sheets and data manuals
Complete user’s guides
Development support tools
Hardware and software application reports
TMS320C55x reference documentation includes, but is not limited to, the following:
•
•
•
•
•
•
•
•
•
TMS320C55x DSP CPU Reference Guide (literature number SPRU371)
TMS320C55x DSP Mnemonic Instruction Set Reference Guide (literature number SPRU374)
TMS320C55x DSP Algebraic Instruction Set Reference Guide (literature number SPRU375)
TMS320C55x DSP Programmer’s Guide (literature number SPRU376)
TMS320C55x DSP Peripherals Overview Reference Guide (literature number SPRU317)
TMS320C55x Optimizing C/C++ Compiler User’s Guide (literature number SPRU281)
TMS320C55x Assembly Language Tools User’s Guide (literature number SPRU280)
TMS320C55x DSP Library Programmer’s Reference (literature number SPRU422)
TMS320VC5507/5509 DSP Universal Serial Bus (USB) Module Reference Guide (literature number
SPRU596)
•
•
Using the USB APLL on the TMS320VC5507/5509A Application Report (literature number SPRA997)
Using the TMS320VC5503/VC5507/VC5509/VC5509A Bootloader Application Report (literature
number SPRA375)
•
Disabling the Internal Oscillator on the TMS320VC5507/5509/5509A DSP application report (literature
number SPRA078)
•
Using the TMS320C5509/C5509A USB Bootloader Application Report (literature number SPRA840)
The reference guides describe in detail the TMS320C55x™ DSP products currently available and the
hardware and software applications, including algorithms, for fixed-point TMS320™ DSP family of devices.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320™ DSP newsletter, Details on Signal Processing, is
published quarterly and distributed to update TMS320™ DSP customers on product information.
56
Support
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com
uniform resource locator (URL).
4.3 TMS320VC5507 Device Nomenclature
TMS 320 VC 5507 GHH
PREFIX
TMX = Experimental device
TMP = Prototype device
TMS = Qualified device
SMJ = MIL-STD-883C
SM High Rel (non-883C)
†‡§
PACKAGE TYPE
=
GHH
ZHH
=
=
179-terminal plastic BGA
179-terminal plastic BGA with Pb-free
soldered balls
DEVICE FAMILY
320 = TMS320 family
PGE
=
144-pin plastic LQFP
DEVICE
55x DSP: 5507
TECHNOLOGY
VC
= Dual-Supply CMOS
†
‡
§
BGA
LQFP = Low-Profile Quad Flatpack
The ZHH mechanical package designator representsthe version of the GHH with PbFree soldered balls. The ZHH package
).
=
Ball Grid Array
devices are supported in the same speed grades as the GHH package devices (available upon request
For actual device part numbers (P/Ns) and ordering information, see the Mechanical Data section of this document or the
TI website (www.ti.com).
Figure 4-1. Device Nomenclature for the TMS320VC5507
Copyright © 2009, Texas Instruments Incorporated
Support
57
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
5
Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the
SM320VC5507 DSP.
All electrical and switching characteristics in this data manual are valid over the recommended operating
conditions unless otherwise specified.
The list of absolute maximum ratings are specified over operating case temperature. Stresses beyond those
listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under
Section 5.2 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability. All voltage values are with respect to VSS. Figure 5-1 provides the test load circuit values for a
3.3-V I/O.
5.1 ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
V
DVDD
CVDD
VI
Supply voltage I/O range
Supply voltage core range
Input voltage range
–0.3 to 4.0
–0.3 to 2.0
–0.3 to 4.5
–0.3 to 4.5
–55 to 85
–55 to 150
V
V
VO
Output voltage range
V
TC
Operating case temperature range
Storage temperature range
°C
°C
Tstg
58
Electrical Specifications
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
5.2 RECOMMENDED OPERATING CONDITIONS
5.2.1 Recommended Operating Conditions for CVDD = 1.2 V (108 MHz)
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX UNIT
CORE
CVDD
Device supply voltage
1.14
1.2
1.26
V
PERIPHERALS
RCVDD
RTC module supply voltage, core
1.14
1.14
1.14
3
1.2
1.2
1.2
3.3
1.26
1.26
1.26
3.6
V
V
V
V
RDVDD
RTC module supply voltage, I/O (RTCINX1 and RTCINX2)
USBPLL supply voltage(1)
USBPLLVDD
USBVDD
USB module supply voltage, I/O (DP, DN, and PU)
Device supply voltage, I/O (except DP, DN, PU, SDA,
SCL)(2)
DVDD
2.7
3.3
3.6
V
ADVDD
AVDD
A/D module digital supply voltage
A/D module analog supply voltage
2.7
2.7
3.3
3.3
3.6
3.6
V
V
GROUNDS
VSS
Supply voltage, GND, I/O, and core
Supply voltage, GND, A/D module, digital
Supply voltage, GND, A/D module, analog
Supply voltage, GND, USBPLL
DN and DP(3)
0
0
0
0
V
V
V
V
ADVSS
AVSS
USBPLLVSS
2
SDA & SCL: VDD related
0.7 x
DVDD
DVDD(max)
+0.5
input levels(2)
VIH
High–level input voltage, I/O
V
V
All other inputs
(including hysteresis
inputs)
DN and DP(3)
2
DVDD + 0.3
0.8
SDA & SCL: VDD related
-0.5
-0.3
0.3 x DVDD
input levels(2)
VIL
Low–level input voltage, I/O
All other inputs
(including hysteresis
inputs)
0.8
0.1 x
DVDD
Vhys
Hysteresis level
Inputs with hysteresis only
V
DN and DP(3)
(VOH = 2.45 V)
-17
-4
IOH
High–level output current
mA
All other outputs
DN and DP(3)
(VOL = 0.36 V)
SDA and SCL(2)
17
IOL
Low–level output current
mA
°C
3
4
All other outputs
TC
Operating case temperature
-55
85
(1) USB PLL is susceptible to power supply ripple. The maximum allowable supply ripple is 1% for 1 Hz to 5 kHz; 1.5% for 5 kHz to 10
MHz; 3% for 10 MHz to 100 MHz, and less than 5% for 100 MHz or greater.
(2) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down. Due to the fact that different voltage devices can be connected to the I2C bus, the level of logic 0 (low) and logic 1 (high) are not
fixed and depends on the associated VDD
.
(3) USB I/O pins DP and DN can tolerate a short circuit at D+ and D− to 0 V or 5 V, as long as the recommended series resistors (see
Figure 5-40 ) are connected between the D+ and DP (package), and the D− and DN (package). Do not apply a short circuit to the USB
I/O pins DP and DN in absence of the series resistors.
Copyright © 2009, Texas Instruments Incorporated
Electrical Specifications
59
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
MAX UNIT
5.2.2 Recommended Operating Conditions for CVDD = 1.35 V (144 MHz)
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
CORE
CVDD
Device supply voltage
1.28
1.35
1.42
V
PERIPHERALS
RCVDD
RTC module supply voltage, core
1.28
1.28
1.28
3
1.35
1.35
1.35
3.3
1.42
1.42
1.42
3.6
V
V
V
V
RDVDD
RTC module supply voltage, I/O (RTCINX1 and RTCINX2)
USBPLL supply voltage(1)
USBPLLVDD
USBVDD
USB module supply voltage, I/O (DP, DN, and PU)
Device supply voltage, I/O (except DP, DN, PU, SDA,
SCL)(2)
DVDD
2.7
3.3
3.6
V
ADVDD
AVDD
A/D module digital supply voltage
A/D module analog supply voltage
2.7
2.7
3.3
3.3
3.6
3.6
V
V
GROUNDS
VSS
Supply voltage, GND, I/O, and core
Supply voltage, GND, A/D module, digital
Supply voltage, GND, A/D module, analog
Supply voltage, GND, USBPLL
DN and DP(3)
0
0
0
0
V
V
V
V
ADVSS
AVSS
USBPLLVSS
2
SDA & SCL: VDD related
0.7 x
DVDD
DVDD(max)
+0.5
input levels(2)
VIH
High–level input voltage, I/O
V
V
All other inputs
(including hysteresis
inputs)
DN and DP(3)
2
DVDD + 0.3
0.8
SDA & SCL: VDD related
-0.5
-0.3
0.3 x DVDD
input levels(2)
VIL
Low–level input voltage, I/O
All other inputs
(including hysteresis
inputs)
0.8
0.1 x
DVDD
Vhys
Hysteresis level
Inputs with hysteresis only
V
DN and DP(3)
(VOH = 2.45 V)
-17
-4
IOH
High–level output current
mA
All other outputs
DN and DP(3)
(VOL = 0.36 V)
SDA and SCL(2)
17
IOL
Low–level output current
mA
°C
3
4
All other outputs
TC
Operating case temperature
-55
85
(1) USB PLL is susceptible to power supply ripple. The maximum allowable supply ripple is 1% for 1 Hz to 5 kHz; 1.5% for 5 kHz to 10
MHz; 3% for 10 MHz to 100 MHz, and less than 5% for 100 MHz or greater.
(2) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down. Due to the fact that different voltage devices can be connected to the I2C bus, the level of logic 0 (low) and logic 1 (high) are not
fixed and depends on the associated VDD
.
(3) USB I/O pins DP and DN can tolerate a short circuit at D+ and D− to 0 V or 5 V, as long as the recommended series resistors (see
Figure 5-40 ) are connected between the D+ and DP (package), and the D− and DN (package). Do not apply a short circuit to the USB
I/O pins DP and DN in absence of the series resistors.
60
Electrical Specifications
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
5.2.3 Recommended Operating Conditions for CVDD = 1.6 V (200 MHz)
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX UNIT
CORE
CVDD
Device supply voltage
1.55
1.6
1.65
V
PERIPHERALS
RCVDD
RTC module supply voltage, core
1.55
1.55
1.55
3
1.6
1.6
1.6
3.3
1.65
1.65
1.65
3.6
V
V
V
V
RDVDD
RTC module supply voltage, I/O (RTCINX1 and RTCINX2)
USBPLL supply voltage(1)
USBPLLVDD
USBVDD
USB module supply voltage, I/O (DP, DN, and PU)
Device supply voltage, I/O (except DP, DN, PU, SDA,
SCL)(2)
DVDD
2.7
3.3
3.6
V
ADVDD
AVDD
A/D module digital supply voltage
A/D module analog supply voltage
2.7
2.7
3.3
3.3
3.6
3.6
V
V
GROUNDS
VSS
Supply voltage, GND, I/O, and core
Supply voltage, GND, A/D module, digital
Supply voltage, GND, A/D module, analog
Supply voltage, GND, USBPLL
DN and DP(3)
0
0
0
0
V
V
V
V
ADVSS
AVSS
USBPLLVSS
2
SDA & SCL: VDD related
0.7 x
DVDD
DVDD(max)
+0.5
input levels(2)
VIH
High–level input voltage, I/O
V
V
All other inputs
(including hysteresis
inputs)
DN and DP(3)
2
DVDD + 0.3
0.8
SDA & SCL: VDD related
-0.5
-0.3
0.3 x DVDD
input levels(2)
VIL
Low–level input voltage, I/O
All other inputs
(including hysteresis
inputs)
0.8
0.1 x
DVDD
Vhys
Hysteresis level
Inputs with hysteresis only
V
DN and DP(3)
(VOH = 2.45 V)
-17
-4
IOH
High–level output current
mA
All other outputs
DN and DP(3)
(VOL = 0.36 V)
SDA and SCL(2)
17
IOL
Low–level output current
mA
°C
3
4
All other outputs
TC
Operating case temperature
-55
85
(1) USB PLL is susceptible to power supply ripple. The maximum allowable supply ripple is 1% for 1 Hz to 5 kHz; 1.5% for 5 kHz to 10
MHz; 3% for 10 MHz to 100 MHz, and less than 5% for 100 MHz or greater.
(2) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down. Due to the fact that different voltage devices can be connected to the I2C bus, the level of logic 0 (low) and logic 1 (high) are not
fixed and depends on the associated VDD
.
(3) USB I/O pins DP and DN can tolerate a short circuit at D+ and D− to 0 V or 5 V, as long as the recommended series resistors (see
Figure 5-40 ) are connected between the D+ and DP (package), and the D− and DN (package). Do not apply a short circuit to the USB
I/O pins DP and DN in absence of the series resistors.
Copyright © 2009, Texas Instruments Incorporated
Electrical Specifications
61
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
5.3 ELECTRICAL CHARACTERISTICS
5.3.1 Electrical Characteristics Over Recommended Operating Case Temperature Range
for CVDD = 1.2 V (108 MHz) (Unless Otherwise Noted)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
USBVDD = 3.0 V-3.6 V,
IOH = -300 μA
DN and DP(1)
PU
2.8
USBVDD
High–level output
voltage
USBVDD = 3.0 V-3.6 V,
IOH = -300 μA
0.9 x
USBVDD
VOH
USBVDD
V
DVDD = 2.7 V-3.6 V,
IOH = MAX
0.75 x
DVDD
All other outputs
SDA & SCL(2)
Low–level output voltage DN and DP(1)
At 3 mA sink current
IOL = 3.0 mA
0
0.4
0.3
0.4
VOL
V
All other outputs
IOL = MAX
Output–only or
I/O pins with bus
keepers (enabled)
DVDD = MAX,
VO = VSS to DVDD
–300
–5
300
5
Input current for outputs
in high–impedance
IIZ
μA
All other
output–only or I/O
pins
DVDD = MAX,
VO = VSS to DVDD
Input pins with
internal pulldown
(enabled)
DVDD = MAX,
VI = VSS to DVDD
30
300
–30
Input pins with
internal pullup
(enabled)
DVDD = MAX,
VI = VSS to DVDD
–300
II
Input current
μA
DVDD = MAX,
VI = VSS to DVDD
X2/CLKIN
–50
–5
50
5
All other input–only DVDD = MAX,
pins
VI = VSS to DVDD
CVDD = 1.2 V,
CPU clock = 108 MHz,
TC = 25°C
CVDD Supply current, CPU + internal memory
access(3)
IDDC
IDDP
IDDC
IDDP
0.45
5.5
100
10
mA/MHz
mA
DVDD = 3.3 V,
CPU clock = 108 MHz,
TC = 25°C
DVDD supply current, pins active(4)
Oscillator disabled. CVDD = 1.2 V,
CVDD supply current,
standby(5)
All domains in
low–power state
TC = 25°C
(Nominal process)
μA
Oscillator disabled. DVDD = 3.3 V,
DVDD supply current,
standby
All domains in
low–power state.
No I/O activity,
TC = 25°C
μA
Ci
Input capacitance
Output capacitance
3
3
pF
pF
Co
(1) USB I/O pins DP and DN can tolerate a short circuit at D+ and D− to 0 V or 5 V, as long as the recommended series resistors (see
Figure 5-40 ) are connected between the D+ and DP (package), and the D− and DN (package). Do not apply a short circuit to the USB
I/O pins DP and DN in absence of the series resistors.
(2) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(3) CPU executing 75% Dual MAC + 25% ADD with moderate data bus activity (table of sine values). CPU and CLKGEN (DPLL) domain
are active. All other domains are idled.
(4) One word of a table of a 16-bit sine value is written to the EMIF every 250 ns (64 Mbps). Each EMIF output pin is connected to a 10-pF
load.
(5) In CLKGEN domain idle mode, X2/CLKIN becomes output and is driven low to stop external crystals (if used) from oscillating. Standby
current will be higher if an external clock source tries to drive the X2/CLKIN pin during this time.
62
Electrical Specifications
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
5.3.2 Electrical Characteristics Over Recommended Operating Case Temperature Range
for CVDD = 1.35 V (144 MHz) (Unless Otherwise Noted)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
USBVDD = 3.0 V-3.6 V,
IOH = -300 μA
DN and DP(1)
High–level output voltage PU
All other outputs
2.8
USBVDD
USBVDD = 3.0 V-3.6 V,
IOH = -300 μA
0.9 x
USBVDD
VOH
USBVDD
V
DVDD = 2.7 V-3.6 V,
IOH = MAX
0.75 x DVDD
0
SDA & SCL(2)
Low–level output voltage DN and DP(1)
All other outputs
At 3 mA sink current
IOL = 3.0 mA
0.4
0.3
0.4
VOL
V
IOL = MAX
Output–only or
I/O pins with bus
keepers (enabled)
DVDD = MAX,
VO = VSS to DVDD
–300
–5
300
5
Input current for outputs
in high–impedance
IIZ
μA
All other
output–only or I/O
pins
DVDD = MAX,
VO = VSS to DVDD
Input pins with
internal pulldown
(enabled)
DVDD = MAX,
VI = VSS to DVDD
30
300
–30
Input pins with
internal pullup
(enabled)
DVDD = MAX,
VI = VSS to DVDD
–300
II
Input current
μA
DVDD = MAX,
VI = VSS to DVDD
X2/CLKIN
–50
–5
50
5
All other
input–only pins
DVDD = MAX,
VI = VSS to DVDD
CVDD = 1.35 V,
CPU clock = 144 MHz,
TC = 25°C
CVDD Supply current, CPU + internal
memory access(3)
IDDC
0.51
5.5
mA/MHz
mA
DVDD = 3.3 V,
CPU clock = 144 MHz,
TC = 25°C
IDDP
DVDD supply current, pins active(4)
Oscillator
CVDD = 1.35 V,
TC = 25°C
(Nominal process)
CVDD supply current,
disabled. All
domains in
IDDC
125
10
μA
μA
standby(5)
low–power state
Oscillator
DVDD = 3.3 V,
No I/O activity,
TC = 25°C
DVDD supply current,
standby
disabled. All
domains in
IDDP
low–power state.
Ci
Input capacitance
Output capacitance
3
3
pF
pF
Co
(1) USB I/O pins DP and DN can tolerate a short circuit at D+ and D− to 0 V or 5 V, as long as the recommended series resistors (see
Figure 5-40 ) are connected between the D+ and DP (package), and the D− and DN (package). Do not apply a short circuit to the USB
I/O pins DP and DN in absence of the series resistors.
(2) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(3) CPU executing 75% Dual MAC + 25% ADD with moderate data bus activity (table of sine values). CPU and CLKGEN (DPLL) domain
are active. All other domains are idled.
(4) One word of a table of a 16-bit sine value is written to the EMIF every 250 ns (64 Mbps). Each EMIF output pin is connected to a 10-pF
load.
(5) In CLKGEN domain idle mode, X2/CLKIN becomes output and is driven low to stop external crystals (if used) from oscillating. Standby
current will be higher if an external clock source tries to drive the X2/CLKIN pin during this time.
Copyright © 2009, Texas Instruments Incorporated
Electrical Specifications
63
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
5.3.3 Electrical Characteristics Over Recommended Operating Case Temperature Range
for CVDD = 1.6 V (200 MHz) (Unless Otherwise Noted)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
USBVDD = 3.0 V-3.6 V,
IOH = -300 μA
DN and DP(1)
High–level output voltage PU
All other outputs
2.8
USBVDD
USBVDD = 3.0 V-3.6 V,
IOH = -300 μA
0.9 x
USBVDD
VOH
USBVDD
V
DVDD = 2.7 V-3.6 V,
IOH = MAX
0.75 x DVDD
0
SDA & SCL(2)
Low–level output voltage DN and DP(1)
All other outputs
At 3 mA sink current
IOL = 3.0 mA
0.4
0.3
0.4
VOL
V
IOL = MAX
Output–only or
I/O pins with bus
keepers (enabled)
DVDD = MAX,
VO = VSS to DVDD
–300
–5
300
5
Input current for outputs
in high–impedance
IIZ
μA
All other
output–only or I/O
pins
DVDD = MAX,
VO = VSS to DVDD
Input pins with
internal pulldown
(enabled)
DVDD = MAX,
VI = VSS to DVDD
30
300
–30
Input pins with
internal pullup
(enabled)
DVDD = MAX,
VI = VSS to DVDD
–300
II
Input current
μA
DVDD = MAX,
VI = VSS to DVDD
X2/CLKIN
–50
–5
50
5
All other
input–only pins
DVDD = MAX,
VI = VSS to DVDD
CVDD = 1.6 V,
CPU clock = 200 MHz,
TC = 25°C
CVDD Supply current, CPU + internal memory
access(3)
IDDC
0.6
5.5
mA/MHz
mA
DVDD = 3.3 V,
CPU clock = 200 MHz,
TC = 25°C
IDDP
DVDD supply current, pins active(4)
Oscillator
CVDD = 1.6 V,
TC = 25°C
(Nominal process)
CVDD supply current,
disabled. All
domains in
IDDC
150
10
μA
μA
standby(5)
low–power state
Oscillator
DVDD = 3.3 V,
No I/O activity,
TC = 25°C
DVDD supply current,
standby
disabled. All
domains in
IDDP
low–power state.
Ci
Input capacitance
Output capacitance
3
3
pF
pF
Co
(1) USB I/O pins DP and DN can tolerate a short circuit at D+ and D− to 0 V or 5 V, as long as the recommended series resistors (see
Figure 5-40 ) are connected between the D+ and DP (package), and the D− and DN (package). Do not apply a short circuit to the USB
I/O pins DP and DN in absence of the series resistors.
(2) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(3) CPU executing 75% Dual MAC + 25% ADD with moderate data bus activity (table of sine values). CPU and CLKGEN (DPLL) domain
are active. All other domains are idled.
(4) One word of a table of a 16-bit sine value is written to the EMIF every 250 ns (64 Mbps). Each EMIF output pin is connected to a 10-pF
load.
(5) In CLKGEN domain idle mode, X2/CLKIN becomes output and is driven low to stop external crystals (if used) from oscillating. Standby
current will be higher if an external clock source tries to drive the X2/CLKIN pin during this time.
64
Electrical Specifications
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
Tester Pin Electronics
Data Manual Timing Reference Point
3.5 nH
W
42
Output
Under
Test
Transmission Line
W
Z0 = 50
(see NOTE)
Device Pin
(see NOTE)
4.0 pF
1.85 pF
Figure 5-1. 3.3-V Test Load Circuit
5.4 ESD Performance
ESD stress levels were performed in compliance with the following JEDEC standards with the results indicated
below:
•
•
Charged Device Model (CDM), based on JEDEC Specification JESD22-C101, passed at ±500 V
Human Body Model (HBM), based on JEDEC Specification JESD22-A114, passed at ±1500 V
NOTE
According to industry research publications, ESD-CDM testing results show better correlation to
manufacturing line and field failure rates than ESD-HBM testing. 500-V CDM is commonly
considered as a safe passing level.
5.5 Timing Parameter Symbology
Timing parameter symbols used in the timing requirements and switching characteristics tables are created in
accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related
terminology have been abbreviated as follows:
Lowercase Subscripts and Their Meanings
Letters and Symbols and Their Meanings
a
c
access time
H
L
High
cycle time (period)
delay time
Low
d
V
Z
Valid
dis
en
f
disable time
High-impedance
enable time
fall time
h
hold time
r
rise time
su
t
setup time
transition time
valid time
v
w
x
pulse duration (width)
unknown, changing or don't care level
Copyright © 2009, Texas Instruments Incorporated
Electrical Specifications
65
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
5.6 Clock Options
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two or four or
multiplied by one of several values to generate the internal machine cycle.
5.6.1 Internal System Oscillator With External Crystal
The internal oscillator is always enabled following a device reset. The oscillator requires an external crystal
connected across the X1 and X2/CLKIN pins. If the internal oscillator is not used, an external clock source must
be applied to the X2/CLKIN pin and the X1 pin should be left unconnected. Since the internal oscillator can be
used as a clock source to the PLLs, the crystal oscillation frequency can be multiplied to generate the CPU clock
and USB clock, if desired.
The crystal should be in fundamental-mode operation, and parallel resonant, with a maximum effective series
resistance (ESR) specified in Table 5-1. The connection of the required circuit is shown in Figure 5-2. Under
some conditions, all the components shown are not required. The capacitors, C1 and C2, should be chosen such
that Equation 2 below is satisfied. CL in Equation 2 is the load specified for the crystal that is also specified in
Table 5-1.
C1C2
CL =
(C1 + C2)
(2)
X2/CLKIN
X1
R
S
Crystal
C1
C2
Figure 5-2. Internal System Oscillator With External Crystal
Table 5-1. Recommended Crystal Parameters
FREQUENCY RANGE
(MHz)
MAX ESR (Ω)
TYP CLOAD (pF)
MAX CSHUNT (pF)
RS (Ω)
20-15
15-12
12-10
10-8
8-6
20
30
40
60
80
80
10
16
16
18
18
18
7
7
7
7
7
7
0
0
100
470
1.5k
2.2k
6-5
Although the recommended ESR presented in Table 5-1 is maximum, theoretically a crystal with a lower
maximum ESR might seem to meet the requirement. It is recommended that crystals which meet the maximum
ESR specification in Table 5-1 are used.
5.6.2 Layout Considerations
Since parasitic capacitance, inductance and resistance can be significant in any circuit, good PC board layout
66
Electrical Specifications
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
practices should always be observed when planning trace routing to the discrete components used in the
oscillator circuit. Specifically, the crystal and the associated discrete components should be located as close to
the DSP as physically possible. Also, X1 and X2/CLKIN traces should be separated as soon as possible after
routing away from the DSP to minimize parasitic capacitance between them, and a ground trace should be run
between these two signal lines. This also helps to minimize stray capacitance between these two signals.
5.6.3 Clock Generation in Bypass Mode (DPLL Disabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of one, two, or four
to generate the internal CPU clock cycle. The divide factor (D) is set in the BYPASS_DIV field of the clock mode
register. The contents of this field only affect clock generation while the device is in bypass mode. In this mode,
the digital phase-locked loop (DPLL) clock synthesis is disabled.
Table 5-2 and Table 5-3 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 5-3).
Table 5-2. CLKIN Timing Requirements
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
NO.
UNIT
MIN
MAX
400(1)
4
MIN
MAX
C1
C2
tc(CI)
Cycle time, X2/CLKIN
Fall time, X2/CLKIN
20
20 400(1)
ns
ns
ns
ns
ns
tf(CI)
4
C3
tr(CI)
Rise time, X2/CLKIN
4
4
C10
C11
tw(CIL)
tw(CIH)
Pulse duration, CLKIN low
Pulse duration, CLKIN high
6
6
6
6
(1) This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. If an external crystal is used, the X2/CLKIN
cycle time is limited by the crystal frequency range listed in Table 5-1 .
Table 5-3. CLKOUT Switching Characteristics
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
TYP
NO.
UNIT
MIN
MAX
MIN
20(1)
TYP
MAX
D x tc(CI)
(2)
C4
C5
tc(CO)
Cycle time, CLKOUT
20(1) D x tc(CI)
1600(3)
1600(3)
ns
ns
(2)
Delay time, X2/CLKIN high to
CLKOUT high/low
td(CI–CO)
5
15
25
5
15
25
C6
C7
C8
C9
tf(CO)
Fall time, CLKOUT
1
1
1
1
ns
ns
ns
ns
tr(CO)
Rise time, CLKOUT
tw(COL)
tw(COH)
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
H - 1
H - 1
H + 1
H + 1
H - 1
H - 1
H + 1
H + 1
(1) It is recommended that the DPLL synthesized clocking option be used to obtain maximum operating frequency.
(2) D = 1/(PLL Bypass Divider)
(3) This device utilizes a fully static design and therefore can operate with tc(CO) approaching ∞. If an external crystal is used, the X2/CLKIN
cycle time is limited by the crystal frequency range listed in Table 5-1 .
Copyright © 2009, Texas Instruments Incorporated
Electrical Specifications
67
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
C2
C1
C11
C3
C10
X2/CLKIN
C4
C9
C7
CLKOUT
C5
C6
C8
NOTE A: The relationship of X2/CLKIN to CLKOUT depends on the PLL bypass divide factor chosen for the CLKMD register. The wavefo rm
relationship shown in Figure 53 is intended to illustrate the timing parameters based on CLKOUT = 1/2(CLKIN) configuration.
Figure 5-3. Bypass Mode Clock Timings
5.6.4 Clock Generation in Lock Mode (DPLL Synthesis Enabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a synthesis factor of N to
generate the internal CPU clock cycle. The synthesis factor is determined by:
M
N =
DL
(3)
Where:
1. M = the multiply factor set in the PLL_MULT field of the clock mode register
2. DL = the divide factor set in the PLL_DIV field of the clock mode register
Valid values for M are (multiply by) 2 to 31. Valid values for DL are (divide by) 1, 2, 3, and 4.
For detailed information on clock generation configuration, see the TMS320C55x DSP Peripherals Overview
Reference Guide (literature number SPRU317).
Table 5-4 and Table 5-5 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 5-4).
Table 5-4. CLKIN Timing Requirements
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
NO.
UNIT
MIN
20(1)
MAX
400
MIN
20(1)
MAX
400
4
C1
C2
tc(CI)
Cycle time, X2/CLKIN
Fall time, X2/CLKIN
DPLL synthesis enabled
ns
ns
ns
ns
ns
tf(CI)
4
4
C3
tr(CI)
Rise time, X2/CLKIN
4
C10
C11
tw(CIL)
tw(CIH)
Pulse duration, CLKIN low
Pulse duration, CLKIN high
6
6
6
6
(1) This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. If an external crystal is used, the X2/CLKIN
cycle time is limited by the crystal frequency range listed in Table 5-1 .
68
Electrical Specifications
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
Table 5-5. Multiply-By-N Clock Option Switching Characteristics
CVDD = 1.2 V
CVDD = 1.35 V
MAX MIN TYP MAX
CVDD = 1.6 V
UNIT
NO.
MIN
TYP
MIN
TYP MAX
tc(CI)
tc(CI)
x
tc(CI) x
C4
tc(CO)
Cycle time, CLKOUT
9.26
1600 6.95
1600
5
x
1600
ns
N(1)
N(1)
N(1)
C6
C7
C8
C9
tf(CO)
Fall time, CLKOUT
1
1
1
1
1
1
ns
ns
ns
ns
tr(CO)
Rise time, CLKOUT
tw(COL)
tw(COH)
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
H - 1
H - 1
H + 1 H - 1
H + 1 H - 1
H + 1
H + 1
H - 1
H - 1
H + 1
H + 1
Delay time, X2/CLKIN high/low to
CLKOUT high/low
C12
td(CI–CO)
5
15
25
5
15
25
5
15
25
ns
(1) N = Clock frequency synthesis factor
C2
C3
C11
C10
C1
X2/CLKIN
C9
C8
C6
C12
C4
C7
CLKOUT
Bypass Mode
NOTE A: The relationship of X2/CLKIN to CLKOUT depends on the PLL multiply and divide factor chosen for the CLKMD register. The waveform
relationship shown in Figure 53 is intended to illustrate the timing parameters based on CLKOUT = 1xCLKIN configuration.
Figure 5-4. External Multiply-by-N Clock Timings
5.6.5 Real-Time Clock Oscillator With External Crystal
The real-time clock module includes an oscillator circuit. The oscillator requires an external 32.768-kHz crystal
connected across the RTCINX1 and RTCINX2 pins. The connection of the required circuit, consisting of the
crystal and two load capacitors, is shown in Figure 5-5. The load capacitors, C1 and C2, should be chosen such
that Equation 4 below is satisfied. CL in Equation 4 is the load specified for the crystal.
C1C2
CL =
(C1 + C2)
(4)
RTCINX1
RTCINX1
Crystal
32.768 kHz
C1
C2
Figure 5-5. Real-Time Clock Oscillator With External Crystal
Copyright © 2009, Texas Instruments Incorporated
Electrical Specifications
69
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
NOTE
The RTC can be idled by not supplying its 32-kHz oscillator signal. In order to keep RTC power
dissipation to a minimum when the RTC module is not used, it is recommended that the RTC
module be powered up, the RTC input pin (RTCINX1) be pulled low, and the RTC output pin
(RTCINX2) be left floating.
Table 5-6. Recommended RTC Crystal Parameters
PARAMETER
MIN
NOM
MAX
UNIT
kHz
kΩ
fo
Frequency of oscillation(1)
Series resistance(1)
Load capacitance
32.768
ESR
CL
30
60
12.5
pF
DL
Crystal drive level
1
μW
(1) ESR must be 200 kΩ or greater at frequencies other than 32.768 kHz. Otherwise, oscillations at overtone frequencies may occur.
5.7 Memory Interface Timings
5.7.1 Asynchronous Memory Timings
Table 5-7 and Table 5-8 assume testing over recommended operating conditions (see Figure 5-6 and
Figure 5-7).
Table 5-7. Asynchronous Memory Cycle Timing Requirements
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
NO.
UNIT
MIN
MAX
MIN
MAX
M1
M2
M3
M4
tsu (DV–COH)
th (COH–DV)
tsu (ARDY–COH)
th (COH–ARDY)
Setup time, read data valid before CLKOUT high(1)
Hold time, read data valid after CLKOUT high
Setup time, ARDY valid before CLKOUT high(1)
Hold time, ARDY valid after CLKOUT high
6
0
5
0
7
0
ns
ns
ns
ns
10
0
(1) To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or
hold time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
Table 5-8. Asynchronous Memory Cycle Switching Characteristics
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
NO.
UNIT
MIN
MAX
MIN
MAX
M5
M6
td (COH–CEV)
td (COH–CEIV)
td (COH–BEV)
td (COH–BEIV)
td (COH–AV)
Delay time, CLKOUT high to CEx valid
Delay time, CLKOUT high to CEx invalid
Delay time, CLKOUT high to BEx valid
Delay time, CLKOUT high to BEx invalid
Delay time, CLKOUT high to address valid
Delay time, CLKOUT high to address invalid
Delay time, CLKOUT high to AOE valid
Delay time, CLKOUT high to AOE invalid
Delay time, CLKOUT high to ARE valid
Delay time, CLKOUT high to ARE invalid
Delay time, CLKOUT high to data valid
Delay time, CLKOUT high to data invalid
Delay time, CLKOUT high to AWE valid
Delay time, CLKOUT high to AWE invalid
-2
-2
4
4
4
-2
-2
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
4
M7
M8
-2
-2
M9
4
4
M10
M11
M12
M13
M14
M15
M16
M17
M18
td (COH–AIV)
-2
-2
-2
-2
-2
-2
-2
-2
-2
-2
td (COH–AOEV)
td (COH–AOEIV)
td (COH–AREV)
td (COH–AREIV)
td (COH–DV)
4
4
4
4
4
4
4
4
4
4
td (COH–DIV)
-2
-2
-2
-2
-2
-2
td (COH–AWEV)
td (COH–AWEIV)
4
4
4
4
70
Electrical Specifications
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
Extended
Hold = 2
Hold
= 1
Setup = 2
M5
Strobe = 5
Not Ready = 2
†
‡
CLKOUT
M6
M8
CEx
M7
BEx
§
M9
M10
A[20:0]
M2
M1
D[15:0]
AOE
M11
M12
M13
M14
ARE
AWE
M4
M4
M3
M3
ARDY
†
‡
§
CLKOUT is equal to CPU clock
CEx becomes active depending on the memory address space being accessed
A[13:0] for LQFP
Figure 5-6. Asynchronous Memory Read Timings
Copyright © 2009, Texas Instruments Incorporated
Electrical Specifications
71
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
Extended
Hold = 2
Setup = 2
Strobe = 5
Not Ready = 2
Hold = 1
†
CLKOUT
M5
M7
M6
M8
‡
CEx
BEx
M9
M10
M16
§
A[20:0]
M15
D[15:0]
AOE
ARE
M17
M18
AWE
M4
M3
M4
M3
ARDY
†
CLKOUT is equal to CPU clock
‡
§
CEx becomes active depending on the memory address space being accessed
A[13:0] for LQFP
Figure 5-7. Asynchronous Memory Write Timings
5.7.2 Synchronous DRAM (SDRAM) Timings
Table 5-9 and Table 5-10 assume testing over recommended operating conditions (see Figure 5-8 through
Figure 5-14).
Table 5-9. Synchronous DRAM Cycle Timing Requirements
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
NO.
UNIT
MIN
MAX
MIN
MAX
M19
M20
M21
tsu (DV–CLKMEMH)
th (CLKMEMH–DV)
tc (CLKMEM)
Setup time, read data valid before CLKMEM high
Hold time, read data valid after CLKMEM high
Cycle time, CLKMEM
3
2
3
2
ns
ns
ns
9.26(1)
7.52(2)
(1) Maximum SDRAM operating frequency = 108 MHz. Actual attainable maximum operating frequency will depend on the quality of the PC
board design and the memory chip timing requirement.
(2) Maximum SDRAM operating frequency = 133 MHz. Actual attainable maximum operating frequency will depend on the quality of the PC
board design and the memory chip timing requirement.
Table 5-10. Synchronous DRAM Cycle Switching Characteristics
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
NO.
UNIT
MIN
1.2
MAX
MIN
1.2
MAX
M22
M23
M24
td (CLKMEMH–CEL)
td (CLKMEMH–CEH)
td (CLKMEMH–BEV)
Delay time, CLKMEM high to CEx low
Delay time, CLKMEM high to CEx high
Delay time, CLKMEM high to BEx valid
7
7
7
5
ns
ns
ns
1.2
1.2
1.2
1.2
5
5
72
Electrical Specifications
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
Table 5-10. Synchronous DRAM Cycle Switching Characteristics (continued)
CVDD = 1.2 V
CVDD = 1.35 V
CVDD = 1.6 V
NO.
UNIT
MIN
1.2
MAX
MIN
1.2
MAX
M25
M26
M27
M28
M29
M30
M31
M32
M33
M34
M35
M36
M37
M38
M39
td (CLKMEMH–BEIV)
td (CLKMEMH–AV)
td (CLKMEMH–AIV)
Delay time, CLKMEM high to BEx invalid
Delay time, CLKMEM high to address valid
Delay time, CLKMEM high to address invalid
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
5
5
5
5
5
5
5
5
5
5
5
5
5
5
td (CLKMEMH–SDCASL) Delay time, CLKMEM high to SDCAS low
td (CLKMEMH–SDCASH) Delay time, CLKMEM high to SDCAS high
td (CLKMEMH–DV)
Delay time, CLKMEM high to data valid
Delay time, CLKMEM high to data invalid
Delay time, CLKMEM high to SDWE low
Delay time, CLKMEM high to SDWE high
Delay time, CLKMEM high to SDA10 valid
td (CLKMEMH–DIV)
td (CLKMEMH–SDWEL)
td (CLKMEMH–SDWEH)
td (CLKMEMH–SDA10V)
td (CLKMEMH–SDA10IV) Delay time, CLKMEM high to SDA10 invalid
td (CLKMEMH–SDRASL) Delay time, CLKMEM high to SDRAS low
td (CLKMEMH–SDRASH) Delay time, CLKMEM high to SDRAS high
td (CLKMEMH–CKEL)
td (CLKMEMH–CKEH)
Delay time, CLKMEM high to CKE low
Delay time, CLKMEM high to CKE high
READ
READ
READ
M21
CLKMEM
M22
M23
M27
†
‡
CEx
BEx
M24
M26
CA1
CA2
CA3
EMIF.A[13:0]
M19
M20
D[15:0]
SDA10
SDRAS
SDCAS
D1
D2
D3
M34
M35
M28
M29
SDWE
†
The chip enable that becomes active depends on the address being accessed.
All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals r emain
active until the next access that is not an SDRAM read occurs.
‡
Figure 5-8. Three SDRAM Read Commands
Copyright © 2009, Texas Instruments Incorporated
Electrical Specifications
73
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
WRITE
WRITE
WRITE
CLKMEM
M22
M24
M26
M23
†
CEx
M25
M27
M31
‡
BEx
BE1
CA1
D1
BE2
CA2
D2
BE3
CA3
EMIF.A[13:0]
M30
M34
D[15:0]
SDA10
SDRAS
SDCAS
D3
M35
M28
M32
M29
M33
SDWE
†
The chip enable that becomes active depends on the address being accessed.
All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals r emain
active until the next access that is not an SDRAM read occurs.
‡
Figure 5-9. Three SDRAM WRT Commands
74
Electrical Specifications
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
ACTV
CLKMEM
M22
M23
†
‡
CEx
BEx
M26
EMIF.A[13:0]
D[15:0]
Bank Activate/Row Address
M34
M36
SDA10
M37
SDRAS
SDCAS
SDWE
†
‡
The chip enable that becomes active depends on the address being accessed.
All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals r emain
active until the next access that is not an SDRAM read occurs.
Figure 5-10. SDRAM ACTV Command
Copyright © 2009, Texas Instruments Incorporated
Electrical Specifications
75
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
DCAB
CLKMEM
M22
M23
†
CEx
‡
BEx
EMIF.A[13:0]
D[15:0]
M35
M37
M34
M36
SDA10
SDRAS
SDCAS
M33
M32
SDWE
The chip enable that becomes active depends on the address being accessed.
†
‡
All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals r emain
active until the next access that is not an SDRAM read occurs.
Figure 5-11. SDRAM DCAB Command
76
Electrical Specifications
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
REFR
CLKMEM
M22
M23
†
‡
CEx
BEx
EMIF.A[13:0]
D[15:0]
SDA10
M37
M36
M28
SDRAS
SDCAS
M29
SDWE
†
The chip enable that becomes active depends on the address being accessed.
All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals
remain active until the next access that is not an SDRAM read occurs.
‡
Figure 5-12. SDRAM REFR Command
Copyright © 2009, Texas Instruments Incorporated
Electrical Specifications
77
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
MRS
CLKMEM
M22
M23
†
CEx
‡
BEx
M26
M27
§
MRS Value 0x30
EMIF.A[13:0]
D[15:0]
SDA10
M37
M29
M33
M36
M28
M32
SDRAS
SDCAS
SDWE
†
The chip enable that becomes active depends on the address being accessed.
All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals remain
‡
active until the next access that is not an SDRAM read occurs.
Write burst length = 1
Read latency = 3
§
Burst type = 0 (serial)
Burst length = 1
Figure 5-13. SDRAM MRS Command
78
Electrical Specifications
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
Exit Self-Refresh
Enter Self-Refresh
CLKMEM
M38
M22
M39
M23
CKE
(XF or GPIO4)
CEx
M36
M28
SDRAS
SDCAS
SDWE
SDA10
Figure 5-14. SDRAM Self-Refresh Command
5.8 Reset Timings
5.8.1 Power-Up Reset (On-Chip Oscillator Active)
Table 5-11 assumes testing over recommended operating conditions (see Figure 5-15).
Table 5-11. Power-Up Reset (On-Chip Oscillator Active) Timing Requirements
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
MIN MAX
3P(2)
NO.
UNIT
MIN
3P(2)
MAX
R1
th (SUPSTBL-RSTL)
Hold time, RESET low after oscillator stable(1)
ns
(1) Oscillator stable time depends on the crystal characteristic (i.e., frequency, ESR, etc.) which varies from one crystal manufacturer to
another. Based on the crystal characteristics, the oscillator stable time can be in the range of a few to 10s of ms. A reset circuit with
100-ms or more delay time will ensure the oscillator stabilized before the RESET goes high.
(2) P = 1/(input clock frequency) in ns. For example, when input clock is 12 MHz, P = 83.33 ns.
CLKOUT
CV
DD
DV
DD
R1
RESET
Figure 5-15. Power-Up Reset (On-Chip Oscillator Active) Timings
Copyright © 2009, Texas Instruments Incorporated
Electrical Specifications
79
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
5.8.2 Power-Up Reset (On-Chip Oscillator Inactive)
Table 5-12 and Table 5-13 assume testing over recommended operating conditions (see Figure 5-16).
Table 5-12. Power-Up Reset (On-Chip Oscillator Inactive) Timing Requirements
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
MIN MAX
3P(1)
NO.
UNIT
MIN
3P(1)
MAX
R2
th (CLKOUTV-RSTL)
Hold time, CLKOUT valid to RESET low
ns
(1) P = 1/(input clock frequency) in ns. For example, when input clock is 12 MHz, P = 83.33 ns.
Table 5-13. Power-Up Reset (On-Chip Oscillator Inactive) Switching Characteristics
CVDD = 1.2 V
CVDD = 1.35 V
CVDD = 1.6 V
NO.
UNIT
MIN
MAX
30
MIN
MAX
30
R3
td (CLKINV-CLKOUTV) Delay time, CLKIN valid to CLKOUT valid
ns
X2/CLKIN
R3
CLKOUT
CV
DV
DD
DD
R2
RESET
Figure 5-16. Power-Up Reset (On-Chip Oscillator Inactive) Timings
5.8.3 Warm Reset
Table 5-14 and Table 5-15 assume testing over recommended operating conditions (see Figure 5-17).
Table 5-14. Reset Timing Requirements
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
MIN MAX
3P(1)
NO.
UNIT
MIN
3P(1)
MAX
R4
tw (RSL)
Pulse width, reset low
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
80
Electrical Specifications
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
Table 5-15. Reset Switching Characteristics(1)
CVDD = 1.2 V
CVDD = 1.35 V
CVDD = 1.6 V
UNIT
NO.
MIN
MAX
MIN
MAX
R5
R6
R7
R8
td (RSTH–BKV)
td (RSTH–HIGHV)
td (RSTL–ZIV)
td (RSTH–ZV)
Delay time, reset high to BK group valid(2)
Delay time, reset high to High group valid(3)
Delay time, reset low to Z group invalid(4)
Delay time, reset high to Z group valid(4)
38P + 15
38P + 15
1P + 15
38P + 15
38P + 15
38P + 15
1P + 15
38P + 15
ns
ns
ns
ns
(1) P = 1/CPU clock frequency in ns. For example, when CPU is running at 200 MHz, P = 5 ns.
(2) BK group: Pins with bus keepers, holds previous state during reset. Following low-to-high transition of RESET, these pins go to their
post-reset logic state.
BK group pins: A’[0], A[15:0], D[15:0], C[14:2], C0, GPIO5, DX1, and DX2
(3) High group: Following low-to-high transition of RESET, these pins go to logic-high state.
High group pins: C1[HPI.HINT], XF
(4) Z group: Bidirectional pins which become input or output pins. Following low-to-high transition of RESET, these pins go to
high-impedance state.
Z group pins: C1[EMIF.AOE], GPIO[7:6, 4:0], TIN/TOUT0, SDA, SCL, CLKR0, FSR0, CLKX0, DX0, FSX0, FSX2, CLKX2, FSR2, DR2,
CLKR2, FSX1, CLKX1, FSR1, DR1, CLKR1, A[20:16]
RESET
R5
†
BK Group
R6
‡
High Group
R7
R8
§
Z Group
†
‡
§
BK group pins: A’[0], A[15:0], D[15:0], C[14:2], C0, GPIO5, DX1, and DX2
High group pins: C1[HPI.HINT], XF
Z group pins: C1[EMIF.AOE], GPIO[7:6, 4:0], TIN/TOUT0, SDA, SCL, CLKR0, FSR0, CLKX0, DX0, FSX0, FSX2, CLKX2, FSR2, DR2, CLKR2,
FSX1, CLKX1, FSR1, DR1, CLKR1, A[20:16]
Figure 5-17. Reset Timings
5.9 External Interrupt Timings
Table 5-16 assumes testing over recommended operating conditions (see Figure 5-18).
Table 5-16. External Interrupt Timing Requirements(1)
CVDD = 1.2 V
CVDD = 1.35 V
CVDD = 1.6 V
NO.
UNIT
MIN MAX
MIN
2P
3P
MAX
I1
I2
tw (INTH)A
tw (INTL)A
Pulse width, interrupt high, CPU active
Pulse width, interrupt low, CPU active
2P
3P
ns
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
I1
INTn
I2
Figure 5-18. External Interrupt Timings
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Electrical Specifications
81
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
5.10 Wake-Up From IDLE
(2)assumes testing over recommended operating conditions (see Figure 5-19).
Table 5-17. Wake-Up From IDLE Switching Characteristics(1)
CVDD = 1.2 V
CVDD = 1.35 V
CVDD = 1.6 V
MIN TYP MAX
1.25(2)
NO.
UNIT
MIN
TYP
MAX
Delay time, wake–up event low to clock
generation enable
ID1 td (WKPEVTL–CLKGEN)
1.25(2)
ms
(CPU and clock domain idle)
Hold time, clock generation enable to wake–up
event low
(CPU and clock domain in idle)
ID2 th (CLKGEN–WKPEVTL)
3P(3)
3P
3P(3)
3P
ns
ns
Pulse width, wake–up event low
(for CPU idle only)
ID3 tw (WKPEVTL)
(2) P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(2) Estimated data based on 12-MHz crystal used with on-chip oscillator at 25°C. This number will vary based on the actual crystal
characteristics operating condition and the PC board layout and the parasitics.
(3) Following the clock generation domain idle, the INTx becomes level-sensitive and stays that way until the low-to-high transition of INTx
following the CPU wake-up. Holding the INTx low longer than minimum requirement will send more than one interrupt to the CPU. The
number of interrupts sent to the CPU depends on the INTx-low time following the CPU wake-up from IDLE.
Figure 5-19. Wake-Up From IDLE Timings
5.11 XF Timings
Table 5-18 assumes testing over recommended operating conditions (see Figure 5-20).
Table 5-18. XF Switching Characteristics
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
NO.
UNIT
MIN
MAX
MIN
–1
–1
MAX
Delay time, CLKOUT high to XF high
Delay time, CLKOUT high to XF low
–1
–1
3
3
3
X1
td (XF)
ns
3
†
CLKOUT
X1
XF
†
CLKOUT reflects the CPU clock.
Figure 5-20. XF Timings
82
Electrical Specifications
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
5.12 General-Purpose Input/Output (GPIOx) Timings
Table 5-19 and Table 5-20 assume testing over recommended operating conditions (see Figure 5-21).
Table 5-19. GPIO Pins Configured as Inputs Timing Requirements
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
NO.
UNIT
MIN
MAX
MIN
MAX
GPIO
4
8
8
0
0
0
4
8
8
0
0
0
Setup time, IOx input valid
before CLKOUT high
G1
tsu (GPIO–COH)
AGPIO(1)
EHPIGPIO(2)
GPIO
AGPIO(1)
EHPIGPIO(2)
ns
Hold time, IOx input valid
after CLKOUT high
G2
th (COH–GPIO)
ns
(1) AGPIO pins: A[15:0]
(2) EHPIGPIO pins: C13, C10, C7, C5, C4, and C0
Table 5-20. GPIO Pins Configured as Outputs Switching Characteristics
CVDD = 1.2 V
CVDD = 1.35 V
CVDD = 1.6 V
MIN MAX
NO.
UNIT
MIN MAX
GPIO
0
0
0
6
11
13
0
0
0
6
11
13
Delay time, CLKOUT high
to IOx output change
G3
td (COH–GPIO)
AGPIO(1)
EHPIGPIO(2)
ns
(1) AGPIO pins: A[15:0]
(2) EHPIGPIO pins: C13, C10, C7, C5, C4, and C0
†
CLKOUT
G1
G2
IOx
Input Mode
G3
IOx
Output Mode
†
CLKOUT reflects the CPU clock.
Figure 5-21. General-Purpose Input/Output (IOx) Signal Timings
Copyright © 2009, Texas Instruments Incorporated
Electrical Specifications
83
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
5.13 TIN/TOUT Timings (Timer0 Only)
Table 5-21 and Table 5-22 assume testing over recommended operating conditions (see Figure 5-22 and
Figure 5-23).
Table 5-21. TIN/TOUT Pins Configured as Inputs Timing Requirements(1) (2)
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
NO.
UNIT
MIN
MAX
MIN
MAX
T4
T5
tw (TIN/TOUTL)
tw (TIN/TOUTH)
Pulse width, TIN/TOUT low
Pulse width, TIN/TOUT high
2P + 1
2P + 1
2P + 1
2P + 1
ns
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(2) Only the Timer0 signal is externally available. The Timer1 signal is internally terminated and is not available for external use.
Table 5-22. TIN/TOUT Pins Configured as Outputs Switching Characteristics(1) (2) (3)
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
NO.
UNIT
MIN
MAX
MIN
MAX
T1
T2
T3
td (COH–TIN/TOUTH) Delay time, CLKOUT high to TIN/TOUT high
td (COH–TIN/TOUTL) Delay time, CLKOUT high to TIN/TOUT low
-1
-1
3
3
-1
-1
3
ns
ns
ns
3
tw (TIN/TOUT)
Pulse duration, TIN/TOUT (output)
P - 1
P - 1
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(2) Only the Timer0 signal is externally available. The Timer1 signal is internally terminated and is not available for external use.
(3) For proper operation of the TIN/TOUT pin configured as an output, the timer period must be configured for at least 4 cycles.
T5
T4
TIN/TOUT
as Input
Figure 5-22. TIN/TOUT Timings When Configured as Inputs
CLKOUT
T2
T3
T1
TIN/TOUT
as Output
Figure 5-23. TIN/TOUT Timings When Configured as Outputs
84
Electrical Specifications
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
5.14 Multichannel Buffered Serial Port (McBSP) Timings
5.14.1 McBSP0 Timings
Table 5-23 and Table 5-24 assume testing over recommended operating conditions (see Figure 5-24 and
Figure 5-25).
Table 5-23. McBSP0 Timing Requirements(1)
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
NO.
UNIT
MIN
2P(2)
MAX
MIN
2P(2)
MAX
MC1
MC2
tc (CKRX)
tw (CKRX)
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
ns
ns
Pulse duration, CLKR/X
high or CLKR/X low
P–1(2)
P–1(2)
MC3
MC4
tr (CKRX)
tf (CKRX)
Rise time, CLKR/X
Fall time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
6
6
6
6
ns
ns
10
2
7
2
Setup time, external FSR
high before CLKR low
MC5
MC6
MC7
MC8
MC9
MC10
tsu (FRH–CKRL)
th (CKRL–FRH)
tsu (DRV–CKRL)
th (CKRL–DRV)
tsu (FXH–CKXL)
th (CKXL–FXH)
ns
ns
ns
ns
ns
ns
-3
1
-3
1
Hold time, external FSR
high after CLKR low
10
2
7
Setup time, DR valid before
CLKR low
2
-2
3
-2
3
Hold time, DR valid after
CLKR low
13
3
8
Setup time, external FSX
high before CLKX low
2
-3
1
-3
1
Hold time, external FSX
high after CLKX low
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
Table 5-24. McBSP0 Switching Characteristics(1) (2)
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
NO.
UNIT
MIN
MAX
MIN
2P
MAX
MC1
MC3
MC4
tc (CKRX)
tr (CKRX)
tf (CKRX)
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
CLKR/X int
CLKR/X int
CLKR/X int
CLKR int
2P
ns
ns
ns
Rise time, CLKR/X
1
1
1
1
Fall time, CLKR/X
MC11 tw (CKRXH)
MC12 tw (CKRXL)
Pulse duration, CLKR/X high
Pulse duration, CLKR/X low
D-2(3)
C-2(3)
D+2(3)
C+2(3)
D-1(3)
C-1(3)
D+1(3) ns
C+1(3) ns
-2
4
1
13
2
-2
4
1
Delay time, CLKR high to internal FSR
valid
MC13 td (CKRH–FRV)
MC14 td (CKXH–FXV)
MC15 tdis (CKXH–DXHZ)
ns
8
CLKR ext
CLKX int
-2
4
-2
4
2
Delay time, CLKX high to internal FSX
valid
ns
9
CLKX ext
CLKX int
15
5
0
-5
3
1
ns
11
Disable time, DX high–impedance from
CLKX high following last data bit
CLKX ext
10
18
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
(3) T=CLKRX period = (1 + CLKGDV) * P
C=CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D=CLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
Copyright © 2009, Texas Instruments Incorporated
Electrical Specifications
85
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
(1) (2)
Table 5-24. McBSP0 Switching Characteristics
(continued)
CVDD = 1.2 V
CVDD = 1.35 V
CVDD = 1.6 V
MIN MAX
NO.
UNIT
MIN MAX
Delay time, CLKX high to DX valid. This
applies to all bits except the first bit
transmitted.
CLKX int
CLKX ext
5
4
9
15
CLKX int
CLKX ext
CLKX int
4
13
2
7
Delay time, CLKX
DXENA = 0
high to DX valid(4)
MC16 td (CKXH–DXV)
ns
Only applies to first bit
transmitted when in
2P + 1
2P + 1
Data Delay 1 or 2
(XDATDLY = 01b or
10b) modes
DXENA = 1
DXENA = 0
CLKX ext
2P + 4
2P + 3
Enable time, DX
driven from CLKX
high(4)
CLKX int
CLKX ext
CLKX int
-1
6
-3
3
Only applies to first bit
transmitted when in
Data Delay 1 or 2
(XDATDLY= 01b or
10b) modes
P - 1
P - 3
MC17 ten (CKXH–DX)
MC18 td (FXH–DXV)
MC19 ten (FXH–DX)
ns
ns
ns
DXENA = 1
DXENA = 0
DXENA = 1
CLKX ext
P + 6
P + 3
FSX int
FSX ext
FSX int
2
13
2
8
Delay time, FSX high
to DX valid(4)
Only applies to first bit
transmitted when in
Data Delay 0
(XDATDLY= 00b)
mode.
2P + 1
2P + 1
FSX ext
2P + 10
2P + 10
Enable time, DX
driven from FSX
high(4)
FSX int
FSX ext
FSX int
0
8
0
3
DXENA = 0
DXENA = 1
Only applies to first bit
transmitted when in
Data Delay 0
(XDATDLY= 00b)
mode
P - 3
P - 3
FSX ext
P + 8
P + 4
(4) See the TMS320C55x DSP Peripherals Overview Reference Guide (literature number SPRU317) for a description of the DX enable
(DXENA) and data delay features of the McBSP.
5.14.2 McBSP1 and McBSP2 Timings
Table 5-25 and Table 5-26 assume testing over recommended operating conditions (see Figure 5-24 and
Figure 5-25).
Table 5-25. McBSP1 and McBSP2 Timing Requirements(1)
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
NO.
UNIT
MIN
2P(2)
MAX
MIN
2P(2)
MAX
MC1
MC2
tc (CKRX)
tw (CKRX)
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
ns
ns
Pulse duration, CLKR/X
high or CLKR/X low
P–1(2)
P–1(2)
MC3
MC4
tr (CKRX)
tf (CKRX)
Rise time, CLKR/X
Fall time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR int
6
6
6
6
ns
ns
11
3
7
3
Setup time, external FSR
high before CLKR low
MC5
tsu (FRH–CKRL)
ns
CLKR ext
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
86
Electrical Specifications
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
(1)
Table 5-25. McBSP1 and McBSP2 Timing Requirements
(continued)
CVDD = 1.2 V
CVDD = 1.35 V
CVDD = 1.6 V
UNIT
NO.
MIN
MAX
MIN
MAX
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
-3
1
-3
1
Hold time, external FSR
high after CLKR low
MC6
MC7
MC8
MC9
MC10
th (CKRL–FRH)
tsu (DRV–CKRL)
th (CKRL–DRV)
tsu (FXH–CKXL)
th (CKXL–FXH)
ns
ns
ns
ns
ns
11
3
7
Setup time, DR valid before
CLKR low
3
-2
3
-2
3
Hold time, DR valid after
CLKR low
14
4
9
Setup time, external FSX
high before CLKX low
3
-3
1
-3
1
Hold time, external FSX
high after CLKX low
Table 5-26. McBSP0 Switching Characteristics(1) (2)
CVDD = 1.2 V
CVDD = 1.35 V
CVDD = 1.6 V
NO.
UNIT
MIN MAX
MIN
2P
MAX
MC1
MC3
MC4
tc (CKRX)
tr (CKRX)
tf (CKRX)
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
CLKR/X int
CLKR/X int
CLKR/X int
CLKR int
2P
ns
ns
ns
Rise time, CLKR/X
2
2
2
Fall time, CLKR/X
2
MC11 tw (CKRXH)
MC12 tw (CKRXL)
Pulse duration, CLKR/X high
Pulse duration, CLKR/X low
D - 2(3)
C - 2(3)
D + 2(3) D - 2(3) D + 2(3) ns
C + 2(3) C - 2(3) C + 2(3) ns
-3
3
2
14
2
-3
3
2
9
Delay time, CLKR high to internal FSR
valid
MC13 td (CKRH–FRV)
MC14 td (CKXH–FXV)
MC15 tdis (CKXH–DXHZ)
ns
ns
ns
CLKR ext
CLKX int
-3
4
-3
4
2
Delay time, CLKX high to internal FSX
valid
CLKX ext
CLKX int
15
3
9
-3
10
-5
3
1
Disable time, DX high–impedance from
CLKX high following last data bit
CLKX ext
CLKX int
19
5
12
3
Delay time, CLKX high to DX valid. This
applies to all bits except the first bit
transmitted.
CLKX ext
15
9
CLKX int
CLKX ext
CLKX int
4
15
2
9
Delay time, CLKX
DXENA = 0
high to DX valid(4)
MC16 td (CKXH–DXV)
ns
Only applies to first bit
transmitted when in
2P + 1
2P + 1
Data Delay 1 or 2
(XDATDLY=01b or
10b) modes
DXENA = 1
CLKX ext
2P + 5
2P + 3
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
(3) T=CLKRX period = (1 + CLKGDV) * P
C=CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D=CLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
(4) See the TMS320C55x DSP Peripherals Overview Reference Guide (literature number SPRU317) for a description of the DX enable
(DXENA) and data delay features of the McBSP.
Copyright © 2009, Texas Instruments Incorporated
Electrical Specifications
87
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
(1) (2)
Table 5-26. McBSP0 Switching Characteristics
(continued)
CVDD = 1.2 V
CVDD = 1.35 V
CVDD = 1.6 V
MIN MAX
NO.
UNIT
MIN MAX
Enable time, DX
driven from CLKX
high(4)
CLKX int
CLKX ext
CLKX int
-2
9
-4
4
DXENA = 0
Only applies to first bit
transmitted when in
Data Delay 1 or 2
(XDATDLY=01b or
10b) modes
P - 2
P - 4
MC17 ten (CKXH–DX)
ns
DXENA = 1
DXENA = 0
DXENA = 1
CLKX ext
P + 9
P + 4
FSX int
FSX ext
FSX int
3
2
8
Delay time, FSX high
to DX valid(4)
13
Only applies to first bit
transmitted when in
Data Delay 0
(XDATDLY=00b)
mode.
2P + 1
2P + 1
MC18 td (FXH–DXV)
ns
ns
FSX ext
2P + 12
2P + 7
Enable time, DX
driven from FSX
high(4)
FSX int
FSX ext
FSX int
1
8
0
4
DXENA = 0
DXENA = 1
Only applies to first bit
transmitted when in
Data Delay 0
(XDATDLY=00b)
mode
P - 1
P - 3
MC19 ten (FXH–DX)
FSX ext
P + 8
P + 5
MC1
MC2, MC11
MC3
MC2, MC12
CLKR
FSR (Int)
FSR (Ext)
MC13
MC4
MC13
MC5
MC6
MC7
MC8
DR
Bit (n1)
(n2)
(n3)
(n4)
(RDATDLY=00b)
MC7
MC8
(n2)
DR
Bit (n1)
(n3)
(RDATDLY=01b)
MC7
MC8
(n2)
DR
Bit (n1)
(RDATDLY=10b)
Figure 5-24. McBSP Receive Timings
88
Electrical Specifications
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
MC1
MC2, MC11
MC2, MC12
MC3
MC4
CLKX
MC14
MC14
FSX (Int)
MC9
MC10
FSX (Ext)
MC18
MC16
MC19
DX
(XDATDLY=00b)
Bit 0
Bit (n1)
MC17
(n2)
(n3)
(n4)
(n3)
MC16
(n2)
DX
(XDATDLY=01b)
Bit 0
Bit (n1)
MC17
MC16
MC15
Bit 0
DX
(XDATDLY=10b)
Bit (n1)
(n2)
Figure 5-25. McBSP Transmit Timings
5.14.3 McBSP as SPI Master or Slave Timings
Table 5-27 to Table 5-34 assume testing over recommended operating conditions (see Figure 5-26 through
Figure 5-29).
Table 5-27. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)(1) (2)
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
NO.
UNIT
MASTER
MIN MAX
SLAVE
MIN MAX
MASTER
SLAVE
MIN MAX
MIN MAX
MC23 tsu (DRV–CKXL)
MC24 th (CKXL–DRV)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
15
0
3 - 6P
3 + 6P
10
0
3 - 6P
3 + 6P
ns
ns
Setup time, FSX low before CLKX
high
MC25 tsu (FXL–CKXH)
MC26 tc (CKX)
5
5
ns
ns
Cycle time, CLKX
2P
16P
2P
16P
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2) P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
Copyright © 2009, Texas Instruments Incorporated
Electrical Specifications
89
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
Table 5-28. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)(1) (2)
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
NO.
UNIT
(3)
(3)
MASTER
MIN MAX
SLAVE
MIN MAX
MASTER
MIN MAX
SLAVE
MIN
MAX
Delay time, CLKX low to FSX
low(4)
MC27 td (CKXL–FXL)
MC28 td (FXL–CKXH)
MC29 td (CKXH–DXV)
T - 5 T + 5
C - 5 C + 5
T - 4 T + 4
C - 4 C + 4
ns
ns
ns
Delay time, FSX low to CLKX
high(5)
Delay time, CLKX high to DX
valid
-4
6
3P + 3 5P + 15
-3
3
3P + 3
5P + 8
Disable time, DX
high–impedance following last
data bit from CLKX low
tdis
(CKXL–DXHZ)
MC30
C - 4 C + 4
C - 3 C + 1
ns
Disable time, DX
MC31 tdis (FXH–DXHZ) high–impedance following last
data bit from FSX high
3P+ 4 3P + 19
3P + 4 3P + 18
3P+ 3 3P + 11
3P + 4 3P + 10
ns
ns
MC32 td (FXL–DXV)
Delay time, FSX low to DX valid
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2) P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
(3) T = CLKX period = (1 + CLKGDV) * 2P
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
(4) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on
FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
(5) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
MC25
MC28
MC26
LSB
MSB
CLKX
FSX
MC29
MC27
MC31
MC30
MC32
DX
DR
Bit 0
Bit (n1)
Bit (n1)
(n2)
(n3)
(n3)
(n4)
(n4)
MC23
MC24
(n2)
Bit 0
Figure 5-26. McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
90
Electrical Specifications
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
Table 5-29. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)(1) (2)
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
NO.
MASTER
MIN
15
SLAVE
MA
MASTER
SLAVE
UNIT
MAX MIN
MIN MAX MIN MAX
X
MC33 tsu (DRV–CKXH)
MC34 th (CKXH–DRV)
MC25 tsu (FXL–CKXH)
MC26 tc (CKX)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX high
Cycle time, CLKX
3 - 6P
3 + 6P
5
10
0
3 - 6P
3 + 6P
5
ns
ns
ns
ns
0
2P
16P
2P
16P
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2) P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
Table 5-30. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)(1) (2)
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
NO.
UNIT
(3)
(3)
MASTER
MIN MAX
SLAVE
MIN MAX
MASTER
SLAVE
MIN MAX
MIN
MAX
Delay time, CLKX low to FSX
low(4)
MC27 td (CKXL–FXL)
C - 5 C + 5
T - 5 T + 5
C - 4
C + 4
ns
ns
Delay time, FSX low to CLKX
high(5)
MC28 td (FXL–CKXH)
MC35 td (CKXL–DXV)
T - 4
-3
T + 4
3
Delay time, CLKX low to DX valid
-4
-4
6
4
3P + 3 5P + 15
3P + 4 3P + 19
3P + 3 5P + 8 ns
3P + 3 3P + 12 ns
Disable time, DX high–impedance
following last data bit from CLKX
low
tdis
(CKXL–DXHZ)
MC30
-3
1
MC32 td (FXL–DXV)
Delay time, FSX low to DX valid
D - 4 D + 4 3P + 4 3P + 18
D - 3
D + 3 3P + 4 3P + 10 ns
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2) P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
(3) T = CLKX period = (1 + CLKGDV) * 2P
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
(4) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on
FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
(5) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
MC25
MC28
MC26
LSB
MSB
CLKX
FSX
MC35
MC27
MC32
MC30
DX
DR
Bit 0
Bit 0
Bit (n1)
(n2)
(n3)
(n3)
(n4)
(n4)
MC33
MC34
(n2)
Bit (n1)
Figure 5-27. McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
Copyright © 2009, Texas Instruments Incorporated
Electrical Specifications
91
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
Table 5-31. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)(1) (2)
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
NO.
MASTER
SLAVE
MASTER
SLAVE
UNIT
MA
X
MIN MAX
MIN
MIN MAX MIN MAX
MC33 tsu (DRV–CKXH)
MC34 th (CKXH–DRV)
MC36 tsu (FXL–CKXL)
MC26 tc (CKX)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX low
Cycle time, CLKX
15
0
3 - 6P
3 + 6P
5
10
0
3 - 6P
3 + 6P
5
ns
ns
ns
ns
2P
16P
2P
16P
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2) P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
Table 5-32. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)(1) (2)
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
NO.
UNIT
(3)
(3)
MASTER
MIN MAX
SLAVE
MIN MAX
MASTER
MIN MAX
SLAVE
MIN MAX
Delay time, CLKX high to FSX
low(4)
MC37 td(CKXH–FXL)
T - 5 T + 5
T - 4 T + 4
ns
MC38 td(FXL–CKXL)
MC35 td(CKXL–DXV)
Delay time, FSX low to CLKX low(5)
Delay time, CLKX low to DX valid
Disable time, DX high–impedance
D - 5 D + 5
D - 4 D + 4
ns
ns
-4
6
3P + 3 5P + 15
-3
3
3P + 3 5P + 8
MC39 tdis(CKXH–DXHZ) following last data bit from CLKX
high
D - 4 D + 4
D - 3 D + 1
ns
Disable time, DX high–impedance
MC31 tdis(FXH–DXHZ)
3P + 4 3P +19
3P + 4 3P + 18
3P + 3 3P +11
3P + 4 3P + 10
ns
ns
following last data bit from FSX high
MC32 td(FXL–DXV)
Delay time, FSX low to DX valid
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2) P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
(3) T = CLKX period = (1 + CLKGDV) * 2P
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
(4) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on
FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
(5) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
MC36
LSB
MSB
MC26
CLKX
FSX
MC38
MC35
MC37
MC31
MC39
MC32
DX
DR
Bit 0
Bit (n1)
(n2)
(n3)
(n3)
(n4)
MC33
MC34
(n2)
Bit 0
Bit (n1)
(n4)
Figure 5-28. McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
92
Electrical Specifications
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
Table 5-33. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)(1) (2)
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
NO.
UNIT
MASTER
SLAVE
MASTER
SLAVE
MIN MAX MIN MAX MIN MAX MIN MAX
MC23 tsu (DRV–CKXL)
MC24 th (CKXL–DRV)
MC36 tsu (FXL–CKXL)
MC26 tc (CKX)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX low
Cycle time, CLKX
15
0
3 - 6P
3 + 6P
5
10
0
3 - 6P
3 + 6P
5
ns
ns
ns
ns
2P
16P
2P
16P
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2) P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
Table 5-34. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)(1) (2)
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
NO.
UNIT
(3)
(3)
MASTER
MIN MAX
SLAVE
MIN MAX
MASTER
MIN MAX
SLAVE
MIN MAX
Delay time, CLKX high to FSX
low(4)
MC37 td(CKXH–FXL)
MC38 td(FXL–CKXL)
MC29 td(CKXH–DXV)
D - 5 D + 5
T - 5 T + 5
D - 4 D + 4
T - 4 T + 4
ns
ns
Delay time, FSX low to CLKX
low(5)
Delay time, CLKX high to DX
valid
-4
-4
6
4
3P + 3 5P + 15
3P + 4 3P + 19
-3
-3
3
1
3P + 3
5P + 8 ns
Disable time, DX
MC39 tdis(CKXH–DXHZ) high–impedance following last
data bit from CLKX high
3P + 3 3P + 12 ns
MC32 td(FXL–DXV)
Delay time, FSX low to DX valid
C - 4 C + 4 3P + 4 3P + 18
C - 3 C + 3 3P + 4 3P + 10 ns
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2) P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
(3) T = CLKX period = (1 + CLKGDV) * 2P
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
(4) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on
FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
(5) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
MC36
LSB
MSB
MC26
CLKX
FSX
MC38
MC32
MC29
MC37
MC39
DX
DR
Bit 0
Bit 0
Bit (n1)
Bit (n1)
(n2)
(n3)
(n4)
MC23
MC24
(n2)
(n3)
(n4)
Figure 5-29. McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
Copyright © 2009, Texas Instruments Incorporated
Electrical Specifications
93
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
5.14.4 McBSP General-Purpose I/O Timings
Table 5-35 and Table 5-36 assume testing over recommended operating conditions (see Figure 5-30).
Table 5-35. McBSP General-Purpose I/O Timing Requirements
CVDD = 1.2 V
CVDD = 1.35 V
CVDD = 1.6 V
MIN MAX
NO.
UNIT
MIN MAX
MC20
MC21
tsu(MGPIO–COH)
th(COH–MGPIO)
Setup time, MGPIOx input mode before CLKOUT high(1)
Hold time, MGPIOx input mode after CLKOUT high(1)
7
0
7
0
ns
ns
(1) MGPIOx refers to CLKRx, FSRx, DRx, CLKXx, or FSXx when configured as a general-purpose input.
Table 5-36. McBSP General-Purpose I/O Switching Characteristics
CVDD = 1.2 V
CVDD = 1.35 V
CVDD = 1.6 V
MIN MAX
NO.
UNIT
MIN
MAX
MC22
td(COH-MGPIO)
Delay time, CLKOUT high to MGPIOx output mode(1)
0
7
0
7
ns
(1) MGPIOx refers to CLKRx, FSRx, CLKXx, FSXx, or DXx when configured as a general-purpose output.
Figure 5-30. McBSP General-Purpose I/O Timings
94
Electrical Specifications
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
5.15 Enhanced Host-Port Interface (EHPI) Timings
Table 5-37 and Table 5-38 assume testing over recommended operating conditions (see Figure 5-31 through
Figure 5-36).
Table 5-37. EHPI Timing Requirements
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
NO.
UNIT
MIN
MAX
MIN
MAX
E11
E12
tsu (HASL–HDSL)
th (HDSL–HASL)
Setup time, HAS low before HDS low
Hold time, HAS low after HDS low
4
3
4
3
ns
ns
Setup time, (HR/W, HA[13:0], HBE [1:0], HCNTL[1:0]) valid
before HDS low
E13
E14
tsu (HCNTLV–HDSL)
th (HDSL–HCNTLIV)
2
2
ns
ns
Hold time, (HR/W, HA[13:0], HBE [1:0], HCNTL[1:0]) invalid
after HDS low
4
4
E15
E16
E17
E18
tw (HDSL)
Pulse duration, HDS low
4P(1)
4P(1)
3
4P(1)
4P(1)
3
ns
ns
ns
ns
tw (HDSH)
Pulse duration, HDS high
tsu (HDV–HDSH)
th (HDSH–HDIV)
Setup time, HD bus write data valid before HDS high
Hold time, HD bus write data invalid after HDS high
4
4
Setup time, (HR/W, HBE [1:0], HCNTL[1:0]) valid before
HAS low
E19
E20
tsu (HCNTLV–HASL)
th (HASL–HCNTLIV)
3
4
3
4
ns
ns
Hold time, (HR/W, HBE [1:0], HCNTL[1:0]) valid after HAS
low
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
Table 5-38. EHPI Switching Characteristics
CVDD = 1.2 V
CVDD = 1.35 V
CVDD = 1.6 V
MIN MAX
NO.
UNIT
MIN MAX
26
E1
E2
E4
E5
ten (HDSL–HDD)M
td (HDSL–HDV)M
ten (HDSL–HDD)R
td (HDSL–HDV)R
Enable time, HDS low to HD bus enabled (memory access)
6
6
19
ns
ns
ns
ns
Delay time, HDS low to HD bus read data valid
(memory access)
14P(1) (2)
6
14P(1) (2)
6
Enable time, HDS low to HD enabled (register access)
26
26
19
19
Delay time, HDS low to HD bus read data valid
(register access)
E6
E7
tdis (HDSH–HDIV)
td (HDSL–HRDYL)
td (HDV–HRDYH)
td (HDSH–HRDYL)
Disable time, HDS high to HD bus read data invalid
Delay time, HDS low to HRDY low (during reads)
Delay time, HD bus valid to HRDY high (during reads)
Delay time, HDS high to HRDY low (during writes)
6
2
26
18
6
2
19
15
ns
ns
ns
ns
ns
ns
E8
E9
18
11
15
8
E10
E21
td (HDSH–HRDYH) Delay time, HDS high to HRDY high (during writes)
td (COH–HINT) Delay time, CLKOUT high to HINT high/low
14P(1) (2)
0
14P(1) (2)
0
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(2) EHPI latency is dependent on the number of DMA channels active, their priorities and their source/destination ports. The latency shown
assumes no competing CPU or DMA activity to the memory resource being accessed by the EHPI.
†
CLKOUT
E21
HINT
†
CLKOUT reflects the CPU clock.
Figure 5-31. HINT Timings
Copyright © 2009, Texas Instruments Incorporated
Electrical Specifications
95
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
Read
E15
Write
HCS
HDS
E16
E13
E15
E14
E14
E13
HR/W
HBE[1:0]
HCNTL0
HA[13:0]
Valid
Valid
Valid
Valid
Valid
Valid
E2
E1
E6
HD[15:0]
(read)
Read Data
E17
E18
HD[15:0]
(write)
Write Data
E9
E10
E7
E8
HRDY
NOTES: A. Any non-multiplexed access with HCNTL0 low will result in HPIC register access. For data read or write, HCNTL0 must stay high
during the EHPI access.
B. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur
concurrent with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied permanently active and HCS is used as a strobe,
the timing requirements shown for HDS apply to HCS. HRDY is always driven to the same value as its internal state.
Figure 5-32. EHPI Nonmultiplexed Read/Write Timings
96
Electrical Specifications
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
Read
Write
E12
HCS
HAS
E11
E12
E11
E15
E16
E19
E15
E14
HDS
E20
E19
E20
E13
E14
E13
HR/W
Valid
Valid
HBE[1:0]
Valid (11)
Valid (11)
HCNTL[1:0]
E2
E6
E1
HD[15:0]
(read)
Read Data
E17
E18
HD[15:0]
(write)
Write Data
E10
E7
E8
E9
HRDY
NOTE: The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur concurrent
with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied permanently active and HCS is used as a strobe, the timing
requirements shown for HDS apply to HCS. HRDY is always driven to the same value as its internal state.
Figure 5-33. EHPI Multiplexed Memory (HPID) Read/Write Timings Without Autoincrement
Copyright © 2009, Texas Instruments Incorporated
Electrical Specifications
97
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
HCS
E11
E12
E15
HAS
E16
HDS
E19
E20
E13
E14
HR/W
HBE[1:0]
Valid
Valid
HCNTL[1:0]
Valid (01)
E1
Valid (01)
E1
E2
E2
E6
E6
HD[15:0]
(read)
Read Data
Read Data
E7
E8
E7
E8
HRDY
HPIA contents
n
n + 1
n + 2
NOTES: A. During autoincrement mode, although the EHPI internally increments the memory address, reads of the HPIA register by the host
will always indicate the base address.
B. In autoincrement mode, if HBE[1:0] are used to access the data as 8-bit-wideunits, the HPIA increments only following each high
byte (HBE1 low) access.
C. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur
concurrent with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied permanently active and HCSis used as a strobe,
the timing requirements shown for HDS apply to HCS. HRDY is always driven to the same value as its internal state.
Figure 5-34. EHPI Multiplexed Memory (HPID) Read Timings With Autoincrement
98
Electrical Specifications
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
HCS
HAS
E12
E15
E11
E16
HDS
E19
E20
E13
E14
HR/W
HBE[1:0]
Valid
Valid
HCNTL[1:0]
Valid (01)
Valid (01)
E17
E18
E10
HD[15:0]
(write)
Write Data
Write Data
E10
E9
E9
HRDY
n
HPIA contents
n + 1
NOTES: A. During autoincrement mode, although the EHPI internally increments the memory address, reads of the HPIA register by the host
will always indicate the base address.
B. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur
concurrent with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied permanently active and HCSis used as a strobe,
the timing requirements shown for HDS apply to HCS. HRDY is always driven to the same value as its internal state.
Figure 5-35. EHPI Multiplexed Memory (HPID) Write Timings With Autoincrement
Copyright © 2009, Texas Instruments Incorporated
Electrical Specifications
99
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
Read
Write
E12
HCS
E11
E11
E12
HAS
E15
E16
E15
HDS
E19
E20
E19
E20
E14
E13
E14
E13
HR/W
Valid
Valid
HBE[1:0]
Valid (10 or 00)
Valid (10 or 00)
HCNTL[1:0]
E5
E6
E4
HD[15:0]
(read)
Read Data
E17
E18
HD[15:0]
(write)
Write Data
HRDY
NOTES: A. During autoincrement mode, although the EHPI internally increments the memory address, reads of the HPIA register by the host
will always indicate the base address.
B. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur
concurrent with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied permanently active and HCSis used as a strobe,
the timing requirements shown for HDS apply to HCS. HRDY is always driven to the same value as its internal state.
Figure 5-36. EHPI Multiplexed Register Read/Write Timings
100
Electrical Specifications
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
5.16 I2C Timings
Table 5-39 and Table 5-39 assume testing over recommended operating conditions (see Figure 5-37 and
Figure 5-38).
Table 5-39. I2C Signals (SDA and SCL) Timing Requirements
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
NO.
STANDARD
MODE
FAST
MODE
STANDARD
MODE
FAST
MODE
UNIT
MIN
MAX
MIN
2.5
MAX
MIN
MAX
MIN
MAX
IC1 tc (SCL)
Cycle time, SCL
10
10
2.5
0.6
μs
μs
Setup time, SCL high
before SDA low for a
repeated START
condition
IC2 tsu (SCLH–SDAL)
4.7
4
0.6
4.7
Hold time, SCL low
after SDA low for a
START and a
IC3 th (SCLL–SDAL)
0.6
4
0.6
μs
repeated START
condition
Pulse duration, SCL
low
IC4 tw (SCLL)
4.7
4
1.3
0.6
4.7
4
1.3
0.6
μs
μs
ns
Pulse duration, SCL
high
IC5 tw (SCLH)
Setup time, SDA valid
before SCL high
IC6 tsu (SDA–SCLH)
IC7 th (SDA–SCLL)
250
0(2)
100(1)
0(2)
250
0(2)
100(1)
Hold time, SDA valid
after SCL low
0.9(3)
0(2) 0.9(3) μs
Pulse duration, SDA
high between STOP
and START
IC8 tw (SDAH)
4.7
1.3
4.7
1.3
μs
conditions
20 +
20 +
0.1Cb
IC9 tr (SDA)
IC10 tr (SCL)
IC11 tf (SDA)
IC12 tf (SCL)
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
1000
1000
300
300
300
300
300
1000
1000
300
0.1Cb
300 ns
300 ns
300 ns
300 ns
μs
(4)
(4)
20 +
20 +
0.1Cb
(4)
0.1Cb
(4)
20 +
20 +
0.1Cb
(4)
0.1Cb
(4)
20 +
20 +
300
300
0.1Cb
(4)
0.1Cb
(4)
Setup time, SCL high
before SDA high (for
STOP condition)
IC13 tsu (SCLH–SDAH)
4
0.6
0
4
0.6
0
Pulse duration, spike
(must be suppressed)
IC14 tw (SP)
50
50 ns
Capacitive load for
each bus line
(4)
IC15 Cb
400
400
400
400 pF
(1) A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be
met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns
(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
(2) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(3) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW period [tw(SCLL)] of the SCL signal.
(4) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
Copyright © 2009, Texas Instruments Incorporated
Electrical Specifications
101
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
IC11
IC9
SDA
SCL
IC6
IC8
IC14
IC13
IC4
IC5
IC10
IC1
IC3
IC12
IC3
IC2
IC7
Stop
Start
Repeated
Start
Stop
Figure 5-37. I2C Receive Timings
Table 5-40. I2C Signals (SDA and SCL) Timing Requirements
CVDD = 1.2 V
CVDD = 1.35 V
CVDD = 1.6 V
NO.
STANDARD
MODE
FAST
MODE
STANDARD
MODE
FAST
MODE
UNIT
MIN MAX
MIN
MAX
MIN
10
MAX
MIN MAX
IC16 tc(SCL)
Cycle time, SCL
10
2.5
2.5
μs
μs
Delay time, SCL high to
SDA low for a repeated
START condition
IC17 td(SCLH–SDAL)
4.7
0.6
4.7
0.6
Delay time, SDA low to
SCL low for a START and
a repeated START
condition
IC18 td(SDAL–SCLL)
4
0.6
4
0.6
μs
IC19 tw(SCLL)
IC20 tw(SCLH)
Pulse duration, SCL low
Pulse duration, SCL high
4.7
4
1.3
0.6
4.7
4
1.3
0.6
μs
μs
Delay time, SDA valid to
SCL high
IC21 td(SDA–SCLH)
IC22 tv(SCLL–SDAV)
250
0
100
0
250
0
100
0
ns
Valid time, SDA valid after
SCL low
0.9
0.9
μs
Pulse duration, SDA high
between STOP and
START conditions
IC23 tw(SDAH)
IC24 tr(SDA)
IC25 tr(SCL)
IC26 tf(SDA)
IC27 tf(SCL)
4.7
1.3
4.7
1.3
μs
ns
ns
ns
ns
20 +
20 +
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
1000
1000
300
300
300
300
300
1000
1000
300
0.1Cb
300
300
300
300
(1)
0.1Cb
(1)
20 +
20 +
0.1Cb
(1)
0.1Cb
(1)
20 +
20 +
0.1Cb
(1)
0.1Cb
(1)
20 +
20 +
300
300
0.1Cb
(1)
0.1Cb
(1)
Delay time, SCL high to
SDA high for a STOP
condition
IC28 td(SCLH–SDAH)
4
0.6
4
0.6
μs
Capacitance for each
I2C pin
IC29 Cp
10
10
10
10
pF
(1) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
102 Electrical Specifications
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
IC24
www.ti.com
IC26
SDA
IC21
IC23
IC19
IC28
IC20
IC27
IC25
SCL
IC16
IC18
IC18
IC17
IC22
Stop
Start
Repeated
Start
Stop
Figure 5-38. I2C Transmit Timings
5.17 Universal Serial Bus (USB) Timings
Table 5-41 assumes testing over recommended operating conditions (see Figure 5-39 and Figure 5-40).
Table 5-41. Universal Serial Bus (USB) Characteristics
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
NO.
FULL SPEED
12Mbps
FULL SPEED
12Mbps
UNIT
MIN
TYP
MAX
20
MIN
TYP
MAX
20
U1 tr
U2 tf
Rise time of DP and DN signals(1)
Fall time of DP and DN signals(1)
Rise/Fall time matching(2)
Output signal cross–over voltage(1)
Differential propagation jitter(3) (4)
Operating frequency (full speed mode)
Series resistor
4
4
4
4
ns
ns
20
20
tRFM
VCRS
tjr
90
1.3
-2
111.11
90
1.3
-2
111.11
%
2
2
2
2
V
ns
fop
12
12
Mb/s
W
U3 Rs(DP)
U4 Rs(DN)
U5 Cedge(DP)
U6 Cedge(DN)
24
24
22
22
24
24
22
22
Series resistor
W
Edge rate control capacitor
Edge rate control capacitor
pF
pF
(1) CL = 50 pF
(2) (tr/tf) x 100
(3)
tpx(1) − tpx(0)
(4) USB PLL is susceptible to power supply ripple, refer to recommend operating conditions for allowable supply ripple to meet the USB
peak-to-peak jitter specification.
tperiod + Jitter
VOH
VOL
D-
90%
10%
VCRS
D+
U2
U1
Figure 5-39. USB Timings
Copyright © 2009, Texas Instruments Incorporated
Electrical Specifications
103
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
SPRS613–SEPTEMBER 2009
www.ti.com
5507
USBV
DD
PU
DP
R(PU)
1.5 k
U3
D+
U5
C
L
L
U4
DN
D
U6
C
NOTES: A. A full-speed buffer is measured with the load shown.
B. = 50 pF
C
L
Figure 5-40. Full-Speed Loads
5.18 ADC Timings
Table 5-42 assumes testing over recommended operating conditions.
Table 5-42. ADC Characteristics
CVDD = 1.2 V
CVDD = 1.35 V
CVDD = 1.6 V
NO.
UNIT
MIN
MAX
MIN
500
MAX
A1
A2
A3
tc(SCLC)
td(AQ)
Cycle time, ADC internal conversion clock
500
ns
Delay time, ADC sample and hold acquisition
time
40
40
μs
td(CONV)
Delay time, ADC conversion time
Static differential non–linearity error
Static integral non–linearity error
Zero–scale offset error
13 * tc(SCLC)
13 * tc(SCLC)
ns
2
3
9
9
2
3
9
9
A4
SDNL
LSB
A5
A6
A7
Zset
Fset
LSB
LSB
MW
Full–scale offset error
Analog input impedance
1
1
104
Electrical Specifications
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
SM320VC5507-EP
www.ti.com
SPRS613–SEPTEMBER 2009
6
Mechanical Data
6.1 Package Thermal Resistance Characteristics
Table 6-1 and Table 6-2 provide the estimated thermal resistance characteristics for the SM320VC5507
DSP package types.
Table 6-1. Thermal Resistance Characteristics (Ambient)
(1)
PACKAGE
R
ΘJA (°C/W)
BOARD TYPE
High–K
High–K
High–K
High–K
Low–K
AIRFLOW (LFM)
71.2
0
61.8
150
250
500
0
58.9
54.8
PGE
103.6
84.2
Low–K
150
250
500
77.8
Low–K
69.4
Low–K
(1) Board types are as defined by JEDEC. Reference JEDEC Standard JESD51-9, Test Boards for Area Array Surface Mount Package
Thermal Measurements.
Table 6-2. Thermal Resistance Characteristics (Case)
(1)
PACKAGE
RΘJA (°C/W)
BOARD TYPE
PGE
13.8
2s JEDEC Test Card
(1) Board types are as defined by JEDEC. Reference JEDEC Standard JESD51-9, Test Boards for Area Array Surface Mount Package
Thermal Measurements.
6.2 Packaging Information
The following packaging information reflects the most current released data available for the designated
device(s). This data is subject to change without notice and without revision of this document.
Copyright © 2009, Texas Instruments Incorporated
Mechanical Data
105
Submit Documentation Feedback
Product Folder Link(s): SM320VC5507-EP
PACKAGE OPTION ADDENDUM
www.ti.com
5-Oct-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SM320VC5507PGESEP
ACTIVE
LQFP
PGE
144
60 Green (RoHS & CU NIPDAU Level-4-260C-72 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
M
0,08
0,17
0,50
0,13 NOM
144
37
1
36
Gage Plane
17,50 TYP
20,20
SQ
19,80
0,25
0,05 MIN
22,20
SQ
0°–7°
21,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147/C 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
www.ti.com/audio
Data Converters
DLP® Products
Automotive
www.ti.com/automotive
www.ti.com/communications
Communications and
Telecom
DSP
dsp.ti.com
Computers and
Peripherals
www.ti.com/computers
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
Consumer Electronics
Energy
www.ti.com/consumer-apps
www.ti.com/energy
Logic
Industrial
www.ti.com/industrial
Power Mgmt
Microcontrollers
RFID
power.ti.com
Medical
www.ti.com/medical
microcontroller.ti.com
www.ti-rfid.com
Security
www.ti.com/security
Space, Avionics &
Defense
www.ti.com/space-avionics-defense
RF/IF and ZigBee® Solutions www.ti.com/lprf
Video and Imaging
Wireless
www.ti.com/video
www.ti.com/wireless-apps
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2010, Texas Instruments Incorporated
相关型号：
V62/10603-01XE
3.0-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER SERIAL ANALOG-TO-DIGITAL CONVERTER WITH AUTOPOWER-DOWN
TI
V62/10604-01XE
All-Format Oversampled Component Video/PC Graphics D/A System With Three 11-Bit DACs, CGMS Data Insertion
TI
©2020 ICPDF网 联系我们和版权申明