TB6571FG_技术文档

TB6571FG

TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic

TB6571FG

3-Phase Full-Wave Brushless Motor Controller

Featuring Speed Control and Sine Wave PWM Drive

The TB6571FG is a 3-phase full-wave brushless motor

controller IC that employs a sine wave PWM drive mechanism

with a speed control function.

Sine wave current driving with 2-phase modulation enables the

IC to drive a motor with high efficiency and low noise.

It also incorporates a speed control circuit that can vary the

motor speed using to an external clock.

Features

Weight: 0.50 g (typ.)

•

Sine wave PWM drive

2-phase modulation with low switching loss

Triangular wave generator

Dead time function

Speed control function

External clock input

Speed discrimination + PLL speed control circuit

Ready circuit output

FG amplifier

Automatic lead angle correction

Forward/stop/reverse/brake functions

Current limiter

Lock protection

TB6571FG:

TB6571FG is a Pb-free product.

The following conditions apply to solderability:

*Solderability

1. Use of Sn-63Pb solder bath

*solder bath temperature = 230°C

*dipping time = 5 seconds

*number of times = once

*use of R-type flux

2. Use of Sn-3.0Ag-0.5Cu solder bath

*solder bath temperature=245°C

*dipping time = 5 seconds

*the number of times = once

*use of R-type flux

z

This product has a MOS structure and is sensitive to electrostatic discharge. When handling the product,

ensure that the environment is protected against electrostatic discharge by using an earth strap, a

conductive mat and an ionizer. Ensure also that the ambient temperature and relative humidity are

maintained at reasonable levels.

Install the product correctly. Otherwise, breakdown, damage and/or degradation in the product or

equipment may result.

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TB6571FG

Pin Functions

Pin No.

Name

Pin Functions

Remarks

1

2

LC (L1)

NC

Phase-C energization signal output (L1)

No connection

For source driving for phase-C output FET gate (lower N-ch)

3

HA+

Phase-A hall signal input + pin

Phase-A hall signal input - pin

Phase-B hall signal input + pin

Phase-B hall signal input - pin

Phase-C hall signal input + pin

Phase-C hall signal input - pin

FG amplifier input + pin

Input the positive phase-A Hall device signal.

Input the negative phase-A Hall device signal.

Input the positive phase-B Hall device signal.

Input the negative phase-B Hall device signal.

Input the positive phase-C Hall device signal.

Input the negative phase-C Hall device signal.

FG signal input

4

HA−

5

HB+

6

HB−

7

HC+

HC−

FGin+

FGin−

FGo

8

9

10

11

12

13

14

15

16

FG amplifier input - pin

FG signal input

FG amplifier output pin

CW/CCW Forward/reverse switching pin

H: Reverse/L: Forward

BRAKE

START

Fref

Brake

Pull-up resistor, L for braking (all-phase ON for lower circuit)

Pull-up resistor, L for start, H for standby

Pull-up resistor

Start

External clock input

FG hysteresis comparator output pin

FGS

Open collector output, I = 1 mA (max)

O

Open collector output.

Within ±6%: L, Otherwise: High impedance

17

Ready

Vref1

Ready output pin

18

19

20

21

22

5-V reference power supply

5-V output. Connect to GND through a capacitor.

Connect a resistor.

PLL-GAIN PLL gain adjustment pin

S-GND

CP

Ground pin

Charge pump pin for speed control

Capacitor pin for VCO

Connect to GND through a capacitor.

VCO

Frequency setting pin 1 for internal

reference clock

23

24

Td1

Td2

Connect external CR to generate a reference clock.

Frequency setting pin 2 for internal

reference clock

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

LP1

L1

For LPF

Lead angle correction circuit

Oscillation pin for lock protection circuit

Internal logic power supply pin

8-V reference power supply

Ground pin

Connect an external capacitor.

L2

Connect an external resistor for adjusting the correction gain.

Connect to GND through a capacitor.

L3

CLd

VDD

Vref2

P-GND

CP1

CP2

CP3

VCC

Idc2

5-V output. Connect to GND through a capacitor.

8-V output. Connect to GND through a capacitor.

Charge pump pin

For generating upper N-ch FET gate voltage

Charge pump pin

Voltage input pin for control power supply

V

(opr.) = 10~28 V

CC

Input pin for output current detection signal GND sense pin

Idc1

Input pin for output current detection signal Gate block operation when 0.25 V (typ.) or higher

LA (U1)

LA (U2)

Phase-A energization signal output (U1)

Phase-A energization signal output (U2)

For source driving for phase-A output FET gate (upper N-ch)

For sink driving for phase-A output FET gate (upper N-ch)

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TB6571FG

Pin No.

Name

Pin Functions

Phase-A motor pin

Remarks

41

42

43

44

45

46

47

48

49

50

51

52

OUT-A

LA (L2)

LA (L1)

LB (U1)

LB (U2)

OUT-B

LB (L2)

LB (L1)

LC (U1)

LC (U2)

OUT-C

LC (L2)

Phase-A energization signal output (L2)

Phase-A energization signal output (L1)

Phase-B energization signal output (U1)

Phase-B energization signal output (U2)

Phase-B motor pin

For sink driving for phase-A output FET gate (lower N-ch)

For source driving for phase-A output FET gate (lower N-ch)

For source driving for phase-B output FET gate (upper N-ch)

For sink driving for phase-B output FET gate (upper N-ch)

Phase-B energization signal output (L2)

Phase-B energization signal output (L1)

Phase-C energization signal output (U1)

Phase-C energization signal output (U2)

Phase-C motor pin

For sink driving for phase-B output FET gate (lower N-ch)

For source driving for phase-B output FET gate (lower N-ch)

For source driving for phase-C output FET gate (upper N-ch)

For sink driving for phase-C output FET gate (upper N-ch)

Phase-C energization signal output (L2)

For sink driving for phase-C output FET gate (lower N-ch)

Pin Layout

39 38 37 36 35 34 33 32 31 30 29 28 27

LA(U2) 40

OUT-A 41

LA(L2) 42

LA(L1) 43

LB(U1) 44

LB(U2) 45

OUT-B 46

LB(L2) 47

LB(L1) 48

LC(U1) 49

LC(U2) 50

OUT-C 51

LC(L2) 52

26 L1

25 LP1

24 Td2

23 Td1

22 VCO

21 CP

20 S-GND

19 PLL_Gain

18 Vref1

17 Ready

FGS

16

15 Fref

14 START

1

2

3

4

5

6

7

8

9

10 11 12 13

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TB6571FG

Maximum Ratings (Ta = 25°C)

Characteristics

Symbol

Rating

Unit

Supply voltage

Input voltage

V

30

5.5

V

CC

V

(Note 1)

(Note 2)

(Note 3)

(Note 4)

(Note 5)

(Note 6)

IN

5.5

Output voltage

Output current

V

OUT

40

20

I

mA

OUT

10

Power dissipation

P

1.3

W

°C

D

Operating temperature

Storage temperature

T

−30~85

−55~150

opr

T

stg

Note 1: CW/CCW, STB,START,BRAKE, Idc,Fref

Note 2: Ready, FGS

Note 3: LA (U), LB (U), LC (U)

Note 4: LA (U), LB (U), LC (U), LA (L), LB (L), LC (L)

Note 5: Vref1

Note 6: When mounted on the board

(glass epoxy, 50 mm × 50 mm × 1.6 mm, copper foil 36%, thickness = 18 µm, single-sided)

The absolute maximum ratings of a semiconductor device are a set of specified parameter values, which must not

be exceeded during operation, even for an instant.

If any of these rating would be exceeded during operation, the device electrical characteristics may be irreparably

altered and the reliability and lifetime of the device can no longer be guaranteed.

Moreover, these operations with exceeded ratings may cause break down, damage and/or degradation to any other

equipment. Applications using the device should be designed such that each maximum rating will never be exceeded

in any operating conditions.

Before using, creating and/or producing designs, refer to and comply with the precautions and conditions set forth in

this documents.

Operating Conditions (Ta = 25°C)

Characteristics

Symbol

Rating

Unit

Supply voltage

External clock frequency

V

10~28

V

CC

Fref

200~2 k

Hz

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TB6571FG

Functional Description

The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purpose.

Sine Wave PWM Drive

Upon start-up, the TB6571FG drives the motor with square waves for 120° energization using phase

detection signals (hall device signals).

If the frequency (f) of the position detection signal (hall device signal) for a single phase exceeds the

specified value (f ), the TB6571FG switches to 180° energization.

H

The following formula determines: f = fx1 / (2¹⁰× 32 × 6)

H

fx1: The system clock frequency (fx1) is obtained by multiplying the external clock frequency (fref).

fx 1 = 4 × 1024 × fref

Thus, a transition from 120° energization to 180° energization occurs according to the external clock

frequency.

Mode Table

Rotation State

Drive Mode

f

> f

< f

Square wave drive (120°energization)

Sine wave PWM drive (180°energization)

H

Phase-A

Counter

LA (U)

LA (L)

PLL (frequency

multiplication)

Position signal

Phase-B

LB (U)

LB (L)

Phase alignment

(A, B, C)

Phase-

C

Sine wave pattern

(modulation signal)

Comparator

Frequency multiplication

of external clock

LC (U)

LC (L)

Speed control

signal

Triangular wave

(carrier frequency)

Generate internal

reference clock

C/R

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TB6571FG

The TB6571FG uses position detection signals to create modulation waveforms, which it compares with

triangular waves to generate sine wave PWM signals.

It counts the time between zero-crossing points for the three position detection signals (electrical angle:

60°) and uses the time as data for the next 60° phase of the modulation waveforms.

A 60° phase part of a modulation waveform consists of 32 data items. The time width for a single data

item in a 60° phase part is 1/32 of that for the preceding 60° phase part. The modulation waveform

proceeds with that width.

HA

(6)

(1)

(3)

* HA, HB, HC: Hall amplifier

HB

(5)

(2)

HC

(6)’

(1)’

(2)’

(3)’

S

A

B

S

C

In the above chart, the time between HA rising and HC falling is marked (1). The modulation waveform

within the (1)' period proceeds with a width that is 1/32 of (1). In the same way, the waveform within the

(2)' period proceeds with 1/32 of (2), which is the time between HC falling and HB rising.

If next zero-crossing does not take place appear after 32 data items, the next 32 data items proceed with

the same time width until next zero-crossing occurs.

*t

32

31

30

6

5

4

3

2

1

S

B

(1)’

32 data item

* t = t (1) × 1/32

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TB6571FG

In addition, the TB6571FG performs phase alignment with the modulation waveforms at each

zero-crossing in the position detection signals.

For every 60° of electrical angle, it synchronizes with the rising and falling edges of the position detection

signals (Hall amplifier output signals), thus resetting the modulation waveforms.

If zero-crossing timing is shifted in position detection signals, causing next zero-crossing to occur before

32 data items are reached for the 60° phase, the data is reset and data for the next 60° phase is started.

In that case, the modulation waveforms become discontinuous at a reset.

HA

HB

HC

3

(1)

(2)

2

1

31

30

29

28

4

3

2

1

S

B

Reset

(1)’

Operating Waveforms for Sine wave PWM Drive

Modulation signal

Carrier frequency

2.7 V

(typ.)

Phase-A

(inside IC)

GND

V

CC

V

A

B

C

GND

voltage

V

CC

V

GND

V

CC

V

GND

Line-to-line

voltage

V

AB

(V − V )

A

B

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TB6571FG

Timing Charts

HA

HB

HC

Position

detection

(Hall amplifier

output)

LA (U)

LB (U)

LC (U)

LA (L)

LB (L)

LC (L)

Energization

signal output

when driven

with square

wave

S

A

B

C

Modulation

waveform when

driven with sine

wave (inside IC)

S

Forward rotation

Position

HA

HB

HC

detection

(Hall amplifier

output)

LA (U)

LB (U)

LC (U)

LA (L)

LB (L)

LC (L)

Energization

signal output

when driven

with square

wave

S

A

B

C

Modulation

waveform when

driven with sine

wave (inside IC)

S

Reverse rotation

* HA, HB, HC: Hall amplifier outputs

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TB6571FG

Generating an Internal Reference Clock

The TB6571FG uses external C and R to generate a reference clock internally.

It uses the reference clock to generate triangular waves, which determine the carrier frequency, and set a

dead time.

The clock also functions as a reference clock for the charge pump (booster) and lead angle circuit ADC.

Generating Triangular Waves

The TB6571FG compares the modulation waveforms with triangular waves to generate PWM signals.

The carrier frequency for PWM control depends on the frequency of the triangular waves.

The triangular waves are switched according to the internal reference clock frequency.

The following formula obtains the PWM frequency, where fx2 is the internal reference clock frequency:

PWM frequency fpwm = fx2/252 (= triangular wave frequency)

For example: When fx2 = 5 MHz: fpwm = 19.8 kHz

When fx2 = 4 MHz: fpwm = 15.8 kHz

When fx2 = 3 MHz: fpwm = 11.9 kHz

Dead time Setup Circuit

To apply PWM control with synchronous regeneration for output FETs, the TB6571FG sets a dead time for

energization signal outputs, thus preventing the upper and lower output power FETs from turning on

simultaneously.

It uses the internal reference clock, generated from external CR, to set a dead time.

Dead Time

LA (U)

(LB (U), LC (U) )

TOFF

LA (L)

(LB (L), LC (L) )

The following formula obtains the dead time, where fx2 is the internal reference clock frequency:

Dead time td = (1/fx2) × 4

For example: When fx2 = 5 MHz: td = 0.8 µs

When fx2 = 4 MHz: td = 1.0 µs

When fx2 = 3 MHz: td = 1.3 µs

Charge Pump

The TB6571FG incorporates a charge pump to drive two N-ch FETs in the external output FET configuration,

in particular, to generate the gate voltage for the upper N-ch FET.

The booster voltage is V

CC

+ 8.0 V and the upper gate drive voltage is V + 7.75 V.

CC

The charge pump boosts the voltage using a frequency that is 1/16 of the internal reference clock frequency, fx2

(250 kHz when fx2 = 4 MHz).

Motor Output Pins

During PWM operation, the source voltage for the upper external N-ch FET swings between GND and VM.

VGS for the Nch-FET is clamped so that it does not exceed VGS (max) = 20 V.

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TB6571FG

External FET Gate Drive Output

The output for driving the upper FET is divided into two pins

so that resistor adjustment is enabled only for gate driving

(sourcing), thus reducing impedance for extraction.

The output for driving the lower FET is also divided.

The upper FET is driven with the LA(U1) pin on the source

and the LA(U2) pin on the sink. The lower FET is driven with

LA(L1) on the source and LA(L2) on the sink.

LA(U1)

LA(U2)

Upper FET

OUT-A

LA(L1)

LA(L2)

Lower FET

Speed Control

Phase

comparator

LPF

VCO

1/1024

1/4

frequency

divider

frequency

divider

Sine wave system clock

Speed

discriminator

1024

Charge

pump

Control

amplifier

Fref signal

FG signal

PLL

CP

PLL-Gain

5V

FG

amplifier

•

The TB6571FG uses a speed discriminator and PLL to control speed.

The speed discriminator has two counter stages, each of which alternately counts a single period of the FG

signal. The resulting difference signal is output as two signals (charge pulses and discharge pulses).

•

The PLL counts the phase difference between the 1/2 FG signal and reference signal. The resulting

difference signal is output as two signals (charge pulses and discharge pulses). The phase difference is

assumed to be zero when the FG frequency is outside the lock range (±6% of the specified value).

•

The gain ratio between the speed discriminator and PLL is set using an external resistor.

The total gain is set using an external constant for the charge pump.

VCO PLL

The maximum guaranteed range for the VCO oscillation frequency is a quadruple width, with a single

external constant as a condition.

•

FG frequency = speed control clock/speed discriminator

→ Speed control clock = FG frequency × speed discriminator

FG frequency = 200 to 2 k, speed discriminator = 1024

Speed control clock = 0.2048 to 2.048 MHz

System clock = speed control clock × 4

= 0.8192 to 8.192 MHz

•

When the Fref input is open, the output is turned off.

Note that a sudden variation in rotation speed may cause a motor current to be regenerated into the power

supply, resulting in the rise of the motor voltage.

(Note)

When the system clock is saturated, a READY signal may remain being L output even if external clock

•

frequency and FG frequency shift. Please confirm optimization of a VCO system PLL circuit

constant(25pin,22pin).

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TB6571FG

Charge Pump

Speed discriminator

PLL

V

DD

Charge

signal

Charge

signal

I2

I1

CP

To control

amplifier

Discharge signal

I1

•

The charge pump consists of MOS transistors, which enable fast switching, thus allowing control with

higher resolution.

For the speed discriminator and PLL gains, the ratio of the charge/discharge current is specified using an

external resistor (PLL-Gain).

The charge/discharge current for the speed discriminator, I1, is 100 µA (typ.) and the PLL

charge/discharge current, I2, can be specified using the external PLL-Gain voltage.

PLL-Gain-Gcharacteristics

PLL ain特性

20

18

16

14

12

10

8

6

4

2

0

1

2

3

4

5

ＰＬＬ-ＧＡＩＮ入力電圧

PLL-Gain input voltage

•

The charge pump is placed in discharge mode upon stop or braking.

Because the external capacitance becomes zero upon stop or braking, the charge-up time upon start is

constant, so that the time required for the motor to start is also stable.

Upon start, the charge pump is forcibly charged.

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TB6571FG

Control amplifier

V

ref

V

DD

CP

• The voltage integrated in the charge pump is input to the control amplifier.

The input is placed in high-impedance state because it is a P-ch gate.

• The control amplifier circuit has an offset of 0.45 V (typ.). If the CP pin voltage exceeds the offset value,

the energization signal outputs become active. It incorporates a clamp circuit that saturates the PWM

duty ratio for the energization signal outputs when the CP pin voltage becomes 2.7 V (typ.).

100

0.45

2.7

VCP (V)

• The PWM duty ratio indicates the value at the peak of the modulation waveform. A duty ratio of 100%

indicates that the peak value coincides with the peak of the triangular wave.

(PWM duty ratio: 100%)

Triangular wave

Modulation waveform

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TB6571FG

FG amplifier/hysteresis comparator

V

ref

V

ref

V

CC

V

CC

V

CC

+

−

FGin

FGS

FGo

• The FG amplifier supports pattern FG and incorporates an internal reference voltage of 2.5 V.

Entering a sine wave of 50 mVpp or greater results in a signal multiplied by the gain being output.

The open loop gain is 45 dB (min) (design target value).

• The FG amplifier is followed by a hysteresis comparator, which compares the FG output and delivers it to

the FGS.

The comparator has a single-side hysteresis of 200 mV for the 2.5 V reference voltage. The square wave

signal output from the FGS enters the internal counter.

• The FGO output dynamic range is as follows:

1.0 V~V −1.0 V at IFGO = ±200 µA

ref

2.7 V (typ.)

2.5 V (typ.)

200 mV (typ.)

FGO

FGS

• The FGS has an open-collector output. Connect a pull-up resistor considering the following characteristics.

The input current is 1 mA (max).

VFGS = 0.7 V (max) at IFGS = 1 mA

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TB6571FG

Hall amplifier

V

ref

V

CC

+

−

HA

• The Hall amplifier accepts Hall device output signals. If input signals contain noise, connect a capacitor

between inputs.

• The common-mode input voltage range is: VCMRH = 1.5 to 3.5 V.

The Hall amplifier has an input hysteresis of ±8 mV(typ).

• The Hall amplifier converts Hall device signals into square waves, which then enter the internal logic.

• If positive/negative inputs are open, all external MOS FETs is turned off.

Ready circuit

• The Ready circuit indicates the motor rotation speed state using two states (L and HZ) of an open-collector

output.

When the motor is rotating, the circuit counts FG signals and outputs the following states according to

whether the frequency is within or outside ±6% of the specified value:

• Within ±6% of motor rotation speed: L output

• Outside ±6% of motor rotation speed: HZ (high impedance)

• Connect a pull-up resistor to the Ready output pin. Determine the resistance considering the following

characteristics. The input current is 2 mA (max).

VCER = 0.5 V (max) at IR = 2 mA

V

CC

V

DD

Ready

(Note)

•

When the system clock is saturated, a READY signal may remain being L output even if external clock

frequency and FG frequency shift. Please confirm optimization of a VCO system PLL circuit

constant(25pin,22pin).

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TB6571FG

Forward/reverse rotation circuit

V

DD

CW/CCW

The circuit accepts a TTL input and incorporates a pull-up resistor.

CW/CCW Input

Mode

H

L

Reverse

Forwared

+

Forward: Hall device signals HA → HB → HC

Note that abrupt switching between forward and reverse rotation may result in an output FET being damaged

due to reverse torque.

Start circuit

V

DD

START

The circuit accepts a TTL input and incorporates a pull-up resistor.

START Input

Mode

H

L

Stop

Start

Brake

V

DD

BRAKE

The circuit accepts a TTL input and incorporates a pull-up resistor.

BRAKE Input

Mode

H

L

OPERATION

BRAKE

Note that abrupt braking from high-speed rotation may result in an output FET being damaged.

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TB6571FG

Operation sequence

VM power supply

Vref power

supply (+5 V)

V

power

DD

supply (+5 V)

V1 power

supply (+8 V)

Internal reference

clock fx2

Output charge

pump voltage

External reference

clock fref

System clock fx1

(fref multiplied)

PLL lockup time

START signal

Rotate

Stop

Rotate

Brake

BRAKE signal

START 信号

BRAKE 信号

Mode

Description

H

Ｌ

L

H or L

Ｈ

Stop

Rotate

Brake

Turn all external FETs off.

Energize

Ｌ

Turn all lower external FETs on.

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TB6571FG

Automatic phase lead angle correction circuit

・ The circuit corrects the lead angle using the motor current value.

Automatic lead angle correction

Motor current

Peak

hold

Amp.

A-D conversion

Gain x VRF

(peak)

VRF

LA 値

RF

R4

C2

R3

R2

*)Gain = (R2+R3) / R2

VRF

Gain x VRF

(peak)

Gain x VRF

V

Î

LA value

Î

[

T

• The circuit can advance the phase of an energization signal relative to the induced voltage for input of

0 to 2.5 V (16 steps).

0 V → 0°

2.5 V → 29°(29° for an input voltage higher than 2.5 V)

58°

29°

5.4°

0°

2.5 V

LA

0

5 V

・

The circuit clamps the lead angle at 29°.

It logically clamps the angle between 0° and 29°, rather than clamping the input voltage.

Lock protection circuit

• The circuit turns the output power FET off if the motor is locked.

• It turns off both upper and lower output power FETs if it detects the Ready signal with the following

condition satisfied.

The circuit latched state is terminated once the TB6571FG is placed in the stop or brake state.

Detected signal

Ready signal

Condition for triggering lock protection

The Ready signal output remains high

for at least 5.5 seconds (typ.).

• A reference oscillation waveform for lock protection is generated using an external capacitor connected

to the CLD pin and counted with the internal 5-bit counter.

• When CLD = 0.1 µF, the oscillation frequency is approximately 25 Hz, so that the lock protection

triggering time is 5.5 seconds (typ.).

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TB6571FG

Constant voltage circuit

(1) Vref1

• The circuit creates 5 V for biasing the internal analog circuit and outputs it from the Vref pin.

Connect a capacitor (0.1 µF to 1 µF) between the Vref pin and L-GND to prevent oscillation and

absorb noise.

The output load current is 10 mA.

Vref = 5 V (typ.) ± 0.5 V at Io = 10 mA

(2)

V

DD

• The circuit outputs 5 V for biasing the internal logic circuit from the V

pin.

DD

pin and L-GND to prevent oscillation

Connect a capacitor (1 µF recommended) between the V

DD

and absorb noise.

Connect no load to the V

DD

pin.

(3) Vref2

• The circuit creates 8 V for output FET gate driving and outputs it from the Vref2 pin.

Connect a capacitor (1 µF or larger) between the Vref2 pin and L-GND to prevent oscillation and

absorb noise.

Overcurrent protection circuit

V

ref

V

CC

Idc

• The circuit turns the external output power FET off if the detected voltage is higher than 0.25 V (typ.).

It re-activates the FET according to the carrier frequency.

Note that the Idc pin accepts a direct analog comparator input and is highly sensitive. Use C and R,

therefore, for filtering so that output current noise due to chopping does not activate the overcurrent

protection circuit.

Power supply monitor circuit

The circuit monitors the Vref and Vcc voltages and turns the external power FET off if any of the following

conditions are satisfied:

V

CC

(H) ≤ 9 V, V (L) ≤ 8.5 V, Vref1 (H) ≤ 4.5 V, Vref1 (L) ≤ 4.0 V

CC

Thermal shutdown circuit

The circuit turns the external output power FET off if the junction temperature TSD (ON) exceeds 160°C.

The thermal shutdown state is terminated once the TB6571FG is placed in the stop or brake state.

19

2005-04-15

TB6571FG

Electrical characteristics (V = 24 V, Ta = 25°C)

CC

Test

Circuit

Characteristics

Symbol

Test conditions

Min

Typ.

Max

Units

I

Start

Stop

6.0

12.0

9.0

18.0

12.6

CC1

CC2

Supply current

ｍΑ

5.4

Common-mode input

voltage range

VCMRH

1.5



3.5

V

Hall

amplifier

Input amplitude range

Input hysteresis

Input current

VH

VhysH

IinH

50

± 4



± 8



± 12

1

mVpp

mV



(Design target value)

VCMRH = 2.5 V, 1-phase

µA

Open collector output,

ICER = 2 mA

Remaining output voltage

VCER



0.5

V

Ready

circuit

Output leakage current

Input offset voltage

ILR

Vready = 6 V



1

µA

VOSFG

± 7

mV

Remaining output voltage

(upper)

Vref1

−1.2

VOFG (H)

VOFG (L)

IFG = 100 µA (source current)

IFG = 100 µA (sink current)



Vref1

1.2

FG

amplifier

V

Remaining output voltage

(lower)



Vref1/

2

Reference voltage

Hysteresis width

VrefFG

VhysS

VCES

VLS

2.2

0.15



2.8

0.25

0.5

1

V

0.2



FG

hysteresis

comparat-

or

Open collector output,

ICES = 1 mA

Remaining output voltage

Output leakage current

Input voltage (H)

V

VFGS = 6 V



µA

CW/CCW, STB, BRAKE,

START

Vin(H)

2.0

5.5

V

Control

input

circuit

CW/CCW, STB, BRAKE,

START

Input voltage (L)

Vin(L)

0



0.8

Input current (H)

Input current (L)

Input voltage (H)

Input voltage (L)

Input current (H)

Input current (L)

IinCW (H)

IinCW (L)

VinSB (H)

VinSB (L)

Iin (H)

Vin = 5 V

Vin = GND

Fref



70

2.0

0



100



1

µA

130

5.5

0.8

1

V

Fref



Fref input

circuit

Vin = 5 V

Vin = GND



70



µA

Iin (L)

100

130

V

+

V

+

V

+

CC

7

CC

8

CC

9

Charge pump voltage

VG

V

VG

−1.0

VO (U)-(H)



VG

LA (U)/LB (U)/LC (U),

Io = 20 mA

VO (U)-(L)

VO (L)-(H)

VO (L)-(L)



7.25



0.5

8.25

0.5

Energization signal output voltage

V

7.75



LA (L) /LB (L) /LC (L),

Io = 20 mA

V

4.5

8.2

5.0

8.7

5.5

DD

Internal supply voltage output

Vref1

Vref2

5.5

9.2

Current limiter circuit reference

voltage

Vdc

0.23

0.25

0.27

V

Internal clock frequency

fx2

R=10ｋΩ,C=51pF

3.4

1.2

3.8

1.7

4.2

2.2

MHz

TOFF1

TOFF2

Dead time

µs

Phase lead angle

controller

Upper clamp limit

ACLH



29



°

20

2005-04-15

TB6571FG

Test

Circuit

Characteristics

Symbol

Test conditions

Min

Typ.

Max

Units

Rising voltage

Saturation voltage

Input current

VCR

VCLP

IinCP

0.3

2.7



0.5

2.85

0

0.6

3.0



V

Control

amplifier

µA

(source current), Vcp = 3.1 V,

V(PLL-GAIN)＝0V

Charge current

Icp +

Icp −

70

100

150

Charge

pump

µA

(sink current), Vcp = 0.35 V,

V(PLL-GAIN)＝0V

Discharge current

Reference clock

frequency

CLd = 0.1 µF

Lock

protection

circuit

FLd

tLd

17.5

4.2

25

30

Hz

s

Operating time

5.5

7.0

21

2005-04-15

TB6571FG

Package Dimensions

Weight: 0.0 g (typ.)

22

2005-04-15

TB6571FG

RESTRICTIONS ON PRODUCT USE

030619EBA

• The information contained herein is subject to change without notice.

• The information contained herein is presented only as a guide for the applications of our products. No

responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which

may result from its use. No license is granted by implication or otherwise under any patent or patent rights of

TOSHIBA or others.

• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor

devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical

stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of

safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of

such TOSHIBA products could cause loss of human life, bodily injury or damage to property.

In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as

set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and

conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability

Handbook” etc..

• The TOSHIBA products listed in this document are intended for usage in general electronics applications

(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,

etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires

extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or

bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or

spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,

medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this

document shall be made at the customer’s own risk.

• The products described in this document are subject to the foreign exchange and foreign trade laws.

• TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced

and sold, under any law and regulations.

23

2005-04-15


型号：	TB6571FG
厂家：	TOSHIBA
描述：	IC BRUSHLESS DC MOTOR CONTROLLER, 20 A, PQFP52, 10 X 10 MM, 0.65 MM PITCH, ROHS COMPLIANT, PLASTIC, QFP-52, Motion Control Electronics 电动机控制信息通信管理
文件：	总23页 (文件大小：216K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TB6571FG [TOSHIBA]

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