RF1K4915796 [ETC]
TRANSISTOR | MOSFET | N-CHANNEL | 30V V(BR)DSS | 6.3A I(D) | SO ; 晶体管| MOSFET | N沟道| 30V V（ BR ） DSS | 6.3AI （ D） | SO\n
| 型号： | RF1K4915796 |
| 厂家： | 
ETC |
| 描述： | TRANSISTOR | MOSFET | N-CHANNEL | 30V V(BR)DSS | 6.3A I(D) | SO
|
| 文件： | 总8页 (文件大小：271K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RF1K49157
Data Sheet
January 2002
6.3A, 30V, 0.030 Ohm, Single N-Channel
LittleFET™ Power MOSFET
Features
• 6.3A, 30V
• r = 0.030Ω
This Single N-Channel power MOSFET is manufactured
using an advanced MegaFET process. This process, which
uses feature sizes approaching those of LSI integrated
circuits, gives optimum utilization of silicon, resulting in
outstanding performance. It was designed for use in
applications such as switching regulators, switching
convertors, motor drivers, relay drivers, and low voltage bus
switches. This device can be operated directly from
integrated circuits.
DS(ON)
• Temperature Compensating PSPICE™ Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Formerly developmental type TA49157.
Symbol
Ordering Information
NC (1)
DRAIN (8)
DRAIN (7)
PART NUMBER
PACKAGE
BRAND
RF1K49157
RF1K49157
MS-012AA
SOURCE (2)
NOTE: When ordering, use the entire part number. For ordering in tape
and reel, add the suffix 96 to the part number, i.e., RF1K4915796.
SOURCE (3)
GATE (4)
DRAIN (6)
DRAIN (5)
Packaging
JEDEC MS-012AA
BRANDING DASH
5
1
2
3
4
©2002 Fairchild Semiconductor Corporation
RF1K49157 Rev. B
RF1K49157
o
Absolute Maximum Ratings
T = 25 C Unless Otherwise Specified
A
RF1K49157
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
30
30
V
V
V
DSS
DGR
Drain to Gate Voltage (R
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
±20
GS
Drain Current
Continuous (Pulse width = 1s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
6.3
A
D
Pulsed (Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Refer to Peak Current Curve
Refer to UIS Curve
DM
Pulsed Avalanche Rating (Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Power Dissipation
o
T
= 25 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
2
W
A
D
o
o
Derate Above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.016
W/ C
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T
J
-55 to 150
C
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44T
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
o
300
260
C
C
L
o
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
o
o
1. T = 25 C to 125 C.
J
o
Electrical Specifications
T = 25 C, Unless Otherwise Specified
A
PARAMETER
SYMBOL
BV
TEST CONDITIONS
= 250µA, V = 0V, (Figure 12)
MIN
TYP
MAX
UNITS
V
Drain to Source Breakdown Voltage
Gate Threshold Voltage
I
30
1
-
-
-
-
DSS
D
GS
V
V
= V , I = 250µA, (Figure 11)
3
V
GS(TH)
GS
DS D
o
Zero Gate Voltage Drain Current
I
V
V
= 30V,
= 0V
T
T
= 25 C
-
1
µA
µA
nA
Ω
DSS
DS
GS
A
o
= 150 C
-
-
50
A
Gate to Source Leakage Current
Drain to Source On Resistance
I
V
= ±20V
-
-
±100
GSS
GS
r
I
= 6.3A
(Figures 9, 10)
V
= 10V
-
-
0.030
DS(ON)
D
GS
GS
V
= 4.5V
-
-
0.060
Ω
Turn-On Time
t
V
= 15V, I ≈ 6.3A,
-
-
85
ns
ON
DD
D
R
R
= 2.38Ω, V = 10V,
L
GS
Turn-On Delay Time
Rise Time
t
-
22
43
125
85
-
-
ns
d(ON)
= 25Ω
GS
t
-
-
-
ns
r
Turn-Off Delay Time
Fall Time
t
-
ns
d(OFF)
t
-
-
ns
f
Turn-Off Time
t
-
265
88
48
3.5
-
ns
OFF
Total Gate Charge
Gate Charge at 10V
Threshold Gate Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Q
V
V
V
V
= 0V to 20V
= 0V to 10V
= 0V to 2V
V = 24V,
DD
-
70
38
2.8
1575
700
200
-
nC
nC
nC
pF
pF
pF
g(TOT)
GS
GS
GS
DS
I
= 6.3A,
D
Q
-
g(10)
g(TH)
R
= 3.81Ω
L
(Figure 14)
Q
-
C
= 25V, V
GS
= 0V,
-
ISS
OSS
RSS
f = 1MHz
(Figure 13)
C
C
-
-
-
-
o
Thermal Resistance Junction-to-Ambient
R
Pulse width = 1s
Device mounted on FR-4 material
-
62.5
C/W
JA
θ
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.25
60
UNITS
V
V
I
I
= 6.3A
-
-
-
-
SD
SD
t
= 6.3A, dI /dt = 100A/µs
SD
ns
rr
SD
©2002 Fairchild Semiconductor Corporation
RF1K49157 Rev. B
RF1K49157
Typical Performance Curves
1.2
1.0
0.8
7
6
5
4
3
2
0.6
0.4
0.2
0
1
0
0
25
50
75
100
125
150
25
50
75
100
125
150
o
o
T , AMBIENT TEMPERATURE ( C)
T , AMBIENT TEMPERATURE ( C)
A
A
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
10
1
0.5
P
DM
0.2
0.1
0.1
t
1
t
2
0.05
0.02
0.01
NOTES:
DUTY FACTOR: D = t /t
1
2
SINGLE PULSE
PEAK T = P
x Z
x R
+ T
JA A
J
DM
2
JA
θ
θ
0.01
-3
-2
10
-1
0
1
3
10
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
10
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
100
10
300
o
T
= MAX RATED, T = 25 C
A
V
= 20V
= 10V
o
J
GS
T
= 25 C
A
V
GS
100
10
1
5ms
10ms
THERMAL IMPEDANCE
MAY LIMIT CURRENT
IN THIS REGION
1
100ms
FOR TEMPERATURES
o
0.1
0.01
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
1s
OPERATION IN THIS
AREA MAY BE
150 - T
125
V
= 30V
A
I = I
DSS(MAX)
DC
25
LIMITED BY r
DS(ON)
-5
-4
10
-3
10
-2
-1
0
1
0.1
1
10
100
10
10
10
10
10
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
t, PULSE WIDTH (s)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
©2002 Fairchild Semiconductor Corporation
RF1K49157 Rev. B
RF1K49157
Typical Performance Curves (Continued)
50
If R = 0
50
40
t
= (L)(I )/(1.3*RATED BV
DSS
- V )
DD
AV
If R ≠ 0
= (L/R)ln[(I *R)/(1.3*RATED BV
AS
PULSE DURATION = 80µs
V
= 20V
= 10V
= 7V
GS
DUTY CYCLE = 0.5% MAX
V
V
GS
t
- V ) +1]
DD
o
AV
AS DSS
T
= 25 C
A
GS
V
= 5V
GS
o
10
STARTING T = 25 C
J
30
20
10
0
V
= 4V
GS
o
STARTING T = 150 C
J
1
0.1
1
10
100
0
1
2
3
4
5
t
, TIME IN AVALANCHE (ms)
AV
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE 7. SATURATION CHARACTERISTICS
50
40
250
200
o
o
25 C
V
= 15V
DD
PULSE DURATION = 80µs
-55 C
PULSE DURATION = 80µs
I
= 15A
o
D
DUTY CYCLE = 0.5% MAX
= 15V
150 C
DUTY CYCLE = 0.5% MAX
V
DD
I
= 6.3A
= 3.5A
= 1.75A
D
I
D
I
D
30
20
150
100
50
10
0
0
8
6
10
2
4
0
1.5
3.0
4.5
6.0
7.5
V
, GATE TO SOURCE VOLTAGE (V)
V
, GATE TO SOURCE VOLTAGE (V)
GS
GS
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
2.0
1.5
1.0
2.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= V , I = 250µA
DS
GS
D
V
= 10V, I = 6.3A
GS
D
1.5
1.0
0.5
0
0.5
0
-80
-40
0
40
80
120
160
-80
-40
0
40
80
120
160
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
©2002 Fairchild Semiconductor Corporation
RF1K49157 Rev. B
RF1K49157
Typical Performance Curves (Continued)
2.0
2500
V
= 0V, f = 1MHz
I
= 250µA
GS
ISS
D
C
C
C
= C
+ C
GS
GD
= C
= C
RSS
OSS
GD
DS
2000
1500
1000
+ C
GD
1.5
C
ISS
1.0
0.5
0
C
C
OSS
RSS
500
0
-80
-40
0
40
80
120
160
0
5
V
10
, DRAIN TO SOURCE VOLTAGE (V)
DS
15
20
25
o
T , JUNCTION TEMPERATURE ( C)
J
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
10.0
30
22.5
7.5
V
= BV
DSS
DD
R
= 4.76Ω
L
I
= 0.8mA
G(REF)
15
7.5
0
5.0
V
= 10V
GS
PLATEAU VOLTAGES IN
DESCENDING ORDER:
2.5
0
V
V
V
V
= BV
DD
DD
DD
DD
DSS
= 0.75 BV
= 0.50 BV
= 0.25 BV
DSS
DSS
DSS
I
I
G(REF)
G(REF)
t, TIME (µs)
20---------------------
80---------------------
I
I
G(ACT)
G(ACT)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t TO OBTAIN
P
AS
+
-
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
AS
0V
0.01Ω
t
AV
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
©2002 Fairchild Semiconductor Corporation
RF1K49157 Rev. B
RF1K49157
Test Circuits and Waveforms (Continued)
t
t
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
r
V
DS
90%
90%
R
L
+
10%
10%
0
0
V
DD
R
G
-
90%
50%
DUT
V
GS
50%
PULSE WIDTH
10%
V
GS
FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
FIGURE 17. SWITCHING TIME TEST CIRCUIT
V
DS
V
Q
DD
g(TOT)
R
L
V
DS
V
= 20V
GS
Q
g(10)
V
GS
+
-
V
= 10V
V
V
GS
DD
GS
V
= 2V
GS
DUT
0
I
G(REF)
Q
g(TH)
I
G(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORM
Soldering Precautions
o
The soldering process creates a considerable thermal stress
on any semiconductor component. The melting temperature
of solder is higher than the maximum rated temperature of
the device. The amount of time the device is heated to a high
temperature should be minimized to assure device reliability.
Therefore, the following precautions should always be
observed in order to minimize the thermal stress to which the
devices are subjected.
3. Themaximumtemperaturegradientshouldbelessthan5 C
per second when changing from preheating to soldering.
4. The peak temperature in the soldering process should be
o
at least 30 C higher than the melting point of the solder
chosen.
5. The maximum soldering temperature and time must not
o
exceed 260 C for 10 seconds on the leads and case of
the device.
6. After soldering is complete, the device should be allowed
to cool naturally for at least three minutes, as forced
cooling will increase the temperature gradient and may
result in latent failure due to mechanical stress.
1. Always preheat the device.
2. The deltatemperature between the preheatandsoldering
o
should always be less than 100 C. Failure to preheat the
device can result in excessive thermal stress which can
damage the device.
7. During cooling, mechanical stress or shock should be
avoided.
©2002 Fairchild Semiconductor Corporation
RF1K49157 Rev. B
RF1K49157
PSPICE Electrical Model
SUBCKT RF1K49157 2 1 3
;rev 3/14/95
CA 12 8 1.834e-9
CB 15 14 1.72e-9
CIN 6 8 1.416e-9
LDRAIN
DPLCAP
5
DRAIN
2
DBODY 7 5 DBDMOD
10
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
RLDRAIN
DBREAK
EBREAK 11 7 17 18 34.89
EDS 14 8 5 8 1
RDRAIN
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRESH 6 21 19 8 1
EZTEMPCO 20 6 18 22 1
-
11
6
8
+
-
DBODY
ESG
16
EVTHRESH
EBREAK
MOS2
17
18
+
+
-
19
8
LGATE
EZTEMPCO
21
GATE
1
IT 8 17 1
9
20
6
+
-
18
22
MOS1
RGATE
LDRAIN 2 5 1.0e-9
LGATE 1 9 1.04e-9
RLGATE
CIN
RIN
LSOURCE
LSOURCE 3 7 0.237e-9
RSOURCE
SOURCE
3
8
7
MOS1 16 6 8 8 MSTRONG M = 0.99
MOS2 16 21 8 8 MWEAK M = 0.01
RLSOURCE
RBREAK
S1A
12
S2A
15
13 14
RBREAK 17 18 RBREAKMOD 1
RDRAIN 5 16 RDRAINMOD 4.39e-3
RGATE 9 20 1.53
RIN 6 8 1e9
RLDRAIN 2 5 1.0
RLGATE 1 9 10.4
RLSOURCE 3 7 0.237
RSOURCE 8 7 RSOURCEMOD 4.44e-3
RTHRESH 22 8 RTHRESMOD 1
RZTEMPCO 18 19 RZTEMPCOMOD 1
17
18
8
13
S1B
CA
S2B
13
RZTEMPCO
IT
19
-
CB
+
+
6
14
5
8
VBAT
+
EDS
EGS
8
-
-
22
RVTHRESH
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
.MODEL DBDMOD D (IS = 1.14e-12 RS = 6.01e-3 TRS1 = 1.05e-4 TRS2 = -2.46e-5 CJO = 2.62e-9 TT = 2.44e-8)
.MODEL DBREAKMOD D (RS = 4.89e- 1TRS1 = 2.11e- 3TRS2 = -3.19e-6)
.MODEL DPLCAPMOD D (CJO = 1.007e- 9IS = 1e-3 0N = 10)
.MODEL MSTRONG NMOS (VTO = 2.567 KP = 33.21 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAK
NMOS (VTO=2.0225 KP = 33.21 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBREAKMOD RES (TC1 = 9.59e- 4TC2 = -2.87e-7)
.MODEL RDRAINMOD RES (TC1 = 8.08e-3 TC2 = 1.6e-5)
.MODEL RSOURCEMOD RES (TC1=0 TC2=0)
.MODEL RTHRESHMOD RES (TC1=-6.4e-4 TC2=-8.1e-6)
.MODEL RZTEMPCOMOD RES (TC1 = -2.43e- 3TC2 = 1.57e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.47 VOFF= -4.47)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.47 VOFF= -6.47)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.3 VOFF= 1.7)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.7 VOFF= -3.3)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991.
©2002 Fairchild Semiconductor Corporation
RF1K49157 Rev. B
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
â
SMART START™
STAR*POWER™
Stealth™
VCX™
FAST
ACEx™
Bottomless™
CoolFET™
OPTOLOGIC™
OPTOPLANAR™
PACMAN™
FASTr™
FRFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
CROSSVOLT™
DenseTrench™
DOME™
POP™
Power247™
PowerTrenchâ
QFET™
EcoSPARK™
E2CMOSTM
TinyLogic™
QS™
EnSignaTM
TruTranslation™
UHC™
QT Optoelectronics™
Quiet Series™
SILENTSWITCHERâ
FACT™
FACT Quiet Series™
UltraFETâ
STAR*POWER is used under license
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITYARISING OUT OF THE APPLICATION OR USE OFANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICESORSYSTEMSWITHOUTTHEEXPRESSWRITTENAPPROVALOFFAIRCHILDSEMICONDUCTORCORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4
相关型号：
©2020 ICPDF网 联系我们和版权申明