ICS9250-16 [ICSI]
Frequency Generator & Integrated Buffers for Celeron & PII/III⑩; 频率发生器和缓冲器集成的赛扬和PII / III⑩
| 型号： | ICS9250-16 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| 文件： | 总17页 (文件大小：540K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9250-16
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
Pin Configuration
810/810E type chipsetꢀ
Output Features:
*FS2//REF0
VDD0
1
2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GNDL1
IOAPIC0
IOAPIC1
VDDL1
CPUCLK0
VDDL0
CPUCLK1
CPUCLK2
GNDL0
GND5
SDRAM0
SDRAM1
VDD5
SDRAM2
SDRAM3
GND5
SDRAM4
SDRAM5
VDD5
SDRAM6
SDRAM7
GND5
SDRAM_F
VDD5
PD#
X1
X2
GND0
GND1
3V66-0
3V66-1
VDD1
3
4
5
6
7
8
9
•
3 CPU (2.5V) 66.6/133.3MHz (up to 150MHz
achievable through I2C)
•
9 SDRAM (3.3V) @ 133.3MHz (up to 150MHz
achievable through I2C)
•
•
•
•
•
8 PCI (3.3 V) @33.3MHz
VDD2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
2 IOAPIC (2.5V) @ 33.3MHz
PCICLK0
PCICLK1
PCICLK2
GND2
PCICLK3
PCICLK4
GND2
PCICLK5
PCICLK6
PCICLK7
VDD2
2 Hublink clocks (3.3 V) @ 66.6MHz
2 USB (3.3V) @ 48MHz ( Non spread spectrum)
1 REF (3.3V) @ 14.318MHz
Features:
•
Supports spread spectrum modulation,
down spread 0 to -0.5% and ± 0.25% center spread.
I2C support for power management
•
•
•
•
VDD3
GND3
GND4
Efficient power management scheme through PD#
Uses external 14.138MHz crystal
Alternate frequency selections available through I2C
control.
48MHz_0
48MHz_1
VDD4
SCLK
SDATA
FS1
FS0
56-Pin 300mil SSOP
* This input has a 50KW pull-down to GNDꢀ
Block Diagram
X1
X2
XTAL
OSC
REF0
PLL1
Spread
Spectrum
Functionality
/2
/3
VDDL
FS2
FS1
FS0
Function
CPU66/100/133 [2:0]
3
2
8
1
8
X
X
0
0
0
1
Tristate
Test
FS(2:0)
PD#
Control
Logic
3V66 [1:0]
SDRAM [7:0]
SDRAM_F
Active CPU = 66MHz
SDRAM = 100MHz
0
0
1
1
1
1
0
1
1
SDATA
SCLK
Active CPU = 100MHz
SDRAM = 100MHz
PCICLK [7:0]
/2
Config
Reg
Active CPU = 133MHz
SDRAM = 100MHz
IOAPIC [1:0]
VDDL
/2
2
(Special Condition)
Active CPU = 133MHz
SDRAM = 133MHz
PLL2
48MHz [1:0]
1
1
0
2
9250-16 Rev H 9/5/00
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9250-16
General Description
Power Groups
VDD0, GND0 = REF & Crystal
The ICS9250-16 is a single chip clock solution for 810/810E type
chipsetꢀ It provides all necessary clock signals for such
a systemꢀ
VDD1, GND1=3V66(0:1)
VDD2, GND2=PCICLK(0:7)
VDD3, GND3 = PLL core
VDD4, GND4 = 48MHz (0:1)
VDD5, GND5 = SDRAM_F, SDRAM (0:7)
VDDL0, GNDL0=CPUCLK(0:2)
VDDL1, GNDL1=IOAPIC(0:1)
Spread spectrum may be enabled through I2C programmingꢀ Spread
spectrum typically reduces EMI by 8dB to 10 dBꢀ This simplifies
EMI qualification without resorting to board design iterations or
costly shieldingꢀ The ICS9250-16 employs a proprietary closed
loop design, which tightly controls the percentage of spreading
over process and temperature variationsꢀ
Pin Configuration
PIN NUMBER PIN NAME
TYPE
DESCRIPTION
Function Select pin. Determines CPU frequency, all output functionality
(with 50K pull-down).
FS2
IN
1
REF0
OUT 3.3V, 14.318MHz reference clock output.
Crystal input, has internal load cap (33pF) and feedback
3
4
X1
IN
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
X2
OUT
5, 6, 14, 17, 23,
24, 35, 41, 47
GND (0:5)
3V66 [1:0]
VDD (0:5)
PWR Ground pins for 3.3V supply
8, 7
OUT 3.3V Fixed 66MHz clock outputs for HUB
PWR 3.3V power supply
2, 9, 10, 21,
22, 27, 33, 38, 44
20,19,18,16,
15,13,12,11
PCICLK[7:0]
48MHz (0:1)
FS (0:1)
OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS
OUT 3.3V Fixed 48MHz clock outputs for USB
25, 26
28, 29
30
Function Select pins. Determines CPU frequency, all output functionality.
Please refer to Functionality table on page 3.
IN
SDATA
IN
IN
Data input for I2C serial input.
31
SCLK
Clock input of I2C input
Asynchronous active low input pin used to power down the device into
a low power state. The internal clocks are disabled and the VCO and
the crystal are stopped. The latency of the power down will not be
greater than 3ms.
32
PD#
IN
36, 37, 39, 40,
42, 43, 45, 46
3.3V output running 100MHz. All SDRAM outputs can be turned off
through I2C
SDRAM [7:0]
SDRAM_F
OUT
34
OUT 3.3V free running 100MHz SDRAM, cannot be turned off through I2C
56,48
GNDL [1:0]
PWR Ground for 2.5V power supply for CPU & APIC
2.5V Host bus clock output. 66MHz, 100MHz or 133MHz depending
on FS (0:2) pins.
49,50,52
CPUCLK [2:0] OUT
51, 53
54, 55
VDDL (0:1)
PWR 2.5V power supply for CPU & IOAPIC
OUT 2.5V clock outputs running at 33.3MHz.
IOAPIC [1:0]
2
ICS9250-16
Power Down Waveform
Note
1ꢀ After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiionꢀ
2ꢀ Power-up latency <3msꢀ
3ꢀ Waveform shown for 100MHz
Maximum Allowed Current
Max 2.5V supply consumption
Max discrete cap loads,
Vddq2 = 2.625V
Max 2.5V supply consumption
Max discrete cap loads,
Vddq2 = 3.465V
810E
Condition
All static inputs = Vddq3 or GND All static inputs = Vddq3 or GND
Powerdown Mode
10mA
70mA
10mA
310mA
300mA
(PWRDWN# = 0
Full Active 66MHz
SEL1, 0 = 10
Full Active 100MHz
SEL1, 0 = 11
100mA
Clock Enable Configuration
REF,
48MHz
PD# CPUCLK SDRAM IOAPIC 66MHz PCICLK
Osc VCOs
0
1
LOW
ON
LOW
ON
LOW
ON
LOW
ON
LOW
ON
LOW
ON
OFF
ON
OFF
ON
3
ICS9250-16
General I2C serial interface information
The information in this section assumes familiarity with I2C programmingꢀ
For more information, contact ICS for an I2C programming application noteꢀ
How to Write:
Controller (host) sends a start bitꢀ
Controller (host) sends the write address D2(H)
ICS clock will acknowledge
How to Read:
Controller (host) will send start bitꢀ
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a timeꢀ
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1ꢀ
The ICS clock generator is a slave/receiver, I2C componentꢀ It can read back the data stored in the latches for
verificationꢀ Read-Back will support Intel PIIX4 "Block-Read" protocolꢀ
2ꢀ
3ꢀ
4ꢀ
5ꢀ
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3ꢀ3V logic levelsꢀ
The data byte format is 8 bit bytesꢀ
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controllerꢀ The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferredꢀ The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytesꢀ The data is loaded until a Stop sequence is issuedꢀ
6ꢀ
At power-on, all registers are set to a default condition, as shownꢀ
4
ICS9250-16
Byte 5: ICS Reserved Functionality and frequency select register (Default as noted in PWD)
Bit
Desctiption
PWD
Bit7
Bit6
Bit5
ICS RESERVED BIT (Needs to be 0 clock to operate normal)
ICS RESERVED BIT (Needs to be 0 clock to operate normal)
ICS RESERVED BIT (Needs to be 0 clock to operate normal)
Bit (3,0)
0
0
0
CPUCLK SDRAM 3V66 PCICLK
FS2
(HW)
FS0
SEL1
(Bit3)
SEL0
(Bit0)
MHz
MHz
MHz
MHz
(HW)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.67
70.00
100.00
105.00
109.00
112.00
100.00
105.00
109.00
112.00
133.34
105.00
90.00
66.60
70.00
72.67
74.66
66.60
70.00
72.67
74.66
88.66
70.00
60.00
82.66
66.60
75.00
70.00
66.60
33.30
35.00
36.33
37.33
33.30
35.00
36.33
37.33
44.33
35.00
30.00
41.33
33.30
37.50
35.00
33.30
72.67
74.67
100.00
105.00
109.00
112.01
133.34
140.00
120.00
124.00
133.34
150.00
140.00
132.99
Bit
(3,0)
XXXX
Note 1
124.00
100.00
150.00
140.00
132.99
0 = Down Spread Spread Spectrum 0 to -.5%
1 = Center Spread Spread Spectrum ± .25%
Bit4
0
Bit2
Bit1
Not used (Needs to be 1 for normal clock operation)
Not used (Needs to be 1 for normal clock operation)
1
1
Note1: Default at power-up will be for Bit 3 and Bit 0 to be 00, with external hardware selection of FS0, FS2
defining specific frequencyꢀ
5
ICS9250-16
Byte 0: Control Register
(1 = enable, 0 = disable)
Bit
Pin#
Name
Reserved ID
Reserved ID
Reserved ID
Reserved ID
PWD
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
0
0
0
1
SpreadSpectrum
(1=On/0=Off)
Bit 3
1
(Active/Inactive)
Bit 2
Bit 1
Bit 0
26
25
49
48MHz 1
48MHz 0
CPUCLK2
1
1
1
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Notes:
1ꢀ Do not write in ID bits, these bits are for ICS internal use onlyꢀ
2ꢀ Bit 0 will always read back 0ꢀ If readback/rewrite procedure is to
perform, user will need to ensure a "1" is written to Bit 0 for CPUCLK2
to maintain running statusꢀ
Byte 1: Control Register
(1 = enable, 0 = disable)
Bit
Pin#
36
37
39
40
42
43
45
46
Name
SDRAM7
PWD
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Byte 2: Control Register
(1 = enable, 0 = disable)
Bit
Pin#
20
19
18
16
15
13
12
-
Name
PCICLK7
PWD
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
Reserved
Notes:
1ꢀ Inactive means outputs are held LOW and are disabled from switchingꢀ
These outputs are designed to be configured at power-on and are not
expected to be configured during the normal modes of operationꢀ
2ꢀ PWD = Power on Default
6
ICS9250-16
Byte 3: Reserved Register
(1 = enable, 0 = disable)
Bit
Pin#
Name
Reserved
PWD
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 4: Reserved Register
(1 = enable, 0 = disable)
Bit
Pin#
Name
Reserved
PWD
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Notes:
1ꢀ Inactive means outputs are held LOW and are disabled from switchingꢀ
These outputs are designed to be configured at power-on and are not
expected to be configured during the normal modes of operationꢀ
2ꢀ PWD = Power on Default
7
ICS9250-16
Absolute Maximum Ratings
Core Supply Voltage ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 4ꢀ6 V
I/O Supply Voltage ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 3ꢀ6V
Logic Inputs ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ GND 0ꢀ5 V to VDD +0ꢀ5 V
Ambient Operating Temperature ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 0°C to +70°C
Storage Temperature ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the deviceꢀ These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not impliedꢀ Exposure to absolute maximum rating conditions for extended periods
may affect product reliabilityꢀ
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V+/-5%, VDDL = 2.5 V+/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
CONDITIONS
MIN TYP
2
MAX
VDD+0.3
0.8
UNITS
V
IH
V
V
V
IL
V -0.3
SS
IIH
IIL1
IIL2
V = VDD
-5
5
A
µ
IN
V = 0V; Inputs with no pull-up resistors
-5
2
IN
Input Low Current
A
µ
V = 0 V; Inputs with pull-up resistors
-200
-100
97
IN
CL = 0 pF; Select @ 66 MHz
110
105
130
310
300
mA
mA
mA
mA
CL = 0 pF; Select @ 100 MHz
CL = 0 pF; Select @ 133 MHz
CL = Max loads; Select @66 MHz
CL = Max loads; Select @ 100 MHz
91
100
275
267
IDD3.3OP
CL = Max loads; Select @ 133 MHz
CL = 0 pF; Select @ 66 MHz
278
8
350
10
Operating Supply
Current
CL = 0 pF; Select @ 100 MHz
CL = 0 pF; Select @ 133 MHz
CL = Max loads; Select @66 MHz
CL = Max loads; Select @ 100 MHz
11
13
22
31
15
20
IDD2.5OP
70
100
CL = Max loads; Select @ 133 MHz
37
130
IDD3.3PD CL = Max loads
220
<1
400
10
Powerdown Current
A
µ
IDD.25PD Input address VDD or GND
Input Frequency
Pin Inductance
F
VDD = 3.3 V
12
27
14.318
7
16
MHz
nH
pF
i
L
pin
C
IN
Logic Inputs
5
Input Capacitance1
COUT
Output pin capacitance
X1 & X2 pins
6
pF
C
INX
45
5
pF
Transition time1
Settling time1
Clk Stabilization1
Ttrans
Ts
To 1st crossing of target frequency
ms
ms
From1st crossing to 1% target frequency
5
TSTAB
FromVDD = 3.3 Vto 1% target frequency
Output enable delay (all outputs)
Output disable delay (all outputs)
5
ms
ns
ns
t
t
PZH,tPZL
1
1
10
10
Delay1
PHZ,tPLZ
1Guaranteed by design, not 100% tested in production.
8
ICS9250-16
Electrical Characteristics - CPU
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
CONDITIONS
MIN
13.5
13.5
2
TYP
MAX UNITS
1
RDSP2B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
16
21
45
45
Ω
Ω
V
V
1
RDSN2B
VOH2B
VOL2B
IOL = 1 mA
0.4
-27
V
OH @ MIN = 1.0 V
OH @ MAX = 2.375 V
-27
27
-68
-9
IOH2B
IOL2B
Output High Current
mA
mA
V
VOL @ MIN = 1.2 V
OL @ MAX = 0.3 V
54
11
Output Low Current
V
30
Rise Time1
Fall Time1
tr2B
tf2B
VOL = 0.4 V, VOH = 2.0 V
0.4
1.1
1.6
ns
ns
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V, 66, 100 MHz
VT = 1.25 V, 133 MHz
0.4
45
40
1.1
49
48
1.6
55
55
Duty Cycle1
dt2B
%
ps
ps
Skew window1
Jitter, Cycle-to-cycle1
tsk2B
VT = 1.25 V
65
90
175
250
tjcyc-cyc2B VT = 1.25 V
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
CONDITIONS
MIN
12
TYP
14
MAX UNITS
1
RDSP1B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
55
55
Ω
Ω
V
V
1
RDSN1B
12
14.5
VOH1
VOL1
2.4
IOL = 1 mA
0.55
-33
V
V
V
V
OH @ MIN = 1.0 V
-33
30
-108
-9
IOH1
Output High Current
mA
mA
OH @ MAX = 3.135 V
OL @ MIN = 1.95 V
OL @ MAX = 0.4 V
95
IOL1
tr1
Output Low Current
29
38
1.6
1.6
55
Rise Time1
Fall Time1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.4
0.4
45
1.2
1.2
49
ns
ns
%
ps
ps
tf1
Duty Cycle1
dt1
Skew window1
tsk1
VT = 1.5 V
65
175
500
Jitter, Cycle-to-cycle1
tjcyc-cyc1
VT = 1.5 V
120
1Guaranteed by design, not 100% tested in production.
9
ICS9250-16
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
CONDITIONS
MIN
TYP
16
MAX UNITS
1
RDSP4B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
9
9
2
30
30
Ω
Ω
V
V
1
RDSN4B
20
VOH4B
VOL4B
IOL = 1 mA
0.4
-27
VOH @ MIN = 1.0 V
VOH @ MAX = 2.375 V
VOL @ MIN = 1.2 V
-27
27
-68
-9
IOH4B
Output High Current
mA
mA
54
11
IOL4B
tr4B
Output Low Current
V
OL @ MAX = 0.3 V
30
1.6
1.6
55
Rise Time1
Fall Time1
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
0.4
0.4
45
1.1
1.1
49
ns
ns
%
ps
ps
tf4B
Duty Cycle1
dt4B
Skew window1
tsk4B
VT = 1.25 V
81
250
500
Jitter, Cycle-to-cycle1
tjcyc-cyc4B VT = 1.25 V
150
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20-30 pF (unless otherwise specified)
PARAMETER
Output Impedance
Output Impedance
SYMBOL
CONDITIONS
MIN
10
TYP
12
MAX UNITS
1
RDSP3B
VO = VDD*(0.5)
VO = VDD*(0.5)
24
24
Ω
Ω
1
RDSN3B
10
15
V
V
V
V
OH @ MIN = 2.0 V
-54
-92
-16
68
IOH3
Output High Current
mA
mA
OH @ MAX = 3.135 V
OL @ MIN = 1.0 V
OL @ MAX = 0.4 V
-46
54
IOL3
tr3
Output Low Current
29
53
1.6
1.6
55
Rise Time1
Fall Time1
Duty Cycle1
Skew window1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.4
0.4
45
1
ns
ns
%
ps
tf3
1.5
52
dt3
tsk3
VT = 1.5 V
85
250
250
VT = 1.5 V, 66, 100 MHz
VT = 1.5 V, 133 MHz
120
Jitter, Cycle-to-cycle1
tjcyc-cyc3
ps
150
300
1Guaranteed by design, not 100% tested in production.
10
ICS9250-16
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
CONDITIONS
MIN
12
TYP
MAX UNITS
1
RDSP1B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
15
15
55
55
Ω
Ω
V
V
1
RDSN1B
12
VOH1
VOL1
2.4
IOL = 1 mA
0.55
-33
VOH @ MIN = 1.0 V
VOH @ MAX = 3.135 V
VOL @ MIN = 1.95 V
-33
30
-106
-14
94
IOH1
Output High Current
mA
mA
IOL1
tr1
Output Low Current
V
OL @ MAX = 0.4 V
29
38
2
Rise Time1
Fall Time1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.4
0.4
45
1.3
1.4
51
ns
ns
%
ps
ps
tf1
2
Duty Cycle1
dt1
55
500
500
Skew window1
tsk1
VT = 1.5 V
250
150
Jitter, Cycle-to-cycle1
tjcyc-cyc1
VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF, 48MHz_0 (Pin 25)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
CONDITIONS
MIN
20
TYP
29
MAX UNITS
1
RDSP5B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
60
60
Ω
Ω
V
V
1
RDSN5B
20
27
VOH15
VOL5
2.4
IOL = 1 mA
0.55
-23
VOH @ MIN = 1.0 V
VOH @ MAX = 3.135 V
VOL @ MIN = 1.95 V
-29
29
-54
-11
54
IOH5
Output High Current
mA
mA
IOL5
tr5
Output Low Current
V
OL @ MAX = 0.4 V
16
27
4
Rise Time1
Fall Time1
Duty Cycle1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.4
0.4
45
1.3
1.6
53
ns
ns
%
ps
ps
tf5
4
dt5
55
Jitter, Cycle-to-cycle1
Jitter, Cycle-to-cycle1
tjcyc-cyc5
tjcyc-cyc5
VT = 1.5 V, Fixed clocks
VT = 1.5 V, Ref clocks
130
465
500
1000
1Guaranteed by design, not 100% tested in production.
11
ICS9250-16
Electrical Characteristics - 48MHz_1 (Pin 26)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20-30 pF (unless otherwise specified)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
CONDITIONS
MIN
10
TYP
15
MAX UNITS
1
RDSP3B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
24
24
Ω
Ω
V
V
1
RDSN3B
10
15
VOH3
VOL3
2.4
IOL = 1 mA
0.55
-46
VOH @ MIN = 2.0 V
OH @ MAX = 3.135 V
-54
54
-82
-20
95
IOH3
Output High Current
mA
mA
V
VOL @ MIN = 1.0 V
VOL @ MAX = 0.4 V
IOL3
tr3
Output Low Current
28
53
1.6
1.6
55
Rise Time1
Fall Time1
Duty Cycle1
Jitter, Cycle-to-cycle1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.4
0.4
45
1.1
1.3
53
ns
ns
%
ps
tf3
dt3
tjcyc-cyc3B VT = 1.5 V
130
250
1Guaranteed by design, not 100% tested in production.
12
ICS9250-16
30ns
10ns
20ns
40ns
0ns
Cycle Repeats
2.5ns
CPU 66MHz
SDRAM 100MHz
3.3V 66MHz
0.0ns
7.5ns
30ns
30ns
30ns
10ns
10ns
10ns
20ns
20ns
20ns
40ns
40ns
40ns
0ns
0ns
0ns
Cycle Repeats
CPU 100MHz
SDRAM 100MHz
3.3V 66MHz
5.0ns
0.0ns
6.0ns
Cycle Repeats
CPU 133MHz
0.0ns
SDRAM 100MHz
0.0ns
0.0ns
3.3V 66MHz
Cycle Repeats
3.3V 66MHz
PCI 33MHz
1.5-3.5ns
Group Offset Waveforms
13
ICS9250-16
Group Skews (CPU = 66 MHz)
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%
CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF
Refer to Group Offset Waveform diagram for definition of transition edges.
PARAMETER
SYMBOL
Tsk1 CPU-SDRAM
Tw1 CPU-SDRAM
Tsk1 CPU-3V66
Tw1 CPU-3V66
CONDITIONS
MIN
-3
0
TYP
-2.6
150
7.2
MAX UNITS
CPU to SDRAM
Skew1
-2
500
8
ns
ps
ns
ps
ps
ps
ns
ps
ns
ns
CPU @ 1.25 V, SDRAM @ 1.5 V
Skew Window1
Skew1
7
CPU to 3V66
CPU @ 1.25 V, 3V66 @ 1.5 V
SDRAM, 3V66 @ 1.5 V
Skew Window1
Skew1
0
130
100
155
2.4
500
500
500
3.5
500
1
Tsk1 SDRAM-3V66
Tw1 SDRAM-3V66
Tsk1 3V66-PCI
-500
0
SDRAM to 3V66
3V66 to PCI
Skew Window1
Skew1
1.5
0
3V66, PCI @ 1.5 V
Skew Window1
Skew1
Tw1 3V66-PCI
275
-0.4
0.25
Tsk1 IOAPIC-PCI
-1
0
IOAPIC to PCI
IOAPIC @ 1.25 V, PCI @ 1.5 V
Skew Window1
Tw1 IOAPIC-PCI
1
1Guaranteed by design, not 100% tested in production.
Group Skews (CPU = 100 MHz)
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%
CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF
Refer to Group Offset Waveform diagram for definition of transition edges.
PARAMETER
SYMBOL
Tsk2 CPU-SDRAM
Tw2 CPU-SDRAM
Tsk2 CPU-3V66
Tw2 CPU-3V66
CONDITIONS
MIN
4.5
0
TYP
4.9
MAX UNITS
CPU to SDRAM
Skew1
5.5
500
5.5
500
500
500
3.5
500
1
ns
ps
ns
ps
ps
ps
ns
ps
ns
ns
CPU @ 1.25 V, SDRAM @ 1.5 V
Skew Window1
Skew1
140
4.8
4.5
0
CPU to 3V66
CPU @ 1.25 V, 3V66 @ 1.5 V
SDRAM, 3V66 @ 1.5 V
Skew Window1
Skew1
150
100
155
2.4
Tsk2 SDRAM-3V66
Tw2 SDRAM-3V66
Tsk2 3V66-PCI
-500
0
SDRAM to 3V66
3V66 to PCI
Skew Window1
Skew1
1.5
0
3V66, PCI @ 1.5 V
Skew Window1
Skew1
Tw2 3V66-PCI
275
-0.4
0.25
Tsk2 IOAPIC-PCI
-1
IOAPIC to PCI
IOAPIC @ 1.25 V, PCI @ 1.5 V
Skew Window1
Tw2 IOAPIC-PCI
0
1
1Guaranteed by design, not 100% tested in production.
1Guaranteed by design, not 100% tested in production.
14
ICS9250-16
Group Skews (CPU = 133 MHz)
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%
CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF
Refer to Group Offset Waveform diagram for definition of transition edges.
PARAMETER
SYMBOL
Tsk3 CPU-SDRAM
Tw3 CPU-SDRAM
Tsk3 CPU-3V66
Tw3 CPU-3V66
CONDITIONS
MIN
-500
0
TYP
MAX UNITS
CPU to SDRAM
Skew1
70
125
-145
220
100
155
2.4
500
500
500
500
500
500
3.5
500
1
ps
ps
ps
ps
ps
ps
ns
ps
ns
ns
CPU @ 1.25 V, SDRAM @ 1.5 V
Skew Window1
Skew1
-500
0
CPU to 3V66
CPU @ 1.25 V, 3V66 @ 1.5 V
SDRAM, 3V66 @ 1.5 V
Skew Window1
Skew1
Tsk3 SDRAM-3V66
Tw3 SDRAM-3V66
Tsk3 3V66-PCI
-500
0
SDRAM to 3V66
3V66 to PCI
Skew Window1
Skew1
1.5
0
3V66, PCI @ 1.5 V
Skew Window1
Skew1
Tw3 3V66-PCI
275
-0.4
0.25
Tsk3 IOAPIC-PCI
-1
IOAPIC to PCI
IOAPIC @ 1.25 V, PCI @ 1.5 V
Skew Window1
Tw3 IOAPIC-PCI
0
1
1Guaranteed by design, not 100% tested in production.
15
ICS9250-16
Ferrite
Bead
Ferrite
Bead
C2
22µF/20V
Tantalum
C2
22µF/20V
Tantalum
VDD
VDD
1
56
2
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
General Layout Precautions:
1) Use a ground plane on the top routing
layer of the PCB in all areas not used
by tracesꢀ
C1
C1
3
2.5V Power Route
4
2
5
6
2) Make all power traces and ground
traces as wide as the via pad for lower
inductanceꢀ
7
1
8
Clock Load
C3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Notes:
1 All clock outputs should have
provisions for a 15pf capacitor
between the clock output and series
terminating resistorꢀ Not shown in all
places to improve readability of
diagramꢀ
3.3V Power Route
2 Optional crystal load capacitors are
recommendedꢀ They should be
included in the layout but not
inserted unless neededꢀ
3.3V Power Route
Connections to VDD:
= Routed Power
= Ground Connection Key (component side copper)
= Ground Plane Connection
= Power Route Connection
= Solder Pads
= Clock Load
16
ICS9250-16
SYMBOL
In Millimeters
In Inc hes
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
2.794
0.406
0.343
0.254
MIN
MAX
.110
.016
.0135
.010
A
A1
b
2.413
0.203
0.203
0.127
.095
.008
.008
.005
c
SEE VARIATIONS
SEE VARIATIONS
D
E
10.033
7.391
10.668
7.595
.395
.291
.420
.299
E1
e
0.635 BASIC
0.025 BASIC
h
0.381
0.508
0.635
1.016
.015
.020
.025
.040
L
SEE VARIATIONS
SEE VARIATIONS
N
0°
8°
0°
8°
α
VARIATIONS
N
D mm.
D (inch)
MIN
MAX
MIN
MAX
9.652
28
34
48
56
64
9.398
11.303
15.748
18.288
20.828
.370
.445
.620
.720
.820
.380
.455
.630
.730
.830
11.557
16.002
18.542
21.082
J E DE C MO- 118
6/ 1/ 00
DOC# 10-0034
REVB
Ordering Information
ICS9250yF-16-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
17
information being relied upon by the customer is current and accurate.
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