ICS8402010I [IDT]
FEMTOCLOCK™ CRYSTAL-TOLVDS/LVCMOS CLOCK GENERATOR; FEMTOCLOCK ™ CRYSTAL - TOLVDS / LVCMOS时钟发生器
| 型号： | ICS8402010I |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FEMTOCLOCK™ CRYSTAL-TOLVDS/LVCMOS CLOCK GENERATOR |
| 文件： | 总16页 (文件大小：316K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEMTOCLOCK™ CRYSTAL-TO-
LVDS/LVCMOS CLOCK GENERATOR
ICS8402010I
GENERAL DESCRIPTION
FEATURES
ICS8402010I is a low phase noise Clock Generator
• Three banks of outputs:
ICS
HiPerClockS™
and is a member of the HiperClockS™family of high
performance clock solutions from IDT. The device
Bank A/B: three single-ended LVCMOS outputs at 16.66MHz
Bank C: three differential LVDS outputs at 62.5MHz
One single-ended reference clock output at 25MHz
provides three banks of outputs and a reference
clock. Each bank can be independently enabled by
using output enable pins. A 25MHz, 18pF parallel resonant
crystal is used to generate the 16.66MHz, 62.5MHz and 25MHz
frequencies. The typical RMS phase jitter for this device is less
than 1ps.
• Crystal input frequency: 25MHz
• Maximum output frequency: 62.5MHz
• RMS phase jitter @ 62.5MHz, using a 25MHz crystal,
Integration Range (1.875MHz - 20MHz): 0.375ps (typical)
• Full 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS6)
packages
BLOCK DIAGRAM
3
Pullup
OE[2:0]
LVCMOS - 16.66MHz
QA0
QA1
QA2
÷30
÷30
PIN ASSIGNMENT
25MHz
XTAL_IN
LVCMOS - 16.66MHz
QB0
OSC
Phase
Detector
VCO
500MHz
XTAL_OUT
QB1
QB2
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
VDDO_C
VDDO_REF
REF_OUT
GND
1
2
3
4
5
6
7
8
nQC2
QC2
÷20
LVDS 62.5MHz
QC0
ICS8402010I
32-Lead VFQFN
5mm x 5mm x 0.925mm
package body
nQC1
QC1
nQC0
QC1
GND
QA0
÷8
nQC0
QA1
K Package
Top View
nQC1
QC2
QC0
QA2
VDDO_C
VDDO_A
nQC2
9
10 11 12 13 14 15 16
LVCMOS - 25MHz
REF_OUT
IDT™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR
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TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VDDO_REF
Power
Output power supply pin for REF_OUT output.
Single-ended reference clock output. LVCMOS/LVTTL interface
levels.
2
REF_OUT
GND
Output
3, 4, 13,
16, 25, 32
Power
Power supply ground.
5, 6, 7
QA0, QA1, QA2
VDDO_A
Output
Power
Power
Output
Single-ended Bank A clock outputs. LVCMOS/LVTTL interface levels.
Output power supply pin for Bank A LVCMOS outputs.
8
9
VDDO_B
Output power supply pin for Bank B LVCMOS outputs.
10, 11, 12 QB0, QB1, QB2
Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels.
Master reset, resets the internal dividers. During reset, LVCMOS
outputs are pulled LOW and LVDS outputs are pulled LOW and
HIGH, (QCx pulled LOW, nQCx pulled HIGH).
14
MR
Input
Pulldown
LVCMOS/LVTTL interface levels.
15
VDD
Power
Power
Output
Output
Output
Power
Input
Core supply pin.
17, 24
18, 19
20, 21
22, 23
26
VDDO_C
Output power supply pin for Bank C LVDS outputs.
Differential Bank C clock outputs. LVDS interface levels.
Differential Bank C clock outputs. LVDS interface levels.
Differential Bank C clock outputs. LVDS interface levels.
Analog supply pin.
QC0, nQC0
QC1, nQC1
QC2, nQC2
VDDA
27, 28, 29 OE0, OE1, OE2
Pullup
Output enable pins. See Table 3. LVCMOS/LVTTL interface levels.
30,
31
XTAL_IN,
XTAL_OUT
Crystal oscillator interface. XTAL_OUT is the output.
XTAL_IN is the input.
Input
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
QA[0:2],
QB[0:2],
REF_OUT
Power Dissipation
Capacitance (per output)
VDD, VDDO_A = VDDO_B
VDDO_REF = 3.465V
=
CPD
15
pF
RPULLUP
Input Pullup Resistor
51
51
kΩ
kΩ
RPULLDOWN Input Pulldown Resistor
QA[0:2],
QB[0:2],
REF_OUT
ROUT Output Impedance
20
Ω
TABLE 3. OE FUNCTION TABLE
Inputs
OE2
OE1
OE0
Output States
X
X
0
QA0, QB0, QC0 disabled
QA0, QB0, QC0 enabled
QA1, QB1, QC1 disabled
QA1, QB1, QC1 enabled
QA2, QB2, QC2 disabled
QA2, QB2, QC2 enabled
X
X
X
0
X
0
1
X
X
X
X
1
X
X
1
IDT™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR
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ABSOLUTE MAXIMUM RATINGS
NOTE: Stresses beyond those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These
ratings are stress specifications only. Functional operation of
product at these conditions or any conditions beyond those listed
in the DC Characteristics or AC Characteristics is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
-0.5V to VDDO_A, _B + 0.5V
Outputs, IO (LVCMOS)
Outputs, IO (LVDS, VDDO_C
)
Continuous Current
Surge Current
10mA
15mA
Operating Temperature Range, TA -40°C to +85°C
Storage Temperature, TSTG
-65°C to 150°C
Package Thermal Impedance, θJA
Junction-to-Ambient
37.0°C/W (0 mps)
Package Thermal Impedance, θJB
Junction-to-Board
0.5°C/W
Package Thermal Impedance, θJC
Junction-to-Case
29.6°C/W
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_REF = VDDO_C = 3.3V 5ꢀ,TA = -40°C TO 85°C
Symbol
VDD
Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
Core Supply Voltage
Analog Supply Voltage
3.465
VDD
V
V
VDDA
VDD – 0.15
3.3
VDDO_A,
VDDO_B,
VDDO_C,
VDDO_REF
Output Supply Voltage
3.135
3.3V
3.465
V
IDD
Power Supply Current
Analog Supply Current
25
15
mA
mA
IDDA
I
DDO_A + IDDO_B
+
Output Supply Current
30
mA
IDDO_C + IDDO_REF
TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_REF = 3.3V 5ꢀ,TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VDD + 0.3
V
Input Low Voltage
-0.3
0.8
5
V
OE0, OE1, OE2
MR
VDD = VIN = 3.465V
VDD = VIN = 3.465V
µA
µA
µA
µA
Input
High Current
IIH
IIL
150
OE0, OE1, OE2
MR
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
-150
-5
Input
Low Current
Output
REF_OUT,
VOH
VOL
2.6
V
V
VDDO_X = 3.465V
VDDO_X = 3.465V
High Voltage; NOTE 1 QA[0:2], QB[0:2]
Output REF_OUT,
Low Voltage; NOTE 1 QA[0:2], QB[0:2]
0.5
NOTE: VDDO_X denotes VDDO_A, VDDO_B and VDDO_REF.
NOTE 1: Outputs terminated with 50Ω to VDDO_A, _B, _REF/2. See Parameter Measurement Information,
Output Load Test Circuit diagram.
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TABLE 3C. LVDS DC CHARACTERISTICS, VDD = VDDO_C = 3.3V 5ꢀ,TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VOD
Differential Output Voltage
300
450
550
50
mV
mV
V
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
1.325
1.450
1.575
50
Δ VOS
VOS Magnitude Change
mV
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Fundamental
25
Mode of Oscillation
Frequency
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 5. AC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_REF = VDDO_C = 3.3V 5ꢀ,TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
QC[0:2]/
nQC[0:2]
REF_OUT
QA[0:2],
QB[0:2]
QA[0:2],
QB[0:2]
QC[0:2]/
nQC[0:2]
62.5
25
MHz
MHz
MHz
fOUT
Output Frequency
16.66
Output Skew;
NOTE 1, 2
tsk(o)
tsk(b)
125
60
ps
ps
Bank Skew;
NOTE 2, 3
QA[0:2]
QB[0:2]
100
125
ps
ps
RMS Phase Jitter
(Random); NOTE 4
QC[0:2]/
nQC[0:2]
QC[0:2]/
nQC[0:2]
QA[0:2],
QB[0:2]
QC[0:2]/
nQC[0:2]
QA[0:2],
QB[0:2]
62.5MHz, Integration Range:
1.875MHz – 20MHz
tjit(Ø)
tR / tF
0.375
ps
ps
ps
ꢀ
20ꢀ to 80ꢀ
20ꢀ to 80ꢀ
165
450
47
450
1000
53
Output
Rise/Fall Time
odc
Output Duty Cycle
45
55
ꢀ
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO_X/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.
NOTE 4: Please refer to the Phase Noise Plot.
IDT™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR
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TYPICAL PHASE NOISE AT 62.5MHZ (LVDS)
62.5MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.375ps (typical)
Ethernet Filter
Raw Phase Noise Data
Phase Noise Result by adding
Ethernet Filter to raw data
OFFSET FREQUENCY (HZ)
IDT™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR
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PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
1.65V 5ꢀ
,
VDD
SCOPE
VDDO_A,
VDDO_B,
VDDO_REF
SCOPE
Qx
,
VDDA
VDD
VDDO_C
Qx
3.3V 5ꢀ
POWER SUPPLY
LVCMOS
+
Float GND –
LVDS
VDDA
GND
nQx
-1.65V 5ꢀ
3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT
3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
VDDO
Qx
Qy
2
Phase Noise Mask
VDDO
2
tsk(o)
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
LVCMOS OUTPUT SKEW
nQCx
QCx
VDDO
2
QXx
nQCy
QCy
VDDO
2
QXy
tsk(b)
tsk(b)
Where X = A or B
LVDS BANK SKEW
LVCMOS BANK SKEW
IDT™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR
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PARAMETER MEASUREMENT INFORMATION, CONTINUED
VDDO
2
nQC[0:2]
QC[0:2]
QA[0:2], QB[0:2]
tPW
tPW
tPERIOD
tPERIOD
tPW
tPW
odc =
x 100ꢀ
x 100ꢀ
odc =
tPERIOD
tPERIOD
LVDS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
nQC[0:2]
80ꢀ
80ꢀ
80ꢀ
80ꢀ
tR
VOD
QA[0:2], QB[0:2],
REF_OUT
20ꢀ
20ꢀ
20ꢀ
20ꢀ
QC[0:2]
tF
tF
tR
VOS
GND
LVDS OUTPUT RISE/FALL TIME
LVCMOS OUTPUT RISE/FALL TIME
VDDO
VDDO
➤
out
out
out
out
➤
DC Input
LVDS
LVDS
DC Input
100
V
OD/Δ VOD
➤
VOS/Δ VOS
➤
DIFFERENTIAL OUTPUT VOLTAGE SETUP
OFFSET VOLTAGE SETUP
IDT™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR
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APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perfor-
mance, power supply isolation is required. The ICS8402010I pro-
vides separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. VDD, VDDA and VDDO_X should
be individually connected to the power supply plane through
vias, and 0.01µF bypass capacitors should be used for each pin.
Figure 1 illustrates this for a generic VCC pin and also shows that
VDDA requires that an additional 10Ω resistor along with a 10µF
bypass capacitor be connected to the VDDA pin.
3.3V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS OUTPUTS
LVCMOS CONTROL PINS
All unused LVCMOS output can be left floating. There should be
no trace attached.
Control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
LVDS OUTPUTS
All unused LVDS outputs should be terminated with 100Ω resistor
between the differential pair.
IDT™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR
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CRYSTAL INPUT INTERFACE
The ICS8402010I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 2 below
were determined using a 25MHz, 18pF parallel resonant crystal
and were chosen to minimize the ppm error.
XTAL_IN
C1
27p
X1
18pF Parallel Crystal
XTAL_OUT
C2
27p
FIGURE 2. CRYSTAL INPUt INTERFACE
LVCMOS TO XTAL INTERFACE
(Ro) plus the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the crystal
input will attenuate the signal in half. This can be done in one
of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by
removing R1 and making R2 50Ω.
The XTAL_IN input can accept a single-ended LVCMOS
signal through an AC couple capacitor. A general interface
diagram is shown in Figure 3. The XTAL_OUT pin can be left
floating. The input edge rate can be as slow as 10ns. For
LVCMOS inputs, it is recommended that the amplitude be
reduced from full swing to half swing in order to prevent signal
interference with the power rail and to reduce noise. This
configuration requires that the output impedance of the driver
VDD
VDD
R1
.1uf
Ro
Rs
Zo = 50
XTAL_I N
R2
Zo = Ro + Rs
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
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LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
unused outputs.
3.3V
3.3V
LVDS_Driv er
+
R1
100
-
100 Ohm Differiential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
VFQFN EPADTHERMAL RELEASE PATH
In order to maximize both the removal of heat from the package
and the electrical performance, a land pattern must be
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in Figure 5. The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
are application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended
to determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as
many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process
which may result in voids in solder between the exposed pad/
slug and the thermal land. Precautions should be taken to
eliminate any solder voids between the exposed heat slug and
the land pattern. Note: These recommendations are to be used
as a guideline only. For further information, refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadfame Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias.
The vias act as “heat pipes”. The number of vias (i.e.“heat pipes”)
SOLDER
SOLDER
PIN
PIN
EXPOSED HEAT SLUG
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
FIGURE 5. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)
IDT™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8402010I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8402010I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
DD
Core and Output Power Dissipation
•
Power (core, output) = V
* (I + I
+ I ) = 3.465V * (25mA + 30mA + 15mA) = 242.6mW
DDO_X DDA
DD_MAX
DD
LVCMOS Output Power Dissipation
•
Output Impedance R Power Dissipation due to Loading 50Ω to V /2
OUT
DDO
Output Current IOUT = VDDO_MAX / [2 * (50Ω + ROUT)] = 3.465V / [2 * (50Ω + 20Ω)] = 24.7mA
•
•
Power Dissipation on the ROUT per LVCMOS output
2
Power (ROUT) = ROUT * (IOUT
)
= 20Ω * (24.7mA)2 = 12.25mW per output
Total Power Dissipation on the ROUT
Total Power (ROUT) = 12.25mW * 6 = 73.5mW
Total Power Dissipation
•
Total Power
= Power (core, output) + Power Dissipation (ROUT
= 242.6mW + 73.5mW
)
= 316.1mW
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2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the
TM
reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θ
= Junction-to-Ambient Thermal Resistance
JA
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ must be used.
JA
Assuming no air flow and a multi-layer board, the appropriate value is 37°C/W per Table 6.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.316W * 37°C/W = 96.7°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow, and the type of board.
TABLE 6. THERMAL RESISTANCE θ FOR 32-LEAD VFQFN, FORCED CONVECTION
JA
θ vs. Air Flow (Meters per Second)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
37.0°C/W
32.4°C/W
29.0°C/W
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RELIABILITY INFORMATION
TABLE 7. θ VS. AIR FLOW TABLE FOR 32 LEAD VFQFN
JA
θ vs. Air Flow (Meters per Second)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
37.0°C/W
32.4°C/W
29.0°C/W
TRANSISTOR COUNT
The transistor count for ICS8402010I is: 7782
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PACKAGE OUTLINE - K SUFFIX FOR 32 LEAD VFQFN
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package.This draw-
ing is not intended to convey the actual pin count or pin layout of
this device.The pin count and pinout are shown on the front page.
The package dimensions are in Table 8 below.
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS (VHHD -2/ -4)
SYMBOL
Minimum
Maximum
N
A
32
0.80
0
1.0
A1
A3
b
0.05
0.25 Reference
0.18
0.30
e
0.50 BASIC
ND
8
8
NE
D, E
D2, E2
L
5.0 BASIC
3.0
3.3
0.30
0.50
Reference Document: JEDEC Publication 95, MO-220
IDT™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR
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TABLE 8. ORDERING INFORMATION
Part/Order Number
8402010AKI
Marking
Package
Shipping Packaging
Tray
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS402010AI
ICS402010AI
ICS02010AIL
ICS02010AIL
32 Lead VFQFN
8402010AKIT
32 Lead VFQFN
1000 Tape & Reel
Tray
8402010AKILF
8402010AKILFT
32 Lead "Lead-Free" VFQFN
32 Lead "Lead-Free" VFQFN
1000 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
For Tech Support
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
netcom@idt.com
+480-763-2056
www.IDT.com/go/contactIDT
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
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