IRF7475 [INFINEON]
HEXFET Power MOSFET Selection for Non-Isolated DC/DC Converters; HEXFET功率MOSFET选择的非隔离式DC / DC转换器
| 型号： | IRF7475 |
| 厂家： | 
Infineon |
| 描述： | HEXFET Power MOSFET Selection for Non-Isolated DC/DC Converters |
| 文件： | 总10页 (文件大小：611K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 94531A
IRF7475
HEXFET® Power MOSFET
Applications
VDSS
RDS(on) max
Qg
19nC
l High Frequency Point-of-Load
Synchronous Buck Converter for
Applications in Networking &
Computing Systems.
15m @VGS = 4.5V
12V
A
A
D
1
2
3
4
8
S
S
S
G
Benefits
7
D
l Very Low RDS(on) at 4.5V VGS
l Ultra-Low Gate Impedance
l Fully Characterized Avalanche Voltage
and Current
6
D
5
D
SO-8
Top View
Absolute Maximum Ratings
Parameter
Drain-to-Source Voltage
Max.
12
Units
V
VDS
V
Gate-to-Source Voltage
12
GS
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
I
I
I
@ TA = 25°C
11
D
D
@ TA = 100°C
7.0
88
A
DM
Power Dissipation
P
P
@TA = 25°C
@TA = 70°C
2.5
1.6
W
D
D
Power Dissipation
Linear Derating Factor
Operating Junction and
0.02
-55 to + 150
W/°C
°C
T
J
T
Storage Temperature Range
STG
Thermal Resistance
Parameter
Junction-to-Drain Lead
Junction-to-Ambient
Typ.
–––
Max.
20
Units
°C/W
RθJL
RθJA
–––
50
Notes through are on page 10
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1
11/12/02
IRF7475
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max. Units
12 ––– –––
Conditions
VGS = 0V, ID = 250µA
BVDSS
∆Β
V
∆
V
DSS/ TJ
Breakdown Voltage Temp. Coefficient ––– 0.014 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on)
Static Drain-to-Source On-Resistance
–––
–––
0.6
11.5
20
15
50
VGS = 4.5V, ID = 8.8A
VGS = 2.8V, ID = 5.5A
VDS = VGS, ID = 250µA
Ω
m
VGS(th)
Gate Threshold Voltage
–––
3.2
–––
–––
–––
–––
–––
13
2.0
V
∆
VGS(th)
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
–––
–––
–––
–––
–––
22
––– mV/°C
IDSS
100
250
200
-200
–––
19
µA
nA
S
V
V
V
V
DS = 9.6V, VGS = 0V
DS = 9.6V, VGS = 0V, TJ = 125°C
GS = 12V
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Forward Transconductance
Total Gate Charge
GS = -12V
gfs
Qg
VDS = 6.0V, ID = 8.8A
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Qgs1
Pre-Vth Gate-to-Source Charge
Post-Vth Gate-to-Source Charge
Gate-to-Drain Charge
2.6
1.5
3.9
5.0
5.4
17
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
VDS = 6.0V
Qgs2
Qgd
nC
VGS = 4.5V
ID = 7.0A
Qgodr
Gate Charge Overdrive
See Fig. 16
Qsw
Switch Charge (Qgs2 + Qgd)
Qoss
td(on)
tr
Output Charge
nC VDS = 10V, VGS = 0V
VDD = 6.0V, VGS = 4.5V
ID = 8.8A
Turn-On Delay Time
Rise Time
7.5
33
td(off)
tf
Turn-Off Delay Time
Fall Time
13
ns Clamped Inductive Load
7.5
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
––– 1590 –––
––– 1310 –––
V
GS = 0V
pF
VDS = 6.0V
–––
260
–––
ƒ = 1.0MHz
Avalanche Characteristics
Parameter
Typ.
–––
–––
–––
Max.
Units
mJ
A
Single Pulse Avalanche Energy
EAS
IAR
180
8.8
Avalanche Current
Repetitive Avalanche Energy
EAR
0.25
mJ
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
IS
D
S
Continuous Source Current
–––
–––
11
MOSFET symbol
(Body Diode)
Pulsed Source Current
A
showing the
integral reverse
G
ISM
–––
–––
88
(Body Diode)
p-n junction diode.
VSD
trr
Diode Forward Voltage
–––
–––
–––
–––
42
1.3
63
66
V
T = 25°C, I = 8.8A, V = 0V
J S GS
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
ns T = 25°C, I = 8.8A, VDD = 10V
J F
Qrr
ton
di/dt = 100A/µs
44
nC
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
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IRF7475
100
10
1
100
10
1
V
V
GS
GS
TOP
10V
8.0V
4.5V
3.5V
3.0V
2.8V
2.25V
TOP
10V
8.0V
4.5V
3.5V
3.0V
2.8V
2.25V
BOTTOM 2.0V
BOTTOM 2.0V
2.0V
2.0V
20µs PULSE WIDTH
TJ = 25°C
20µs PULSE WIDTH
TJ = 150°C
0.1
0.1
0.1
1
10
100
0.1
1
10
100
V
V
, Drain-to-Source Voltage
,
Drain-to-Source Voltage (V)
(V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
2.0
100
ID = 11A
GS = 4.5V
V
1.5
1.0
0.5
0.0
TJ = 150°C
10
TJ = 25°C
VDS = 10V
20µs PULSE WIDTH
1
-60 -40 -20
0
20
40
60
80 100 120 140 160
1
2
3
4
5
TJ, Junction Temperature (°C)
V
, Gate-to-Source Voltage
GS
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
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3
IRF7475
10000
6
5
4
3
2
1
0
VGS = 0V,
f = 1 MHZ
ID = 7.0A
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
VDS = 12V
V
DS = 6.0V
Coss = Cds + Cgd
Ciss
1000
Coss
Crss
100
1
10
100
0
5
10
15
20
VDS, Drain-to-Source voltage (V)
QG, Total Gate Charge (nC)
Fig 6. Typical Gate Charge Vs.
Fig 5. Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000
100
10
100
10
1
OPERATION IN THIS AREA
LIMITED BY RDS(on)
TJ = 150ºC
10µsec
1msec
10msec
TJ = 25ºC
1
TC = 25ºC
TJ = 150ºC
Single Pulse
V
= 0V
GS
0.1
0.1
0.1
1
10
100
0.0
0.5
1.0
1.5
2.0
VDS, Drain-to-Source Voltage (V)
VSD, Source-to-Drain Voltage (V)
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
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IRF7475
1.6
1.4
1.2
1.0
0.8
12
9
ID = 250µA
6
3
0
25
50
75
100
125
150
-75
-50
-25
0
25
50
75
100
125
150
°
T , Case Temperature ( C)
C
TJ, Temperature (°C)
Fig 10. Threshold Voltage Vs. Temperature
Fig 9. Maximum Drain Current Vs.
Case Temperature
100
10
1
D = 0.50
0.20
0.10
0.05
P
2
DM
0.02
0.01
t
1
t
2
Notes:
1. Duty factor D = t / t
SINGLE PULSE
1
(THERMAL RESPONSE)
2. Peak T =P
J
x Z
+ T
thJA A
DM
0.1
0.00001
0.0001
0.001
0.01
0.1
1
10
100
t , Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF7475
500
400
300
200
100
0
15V
I
D
TOP
3.9A
7.0A
BOTTOM 8.8A
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
GS
Ω
0.01
t
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
150
Starting T , Junction Temperature (°C)
J
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I
AS
RD
VDS
Fig 12b. Unclamped Inductive Waveforms
VGS
D.U.T.
RG
+VDD
-
Current Regulator
Same Type as D.U.T.
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
50KΩ
.2µF
12V
Fig 14a. Switching Time Test Circuit
.3µF
+
V
DS
V
DS
D.U.T.
-
90%
V
GS
3mA
10%
V
I
I
GS
G
D
Current Sampling Resistors
t
t
r
t
t
f
d(on)
d(off)
Fig 13. Gate Charge Test Circuit
Fig 14b. Switching Time Waveforms
6
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IRF7475
Driver Gate Drive
P.W.
P.W.
D =
D.U.T
Period
Period
+
-
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Vds
Vgs
Vgs(th)
Qgs1
Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
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IRF7475
Power MOSFET Selection for Non-Isolated DC/DC Converters
Synchronous FET
Control FET
The power loss equation for Q2 is approximated
by;
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
P = P
+ P + P*
loss
conduction
drive
output
P = Irms 2 × Rds(on)
loss ( )
Power losses in the control switch Q1 are given
by;
+ Q × V × f
(
)
g
g
Qoss
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
+
×V × f + Q × V × f
(
)
in
rr
in
2
This can be expanded and approximated by;
*dissipated primarily in Q1.
P
= I 2 × Rds(on )
(
)
loss
rms
For the synchronous MOSFET Q2, Rds(on) is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and re-
verse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
Qgd
ig
Qgs2
ig
+ I ×
× V × f + I ×
× V × f
in
in
+ Q × V × f
(
)
g
g
Qoss
+
×V × f
in
2
This simplified loss equation includes the terms Qgs2
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to Idmax at which time the drain voltage be-
gins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitances Cds and Cdg when multiplied by
the power supply input buss voltage.
Figure A: Qoss Characteristic
8
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IRF7475
SO-8 Package Details
SO-8 Part Marking
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9
IRF7475
SO-8 Tape and Reel
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
330.00
(12.992)
MAX.
14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Starting TJ = 25°C, L = 4.7mH
RG = 25Ω, IAS = 8.8A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.11/02
10
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