Q67000-A9277 [INFINEON]
5-V Low-Drop Voltage Regulator; 5 -V低压差稳压器
| 型号： | Q67000-A9277 |
| 厂家： | 
Infineon |
| 描述： | 5-V Low-Drop Voltage Regulator |
| 文件： | 总11页 (文件大小：67K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
5-V Low-Drop Voltage Regulator
TLE 4265
Bipolar IC
Features
● Output voltage tolerance ≤ ± 2 %
● Low-drop voltage
● Very low standby current consumption
● Overtemperature protection
● Reverse polarity protection
● Short-circuit proof
● Setable reset threshold
● Wide temperature range
P-TO220-5-1
● Suitable for use in automotive electronics
Type
Ordering Code
Package
TLE 4265
Q67000-A9138
P-TO220-5-1
P-TO220-5-2
TLE 4265S Q67000-A9277
P-TO220-5-2
Functional Description
TLE 4265 is a 5-V low-drop voltage regulator in a TO220-5 package. Maximum input
voltage is 45 V. It can produce an output current of > 200 mA. The IC is shortcircuit-proof
and thermal protected.
Application
The IC regulates an input voltage VI in the range 6 V < VI < 45 V to VQrated = 5.0 V. A reset
signal is generated for an output voltage VQ of < 4.5 V. The reset delay can be set with
an external capacitor. This voltage regulator is especially suitable for microprocessor
applications in automobiles.
Semiconductor Group
1
1998-11-01
TLE 4265
Pin Configuration
(top view)
P-TO220-5-1
P-TO220-5-2
1
2
3
4
5
VΙ
GND
VQ
QRES DRES
AEP01492
Pin Definitions and Functions
Pin
1
Symbol Function
VI
Input voltage; block direct on IC with ceramic capacitor to GND
2
QRES
Reset output; open-collector output connected to output across
resistor of 30 kΩ
3
4
5
GND
DRES
VQ
Ground
Reset delay; wire with capacitor to GND for setting delay
5-V output voltage; block to GND with 22-µF capacitor
Semiconductor Group
2
1998-11-01
TLE 4265
Circuit Description
The control amplifier compares a highly precise reference voltage, produced by resistor
alignment, to a voltage that is proportional to the output voltage and drives the base of
the series transistor via a buffer. A saturation control, a function of the load current,
prevents any over-saturating of the power element. If the output voltage drops below
4.5 V, the external reset-delay capacitor is discharged by the reset generator. If the
voltage on the capacitor reaches the lower threshold VST, a signal is triggered on the
reset output and not canceled again until the upper threshold VdT is exceeded. The IC is
protected against overload, overtemperature and reverse polarity.
Temperature
Saturation
Sensor
Control and
Protection
1
5
4
In-
put
Output
Control
Reset
Delay
Amplifier
Buffer
Reset
Generator
Bandgap
Reference
+
-
Adjustment
2
Reset
Output
3
AEB01493
GND
Semiconductor Group
3
1998-11-01
TLE 4265
Block Diagram
Absolute Maximum Ratings
TJ = – 40 to 150 °C
Parameter
Symbol
Limit Values
Unit Notes
min.
max.
Input
Input voltage
VI
– 42
– 0.3
– 0.3
45
V
V
V
–
–
–
–
Reset Output
Voltage
VR
Vd
42
Reset Delay
Voltage
42
Output
Output voltage
Output current
VQ
IQ
– 0.3
–
7
–
V
–
Limited internally
GND
Current
IGND
– 0.1
–
A
–
Temperatures
Junction temperature
Storage temperature
TJ
–
150
150
°C
°C
–
–
Tstg
– 50
Operating Range
Input voltage
VI
TJ
–
45
V
–
–
Junction temperature
– 40
150
°C
Semiconductor Group
4
1998-11-01
TLE 4265
Absolute Maximum Ratings (cont’d)
TJ = – 40 to 150 °C
Parameter
Symbol
Limit Values
Unit Notes
min.
max.
Thermal Resistance
Junction ambient
Rthja
Rthjc
–
–
70
10
K/W –
K/W –
Junction-case
Optimum reliability and lifetime can be ensured in integrated circuits by not exceeding a
junction temperature of 125 °C during operation. Although operation up to the maximum
permissible junction temperature of 150 °C is possible, such boundary conditions, if
sustained, may affect device reliability.
Characteristics
VI = 13.5 V; TJ = 25 °C (unless specified otherwise)
Parameter
Symbol
Limit Values
min. typ. max.
5.1
Unit Test Condition
Output voltage
VQ
4.9
5
V
5 mA ≤ IQ ≤ 150 mA
6 V ≤ VI ≤ 28 V
– 40 °C ≤ TJ ≤ 125 °C
Output-current limiting IQ
200
–
250
750
–
mA
–
Current consumption
Iq
Iq
Iq
1000 µA
IQ = 0 mA
Iq = II – IQ
Current consumption
–
–
10
15
15
20
mA IQ = 150 mA
Iq = II – IQ
Current consumption
mA IQ = 150 mA
Iq = II – IQ
VI = 4.5 V
Drop voltage
VDr
–
–
0.35 0.5
V
IQ = 150 mA1)
Load regulation
∆VQ
–
25
mV IQ = 5 to 150 mA
Semiconductor Group
5
1998-11-01
TLE 4265
Characteristics (cont’d)
VI = 13.5 V; TJ = 25 °C (unless specified otherwise)
Parameter
Symbol
Limit Values
min. typ. max.
25
Unit Test Condition
Line regulation
∆VQ
–
–
15
54
mV VI = 6 to 28 V
IQ = 150 mA
Supply-voltage rejection
–
dB
fr = 100 Hz
Vr = 0.5 Vpp
SVR
Reset Generator
Switching threshold
Saturation voltage
Saturation voltage
Charge current
VRT
VR
VC
Ich
4.2
–
4.5
0.1
50
4.8
0.4
100
14
V
V
–
IR = 1 mA
–
mV VQ < VRT
7
10
µA
–
–
Delay switching
threshold
Vdt
1.5
1.8
2.1
V
Delay
Delay
td
tt
–
–
18
2
–
–
ms Cd = 100 nF
µs Cd = 100 nF
1) Drop voltage = VI – VQ (measured at point where VQ is 100 mV smaller than at VI = 13.5 V)
Semiconductor Group
6
1998-11-01
TLE 4265
ΙΙ
ΙQ
1
5
2
1000 µF
470 nF
22 µF
5.6 kΩ
TLE 4265
ΙR
VQ
VΙ
4
Ιch
3
ΙGND
VR
CD
VC
AES01494
Test Circuit
1
5
4
Output
Input
6V to 45 V
470 nF
TLE 4265
2
22 µF
Reset
To MC
100 nF
3
AES01495
Application Circuit
Semiconductor Group
7
1998-11-01
TLE 4265
Drop Voltage versus Output Current
Current Consumption versus
Output Current
AED01497
AED01496
28
700
VDr
mV
Ιq
mA
500
400
300
VΙ = 13.5 V
20
16
12
8
Tj = 25 C
200
100
0
4
0
0
50
100
150
200
300
mA
ΙQ
0
50
100
150
200
300
mA
ΙQ
Current Consumption versus Input
Voltage
Output Voltage versus Input Voltage
AED01498
AED01499
30
12
RL = 25 Ω
RL= 25 Ω
VQ
Ι q
V
8
6
4
2
0
mA
20
15
10
5
0
0
2
4
6
V
10
0
10
20
30
V
50
VΙ
VΙ
Semiconductor Group
8
1998-11-01
TLE 4265
Charge Current versus Temperature
Switching Voltage VdT and VST versus
Temperature
AED01501
AED01500
3.2
14
VdT
Ιch
µA
Ιch
V
VΙ = 13.5 V
2.4
2.0
1.6
1.2
0.8
0.4
0
10
VΙ = 13.5 V
V
C = 1.5 V
8
6
4
2
VdT
-40
0
40
80
C
160
-40
0
40
80
C
160
Tj
Tj
Output Voltage versus Temperature
Output Voltage versus Input Voltage
AED01503
AED01502
300
5.10
mA
Tj = 25 C
Ι Q
VQ
VΙ = 13.5 V
V
250
5.00
200
150
100
50
4.90
4.80
4.70
0
-40
0
40
80
C
160
0
10
20
30
40
50
Tj
Vj
Semiconductor Group
9
1998-11-01
TLE 4265
Package Outlines
P-TO220-5-1
(Plastic Transistor Single Outline)
10+0.4
4.6-0.2
10.2-0.2
3.75+0.1
1x45˚
1.27+0.1
2.6
1
5
0.4+0.1
1.7
0.8+0.1
1)
±0.4
4.5
8.4
M
0.6
±0.4
5x
1) 1-0.15 at dam bar (max 1.8 from body)
1) 1-0.15 im Dichtstegbereich (max 1.8 vom Körper)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
Semiconductor Group
10
1998-11-01
TLE 4265
P-TO220-5-2
(Plastic Transistor Single Outline)
10+0.4
4.6-0.2
10.2 -0.2
3.75+0.1
1x45˚
1.27+0.1
1
5
0.4+0.1
1.7
0.8+0.1
1)
±0.15
2.6
M
0.6
5x
1) 1-0.15 at dam bar (max 1.8 from body)
1) 1-0.15 im Dichtstegbereich (max 1.8 vom Körper)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
Semiconductor Group
11
1998-11-01
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