PHD66NQ03LT/T3 [NXP]
TRANSISTOR 66 A, 25 V, 0.0136 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-252AA, PLASTIC, SC-63, TO-252, DPAK-3, FET General Purpose Power;
| 型号： | PHD66NQ03LT/T3 |
| 厂家： | 
NXP |
| 描述： | TRANSISTOR 66 A, 25 V, 0.0136 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-252AA, PLASTIC, SC-63, TO-252, DPAK-3, FET General Purpose Power 开关 脉冲 晶体管 |
| 文件： | 总13页 (文件大小：80K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PHB/PHD66NQ03LT
N-channel TrenchMOS™ logic level FET
Rev. 06 — 2 August 2004
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode field effect transistor in a plastic package using
TrenchMOS™ technology.
1.2 Features
■ Logic level threshold
■ Low on-state resistance.
1.3 Applications
■ DC-to-DC converters
■ General purpose switching.
1.4 Quick reference data
■ VDS ≤ 25 V
■ ID ≤ 66 A
■ RDSon ≤ 10.5 mΩ
■ Qgd = 3.6 nC (typ).
2. Pinning information
Table 1:
Discrete pinning
Pin
1
Description
gate (g)
Simplified outline
Symbol
mb
d
s
mb
[1]
2
drain (d)
3
source (s)
g
mb
mounting base;
connected to drain (d)
mbb076
2
1
3
2
Top view
1
3
SOT404 (D2-PAK)
SOT428 (D-PAK)
[1] It is not possible to make a connection to pin 2 of the SOT404 and SOT428 packages.
PHB/PHD66NQ03LT
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
3. Ordering information
Table 2:
Ordering information
Type number
Package
Name
Description
Version
PHB66NQ03LT
PHD66NQ03LT
D2-PAK
Plastic single-ended surface mounted package (Philips version of D2-PAK); SOT404
3 leads (one lead cropped)
D-PAK
Plastic single-ended surface mounted package (Philips version of D-PAK); SOT428
3 leads (one lead cropped)
4. Limiting values
Table 3:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
25
Unit
V
VDS
VDGR
VGS
ID
drain-source voltage (DC)
25 °C ≤ Tj ≤ 175 °C
-
drain-gate voltage (DC)
gate-source voltage (DC)
drain current (DC)
25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ
-
25
V
-
±20
57
V
Tmb = 25 °C; VGS = 5 V; Figure 2 and 3
Tmb = 100 °C; VGS = 5 V; Figure 2
Tmb = 25 °C; VGS = 10 V
-
A
-
40
A
-
66
A
Tmb = 100 °C; VGS = 10 V
-
45
A
IDM
Ptot
Tstg
Tj
peak drain current
Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3
Tmb = 25 °C; Figure 1
-
228
93
A
total power dissipation
storage temperature
junction temperature
-
W
°C
°C
−55
−55
+175
+175
Source-drain diode
IS
source (diode forward) current (DC) Tmb = 25 °C
-
-
57
A
A
ISM
peak source (diode forward) current Tmb = 25 °C; pulsed; tp ≤ 10 µs
228
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy
unclamped inductive load; ID = 43 A;
tp = 0.15 ms; VDD ≤ 25 V; RGS = 50 Ω;
-
90
mJ
VGS = 10 V; starting at Tj = 25 °C
9397 750 13429
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 06 — 2 August 2004
2 of 13
PHB/PHD66NQ03LT
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
03aa16
03aa24
120
120
Ider
(%)
Pder
(%)
80
80
40
0
40
0
0
50
100
150
200
mb (°C)
0
50
100
150
200
Tmb ( C)
°
T
Ptot
ID
Pder
=
× 100%
Ider
=
× 100%
-----------------------
-------------------
P
I
°
°
tot(25 C)
D(25 C)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
Fig 2. Normalized continuous drain current as a
function of mounting base temperature.
03ag19
103
ID
(A)
t = 10
p
s
µ
Limit RDSon = VDS / ID
102
100
s
µ
DC
1 ms
10 ms
10
100 ms
1
1
10
102
VDS (V)
Tmb = 25 °C; IDM is single pulse; VGS = 5 V
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 13429
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 06 — 2 August 2004
3 of 13
PHB/PHD66NQ03LT
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
5. Thermal characteristics
Table 4:
Thermal characteristics
Symbol Parameter
Conditions
Min Typ Max Unit
Rth(j-mb) thermal resistance from junction to mounting
base
Figure 4
-
-
1.6 K/W
Rth(j-a)
thermal resistance from junction to ambient
SOT404
mounted on a printed-circuit board;
minimum footprint; vertical in still
air
-
-
-
50
75
50
-
-
-
K/W
K/W
K/W
SOT428
mounted on a printed-circuit board;
minimum footprint; vertical in still
air
mounted on a printed-circuit board;
SOT404 minimum footprint; vertical
in still air
5.1 Transient thermal impedance
03ag18
10
Zth(j-mb)
(K/W)
1
= 0.5
δ
0.2
0.1
tp
P
δ =
10-1
0.05
T
0.02
single pulse
t
tp
T
10-2
10-5
10-4
10-3
10-2
10-1
1
10
tp (s)
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
9397 750 13429
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 06 — 2 August 2004
4 of 13
PHB/PHD66NQ03LT
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
6. Characteristics
Table 5:
Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max Unit
Static characteristics
V(BR)DSS drain-source breakdown voltage
ID = 250 µA; VGS = 0 V
Tj = 25 °C
25
22
-
-
-
-
V
V
Tj = −55 °C
VGS(th)
gate-source threshold voltage
drain-source leakage current
ID = 1 mA; VDS = VGS; Figure 9 and 10
Tj = 25 °C
1
1.5
2
V
V
V
Tj = 175 °C
0.5
-
-
-
-
Tj = −55 °C
2.2
IDSS
VDS = 25 V; VGS = 0 V
Tj = 25 °C
-
-
-
-
10
µA
µA
nA
Tj = 175 °C
-
500
100
IGSS
gate-source leakage current
VGS = ±15 V; VDS = 0 V
VGS = 10 V; ID = 25 A; Figure 6 and 8
Tj = 25 °C
10
RDSon
drain-source on-state resistance
-
-
-
9.1
10.5 mΩ
Tj = 175 °C
16.4 18.9 mΩ
11.2 13.6 mΩ
VGS = 5 V; ID = 25 A; Figure 6 and 8
Dynamic characteristics
Qg(tot)
Qgs
Qgd
Ciss
Coss
Crss
td(on)
tr
total gate charge
gate-source charge
gate-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
ID = 50 A; VDS = 15 V; VGS = 5 V;
Figure 11
-
-
-
-
-
-
-
-
-
-
12
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
4.5
3.6
860
330
145
15
-
-
VGS = 0 V; VDS = 25 V; f = 1 MHz;
Figure 13
-
-
-
VDS = 15 V; RL = 0.6 Ω;
25
135
40
40
VGS = 5 V; RG = 5.6 Ω
90
td(off)
tf
turn-off delay time
fall time
25
25
Source-drain diode
VSD
trr
source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 12
-
-
-
0.95 1.2
V
reverse recovery time
recovered charge
IS = 10 A; dIS/dt = −100 A/µs;
GS = 0 V; VR = 25 V
32
20
-
-
ns
nC
V
Qr
9397 750 13429
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 06 — 2 August 2004
5 of 13
PHB/PHD66NQ03LT
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
03ag20
03ag21
80
25
RDSon
(m
T = 25
j
C
°
T = 25
j
C
°
10 V 6 V 5 V
ID
4.5 V
)
Ω
(A)
VGS = 4.5 V
20
15
10
5
60
4 V
5V
40
20
0
6 V
10 V
3.5 V
VGS = 3 V
0
0
0.5
1
1.5
2
0
20
40
60
80
VDS (V)
ID (A)
Tj = 25 °C
Tj = 25 °C
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values.
Fig 6. Drain-source on-state resistance as a function
of drain current; typical values.
03ag22
03af18
80
ID
2
VDS > ID x RDSon
a
(A)
60
1.5
40
20
1
0.5
0
T = 25 C
°
175
2
C
j
°
0
0
1
3
4
5
-60
0
60
120
180
VGS (V)
T ( C)
°
j
Tj = 25 °C and 175 °C; VDS > ID x RDSon
RDSon
a =
----------------------------
RDSon(25 C)
°
Fig 7. Transfer characteristics: drain current as a
function of gate-source voltage; typical values.
Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature.
9397 750 13429
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 06 — 2 August 2004
6 of 13
PHB/PHD66NQ03LT
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
03aa33
03aa36
2.5
VGS(th)
(V)
10-1
ID
(A)
2
10-2
10-3
10-4
10-5
10-6
max
1.5
typ
min
typ
max
min
1
0.5
0
-60
0
60
120
180
0
1
2
3
T ( C)
VGS (V)
°
j
ID = 1 mA; VDS = VGS
Tj = 25 °C; VDS = 5 V
Fig 9. Gate-source threshold voltage as a function of
junction temperature.
Fig 10. Sub-threshold drain current as a function of
gate-source voltage.
03ag25
10
T = 25
C
°
VGS
(V)
j
ID = 50 A
VDD = 15 V
8
6
4
2
0
0
10
20
30
QG (nC)
ID = 50 A; VDS = 15 V
Fig 11. Gate-source voltage as a function of gate charge; typical values.
9397 750 13429
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 06 — 2 August 2004
7 of 13
PHB/PHD66NQ03LT
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
03ag23
03ag24
80
104
VGS = 0 V
IS
(A)
60
C
(pF)
40
20
103
Ciss
Coss
T = 25
j
C
175
C
°
°
Crss
0
102
10-1
0
0.3
0.6
0.9
1.2
1
10
102
VSD (V)
VDS (V)
Tj = 25 °C and 175 °C; VGS = 0 V
VGS = 0 V; f = 1 MHz
Fig 12. Source (diode forward) current as a function of
source-drain (diode forward) voltage; typical
values.
Fig 13. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values.
9397 750 13429
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 06 — 2 August 2004
8 of 13
PHB/PHD66NQ03LT
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
7. Package outline
2
Plastic single-ended surface mounted package (Philips version of D -PAK); 3 leads
(one lead cropped)
SOT404
A
A
E
1
mounting
base
D
1
D
H
D
2
L
p
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
D
E
A
A
b
UNIT
c
D
e
L
H
Q
1
1
p
D
max.
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
1.60
1.20
10.30
9.70
2.90 15.80 2.60
2.10 14.80 2.20
mm
11
2.54
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
99-06-25
01-02-12
SOT404
Fig 14. SOT404 (D2-PAK) package outline.
9397 750 13429
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 06 — 2 August 2004
9 of 13
PHB/PHD66NQ03LT
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads
(one lead cropped)
SOT428
seating plane
y
A
A
E
A
2
A
b
E
1
1
2
mounting
base
D
1
D
H
E
L
2
2
L
1
L
1
3
b
b
w
M
A
c
1
e
e
1
0
10
20 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
D
L
y
1
1
A
A
A
b
D
E
E
H
UNIT
b
b
c
e
e
1
L
L
w
2
1
2
1
E
1
2
max.
min.
min.
0.65
0.45
0.89
0.71
0.9
0.5
2.38
2.22
0.93
0.73
1.1
0.9
5.46
5.26
0.4 6.22
0.2 5.98
6.73
6.47
10.4 2.95
9.6
2.55
4.81
4.45
mm
4.57
0.2
0.2
4.0
2.285
0.5
Note
1. Measured from heatsink back to lead.
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
JEITA
99-09-13
01-12-11
SOT428
TO-252
SC-63
Fig 15. SOT428 (D-PAK) package outline.
9397 750 13429
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 06 — 2 August 2004
10 of 13
PHB/PHD66NQ03LT
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
8. Revision history
Table 6:
Revision history
Document ID
Release Data sheet Change
Document
number
Supersedes
date
20040802 Product
data sheet
status
notice
PHB_PHD66NQ03LT_6
Modifications:
-
9397 750 13429 PHP_PHB_PHD66NQ03LT_5
• Removal of PHP66NQ03LT (now in separate data sheet)
• Data sheet updated to latest standard.
PHP_PHB_PHD66NQ03LT_5 20040415 Product
data sheet
-
-
-
-
-
9397 750 13107 PHP_PHB_PHD66NQ03LT_4
9397 750 10158 PHP_PHB_PHD66NQ03LT_3
9397 750 09284 PHP_PHB_PHD66NQ03LT_2
9397 750 09119 PHP_PHB_PHD66NQ03LT_1
PHP_PHB_PHD66NQ03LT_4 20020909 Product
data sheet
PHP_PHB_PHD66NQ03LT_3 20020312 Product
data sheet
PHP_PHB_PHD66NQ03LT_2 20011210 Product
data sheet
PHP_PHB_PHD66NQ03LT_1 20011012 Product
data sheet
9397 750 08725
-
9397 750 13429
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 06 — 2 August 2004
11 of 13
PHB/PHD66NQ03LT
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
9. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
10. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
12. Trademarks
TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.
11. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
13. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 13429
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 06 — 2 August 2004
12 of 13
PHB/PHD66NQ03LT
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
14. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
1.4
2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Transient thermal impedance . . . . . . . . . . . . . . 4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 12
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Contact information . . . . . . . . . . . . . . . . . . . . 12
3
4
5
5.1
6
7
8
9
10
11
12
13
© Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 2 August 2004
Document order number: 9397 750 13429
Published in The Netherlands
相关型号：
PHD78NQ03LT/T3
TRANSISTOR 75 A, 25 V, 0.0135 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-252, PLASTIC, SC-63, DPAK-3, FET General Purpose Power
NXP
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