UAA3202M-T [NXP]
IC SPECIALTY TELECOM CIRCUIT, PDSO20, PLASTIC, SOT-339, SSOP-20, Telecom IC:Other;
| 型号： | UAA3202M-T |
| 厂家： | 
NXP |
| 描述： | IC SPECIALTY TELECOM CIRCUIT, PDSO20, PLASTIC, SOT-339, SSOP-20, Telecom IC:Other |
| 文件： | 总24页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
UAA3202M
Frequency Shift Keying (FSK)
receiver
1997 Aug 12
Preliminary specification
File under Integrated Circuits, IC01
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
FEATURES
GENERAL DESCRIPTION
• Low cost single-chip FSK receiver
• Superheterodyne architecture with high integration level
• Few external low cost components
• Wide supply voltage range
The UAA3202M is a fully integrated single-chip receiver,
primarily intended for use in VHF and UHF systems
employing direct Frequency Shift Keying (FSK)
modulation. The UAA3202M incorporates a SAW
stabilized local oscillator, balanced mixer, IF amplifier,
limiter, Received Signal Strength Indicator (RSSI), RSSI
comparator, FSK demodulator, data filter and data slicer.
The device features a power-down mode in order to
minimize the average receiver supply current.
• Low power consumption
• Wide frequency range, 150 to 450 MHz
• High sensitivity
• IF band determined by application
• High selectivity
• Very low spurious radiation, −60 dBm
(meets FTZ 17TR2100)
• Automotive temperature range
• Power-down mode
• SSOP20 package.
Applications
• Keyless entry systems
• Car alarm systems
• Remote control systems
• Security systems
• Telemetry systems
• Wireless data transmission
• Domestic appliances.
QUICK REFERENCE DATA
SYMBOL
VCC
PARAMETER
supply voltage
CONDITIONS
MIN.
3.5
TYP.
MAX.
UNIT
−
6
V
ICC
supply current for
operating mode on
operating mode off
sensitivity
V
PWD = 0 V; R2 = 560 Ω
2.0
−
3.4
3
4.7
30
mA
µA
VPWD = VCC
Psens
fi = 433.92 MHz;
−
−
−94
dBm
fmod = 250 Hz square wave;
∆f = ±25 kHz; BER ≤ 3%
Tamb
operating ambient temperature
−40
−
+85
°C
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
UAA3202M
SSOP20
SOT339-1
plastic shrink small outline package; 20 leads; body width 5.3 mm
1997 Aug 12
2
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
BLOCK DIAGRAM
HM9A7
bnok,lfuapgedwith
1997 Aug 12
3
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
PINNING
SYMBOL PIN
DESCRIPTION
negative mixer output
MON
MOP
VCC
1
2
3
4
5
6
7
8
9
positive mixer output
positive supply voltage
oscillator collector
handbook, halfpage
MON
MOP
20 FA
1
2
OSC
OSE
VEO
V
19
18 MXIN
17
EM
oscillator emitter
V
3
CC
negative supply voltage for oscillator
negative supply voltage
RSSI comparator output
comparator input B
OSC
OSE
LIN
4
VEE
16 LFB
5
COMP
CPB
CPA
DATA
PWD
CPC
DMOD
RSSI
LFB
UAA3202M
V
6
15 RSSI
EO
10 comparator input A
11 data output
V
DMOD
7
14
EE
COMP
CPB
8
13 CPC
12 power-down control input
13 comparator input C
14 demodulator frequency adjustment
15 RSSI current output
16 limiter feedback
PWD
9
12
11
CPA
DATA
10
MHA796
LIN
17 limiter input
MXIN
VEM
18 mixer input
19 negative supply voltage for mixer
20 IF amplifier output
Fig.2 Pin configuration.
FA
1997 Aug 12
4
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
FUNCTIONAL DESCRIPTION
Post mixer amplifier
The device is based on the superheterodyne architecture
incorporating a mixer, local oscillator, IF amplifier, limiter,
RSSI, RSSI comparator, FSK demodulator, data filter,
data slicer and power-down circuitry. The device employs
a low IF frequency of typically 1 MHz in order to allow IF
filtering by means of external low cost R, L and C
The Post Mixer Amplifier (PMA) is a differential input,
single-ended output amplifier. It separates the first and
second IF filters from each other. Amplifier gain is provided
in order to reduce the influence of the limiter noise figure
on the total noise figure.
components. If image rejection is required it can be
achieved by applying a matching external front-end SAW
filter. The device provides a wide IF range of 300 kHz in
order to allow the use of a SAW stabilized oscillator.
Limiter
The limiter is a single-ended input multiple stage amplifier
with high total gain. Amplifier stability is achieved by
means of an external DC feedback capacitor, which is also
used to determine the lower limiter cut-off frequency.
An RSSI signal proportional to the limiter input signal is
provided.
The on-chip local oscillator provides the injection signal for
the mixer. Tuning of the on-chip local oscillator is not
necessary. The oscillator frequency is determined by an
external 1-port SAW resonator. The RF input signal is fed
to the mixer and down converted to the IF frequency. After
amplification and filtering the RF signal is applied to a
limiter. The IF filter order and characteristics are
IF filters
IF filtering with high selectivity is realized by means of
external low cost R, L and C components. The first IF filter
is located directly following the mixer output. An external
L/C network assembles a band-pass with low sensitivity in
order to meet the bandwidth of an elliptic low-pass filter
external to the device and is located in front of the limiter.
The filter source impedance is determined by the drive
impedance of the IF amplifier. In order to improve the IF
filter selectivity below the pass-band a high-pass
characteristic is added by means of a DC blocking
capacitor in front of the limiter input and by means of the
limiter DC feedback capacitor.
determined by the external low cost R, L and C
components. The limiter amplifier provides a RSSI signal
which can be routed to an on-chip RSSI level comparator
in order to derive a field strength indication for external
use. The limited IF signal is fed to the FSK demodulator.
The demodulator centre frequency is determined by an
external capacitor. No alignment is necessary for the FSK
demodulator. After filtering the demodulated data signal is
fed to a data slicer and is made available at the data
output. The data filter characteristics are determined by
external capacitors. The data slicer employs an adaptive
slice reference in order to track frequency offsets.
RSSI
The device is switched from power-down to operating
mode and vice versa by means of a control input.
Extremely low supply current is drawn when the device is
in power-down mode. Measures are taken to allow fast
receiver settling when the device is switched from
power-down to operating mode.
The RSSI signal is a current proportional to the limiter input
level (RF input power). By means of an external resistor
the resulting RSSI voltage level is set in order to fit the
application. The RSSI voltage is available to external
circuits and is fed to the input of the RSSI level
comparator. For RSSI filtering an external capacitor is
connected.
Mixer
The mixer is a single balanced emitter coupled mixer with
internal biasing. Matching of the RF source impedance to
the mixer input requires an external matching network.
RSSI level comparator
The RSSI level comparator compares the RSSI level with
a fixed and independent internal reference voltage. If the
RSSI level exceeds the internal reference voltage a logic
HIGH signal is generated. The level comparator provides
some hysteresis in order to avoid spurious oscillation.
The output of the level comparator is designed as an
open-collector with internal pull-up.
Oscillator
The oscillator consists of an on-chip transistor in common
base configuration. An external tank and SAW resonator
determines the oscillator frequency. Oscillator alignment is
not necessary. Oscillator bias is controlled by an external
resistor.
1997 Aug 12
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Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
The other path is fed to an integration circuit with a large
time constant in order to derive the average value
(DC component) as an adaptive slice reference which is
presented to the negative comparator input. The adaptive
reference enables the received data over a large range of
demodulator frequency offsets to be detected.
The integration circuit consists of a simple R/C low-pass
filter with on-chip resistor. The level comparator output is
designed as an open-collector with internal pull-up.
FSK demodulator
The limited IF signal is converted into baseband data by
means of a quadrature FM demodulator consisting of an
all-pass filter and a mixer stage. No alignment of the
demodulator is necessary. The demodulator centre
frequency is set by a capacitor external to the device.
The demodulator provides a large audio bandwidth in
order to allow high data rate applications.
The demodulator can detect a small IF frequency deviation
even if a relatively large IF frequency offset is
encountered.
Power-down circuitry
The device provides a power-down mode. While in
power-down mode the device disables the majority of the
internal circuits and consumes extremely low current.
Measures are taken to allow fast receiver settling when
normal operation is resumed. Thus circuits with large time
constants are only powered down partly or provide a high
impedance during power-down in order to avoid the
discharge of external capacitors as much as possible.
Power-down mode is entered when the control input is
active HIGH. The control input provides an internal pull-up
resistor of high impedance.
Data filters
After demodulation a two-stage data filtering circuit is
provided in order to suppress unwanted frequency
components. Two R/C low-pass filters with on-chip
resistors are provided which are separated by a buffer
stage.
Data slicer
Data detection is provided by means of a level comparator
with adaptive slice reference. After the first data filter stage
the pre-filtered data is split into two parts. One part passes
the second data filter stage and is fed to the positive
comparator input.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS
VCC supply voltage
MIN.
−0.3
MAX.
+8.0
UNIT
V
Tamb
Tstg
operating ambient temperature
storage temperature
electrostatic handling
pins 4 and 5
−40
−55
+85
°C
°C
+125
Vesd
note 1
−2000
−1500
−2000
+1500
+2000
+2000
V
V
V
pins 18 and 19
all other pins
Note
1. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
VALUE
UNIT
thermal resistance from junction to ambient in free air
125
K/W
1997 Aug 12
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Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
DC CHARACTERISTICS
VCC = 3.5 V; Tamb = 25 °C; for application diagram see Fig.11; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VCC
ICC
supply voltage
3.5
−
6
V
supply current for
operating mode on
note 1
VPWD = 0 V;
2.0
3.4
4.7
mA
R2 = 560 Ω
operating mode off
VPWD = VCC
−
3
30
µA
mV
V
VPWD(on)
VPWD(off)
IPWD(on)
PWD voltage for operating mode ON
PWD voltage for operating mode OFF
PWD current for operating mode ON
PWD current for operating mode OFF
0
−
300
VCC
−3
V
CC − 0.3 −
VPWD = 0 V
VPWD = VCC
−30
−
−10
µA
µA
IPWD(off)
1
3
Oscillator
VOSC(DC)
Mixer
DC operating point pin 4
3.28
3.34
3.40
V
VMXIN(DC)
VMOP(DC)
VMON(DC)
DC operating point pin 18
DC operating point pin 2
DC operating point pin 1
0.68
2.78
2.78
0.78
2.98
2.98
0.88
3.18
3.18
V
V
V
Post mixer amplifier
VFA(DC)
DC operating point pin 20
2.14
2.27
2.40
V
Limiter
VLIN(DC)
VLFB(DC)
VRSSI(DC)
DC operating point pin 17
DC operating point pin 16
DC operating point pin 15
3.45
2.76
2.21
3.49
2.81
2.36
3.50
2.86
2.51
V
V
V
Demodulator
VDMOD(DC) DC operating point pin 14
Data slicer
1.63
1.83
2.03
V
VCPC(DC)
VCPA(DC)
VCPB(DC)
VOH(DAT)
VOL(DAT)
DC operating point pin 13
DC operating point pin 10
DC operating point pin 9
note 2
1.43
1.43
1.43
1.93
1.93
1.93
2.43
2.43
2.43
VCC
0.6
V
V
V
V
V
note 2
note 2
HIGH-level data output voltage
LOW-level data output voltage
IDATA = −10 µA
IDATA = 200 µA
V
0
CC − 0.5 −
−
RSSI comparator
VOH(RSSI) HIGH-level comparator output voltage
VOL(RSSI) LOW-level comparator output voltage
IRSSI = −10 µA
IRSSI = 200 µA
V
0
CC − 0.5 −
VCC
0.6
V
V
−
Notes
1. The given values are valid for the whole temperature range from Tamb = −40 to +85 °C.
2. Tune RF input frequency until IF = 1 MHz.
1997 Aug 12
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Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
AC CHARACTERISTICS
VCC = 3.5 V; Tamb = 25 °C; for application diagram see Fig.11; fi = 433.92 MHz; ∆f = ±25 kHz; fmod = 250 Hz square
wave, i.e. 500 bits/s; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
System performance
Psens
Pi(max)
αrad
sensitivity
BER ≤ 3%
−
−
−
−
2
−94
−30
−60
5
dBm
dBm
dBm
ms
maximum input power
spurious radiation
receiver settling time
IF bandwidth range
data frequency
BER ≤ 3%
−
note 1
−
tst
Pi = Psens + 10 dB; see Fig.5
Pi = Psens + 3 dB
−
BIF
850
140
1000 1150 kHz
fD
−
250
Hz
Mixer
Gmix
Ro(mix)
mixer conversion gain
mixer output resistance
31
33
3
35
dB
2.7
3.3
kΩ
Post mixer amplifier
IP3PMA
GPMA
P<1dB
BWPMA
RoPMA
Limiter
Glim
interception point (mixer + PMA)
note 2
−38
9
−35
−
dBm
dB
PMA gain
note 2
10.4 12
compression (mixer + PMA)
PMA LP cut-off frequency
PMA output resistance
Pi = −45 dBm
0
−
1
dBm
MHz
kΩ
5
−
−
1.2
1.4
1.6
limiter gain
60
2
63.5 67
dB
Blim
limiter LP cut-off frequency
limiter input resistance
5
8
MHz
kΩ
Ri(lim)
40
50
60
Demodulator
GDMOD
demodulator gain
note 2
0.8
1
1.2
mV
---------
kHz
fc(DMOD)
demodulator centre frequency
frequency deviation
800
20
1000 1200 kHz
∆f
25
30
70
36
kHz
Ro(DMOD) demodulator output resistance
24
kΩ
Data slicer
BDS
data slicer bandwidth
35
50
−
kHz
Ro(DS)
data slicer output resistance
120
150
180
kΩ
RSSI comparator
Vo(RSSI)
RSSI output voltage
see Fig.3
see Fig.4
−
−
−
−
−
−
−
−
Vo(COMP) COMP output voltage
Pth(on)
threshold for switching COMP output
−99.5 −95.5 −91.5 dBm
voltage to HIGH
Phys(W)
hysteresis width of COMP output voltage
1
2
4
dBm
Notes
1. Measured at the RF input connector of the test board.
2. Measured at test point A in Fig.11.
1997 Aug 12
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Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
2.8
V
(1)
o(RSSI)
(V)
2.7
(2)
(3)
2.6
2.5
2.4
−100
−90
−80
−70
−60
−50
P (dBm)
i
MHA811
(1) Tamb = 85 °C.
(2) Tamb = 25 °C.
(3) Tamb = −40 °C.
Fig.3 RSSI output voltage as a function of RF input power.
MHA812
handbook, halfpage
V
o(COMP)
(V)
P
hys(W)
3.0
0.6
−97.5
−95.5
P (dBm)
i
P
th(ON)
Fig.4 Comparator output voltage as a function of HF input power.
9
1997 Aug 12
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
INTERNAL CIRCUITRY
Table 1 Equivalent pin circuits and pin voltages for rough test of printed circuit board; VCC = 3.5 V; no input signal
DC VOLTAGE
PIN
SYMBOL
EQUIVALENT CIRCUIT
(V)
1
2
MON
MOP
2.98
2.98
V
CC
1.5 kΩ
1.5 kΩ
1
2
V
EE
MHA798
V
EM
3
4
5
VCC
−
3.34
−
OSC
OSE
4
5
6 kΩ
MHA799
V
EE
6
7
8
VEO
0
0
−
VEE
COMP
V
CC
1 kΩ
8
V
MHA800
EE
9
CPB
CPA
1.93
1.93
V
CC
10
9
150 kΩ
150 Ω
10
V
EE
MHA801
1997 Aug 12
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Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
DC VOLTAGE
PIN
SYMBOL
EQUIVALENT CIRCUIT
(V)
11
DATA
−
V
CC
1 kΩ
11
V
MHA802
EE
12
PWD
−
V
CC
300 kΩ
12
MHA803
13
CPC
1.93
V
CC
30 kΩ
13
V
EE
MHA804
14
DMOD
1.83
V
CC
14
V
EE
MHA805
1997 Aug 12
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Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
DC VOLTAGE
PIN
SYMBOL
EQUIVALENT CIRCUIT
(V)
15
RSSI
2.36
V
CC
MHA806
15
16
LFB
2.81
V
CC
16
V
EE
MHA807
17
LIN
3.49
V
CC
50 kΩ
17
MHA808
V
EE
1997 Aug 12
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Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
DC VOLTAGE
PIN
SYMBOL
EQUIVALENT CIRCUIT
(V)
18
19
MXIN
VEM
0.78
0
18
15 Ω
19
MHA809
20
FA
2.27
V
CC
1.2 kΩ
20
MHA810
V
EE
1997 Aug 12
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Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
TEST INFORMATION
Tuning procedure for AC tests
1. Turn on the signal generator (fi = 433.92 MHz; no modulation; RF input level = −60 dBm).
2. Tune C6 (RF stage input) to obtain a peak voltage on test point A (see Fig.11).
3. Turn on modulation (fi = 433.92 MHz; fmod = 250 Hz square wave; ∆f = 25 kHz; RF input level = −60 dBm).
4. Check that data is appearing on the data output (pin 11) and proceed with the AC tests.
AC test conditions
Table 2 Test signals
The reference signal level Pref for the following tests is defined as the minimum input level in dBm to give a
BER ≤ 3 × 10−2 (e.g. 15 bit errors per second for 500 bits/s).
TEST
SIGNAL
FREQUENCY
(MHz)
FREQUENCY
DEVIATION
DATA SIGNAL
MODULATION
1
2
3
433.92
433.92
433.82
250 Hz square wave
FM (FSK)
25 kHz
−
−
no modulation
no modulation
−
−
Table 3 Test results
P1 is the maximum available power from signal generator 1 at the input of the test board; P2 is the maximum available
power from signal generator 2 at the input of the test board.
GENERATOR
TEST
RESULT
1
2
Sensitivity into pin MXIN
(see Fig.6)
modulated test
signal 1; P1 ≤ −94 dBm
−
−
BER ≤ 3 × 10−2
(e.g. 15 bit errors per second for 500 bits/s)
BER ≤ 3 × 10−2
(e.g. 15 bit errors per second for 500 bits/s)
Maximum input power
(see Fig.6)
modulated test
signal 1; P1 ≥ −30 dBm
(minimum Pmax
Receiver turn-on time; note 1 test signal 1;
P1 = Pref + 10 dB
)
−
check that the first 10 bits are correct; error
counting is started 10 ms after PWD
switched to operating mode: ON
Intercept point (mixer + PMA) test signal 3;
test signal 2; IP3 = P1 + 1⁄2 × IM3 (dB); IP3 ≥ −38 dBm
see note 2 and Fig.7
P1 = −55 dBm
P2 = P1
Spurious radiation see note 3
and Fig.8
−
−
no spurious radiation (25 MHz − 1 GHz)
with level higher than −60 dBm
(maximum Pspur
)
1 dB compression point
(mixer + PMA) see note 2
and Fig.9
test signal 3;
−
(Po1 + 70 dB) − [Po2 + 45 dB (minimum
P1 dB)] ≤ 1 dB, where Po1, Po2 is the output
power for test signals with P11 or P12,
respectively
P11 = −70 dBm;
P12 = −45 dBm
(minimum P1dB
)
Notes
1. The power-down voltage VPWD alternates between operating mode ON (100 ms) and OFF (100 ms); see Fig.5.
2. Probe of spectrum analyzer connected to test point A.
3. Spectrum analyzer connected to the input of the test board.
1997 Aug 12
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Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
MHA834
V
PWD
(V)
3.5
0
0
100
200
300
400
500
t (ms)
Fig.5 Timing diagram for pulsed power-down voltage.
GENERATOR 1
BER TEST
FACILITY
(1)
50 Ω
TEST CIRCUIT
(2)
MED900
(1) For test circuit see Fig.11.
(2) For BER test facility see Fig.10.
Fig.6 Test configuration A (single generator).
GENERATOR 1
50 Ω
SPECTRUM
ANALYZER
WITH
50 Ω
2-SIGNAL
POWER
(1)
TEST CIRCUIT
PROBE
COMBINER
GENERATOR 2
50 Ω
IM3
∆f
∆f
∆f = 100 kHz
∆f
MED901
(1) For test circuit see Fig.11.
Fig.7 Test configuration B (IP3).
15
1997 Aug 12
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
SPECTRUM
ANALYZER
INPUT IMPEDANCE
50 Ω
(1)
TEST CIRCUIT
MED902
(1) For test circuit see Fig.11.
Fig.8 Test configuration C (spurious radiation).
GENERATOR 1
SPECTRUM
ANALYZER
WITH
(1)
50 Ω
TEST CIRCUIT
PROBE
MED903
(1) For test circuit see Fig.11.
Fig.9 Test configuration D (1 dB compression point).
TX data
SIGNAL
GENERATOR
MASTER
CLOCK
BIT PATTERN
GENERATOR
PRESET
DELAY
delayed
TX data
DEVICE
UNDER TEST
INTEGRATE
AND DUMP
DATA
COMPARATOR
to error counter
RX data
BER TEST BOARD
MED904
Fig.10 BER test facility.
1997 Aug 12
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Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
APPLICATION INFORMATION
HM8A14
a
1997 Aug 12
17
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
Table 4 Application component list for Fig.11
COMPONENT
VALUE
TOLERANCE
DESCRIPTION
R2
R3
560 Ω
220 Ω
820 kΩ
4.7 µF
150 pF
100 nF
100 pF
2.7 pF
3 to 10 pF
56 pF
±2%
±2%
TC = 50 ppm/K
TC = 50 ppm/K
TC = 50 ppm/K
−
R4
±2%
C1
±20%
±10%
±10%
±10%
±10%
−
C2
TC = 0 ±30 ppm/K; tan δ ≤ 10 × 10−4; f = 1 MHz
TC = 0 ±30 ppm/K; tan δ ≤ 10 × 10−4; f = 1 MHz
TC = 0 ±30 ppm/K; tan δ ≤ 10 × 10−4; f = 1 MHz
TC = 0 ±150 ppm/K; tan δ ≤ 30 × 10−4; f = 1 MHz
TC = 0 ±300 ppm/K; tan δ ≤ 20 × 10−4; f = 1 MHz
TC = 0 ±30 ppm/K; tan δ ≤ 10 × 10−4; f = 1 MHz
TC = 0 ±30 ppm/K; tan δ ≤ 10 × 10−4; f = 1 MHz
TC = 0 ±30 ppm/K; tan δ ≤ 10 × 10−4; f = 1 MHz
TC = 0 ±30 ppm/K; tan δ ≤ 20 × 10−4; f = 1 MHz
TC = 0 ±30 ppm/K; tan δ ≤ 10 × 10−4; f = 1 MHz
tan δ ≤ 25 × 10−3; f = 1 kHz
tan δ ≤ 25 × 10−3; f = 1 kHz
tan δ ≤ 25 × 10−3; f = 1 kHz
TC = 0 ±150 ppm/K; tan δ ≤ 30 × 10−4; f = 1 MHz
tan δ ≤ 25 × 10−3; f = 1 kHz
TC = 0 ±150 ppm/K; tan δ ≤ 30 × 10−4; f = 1 MHz
TC = 0 ±30 ppm/K; tan δ ≤ 10 × 10−4; f = 1 MHz
TC = 0 ±150 ppm/K; tan δ ≤ 30 × 10−4; f = 1 MHz
TC = 0 ±30 ppm/K; tan δ ≤ 10 × 10−4; f = 1 MHz
tan δ ≤ 25 × 10−3; f = 1 kHz
C3
C4
C5
C6
C7
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±5%
C8
33 pF
C9
100 pF
5.6 pF
100 pF
100 nF
2.2 nF
33 nF
C10
C11
C12
C13
C14
C16
C17
C18
C19
C20
C22
C23
C24
C25
L1
3.9 pF
10 nF
1.8 pF
39 pF
3.3 pF
18 pF
47 nF
±10%
±5%
22 pF
TC = 0 ±30 ppm/K; tan δ ≤ 10 × 10−4; f = 1 MHz
tan δ ≤ 25 × 10−3; f = 1 kHz
1 nF
±10%
±10%
±10%
±10%
±10%
±10%
10 nH
150 µH
220 µH
33 nH
470 µH
Q
Q
Q
min = 50 to 450 MHz; TC = 25 to 125 ppm/K
L2
min = 45 to 800 kHz; Cstray ≤ 1 pF
L3
min = 45 to 800 kHz; Cstray ≤ 1 pF
L4
Qmin = 45 to 450 MHz; TC = 25 to 125 ppm/K
min = 45 to 800 kHz; Cstray ≤ 1 pF
L5
Q
Table 5 Surface Acoustic Wave Resonator (SAWR) data
DESCRIPTION
SPECIFICATION
Type
one-port
Centre frequency
Maximum insertion loss
Typical loaded Q
Temperature drift
Turnover temperature
432.92 MHz ±75 kHz
1.5 dB
1600 (50 Ω load)
0.032 ppm/K2
43 °C
1997 Aug 12
18
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
LAYOUT OF PRINTED-CIRCUIT BOARD FOR AC APPLICATION
a. Copper side.
C5
L1
L3
C6
C19
C10
C9
C8
C25
DATA
C20
L2
POWER
DOWN
C13
C14
C24 C21
R2
L5
UAA3202M
COMP
C2
C18
C3
V
CC
L4
C1
SAWR
R3
MHA813
b. Component side.
Fig.12 Printed-circuit board layout.
1997 Aug 12
19
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
PACKAGE OUTLINE
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
D
E
A
X
c
H
v
M
A
y
E
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
7.4
7.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.9
0.5
mm
2.0
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
93-09-08
95-02-04
SOT339-1
MO-150AE
1997 Aug 12
20
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
If wave soldering cannot be avoided, the following
conditions must be observed:
SOLDERING
Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• The longitudinal axis of the package footprint must
be parallel to the solder flow and must incorporate
solder thieves at the downstream end.
Even with these conditions, only consider wave
soldering SSOP packages that have a body width of
4.4 mm, that is SSOP16 (SOT369-1) or
SSOP20 (SOT266-1).
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all SSOP
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
Wave soldering
Wave soldering is not recommended for SSOP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
1997 Aug 12
21
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1997 Aug 12
22
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
NOTES
1997 Aug 12
23
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Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1997
SCA55
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547027/1200/01/pp24
Date of release: 1997 Aug 12
Document order number: 9397 750 02306
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