UAA3500HL [NXP]
Pager receiver; 寻呼接收机
| 型号： | UAA3500HL |
| 厂家： | 
NXP |
| 描述： | Pager receiver |
| 文件： | 总16页 (文件大小：87K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
UAA3500HL
Pager receiver
Preliminary specification
2000 Jan 18
Supersedes data of 1999 Mar 30
File under Integrated Circuits, IC17
Philips Semiconductors
Preliminary specification
Pager receiver
UAA3500HL
FEATURES
The UAA3500HL contains a front-end receiver, which can
be configured through external components for any
frequency band between 130 and 930 MHz. The back-end
receiver consists of the channel filter and limiters. An
external VCO ensures the Local Oscillator (LO) for the
front-end. Designed in an advanced BiCMOS process, it
combines high performance with low-power consumption
and a high degree of integration, thus reducing external
component costs and total radio size.
• Double frequency conversion, zero-IF receiver with:
– Configurable in all paging bands (130 to 930 MHz)
– Low noise amplifier featured with four step Automatic
Gain Control (AGC)
– Down-conversion mixers
– On-chip, zero-IF channel filter
– I/Q, non-demodulated outputs
Its first advantage is to remove the expensive SAW filter
necessary in a superhet architecture, replacing it by an
integrated, elliptic channel filter that provides 70 dB
adjacent channel rejection. The receive front-end section
consists of a low-noise amplifier that drives mixers through
an external LC image rejection filter. The output drives the
I and Q second mixers, whose outputs are at zero
frequency. The receiver back-end section consists of
filters (channel filtering), limiters (limited output required)
and high-pass filters (DC block) to remove DC offsets.
Outputs are I and Q, undemodulated signals.
– Highpass filters to remove DC offsets.
• External Voltage Controlled Oscillator (VCO):
– Both Local Oscillators (LOs) derived from the VCO.
APPLICATIONS
• FLEXTM, ERMES and POCSAG pagers
• Remote control terminals.
GENERAL DESCRIPTION
Its second advantage is to provide the two LO signals from
one VCO only, tuned by a PLL. An on-chip frequency
divider-by-2 and buffers provide the LO sources.
The UAA3500HL is a one-chip pager receiver complying
with POCSAG, FLEXTM and ERMES standards. The IC
performs in accordance with specifications in the
−10 to +55 °C temperature range.
Its third advantage is to provide two voltage regulators,
allowing to obtain 1.0 and 1.8 V regulated voltages.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
UAA3500HL
LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm
SOT313-2
2000 Jan 18
2
Philips Semiconductors
Preliminary specification
Pager receiver
UAA3500HL
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS(1)
MIN.
TYP.
MAX. UNIT
VCC1
supply voltage 1
(B++;see note 2)
1.85 2.1
3.3
V
VCC2
supply voltage 2
(B+; see note 2)
1.05 1.4
1.5
V
ICC1(RX)
supply current from B++
supply current from B+
receiver noise figure
RF input sensitivity
RX section on; DC tested
f
RF = 160 MHz
RF = 280 MHz
−
−
2.4
2.4
−
−
3
mA
mA
mA
f
fRF = 930 MHz
2.35 2.7
ICC2(RX)
RX section on; DC tested
f
RF = 160 MHz
fRF = 280 MHz
RF = 930 MHz
from RF input to 2nd mixer input
−
−
1.3
1.4
−
−
mA
mA
f
1.85 2.3
2.45 mA
NFRX
f
RF = 160 MHz
RF = 280 MHz
−
−
−
2.7
3.1
4.4
−
−
−
dB
dB
dB
f
fRF = 930 MHz
3% BER
RF = 160 MHz; 1600 bits/s 2-level FSK
fRF = 280 MHz; 1600 bits/s 2-level FSK
Pi(ref)
f
−
−128.5
−128
−126.5
−123
70
−
dBm
dBm
dBm
dBm
dB
−
−
f
RF = 930 MHz; 6400 bits/s 2-level FSK
RF = 930 MHz; 6400 bits/s 4-level FSK
−
−
f
−
−
ACR
Tamb
adjacent channel rejection
ambient temperature
65
−
−10 +25
+55
°C
Notes
1. For 930 MHz band; for other conditions see Chapters “DC characteristics” and “AC characteristics”.
2. For B+ and B++, see Fig.3.
2000 Jan 18
3
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V
)
IMOUTA
IMINB IMOUTB
FILINA
FILOUTA
CC(DC
CAPI1A
CAPI1B
V
)
FILOUTB
CC(LO
V
)
M2GND
IMINA
DRV2
FASTON
RXON
CC(FE
CAPI2A
CAPI2B
FILINB
DRV1
M1GND
37 40
35 36 38 39 42 41 46 47 16 17 18 25 24
28 23 43 44
3
4
45
5
GYROUTI
VOLTAGE
REGULATOR
V
BIAS
CC(O)
BUFFER
2
1
CAPI3A
CAPI3B
OUTPUT
PMA
33
32
6
OUTI
RSET
LIMITER
LIMITER
×
26
LNAGND2
AGCADJ
LNA
31
30
RFINA
RFINB
GYRATOR
REGULATOR
34
27
×
RSSI
RSSI
AGC
AGCTAU
29
21
LNAGND1
LOIN
BUFFER
7
OUTQ
LIMITER
LIMITER
×
PMA
OUTPUT
11
BUFFER
CAPQ3A
CAPQ3B
0
12
8
2
UAA3500HL
BUFFER
90
OGND
15
GYROUTQ
BUFFER
22
14
13
20
19
10
9
48
BEGND
FCA022
LOGND
GYRCO1
CAPQ1A
CAPQ2A
CAPQ2B
GYRCO2
CAPQ1B
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Pager receiver
UAA3500HL
PINNING
SYMBOL
CAPI3B
PIN
DESCRIPTION
1
3rd DC filter (I path) external capacitor B (I path)
3rd DC filter (I path) external capacitor A (I path)
2nd DC filter (I path) external capacitor A (I path)
2nd DC filter (I path) external capacitor A (I path)
output stage supply voltage B++ (I path)
output I and Q signals (I path)
output I and Q signals (Q path)
output stage ground
CAPI3A
CAPI2A
CAPI2B
VCC(O)
2
3
4
5
OUTI
6
OUTQ
7
OGND
8
CAPQ2B
CAPQ2A
CAPQ3A
CAPQ3B
GYRCO2
GYRCO1
GYROUTQ
DRV1
9
2nd DC filter external capacitor B (Q path)
2nd DC filter external capacitor A (Q path)
3rd DC filter external capacitor A (Q path)
3rd DC filter external capacitor B (Q path)
external resistor to set-up gyrator filter cut-off frequency
external resistor to set-up gyrator filter cut-off frequency
Q-gyrator output
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
regulator driver (1.8 V)
VCC(FE)
VCC(DC)
CAPQ1B
CAPQ1A
LOIN
regulated voltage for front-end (1.8 V)
input voltage from DC-to-DC converter (2.1 V)
1st DC filter external capacitor (Q path)
1st DC filter external capacitor (Q path)
LO input
LOGND
FASTON
VCC(LO)
DRV2
LO strip ground
fast mode enable
regulated voltage for LO strip (1.0 V)
regulator driver (1.0)
AGCADJ
AGCTAU
RXON
AGC loop gain control
AGC loop time constant
receiver mode enable
LNAGND1
RFINB
receiver LNA (Low Noise Amplifier) ground 1
LNA input B
RFINA
LNA input A
LNAGND2
RSET
receiver LNA ground 2
LNA current setup
RSSI
received signal strength indicator
image rejection filter input A
IMINA
IMINB
image rejection filter input B
M1GND
IMOUTA
IMOUTB
M2GND
first mixer ground
image rejection filter output A
image rejection filter output B
second mixers ground
2000 Jan 18
5
Philips Semiconductors
Preliminary specification
Pager receiver
UAA3500HL
SYMBOL
FILINB
PIN
DESCRIPTION
41
42
43
44
45
46
47
48
band filter input B
band filter input A
FILINA
CAPI1A
CAPI1B
GYROUTI
FILOUTA
FILOUTB
BEGND
1st DC filter external capacitor (I path)
1st DC filter external capacitor (I path)
I-gyrator output
band filter output to second mixers
band filter output to second mixers
receiver back-end ground
CAPI3B
CAPI3A
CAPI2A
CAPI2B
1
2
3
4
5
6
7
8
9
36 IMINB
35 IMINA
34 RSSI
33 RSET
V
32 LNAGND2
31 RFINA
30 RFINB
29 LNAGND1
28 RXON
CC(O)
OUTI
UAA3500HL
OUTQ
OGND
CAPQ2B
CAPQ2A 10
CAPQ3A 11
CAPQ3B 12
27 AGCTAU
26 AGCADJ
25 DRV2
FCA023
Fig.2 Pin configuration.
6
2000 Jan 18
Philips Semiconductors
Preliminary specification
Pager receiver
UAA3500HL
FUNCTIONAL DESCRIPTION
Receiver front-end section
The first, second and third DC block frequencies are set at
4, 8 and 12 Hz respectively by external 330 nF capacitors.
The two voltage regulators are also activated by RXON.
The receiver front-end consists of an LNA, followed by the
first and the second mixers. For operation at low frequency
(160 and 280 MHz, for instance), the first mixer can be
bypassed, saving some current. The image rejection is
done by an external LC filter placed between the LNA, the
first mixer and the antenna selectivity. The IF band is
filtered by an external filter placed between the first mixer
and the second mixers for the I and Q paths. The
At the output of the gyrator filter, the signal is buffered and
logarithmically converted. It then controls the AGC loop.
To rapidly reach the DC operating point, a fast mode is
built into the three DC blocks.
LO
RF signals are in phase, and the LO signals are shifted
by 90°. The output signals are at zero frequency.
The external VCO is AC-coupled at input LOIN. It is then
buffered to drive the first mixer. LOIN also enters a
quadrature divider-by-2, whose output signals are also
buffered to drive the second mixers. The VCO frequency
should be 2⁄3 of the input RF signal.
To increase the immunity to interferers, an AGC loop
controls the LNA gain by attenuating the RF input signal.
Four steps of attenuation are possible (each having 8 dB),
ranging therefore from 0 to 32 dB. The AGC loop
threshold level and time constant may be controlled
externally at pins AGCADJ and AGCTAU. The second
LO I/Q phase shift is made by a quadrature divider, whose
input is the VCO oscillating signal.
The LO signal must be generated with an external
frequency synthesizer and VCO or with a crystal oscillator.
OPERATING MODES
To use the IC, all VCC pins must be connected to the
supply voltage B++ (2.1 V). The 1.8 V regulated voltage
sinks current from B++ and the 1.0 V regulated voltage
from B+ (1.4 V). In a typical application, the B+ supply is
the battery and the B++ supply is the DC/DC converter
located in the baseband chip.
The LNA current is setup by an external resistor. All the
receivers (front-end and back-end) are turned on by
pin RXON.
Receiver back-end section
The down-converted signal is amplified and then filtered
by a Sallen-Key filter, which shows a notch at 15 kHz and
about 6 dB rejection out-of-band. Then comes the first
high-pass filter (DC block), followed by the gyrator filter,
which performs an elliptic, 7-pole low-pass filtering. The
signal is then amplified by the first limiter, filtered by the
second DC block, amplified again, and filtered again by
the third DC block. Finally, an output stage delivers the
signal with rail-to-rail logic levels.
In normal operating mode, the receiver should be
powered-on in fast mode. The fast mode can be turned off
after several milliseconds.
Table 1 gives the definition of the polarity of the switching
signals on the receive section.
Table 1 Switching signals on the receiver
SIGNAL
RXON
SECTION
LEVEL
HIGH
LOW
ON/OFF
on
receive section powered-on
receive section powered-off
fast mode powered-on
off
FASTON
HIGH
LOW
on
fast mode powered-off
off
2000 Jan 18
7
Philips Semiconductors
Preliminary specification
Pager receiver
UAA3500HL
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCC
supply voltage
−
6
V
∆GND
difference in ground supply voltage applied between note 1
all grounds
−
0.3
V
Pl(max)
Tj(max)
P(max)
Tstg
maximum power input
−
−
20
dBm
°C
maximum operating junction temperature
150
500
+150
maximum power dissipation
storage temperature
in stagnant air at 25 °C −
−65
mW
°C
Note
1. Pins short circuited internally must be short circuited externally.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
VALUE
UNIT
K/W
thermal resistance from junction to ambient
in free air
90
HANDLING
All pins withstand the ESD test in accordance with “MIL-STD-883C class 2 (method 3015.5)”.
DC CHARACTERISTICS
VCC = 2.1 V; Tamb = 25 °C; 930 MHz band application, 3% BER and 1600 bits/s 2 level; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Pins: VCC(O), DRV1, VCC(FE), VCC(DC), VCC(LO) and DRV2
VCC1
supply voltage 1
(B++; see note 1)
over full temperature range
over full temperature range
RX section on; DC tested
1.85
2.1
3.3
V
VCC2
supply voltage 2
(B+; see note 1)
1.05
1.4
1.5
V
ICC1(RX)
supply current from B++
f
RF = 160 MHz
fRF = 280 MHz
RF = 930 MHz
RX section on; DC tested
RF = 160 MHz
fRF = 280 MHz
RF = 930 MHz
standby current from B++ Power-down mode; DC tested
standby current from B+ Power-down mode; DC tested
−
2.4
2.4
2.7
−
−
3
mA
mA
mA
−
f
2.35
ICC2(RX)
supply current from B+
f
−
1.3
−
mA
mA
mA
µA
−
1.4
−
f
1.85
0
2.3
2.45
1
ICC1(pd)
ICC2(pd)
0.01
0.01
0
0.5
µA
2000 Jan 18
8
Philips Semiconductors
Preliminary specification
Pager receiver
UAA3500HL
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Pins: RXON, FASTON, OUTI and OUTQ
VIH
VIL
IIH
HIGH-level voltage
V
CC − 0.3 VCC
VCC + 0.3
+0.4
+1
V
LOW-level voltage
−0.3
−1
−
−
−
V
HIGH-level static current
LOW-level static current
V
CC − 0.4 V
µA
µA
IIL
pin at 0.4 V
−1
+1
Pins: CAPI1A, CAPI1B, CAPQ1A and CAPQ1B
VCAP DC level RX section on
Pins: CAPI2A, CAPI2B, CAPQ2A, CAPQ2B
VCAP DC level RX section on
Pins: CAPI3A, CAPI3B, CAPQ3A, CAPQ3B
VCAP DC level
Pins: RFINA and RFINB
VRF DC level
Pins: IMOUTA and IMOUTB
VIMOUT DC level
Pins: VCC(LO)
1.20
1.40
1.30
−
1.40
1.57
1.57
0.92
0.17
1.00
1.80
0.24
1.60
1.80
1.90
−
V
V
V
V
V
V
V
V
RX section on
RX section on
RX section on
RX section on
RX section on
RX section on
−
−
VVcc(lo)
DC level
0.95
1.75
−
1.05
1.85
−
Pins: VCC(FE)
VVcc(fe)
DC level
Pins: FILOUTA and FILOUTB
VFILOUT
DC level
Pins: AGCTAU and RSSI
VRSSI
DC level
DC level
RX section on; FASTON is LOW −
0
0.30
V
V
RX section on;
V
CC − 0.3 VCC
−
FASTON is HIGH
VAGCTAU
RX section on;
FASTON is HIGH
1.50
1.37
1.60
1.42
1.70
1.47
V
Pins: GYROUTI and GYROUTQ
VGYROUT DC level
Output stage
RX section on
V
VOH
VOL
HIGH-level output voltage Io = −5 µA
LOW-level output voltage Io = 5 µA
−
−
V
CC − 0.2 −
V
V
0.2
−
Note
1. For B+ and B++, see Fig.3.
2000 Jan 18
9
Philips Semiconductors
Preliminary specification
Pager receiver
UAA3500HL
AC CHARACTERISTICS
VCC = 2.1 V; Tamb = 25 °C; 930 MHz band application, 3% BER and 1600 bits/s 2 level; on evaluation board according
to Fig.3; system measurement done using PCD5009, PCD5010 baseband; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
Receiver
Pi(ref)
RF input sensitivity
3% BER
f
RF = 160 MHz; 1600 bits/s 2-level FSK
RF = 280 MHz; 1600 bits/s 2-level FSK
−
−128.5
−128
−
−
−
−
dBm
dBm
dBm
dBm
f
−
−
−
fRF = 930 MHz; 6400 bits/s 2-level FSK
RF = 930 MHz; 6400 bits/s 4-level FSK
−126.5
−123
f
G(PCFE)
front-end conversion power
gain
from RF input to 2nd mixer input
fRF = 160 MHz
−
−
−
20
−
−
−
dB
dB
dB
f
RF = 280 MHz
RF = 930 MHz
12.8
12.7
f
NFRX
receiver noise figure
from RF input to 2nd mixer input
f
f
f
RF = 160 MHz
RF = 280 MHz
RF = 930 MHz
−
2.7
3.1
4.4
−38
−
−
−
−
−
−
−
−
−
−
dB
−
dB
−
dB
IP1
1 dB input compression point from RF input to 2nd mixer input
−
dBm
dBm
dBm
dB
IP2
2nd order intercept point
3rd order intercept point
3rd order intermodulation
co-channel rejection
from 2nd mixer input to gyrator output
from RF input to 2nd mixer input; note 1
3 signal measurement
45
−
IP3
−33
−
IM3
CCR
ACR
55
−
threshold +3 dB
5
dB
adjacent channel rejection
channel spacing = 25 kHz; from RF input 65
to gyrator output
70
dB
αbl
blocking immunity
frequency offset >1 MHz
75
7
80
8
−
dB
dB
GAGC
front-end gain reduction by
AGC step
9
AGCth
ton
AGC threshold
above sensitivity
20
−
25
−
30
30
2
dB
ms
dB
kΩ
kΩ
kΩ
kΩ
establishment time
IQ channel unbalance
LNA current set resistor
until sensitivity +3 dB is reached
∆IQ
−
−
RLNA
160 MHz
−
56
47
27
47
−
280 MHz
−
−
930 MHz
−
−
Rgyr
gyrator cut-off frequency set
resistor
cut-off frequency = 8.5 kHz
−
−
LO
fVCO
VCO frequency
−
2⁄3fRF
−
MHz
2000 Jan 18
10
Philips Semiconductors
Preliminary specification
Pager receiver
UAA3500HL
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
LNA
GLNA
RF amplifier power gain
from RF input to image filter output
f
RF = 160 MHz
RF = 280 MHz
−
20
−
−
−
dB
dB
dB
f
−
16.2
fRF = 930 MHz
12.5 14.2
NFLNA
RF amplifier noise figure
from RF input to image filter output
f
RF = 160 MHz
fRF = 280 MHz
RF = 930 MHz
1 dB input compression point from RF input to image filter output
−
1.8
−
dB
−
1.9
−
dB
f
−
2.2
2.5
−
dB
IP1LNA
IP3LNA
−
−27
−17.6
dBm
dBm
3rd order intercept point
from RF input to image filter output
−21
−
First mixer
GFM
1st mixer power gain
−0.5
−
0
−
dB
NFFM
IP1FM
IP3FM
1st mixer noise figure
10.2
−22
13
−
dB
1 dB input compression point
3rd order intercept point
−
dBm
dBm
−12.5 −11
−
Second mixer, PMA, Sallen-Key, 1st DC block and gyrator filter
GvBE
IP3BE
voltage gain
from 2nd mixer input to gyrator output
from 2nd mixer input to gyrator output
42
45
−
−
dB
3rd order intercept point
−
−59
dBm
1st DC block
fcut-off cut-off frequency
measured at gyrator output;
FASTON is LOW
−
4
−
−
Hz
Hz
fcut-off
cut-off frequency
measured at gyrator output;
FASTON is HIGH
150
400
Note
1. The two tones for intermodulation test would normally be set at 2 and 4 or 4 and 8 channels for type approval tests
i.e 930 and 930.1 or 930.1 and 930.2 MHz.
2000 Jan 18
11
Philips Semiconductors
Preliminary specification
Pager receiver
UAA3500HL
APPLICATION INFORMATION
BAND
FILTER
GYROUTI
330 nF
IMAGE
FILTER
48 47
45 44
41 40
37
46
43 42
39 38
IMINB
IMINA
RSSI
36
35
34
33
32
31
CAP13B
1
2
330 nF
CAP13A
CAP12A
RSSI
LNA
3
R
RSET
330 nF
B++
CAP12B
4
LNAGND2
RFINA
V
CC(O)
5
OUTI
6
OUTI
UAA3500HL
RFIN
OUTQ
7
OUTQ
RFINB
30
29
OGND
8
LNAGND1
RXON
CAPQ2B
9
28
27
26
25
RXON
10 nF
330 nF
330 nF
CAPQ2A
CAPQ3A
AGCTAU
10
11
12
AGCADJ
DRV2
B+
CAPQ3B
100
kΩ
15
kΩ
13
14 15 16 17 18 19
21 22 23
24
20
B++
47 kΩ
GYROUTQ
330 nF
FASTON
100 pF
10 µF
100 pF
10 nF
VCO
10 µF
100 kΩ
FCA024
B++
Electrical diagram of the UAA3500HL demonstration board for FLEXTM applications. All matching is to 50 Ω for measurement purposes.
B+ = 1.4 V; B++ = 2.1 V.
Fig.3 Demonstration board diagram.
2000 Jan 18
12
Philips Semiconductors
Preliminary specification
Pager receiver
UAA3500HL
PACKAGE OUTLINE
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
E
37
24
Z
E
e
H
E
A
2
A
(A )
3
A
1
w M
p
θ
pin 1 index
b
L
p
L
13
48
detail X
1
12
Z
v M
D
A
e
w M
b
p
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.27 0.18 7.1
0.17 0.12 6.9
7.1
6.9
9.15 9.15
8.85 8.85
0.75
0.45
0.95 0.95
0.55 0.55
1.60
mm
0.25
0.5
1.0
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
97-08-01
99-12-27
SOT313-2
MS-026
2000 Jan 18
13
Philips Semiconductors
Preliminary specification
Pager receiver
UAA3500HL
SOLDERING
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C. A
mildly-activated flux will eliminate the need for removal of
corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Manual soldering
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
2000 Jan 18
14
Philips Semiconductors
Preliminary specification
Pager receiver
UAA3500HL
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
REFLOW(1)
BGA, SQFP
not suitable
suitable
suitable
suitable
suitable
suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable(2)
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
2000 Jan 18
15
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69
SCA
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
465008/02/pp16
Date of release: 2000 Jan 18
Document order number: 9397 750 06478
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