NVH4L040N65S3F [ONSEMI]
SUPERFET III MOSFET;
| 型号： | NVH4L040N65S3F |
| 厂家： | 
ONSEMI |
| 描述： | SUPERFET III MOSFET |
| 文件： | 总10页 (文件大小：772K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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onsemi andꢀꢀꢀꢀꢀꢀꢀand other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or
subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi
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regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/
or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and holdonsemi and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative
Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.
MOSFET – Single N-Channel,
SUPERFET) III, FRFET)
650 V, 65 A, 40 mW
NVH4L040N65S3F
Features
• Ultra Low Gate Charge & Low Effective Output Capacitance
www.onsemi.com
• Lower FOM (R
x Q
& R
x E
)
DS(on) max.
g typ.
DS(on) max.
OSS
• AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
V
DSS
R
MAX
I MAX
D
DS(ON)
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
650 V
40 mW @ 10 V
65 A
Parameter
Drain−to−Source Voltage
Symbol
Value
650
30
Unit
V
V
DSS
V
GSS
V
GSS
D
Gate−to−Source Voltage
Gate−to−Source Voltage
− DC
V
− AC (f > 1 Hz)
30
V
Drain Current
− Continuous (T = 25°C)
I
D
I
D
65
A
C
G
Drain Current
− Continuous (T = 100°C)
45
A
C
S1: Driver Source
S2: Power Source
Drain Current
− Pulsed (Note 3)
I
162.5
446
3.57
A
DM
S1
S2
Power Dissipation
Power Dissipation
(T = 25°C)
C
P
P
W
D
POWER MOSFET
− Derate Above 25°C
W/°C
°C
D
MARKING
DIAGRAM
Operating Junction and Storage Temperature
Range
T , T
−55 to
+150
J
STG
Single Pulsed Avalanche Energy (Note 4)
Repetitive Avalanche Energy (Note 3)
MOSFET dv/dt
E
E
1009
4.46
100
50
mJ
mJ
AS
AR
$Y&Z&3&K
NVH4L040
N65S3F
dv/dt
dv/dt
V/ns
V/ns
°C
Peak Diode Recovery dv/dt (Note 5)
D
Max. Lead Temperature for Soldering Purposes
(1/8″ from case for 5 s)
T
300
S2
S1
L
G
TO−247−4LD
CASE 340CJ
THERMAL CHARACTERISTICS
Parameter
Symbol
Value
Unit
Thermal Resistance, Junction−to−Case,
Max. (Notes 1, 2)
R
0.28
°C/W
q
JC
$Y
= ON Semiconductor Logo
= Assembly Plant Code
= Data Code (Year & Week)
= Lot
&Z
&3
&K
Thermal Resistance, Junction−to−Ambient,
Max. (Notes 1, 2)
R
40
q
JA
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
NVH4L040N65S3F = Specific Device Code
1. The entire application environment impacts the thermal resistance values shown.
They are not constants and are only valid for the particular conditions noted.
2. Assembled to an infinite heatsink with perfect heat transfer from the case
(assumes 0 K/W thermal interface).
ORDERING INFORMATION
Device
Package
Shipping
3. Repetitive rating: pulse−width limited by maximum junction temperature.
4. I = 9 A, R = 25 W, starting T = 25°C.
AS
G
J
NVH4L040N65S3F TO−247−4LD 30 Units / Tube
(Pb−Free)
5. I ≤ 32.5 A, di/dt ≤ 200 A/ms, V ≤ 400 V, starting T = 25°C.
SD
DD
J
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
August, 2020 − Rev. 0
NVH4L040N65S3F/D
NVH4L040N65S3F
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
C
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Drain−to−Source Breakdown Voltage
BV
BV
V
= 0 V, I = 1 mA, T = 25°C
650
700
V
V
DSS
GS
D
J
V
GS
= 0 V, I = 10 mA, T = 150°C
D J
DSS
Breakdown Voltage Temperature
Coefficient
DBV
/
I
= 10 mA, Referenced to 25_C
640
103
mV/_C
DSS
J
D
DT
Zero Gate Voltage Drain Current
I
mA
V
GS
= 0 V, V = 650 V
10
DSS
DS
V
= 520 V, T = 125_C
DS
C
Gate−to−Body Leakage Current
ON CHARACTERISTICS
Gate Threshold Voltage
I
V
=
30 V, V = 0 V
100
nA
GSS
GS
DS
V
GS(th)
V
V
= V , I = 2.1 mA
3.0
5.0
40
V
mV/_C
mW
S
GS
DS
D
Threshold Temperature Coefficient
Static Drain−to−Source On Resistance
Forward Transconductance
DYNAMIC CHARACTERISTICS
Input Capacitance
DV
/DT
= V , I = 2.1 mA
−9
33.8
40
GS(th)
J
GS
DS
D
R
V
= 10 V, I = 32.5 A
D
DS(on)
GS
DS
g
FS
V
= 20 V, I = 32.5 A
D
pF
C
5665
148
15.8
1347
240
160
28.9
47
iss
Output Capacitance
C
oss
V
GS
= 0 V, V = 400 V, f = 1 MHz
DS
Reverse Transfer Capacitance
Effective Output Capacitance
Energy Related Output Capacitance
Total Gate Charge at 10 V
Threshold Gate Charge
C
rss
oss(eff.)
C
V
V
= 0 V to 400 V, V = 0 V
pF
pF
nC
DS
GS
C
Q
= 0 V to 400 V, V = 0 V
GS
oss(er.)
G(TOT)
DS
Q
G(TH)
V
= 10 V, V = 400 V, I = 32.5 A
DS D
GS
(Note 6)
Gate−to−Source Gate Charge
Gate−to−Drain “Miller” Charge
Equivalent Series Resistance
SWITCHING CHARACTERISTICS
Turn-On Delay Time
Q
GS
GD
Q
65
ESR
f = 1 MHz
1.9
W
t
t
39
27
105
7
ns
ns
ns
ns
d(on)
V
= 10 V, V = 400 V,
DD
Turn-On Rise Time
t
r
GS
D
I
= 32.5 A, R = 2.2 W
g
Turn-Off Delay Time
d(off)
(Note 6)
Turn-Off Fall Time
t
f
SOURCE−DRAIN DIODE CHARACTERISTICS
Maximum Continuous Source−to−
I
65
162.5
1.3
A
A
S
V
V
= 0 V
= 0 V
GS
Drain Diode Forward Current
Maximum Pulsed Source−to−Drain
Diode Forward Current
I
SM
GS
Source−to−Drain Diode Forward
Voltage
V
SD
V
V
GS
= 0 V, I = 32.5 A
SD
ns
Reverse Recovery Time
Charge Time
t
145.9
117.3
28.8
rr
t
a
b
V
GS
= 0 V, dI /dt = 100 A/ms,
F
I
= 32.5 A
SD
Discharge Time
t
Reverse Recovery Charge
Q
744.5
nC
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Essentially independent of operating temperature typical characteristics.
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2
NVH4L040N65S3F
TYPICAL CHARACTERISTICS
200
100
200
8.0 V
V
GS
= 10 V
250 ms Pulse Test
V
GS
= 10 V
8.0 V
7.0 V
6.5 V
T
C
= 150°C
7.0 V
6.5 V
100
6.0 V
6.0 V
5.5 V
10
5.5 V
10
1
1
250 ms Pulse Test
T
C
= 25°C
0.1
0.2
1
10
20
0.1
1
10
20
V
DS
, DRAIN−SOURCE VOLTAGE (V)
V
DS
, DRAIN−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. On−Region Characteristics
200
100
0.06
0.05
0.04
250 ms Pulse Test
= 20 V
T
C
= 25°C
V
DS
V
= 10 V
= 20 V
GS
T = 25°C
J
10
1
V
GS
0.03
0.02
T = 150°C
J
T = −55°C
J
3
4
5
6
7
8
9
0
30
60
90
120
150
180
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
Figure 3. Transfer Characteristics
Figure 4. On−Resistance Variation vs. Drain
Current and Gate Voltage
1000
100
10
1M
100K
10K
1K
250 ms Pulse Test
= 0 V
V
GS
C
C
iss
T = 150°C
J
1
oss
100
10
T = 25°C
J
0.1
C
rss
0.01
1
f = 1 MHz
= 0 V
V
GS
T = −55°C
J
0.001
0.1
0
0.5
1.0
1.5
2.0
0.1
1
10
100
1K
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. Body Diode Forward Voltage
Figure 6. Capacitance Characteristics
Variation vs. Source Current and Temperature
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3
NVH4L040N65S3F
TYPICAL CHARACTERISTICS
10
8
1.2
V
DD
= 130 V
I
D
= 32.5 A
V
= 0 V
= 10 mA
GS
I
D
V
DD
= 400 V
1.1
1.0
6
4
0.9
0.8
2
0
0
60
120
180
175
150
−75
−25
25
75
125
175
Q , TOTAL GATE CHARGE (nC)
T , JUNCTION TEMPERATURE (°C)
J
g
Figure 7. Gate Charge Characteristics
Figure 8. Breakdown Voltage Variation vs.
Temperature
300
100
3.0
2.5
2.0
1.5
1.0
30 ms
V
= 10 V
= 32.5 A
GS
I
D
100 ms
1 ms
10
10 ms
DC
Operation in this Area
is Limited by R
DS(ON)
1
T
= 25°C
T = 150°C
Single Pulse
C
0.5
0
J
0.1
−75
−25
25
75
125
1
10
100
1K
T , JUNCTION TEMPERATURE (°C)
V
DS
, DRAIN−SOURCE VOLTAGE (V)
J
Figure 9. On−Resistance Variation vs.
Figure 10. Maximum Safe Operating Area
Temperature
80
40
35
30
25
20
15
10
70
60
50
40
30
20
5
0
10
0
25
50
75
100
125
0
130
, DRAIN−TO−SOURCE VOLTAGE (V)
DS
260
390
520
650
T , CASE TEMPERATURE (°C)
V
C
Figure 11. Maximum Drain Current vs. Case
Temperature
Figure 12. EOSS vs. Drain−to−Source Voltage
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4
NVH4L040N65S3F
TYPICAL CHARACTERISTICS
200
180
160
140
120
100
80
1.2
1.0
V
= V
DS
= 2.1 mA
GS
I
D
T = 150°C
A
0.8
0.6
60
Pulse Duration = 250 ms
Duty Cycle = 0.5% Max
T = 25°C
A
40
20
0
I
D
= 32.5 A
4
5
6
7
8
9
10
−80
−40
0
40
80
120
160
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE (°C)
J
Figure 13. RDS(ON) vs. Gate Voltage
Figure 14. Normalized Gate Threshold Voltage
vs. Temperature
100
Starting T = 25°C
J
10
Starting T = 125°C
J
1
0.001
0.01
0.1
1
10
100
t , TIME IN AVALANCHE (ms)
AV
Figure 15. Unclamped Inductive Switching
Capability
10
1
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
0.1
P
DM
Z
R
(t) = r(t) x R
q
JC
q
JC
0.01
0.01
= 0.28°C/W
q
JC
t
1
Peak T = PDM x Z (t) + T
Duty Cycle, D = t / t
q
J
JC
C
Single Pulse
0.00001
t
2
1
2
0.001
0.0001
0.001
0.01
0.1
1
t, RECTANGULAR PULSE DURATION (s)
Figure 16. Transient Thermal Response Curve
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5
NVH4L040N65S3F
Figure 17. Gate Charge Test Circuit & Waveform
Figure 18. Resistive Switching Test Circuit & Waveforms
Figure 19. Unclamped Inductive Switching Test Circuit & Waveforms
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6
NVH4L040N65S3F
Figure 20. Peak Diode Recovery dv/dt Test Circuit & Waveforms
SUPERFET and FRFET are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States
and/or other countries.
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7
NVH4L040N65S3F
PACKAGE DIMENSIONS
TO−247−4LD
CASE 340CJ
ISSUE A
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8
NVH4L040N65S3F
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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