CXD2424R [SONY]
Timing Generator for Progressive Scan CCD Image Sensor; 时序发生器逐行扫描CCD图像传感器
| 型号： | CXD2424R |
| 厂家： | 
SONY CORPORATION |
| 描述： | Timing Generator for Progressive Scan CCD Image Sensor |
| 文件： | 总31页 (文件大小：806K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXD2424R
Timing Generator for Progressive Scan CCD Image Sensor
Description
64 pin LQFP (Plastic)
The CXD2424R is an IC developed to generate the
timing pulses required by the Progressive Scan
CCD image sensors as well as signal processing
circuits.
Features
• CCIR support
• Electronic shutter function
• Random trigger shutter function
• Sync signal generator
Absolute Maximum Ratings
• Supply voltage
• Input voltage
• Output voltage
VDD VSS – 0.5 to +7.0
V
• Supports external synchronization
• Supports non-interlaced operation
• Base oscillation 1888fh (29.5MHz)
VI VSS – 0.5 to VDD + 0.5 V
VO VSS – 0.5 to VDD + 0.5 V
• Operating temperature Topr
• Storage temperature Tstg
–20 to +75
°C
°C
–55 to +150
Applications
Progressive Scan CCD cameras
Recommended Operating Conditions
• Supply voltage
VDD
4.75 to 5.25
–20 to +75
V
Structure
• Operating temperature Topr
°C
Silicon gate CMOS IC
Applicable CCD Image Sensors
ICX075AL, ICX075AK
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E95306-PS
CXD2424R
Block Diagram
46 45 44 43
39 38 37 36
58 61 60 57
47
42 41
59
54
53 51 50 49
VRI
HRI
63
62
RG
11
13
OUTPUT CONTROL
XH1
TG
G
XH2 14
A
T
E
V-CONTROL
28
29
30
26
25
22
XSHP
XSHD
XRS
XV1
PULSE GENERATOR
V-DECODER
1/625
H-DECODER
1/472
XV2
TEST1
20
XV3
TEST2
TEST3
21
31
32
48
35
34
33
52
XSG 27
XHHG1A
15
16
1/2
COUNTER
DECODE
TEST4
TEST8
TEST7
TEST6
XHHG1B
XHHG2 17
XVOG
18
19
TEST CIRCUIT
XVHOLD
TEST5
NC
GATE
64
1
2
8 10
3
4
5
6
7
9
12 23 24 40 55 56
29.5MHz
– 2 –
CXD2424R
Pin Configuration
48
47
46 45 44 43
42 41
40
39 38 37
36
35
34 33
TEST4
TEST3
XRS
49
50
51
52
32
31
30
29
28
27
26
25
24
23
CL
CLD
O2FH
NC
XSHD
XSHP
XSG
XV1
FLD 53
BLK
VSS
54
55
XV2
VDD 56
CXD2424R (G/A)
VDD
57
SYNC
HDI
VSS
58
59
60
61
22 XV3
VDI
21 TEST2
20 TEST1
HDO
VDO
HRI
19
18
17
XVHOLD
XVOG
62
63
VRI
XHHG2
64
CKI
1
2
3
4
5
6
7
8
9
10 11 12
13
14 15 16
– 3 –
CXD2424R
Pin Description
Pin
Symbol
No.
I/O
Description
1
2
OSCO
OSCI
O
I
Inverter output for oscillation.
Inverter input for oscillation.
Switching for electronic shutter speed input method. (With pull-down resistor)
Low: Parallel input, High: Serial input
3
PS
I
4
ED0
I
I
Shutter speed setting. Strobe input for serial mode. (With pull-up resistor)
Shutter speed setting. Clock input for serial input. (With pull-up resistor)
Shutter speed setting. Data input for serial input. (With pull-up resistor)
Shutter mode setting. (With pull-up resistor)
GND
5
ED1
6
ED2
I
7
SMD1
Vss
I
8
—
I
9
SMD2
TRIG
RG
Shutter mode setting. (With pull-up resistor)
Trigger input for random trigger shutter.
Reset gate pulse output.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
I
O
O
O
O
O
O
O
O
O
O
O
O
—
—
O
O
O
O
O
O
O
O
O
O
I
XSUB
XH1
CCD discharge pulse output.
Clock output for CCD horizontal register drive.
Clock output for CCD horizontal register drive.
Clock output for transfer between CCD horizontal registers.
Clock output for transfer between CCD horizontal registers.
Clock output for transfer between CCD horizontal registers.
Clock output for transfer from CCD vertical register to CCD horizontal register.
Clock output for adjusting timing of transfer to CCD horizontal register.
Test output. Normally open.
XH2
XHHG1A
XHHG1B
XHHG2
XVOG
XVHOLD
TEST1
TEST2
XV3
Test output. Normally open.
Clock output for CCD vertical register drive.
GND
Vss
VDD
Power supply.
XV2
Clock output for CCD vertical register drive.
Clock output for CCD vertical register drive.
CCD sensor charge readout pulse output.
Precharge level sample-and-hold pulse.
Data sample-and-hold pulse.
XV1
XSG
XSHP
XSHD
XRS
Sample-and-hold pulse.
TEST3
TEST4
TEST5
TEST6
TEST7
Test output. Normally open.
Test output. Normally open.
Test output. Normally open.
Test output. Normally open.
Test input. Set at Low in normal operation. (With pull-down resistor)
– 4 –
CXD2424R
Pin
No.
Symbol
EXT
I/O
Description
Internal synchronization/external synchronization switching. (With pull-down resistor)
Low: Internal synchronization, High: External synchronization
36
37
38
I
I
I
Normal reset/direct reset switching. (With pull-down resistor)
Low: Normal reset, High: Direct reset
REND
REVH
V reset/HV reset switching. (With pull-down resistor)
Low: V reset, High: HV reset
O2FH output control. (With pull-down resistor)
Low: No output, High: Output
39
40
41
OCTL
Vss
I
—
I
GND
Normal operation/random trigger shutter switching. (With pull-down resistor)
Low: Normal operation, High: Random trigger shutter
RDM
Switching for output mode. (With pull-down resistor)
Low: Non-interlaced, High: Interlaced
42
RM
I
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
XCPDM
XCPOB
PBLK
ID
O
O
O
O
O
I
Clamp pulse output.
Clamp pulse output.
Blanking cleaning pulse output.
Line identification output.
Write enable output.
WEN
TEST8
CL
Test input. (With pull-down resistor)
fck clock output. (0°)
O
O
O
—
O
O
—
—
O
I
CLD
O2FH
NC
fck clock output. (180°)
2 fH output.
FLD
Field pulse output.
BLK
Composite blanking output.
GND
Vss
VDD
Power supply.
SYNC
HDI
Composite sync output.
Horizontal sync signal input.
Vertical sync signal input.
Horizontal sync signal output.
Vertical sync signal output.
Horizontal reset signal input.
Vertical reset signal input.
2 fck clock input.
VDI
I
HDO
VDO
HRI
O
O
I
VRI
I
CKI
I
– 5 –
CXD2424R
Electrical Characteristics
DC Characteristics
(VDD = 4.75 to 5.25V, Topr = –20 to +75°C)
Item
Symbol
VDD
Conditions
Min.
4.75
Typ.
5.0
Max.
5.25
Unit
V
Supply voltage
VIH1
0.7VDD
V
Input voltage 1
(Input pins other than those below)
VIL1
0.3VDD
0.3VDD
0.4
V
VIH2
0.7VDD
–0.8
V
Input voltage 2
(Pins 7, 9, 10, 58, 59, 62, 63, and 64)
VIL2
V
VOH1
VOL1
VOH2
VOL2
VOH3
VOL3
VOH4
VOL4
RFB
IOH = –2mA
V
Output voltage 1
(Output pins other than those below)
IOL = 4mA
V
IOH = –4mA
IOL = 8mA
–0.8
V
Output voltage 2 (Pins 28, 29, 30,
31, 32, 33, 34, 49 and 50)
0.4
V
IOH = –12mA
IOL = 12mA
IOH = –12mA
IOL = 12mA
VIN = Vss or VDD
VIL = 0V
VDD – 0.8
VDD/2
250k
V
Output voltage 3
(Pins 11, 13, and 14)
0.4
V
V
Output voltage 4
(Pin 1)
VDD/2
2.5M
V
1M
50k
50k
Ω
Ω
Ω
Feedback resistor
Pull-up resistor
RPU
RPD
VIN = VDD
Pull-down resistor
VDD = 5V
IDD
ICX075AL in normal
operating state
40
mA
Current consumption
I/O Pin Capacitances
Item
(VDD = V = 0V, fM = 1MHz)
Symbol
CIN
Min.
—
Typ.
—
Max.
9
Unit
pF
Input pin capacitance
Output pin capacitance
COUT
—
—
11
pF
– 6 –
CXD2424R
AC Characteristics
1) Phase characteristics of XH1, RG, XSHP, XSHD, XRS, CL, and CLD
tCK
CK
Vpp/2
tpd2
tpd1
0.7VDD
tpd3
XH1
RG
0.3VDD
0.7VDD
tpd4
0.3VDD
0.3VDD
tpd6
tpd5
XSHP
0.7VDD
tpd8
tpd7
XSHD
XRS
0.7VDD
0.3VDD
tpd9
tpd10
0.7VDD
0.3VDD
tpd12
tpd11
0.7VDD
CL
0.3VDD
tpd14
tpd13
0.7VDD
CLD
0.3VDD
(VDD = 5.0V, Topr = 25°C, Load capacity of CL and CLD = 30pF, Load capacity of XH1, XSHP, XSHD, XRS, and RG = 10pF)
Symbol
Definition
Typ.
35
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
CK cycle
tpd1
tpd2
tpd3
tpd4
tpd5
tpd6
tpd7
tpd8
tpd9
tpd10
tpd11
tpd12
tpd13
tpd14
XH1 rising delay, activated by the falling edge of CK
XH1 falling delay, activated by the falling edge of CK
RG falling delay, activated by the rising edge of CK
RG rising delay, activated by the falling edge of CK
XSHP falling delay, activated by the rising edge of CK
XSHP rising delay, activated by the falling edge of CK
XSHD falling delay, activated by the rising edge of CK
XSHD rising delay, activated by the falling edge of CK
XRS falling delay, activated by the falling edge of CK
XRS rising delay, activated by the rising edge of CK
CL falling delay, activated by the rising edge of CK
CL rising delay, activated by the rising edge of CK
CLD falling delay, activated by the rising edge of CK
CLD rising delay, activated by the falling edge of CK
9
11
15
18
18
20
11
17
15
32
0
26
20
– 7 –
CXD2424R
Waveform Characteristics of XH1 and RG
0.9VDD
XH1
0.1VDD
tfH1
trH1
0.9VDD
RG
0.1VDD
trRG
tfRG
(VDD = 5.0V, Topr = 25°C, Load capacity of XH1 = 10pF, Load capacity of RG = 10pF)
Symbol
trH1
Definition
Typ.
Unit
ns
XH1 rise time
2
3
2
2
tfH1
XH1 fall time
RG rise time
RG fall time
ns
trRG
tfRG
ns
ns
– 8 –
CXD2424R
• In the normal reset mode, the signal output is reset to ODD or EVEN field depending on the input timing of
the vertical reset signal as shown in the figure below.
Field identification
VRI
1
2
HDO
tp2
tp1
tp3
fH
fH L: ODD H: EVEN
tp5
tp4
1
2
VDO
VDO
ODD
309.5H
EVEN
309.5H
Symbol
Definition
Specified value Unit
tp1
tp2
tp3
tp4
tp5
Range of resetting to ODD
Range of resetting to EVEN
Range of resetting to ODD
Prohibited area
22.0
31.8
9.8
µs
µs
µs
ns
ns
200
200
Prohibited area
– 9 –
CXD2424R
• In the direct reset mode, the signal output is reset to ODD or EVEN field depending on the input timing of the
vertical reset signal as shown in the figure below.
Field identification
VRI
1
2
HDO
tp2
tp1
tp3
fH
fH L: ODD H: EVEN
tp5
tp4
1
2
VDO
VDO
EVEN
ODD
Symbol
Definition
Specified value Unit
tp1
tp2
tp3
tp4
tp5
Range of resetting to ODD
22.0
31.8
—
µs
µs
µs
ns
ns
Range of resetting to EVEN
Range of resetting to ODD
Prohibited area
1
200
200
Prohibited area
1
In the direct reset mode, the cycle of HD can be arbitrary. Therefore, tp3 is not specified.
– 10 –
CXD2424R
Description of Operation
1. Mode Control
Symbol
RM
Pin No.
42
L
H
Remarks
1/25s non-interlaced
Normal operation
Parallel
1/50s interlaced
Random trigger shutter
Serial
RDM
PS
41
3
Electronic shutter speed input method
EXT
36
Internal synchronization External synchronization
REND
REVH
37
Normal reset
V reset
Direct reset
HV reset
38
2. Mode Relationships
L
H
RM
1/25s non-interlaced
1/50s interlaced
H
L
H
L
EXT
Internal synchronization External synchronization Internal synchronization External synchronization
L
H
L
H
Random
trigger
shutter
Random
trigger
shutter
RDM
Normal
operation
Normal
operation
Normal operation
Direct reset
Normal operation
L
H
REND
REVH
Normal
reset
Direct reset
H
L
L
H
V
HV
V
HV
reset
reset
reset reset
: Disabled
– 11 –
CXD2424R
3. Electronic Shutter
<Shutter Modes>
SMD1 SMD2
L
L
L
H
L
Flickerless: Eliminates fluorescent frequency-induced flicker.
High-speed shutter: Shutter speed faster than 1/50
Low-speed shutter: Shutter speed slower than 1/50
No shutter operation
H
H
H
<Shutter Mode and Speed Setting Method>
PS = Low : Parallel input; set by ED0 to ED2, SMD1, and SMD2.
PS = High : Serial input; set by inputting ED0 (strobe), ED1 (clock), and ED2 (data) to each pin.
3-1. Parallel input
Shutter Speed Compatibility Chart
Mode
PS
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
SMD1
H
L
SMD2
H
L
ED0
X
X
H
L
ED1
X
X
H
H
L
ED2
X
X
H
H
H
H
L
Shutter speed
OFF
Shutter off
1/120 (s)
1/50 (s)
1/125 (s)
1/250 (s)
1/500 (s)
1/1000 (s)
1/2000 (s)
1/4000 (s)
1/10000 (s)
2FLD
Flickerless
L
H
H
H
H
H
H
H
H
L
L
L
H
L
L
L
High-speed
shutter
L
H
L
H
H
L
L
L
L
H
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
H
H
L
H
H
H
H
L
L
4FLD
L
H
L
6FLD
L
L
8FLD
Low-speed
shutter
L
H
L
H
H
L
10FLD
L
L
12FLD
L
H
L
L
14FLD
L
L
L
16FLD
– 12 –
CXD2424R
3-2. Serial input
• For serial input (PS = High), SMD1 and SMD2 bits within ED2 (DATA) take priority over SMD1 (Pin 7) and
SMD2 (Pin 9) pins as SMD1 and SMD2 (shutter mode control). In this case, control by SMD1 and SMD2 pins
is invalid.
ED1 (CLK)
Dummy
ED2 (DATA)
ED0 (STB)
D0
D1
D2
D3
D4
D5
D6
D7
D8 SMD1 SMD2
ED2 data is latched to the register at the rise of ED1, and transferred to the within at the rise of ED0.
AC Characteristics
ED2
ED1
ED0
ts2
th2
ts0
tw1
ts1
tw0
Definition
Symbol
ts2
Min.
20ns
20ns
20ns
20ns
20ns
20ns
Max.
—
ED2 set-up time, activated by the falling edge of ED1
ED2 hold time, activated by the rising edge of ED1
ED1 rising set-up time, activated by the rising edge of ED0
ED0 pulse width
th2
—
ts1
—
tw0
ts0
50µs
—
ED0 rising set-up time, activated by the rising edge of ED1
ED1 pulse width (serial input)
tw1
—
– 13 –
CXD2424R
3-3. Shutter speed calculation formula
High-speed shutter
T = [31210 – (1FF16 – L16)] × 64 + 35.6 (µs)
( L16 = Load value)
Load value Shutter speed
Calculated value
1/10040
1/4394
1/2068
1/1004
1/495
0C816
0CA16
0CE16
0D616
0E616
10516
14316
14916
1/10000
1/4000
1/2000
1/1000
1/500
1/250
1/250
1/125
1/125
1/120
1/120
Low-speed shutter
N = 2 × (1FF16 – L16) FLD
However, “FF” cannot be used as the load value.
Load value Shutter speed (FLD)
1FE16
1FD16
:
2
4
:
10116
10016
508
510
Note) In case of starting with serial input setting (PS = H), be sure to transfer shutter speed data in the range
of specification after power is turned on, and then use it.
– 14 –
CXD2424R
4. Random Trigger Shutter
The random trigger shutter is different from the conventional electronic shutter in that the exposure beginning
can be freely set. The exposure period (shutter speed) can be set as with the conventional electronic shutter.
In this mode, XSUB rises for each 1H, and the charge stored in the sensor is discharged. Because the V clock
(XV1 to XV3) is continuously operating, any unneeded charge in the vertical CCD is eliminated.
XSG pulse is stopped until the external trigger is detected. The image cannot be monitored until the external
trigger is detected and the signal is read out.
When an external trigger is input in this state, HD is forcibly reset when the trigger falls, and XSUB falls once to
clear the charge and then halts. XV1 to XV3, XCPDM, XCPOB, and PBLK are reset with HD. From this point,
exposure begins, and after the preset exposure period has passed, the XSG pulse falls, the charge is
transferred from the sensor to the vertical CCD, and exposure ends. The XSG pulse falls with the time set as
in conventional electronic shutters, regardless of VD. Because HD is reset, the exposure period is accurate in
1H units. The WEN pulse is generated synchronously with the XSG pulse. As the WEN pulse specifies the
signal start, it can be used as the sync signal for writing image data into the frame memory.
In the random trigger shutter mode, V-direction functions of a sync signal generator are halted. As a result,
sync signals VD and FLD are also halted.
TRIG
HD reset
HD
XSUB reset
XSG
XSUB
Shutter speed
XV1
XV2
XV3
WEN
– 15 –
CXD2424R
5. External Synchronization - Reset
HD and VD are reset to synchronize with the external sync signal.
Resetting is done to synchronize a plural number of camera systems whose clock frequencies are the same.
There are two reset inputs: HRI and VRI. When their falling edge is detected, resetting is carried out. The
CXD2424R has two reset modes: normal reset and direct reset. Details of the reset modes are described in
the following pages.
In the 1/25s non-interlaced readout mode, the normal reset mode is not supported, and although the direct
reset mode is supported, the field is not identified.
– 16 –
CXD2424R
5-1. Normal reset
In the normal reset mode, the reset signal is input for resetting, and the sync signal is output continuously from
that time. Only the mode which resets both HD and VD (HV reset) is supported, and the mode which does not
accept the HD reset (V reset) is not supported.
When the H reset signal HRI is continuously with an H cycle, resetting is triggered at the first falling edge, and
after that point no resets are triggered at edges unless HD after resetting exceeds 2bits (136ns) on the internal
clock. In other words, the HRI input jitter is absorbed when it is up to 136 ns. The HRI minimum reset pulse
width is 0.3µs.
In the V direction, counting begins from VRI fall, and V is reset to cause VDO to fall after 312.5 – 3 = 309.5H.
The VRI minimum reset pulse width is 2H.
Resetting is done for ODD or EVEN field, depending on the input timing of the V reset signal. The identification
timing is shown in Electrical Characteristics.
FIELD.E
FIELD.O
HRI
HDO
VRI
7.5H
VDO
309.5H
FIELD.O
FIELD.E
HRI
HDO
VRI
7.5H
VDO
309.5H
H reset
57.6 to 57.7µs (850 to 851bit)
HRI
HD OUT
Reset
6.3 to 6.37µs
– 17 –
CXD2424R
5-2. Direct reset
In the direct reset mode, when the reset signal is input for resetting, a sync signal is output, but there is no
continuous output.
There are two direct reset modes: one to direct reset VD only, and one to reset both HD and VD. (However,
note that even for V reset, the HD signal is acceptable and the reset timing is the same as in normal reset
mode.) In both modes, the VD reset timing is the same.
When the external input V reset signal VRI fall is detected, a judgment is made as to ODD or EVEN. If ODD, V
is reset to cause VDO to fall simultaneously in the middle of HD, and if EVEN, V is reset to cause VDO to fall
simultaneously with HD fall. VRI requires a minimum pulse width of 2H.
H direct reset detects the fall of H reset signal HRI, and resets H so that HDO falls at the next CL falling edge.
The minimum HRI reset pulse width is 0.3µs.
Resetting is done for ODD or EVEN field, depending on the input timing of the V reset signal. The identification
timing is shown in Electrical Characteristics.
5-2-1. V reset
FIELD.E
FIELD.O
HRI
HDO
VRI
7.5H
VDO
FIELD.O
FIELD.E
HRI
HDO
VRI
7.5H
VDO
– 18 –
CXD2424R
5-2-2. HV reset (1/50s interlaced readout mode)
FIELD.E
FIELD.O
HDO
HRI
7.5H
VDO
VRI
XSG
ID
FIELD.O
FIELD.E
HDO
HRI
7.5H
VDO
VRI
XSG
ID
CL
HRI
HDO
– 19 –
CXD2424R
5-2-3. HV reset (1/25s non-interlaced readout mode)
HDO
HRI
7.5H
VDO
VRI
XSG
ID
HDO
HRI
7.5H
VDO
VRI
XSG
ID
CL
HRI
HDO
– 20 –
CXD2424R
Timing Chart (1) <Vertical direction> 1/50s interlaced readout (RM = High)
FLD
VDO
BLK
HDO
XV1
XV2
XV3
OUT1
OUT2
XSG
XVHOLD
XVOG
XHHG1A
XHHG1B
XHHG2
PBLK
XCPOB
XCPDM
ID
WEN
– 21 –
CXD2424R
Timing Chart (2) <Vertical direction> 1/25s non-interlaced readout (RM = Low)
FLD
VDO
BLK
HDO
XV1
XV2
XV3
OUT1
XSG
XVHOLD
XVOG
XHHG1A
XHHG1B
XHHG2
PBLK
XCPOB
XCPDM
ID
WEN
– 22 –
CXD2424R
– 23 –
CXD2424R
– 24 –
CXD2424R
Timing Chart (5) <V2/V3 simultaneous readout timing> 1/50s interlaced (RM = High)
HD
2.58µs (38 bits)
43.25µs (638 bits)
2.58µs (38 bits)
3.25µs (48 bits)
15.59µs (230 bits)
ODD Field
XV1
XV2
XV3
XSG
EVEN Field
XV1
XV2
XV3
XSG
Timing Chart (6) <V2/V3 simultaneous readout timing> 1/25s non-interlaced (RM = Low)
HD
2.58µs (38 bits)
43.25µs (638 bits)
2.58µs (38 bits)
3.25µs (48 bits)
15.59µs (230 bits)
ODD Field
XV1
XV2
XV3
XSG
– 25 –
CXD2424R
Timing Chart (7) <High-speed phase>
HD
CKI
CL
XH1
XH2
RG
XSHP
XSHD
XRS
CLD
– 26 –
CXD2424R
Timing Chart (8) <SG vertical direction>
O: ODD
E: EVEN
Field E
Field O
HDO
7.5H
VDO
SYNC
BLK
25H
FLD
Field O
Field E
HDO
7.5H
VDO
SYNC
BLK
25H
FLD
– 27 –
CXD2424R
Timing Chart (9) <SG horizontal direction>
HDO
BLK
6.92µs (102 bits)
12.0µs (177 bits)
HSYNC
1.48µs
(22 bits)
4.93µs (73 bits)
2.47µs (36 bits)
EQ
VSYNC
VDO
27.07µs (399 bits)
4.93µs (73 bits)
FLD
ODD
EVEN
9.87µs
(145 bits)
11.91µs
(176 bits)
10.22µs
(151 bits)
O2FH
64.0µs (944 bits)
1/2H 32.0µs
(472 bits)
9.87µs
(146 bits)
22.13µs (326 bits)
FH
– 28 –
CXD2424R
Setting Up during Power ON
During power on, after setting random trigger shutter mode once, switch to normal operation mode, and then
use it. To be concrete, control supply voltage of two pins as shown below. The period to set random trigger
shutter mode must be 1 clock (68ns) or more.
Pin No.
Symbol
Supply voltage of pin
during power on
7
SMD1 (with pull-up resistor)
RDM (with pull-down resistor)
Low
→ High
→ Low
High
41
(random trigger shutter)
(normal operation)
<Timing Example>
+5V power supply
(TG power supply)
SMD1 pin voltage
RDM pin voltage
Low
High
0.3VDD
0.7VDD
High
Low
68ns or more
– 29 –
CXD2424R
A N A L O G O U T 2
A N A L O G O U T 1
N . .
N . .
4 7 p
4 7 p
4 7 p
4 7 p
4 7 p
2 . 2 K
2 . 2 K
2 . 2
2 . 2
2 . 2 K
N . C .
1 0 0 0 p
– 30 –
CXD2424R
Package Outline
Unit: mm
64PIN LQFP (PLASTIC)
12.0 ± 0.2
10.0 ± 0.1
48
33
49
32
A
17
(0.22)
64
16
1
+ 0.08
0.18 – 0.03
+ 0.05
0.127 – 0.02
0.5 ± 0.08
+ 0.2
1.5 – 0.1
0.1
0.1 ± 0.1
0° to 10°
NOTE: Dimension “ ” does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
EPOXY RESIN
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
SOLDER/PALLADIUM
LQFP-64P-L01
SONY CODE
EIAJ CODE
PLATING
LQFP064-P-1010
42/COPPER ALLOY
0.3g
JEDEC CODE
PACKAGE MASS
– 31 –
相关型号：
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