ESDALC6V1M6_08 [STMICROELECTRONICS]
4- and 5-line low capacitance Transil arrays for ESD protection; 4-和5-线低电容的Transil阵列的ESD保护
| 型号： | ESDALC6V1M6_08 |
| 厂家： | 
ST |
| 描述： | 4- and 5-line low capacitance Transil arrays for ESD protection |
| 文件： | 总11页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESDALC6V1M6, ESDALC6V1-5M6
4- and 5-line low capacitance Transil™ arrays for ESD protection
Features
■ High ESD protection level
■ High integration
■ Suitable for high density boards
■ 4 unidirectional Transil diodes
Micro QFN package
(ESDALC6V1M6)
■ 5 unidirectional Transil diodes
Figure 1.
Functional diagram
(ESDALC6V1-5M6)
■ Breakdown Voltage VBR = 6.1 V min
■ Low diode capacitance (12 pF typ at 0 V)
■ Low leakage current < 70 nA
ESDALC6V1M6
1
2
3
I/O1
GND
I/O2
I/O5
GND
I/O3
6
²
■ Very small PCB area: 1.45 mm
5
■ 500 microns pitch
■ Lead-free package
4
Complies with the following standards
ESDALC6V1-5M6
■ IEC 61000-4-2
1
2
3
I/O1
GND
I/O2
I/O5
I/O4
I/O3
– 15 kV (air discharge)
– 8 kV (contact discharge)
6
5
■ MIL STD 883G- Method 3015-7: class3B
4
– >8 kV (human body model)
Applications
Description
Where transient overvoltage protection in ESD
sensitive equipment is required, such as:
The ESDALC6V1xxM6 are monolithic arrays
designed to protect up to 4 or 5 lines against ESD
transients.
■ Computers
■ Printers
The device is ideal for applications where both
reduced print circuit board space and power
absorption capability are required.
■ Communication systems
■ Cellular phone handsets and accessories
■ Video equipment
TM: Transil is a trademark of STMicroelectronics
February 2008
Rev 5
1/11
www.st.com
11
Characteristics
ESDALC6V1M6, ESDALC6V1-5M6
1
Characteristics
Table 1.
Symbol
Absolute maximum ratings (Tamb = 25° C)
Parameter
ESD IEC 61000-4-2, air discharge
Value
Unit
15
8
VPP
ESD IEC 61000-4-2, contact discharge
kV
MIL STD 883G- Method 3015-7: class3B, (human body model)
25
Peak pulse power dissipation (8/20 µs)(1)
Tj initial = Tamb
PPP
Ipp
30
3
W
A
Repetitive peak pulse current typical value (8/20 µs)
Junction temperature
Tj
125
° C
Tstg
TL
Storage temperature range
-55 + 150 ° C
260 ° C
-40 + 125 ° C
Maximum lead temperature for soldering during 10 s
Operating temperature range
TOP
1. For a surge greater than the maximum values, the diode will fail in short-circuit.
Table 2.
Symbol
Electrical characteristics (Tamb = 25° C)
Parameter
I
VRM
VBR
VCL
IRM
IPP
Stand-off voltage
I
F
Breakdown voltage
Clamping voltage
V
V
V
V
CL BR
RM
F
V
Leakage current @ VRM
I
I
RM
I
R
Peak pulse current
αT
Voltage temperature coefficient
Forward voltage drop
Slope= 1/R
d
PP
VF
Symbol
VBR
IRM
Test Condition
IR = 1 mA
Min
Typ
Max
Unit
V
6.1
7.2
70
1
VRM = 3 V
nA
V
VF
IF = 10 mA
Rd
2
3
Ω
αT(1)
10-4/° C
pF
IR = 1 mA,
5
C
VR =0 V DC, F = 1 MHz, Vosc = 30 mVRMS
12
15
1. ΔV = αT * (T
- 25° C) * V (25° C)
BR
BR
amb
2/11
ESDALC6V1M6, ESDALC6V1-5M6
Characteristics
Figure 2.
Relative variation of peak pulse
power versus initial junction
temperature
Figure 3.
Peak pulse power versus
exponential pulse duration
PPP(W)
1000
PPP[T initial] /PPP[T initial=25 °C]
j
j
Tj initial = 25°C
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
100
T j(°C)
tP(µs)
0
25
50
75
100
125
150
10
1
10
100
Figure 4.
Clamping voltage versus peak
pulse current (typical values,
8/20 µs waveform)
Figure 5.
Forward voltage drop versus peak
forward current (typical values)
IPP(A)
100.0
IFM(A)
8/20µs
1.E+00
Tj initial =25°C
10.0
1.0
1.E-01
1.E-02
Tj =125°C
Tj =25°C
VFM (V)
1.E-03
0.0
VCL(V)
40
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.1
0
10
20
30
50
60
70
Figure 6.
Junction capacitance versus
reverse voltage applied (typical
values)
Figure 7.
Relative variation of leakage
current versus junction
temperature (typical values)
C(pF)
14
13
12
11
10
9
IR [T] / IR[T=25°C]
j
j
F=1MHz
OSC=30mVRMS
Tj=25°C
100
10
1
V
VR =3V
8
7
6
5
4
3
2
Tj(°C)
VR(V)
1
25
50
75
100
125
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
3/11
Ordering information scheme
ESDALC6V1M6, ESDALC6V1-5M6
Figure 8.
S21 attenuation measurement
results of each channel
Figure 9.
Analog crosstalk measurements
between channels
dB
dB
0.00
-10.00
-20.00
-30.00
-40.00
0.00
-30.00
-60.00
-90.00
-120.00
f/Hz
f/Hz
100.0k
1.0M
10.0M
100.0M
1.0G
100.0k
1.0M
10.0M
100.0M
1.0G
Figure 10. ESD response to IEC 6100-4-2
(+15 kV air discharge) on each
channel
Figure 11. ESD response to IEC 6100-4-2
(-15 kV air discharge) on each
channel
2
Ordering information scheme
Figure 12. Ordering information scheme
ESDA LC 6V1 xx M6
ESD array
Low capacitance
Breakdown voltage
6V1 = 6.1 Volts min
Number of lines
blank = 4 line
-5 = 5 line protection
Package
M6 = Micro QFN 6 leads
4/11
ESDALC6V1M6, ESDALC6V1-5M6
Package information
3
Package information
●
Epoxy meets UL94, V0
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at
www.st.com.
Table 3.
Package dimensions
Dimensions
Millimeters
Min Typ Max
D
N
Ref
Inches
Typ
E
Min
Max
1
2
A
0.50 0.55 0.60 0.020 0.022 0.024
A1 0.00 0.02 0.05 0.000 0.001 0.002
A
b
0.18 0.25 0.30 0.007 0.010 0.012
A1
D(1)
E(1)
1.45
1.00
0.50
0.057
0.039
0.020
1
2
L
k
e(2)
k
b
0.20
0.008
e
L
0.30 0.35 0.40 0.012 0.014 0.016
1.
2.
0.1 mm
0.05 mm
Figure 13. Footprint dimensions in mm [inches]
0.50
0.25
[0.020]
[0.010]
0.65
[0.026]
0.30
1.60
[0.012]
[0.063]
5/11
Package information
Figure 14. Tape and reel specification
ESDALC6V1M6, ESDALC6V1-5M6
Dot identifying Pin A1 location
2.0+/-0.05
4.00+/-0.1
φ 1.5 +/- 0.1
X
X
X
0.75
1.20
4.00
User direction of unreeling
X: Marking
Note:
Product marking may be rotated by 90° for assembly plant differentiation. In no case should
this product marking be used to orient the component for its placement on a PCB. Only pin 1
mark is to be used for this purpose.
6/11
ESDALC6V1M6, ESDALC6V1-5M6
Recommendation on PCB assembly
4
Recommendation on PCB assembly
4.1
Stencil opening design
1. General recommendation on stencil opening design
a) Stencil opening dimensions: L (Length), W (Width), T (Thickness).
Figure 15. Stencil opening dimensions
L
T
W
b) General design rule
Stencil thickness (T) = 75 ~ 125 µm
W
-----
Aspect Ratio =
≥ 1.5
T
L × W
---------------------------
Aspect Area =
≥ 0.66
2T(L + W)
2. Reference design
a) Stencil opening thickness: 100 µm
b) Stencil opening for leads: Opening to footprint ratio is 90%.
Figure 16. Recommended stencil window position
7 µm
7 µm
15 µm
236 µm
250 µm
15 µm
Footprint
Stencil window
Footprint
7/11
Recommendation on PCB assembly
ESDALC6V1M6, ESDALC6V1-5M6
4.2
Solder paste
1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004.
2. “No clean” solder paste is recommended.
3. Offers a high tack force to resist component movement during high speed.
4. Solder paste with fine particles: powder particle size is 20-45 µm.
4.3
Placement
1. Manual positioning is not recommended.
2. It is recommended to use the lead recognition capabilities of the placement system, not
the outline centering.
3. Standard tolerance of 0.05 mm is recommended.
4. 3.5 N placement force is recommended. Too much placement force can lead to
squeezed out solder paste and cause solder joints to short. Too low placement force
can lead to insufficient contact between package and solder paste that could cause
open solder joints or badly centered packages.
5. To improve the package placement accuracy, a bottom side optical control should be
performed with a high resolution tool.
6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is
recommended during solder paste printing, pick and place and reflow soldering by
using optimized tools.
4.4
PCB design preference
1. To control the solder paste amount, the closed via is recommended instead of open
vias.
2. The position of tracks and open vias in the solder area should be well balanced. The
symmetrical layout is recommended, in case any tilt phenomena caused by
asymmetrical solder paste amount due to the solder flow away.
8/11
ESDALC6V1M6, ESDALC6V1-5M6
Recommendation on PCB assembly
4.5
Reflow profile
Figure 17. ST ECOPACK® recommended soldering reflow profile for PCB mounting
Temperature (°C)
260°C max
255°C
220°C
180°C
2°C/s recommended
125 °C
6°C/s max
3°C/s max
0
0
1
2
3
4
5
6
7
Time (min)
10-30 sec
90 to 150 sec
90 sec max
Note:
Minimize air convection currents in the reflow oven to avoid component movement.
9/11
Ordering information
ESDALC6V1M6, ESDALC6V1-5M6
5
Ordering information
Table 4.
Ordering information
Order code
Marking
Package
Micro QFN
Micro QFN
Weight
2.2 mg
2.2 mg
Base qty
3000
Delivery mode
Tape and reel
Tape and reel
G(1)
H(1)
ESDALC6V1M6
ESDALC6V1-5M6
3000
1. The marking can be rotated by 90° to differentiate assembly location
6
Revision history
Table 5.
Date
Document revision history
Revision
Changes
19-Sep-2005
10-Oct-2005
21-Dec-2005
1
2
3
Initial release.
Package title changed from DFN to QFN. No technical changes.
Updated package dimensions in Table 1.
Reformatted to current standard.
01-Feb-2007
14-Feb-2008
4
5
Added note on marking rotation in section 3. Package information.
Reformatted to current standards. Corrected inch measurements in
Table 3 on page 5. Added Section 4: Recommendation on PCB
assembly
10/11
ESDALC6V1M6, ESDALC6V1-5M6
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11/11
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