STV6886_技术文档

STV6886

2

LOW-COST I C CONTROLLED DEFLECTION PROCESSOR

FOR MULTISYNC MONITOR

FEATURES

DESCRIPTION

The STV6886 is a monolithic integrated circuit as-

sembled in a 32-pin shrink dual-in-line plastic

package. This IC controls all the functions related

to horizontal and vertical deflection in multimode

or multi-frequency computer display monitors.

General

■ SYNC PROCESSOR (separate or composite)

■ 12V SUPPLY VOLTAGE

■ 8V REFERENCE VOLTAGE

■ HOR. LOCK/UNLOCK OUTPUT

■ HOR. & VERT. LOCK/UNLOCK INDICATION

The internal sync processor, combined with the

powerful geometry correction block, makes the

STV6886 suitable for very high performance mon-

itors, using few external components.

2

■ READ/WRITE I C INTERFACE

■ HORIZONTAL AND VERTICAL MOIRE

■ B+ REGULATOR

Combined with other ST components dedicated

for CRT monitors (microcontroller, video preampli-

fier, video amplifier, OSD controller) the STV6886

- Internal PWM generator for B+ current mode

step-up converter

2

allows fully I C bus-controlled computer display

- Switchable to step-down converter

2

monitors to be built with a reduced number of ex-

ternal components.

- I C-adjustable B+ reference voltage

- Output pulses synchronized on horizontal

frequency

- Internal maximum current limitation.

Horizontal

■ Self-adaptative

■ Dual PLL concept

■ 80kHz maximum frequency

■ X-ray protection input

SHRINK32 (Plastic Package)

ORDER CODE: STV6886

2

■ I C controls: Horizontal duty-cycle, H-position,

PIN CONNECTIONS

horizontal size amplitude

Vertical

H/HVIN

VSYNCIN

HMOIRE/HLOCK

1

2

3

32

31

30

5V

SDA

SCL

■ Vertical ramp generator

■ 50 to 120 Hz agc loop

■ Geometry tracking with VPOS & VAMP

PLL2C

C0

R0

PLL1F

4

29

28

27

26

25

24

23

22

21

V

CC

BOUT

GND

HOUT

XRAY

EWOUT

VOUT

VCAP

2

5

■ I C controls:VAMP, VPOS, S-CORR, C-CORR

6

■ Vertical breathing compensation

7

2

I C Geometry Corrections

HPOSITION

HFOCUSCAP

FOCUS-OUT

HGND

8

9

■ Vertical parabola generator (Pin Cushion - E/W,

Keystone, Corner Correction)

■ Horizontal dynamic phase

10

11

12

HFLY

V

REF

(Side Pin Balance & Parallelogram)

HREF

COMP

REGIN

13

14

15

16

20

19

18

17

VAGCCAP

VGND

VBREATH

B + GND

■ Horizontal and vertical dynamic focus

(Horizontal Focus Amplitude, Horizontal Focus

Symmetry, Vertical Focus Amplitude)

I

SENSE

Version 4.2

April 2000

1/43

1

TABLE OF CONTENTS

PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

QUICK REFERENCE DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

THERMAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Supply and reference voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

I2C READ/WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

SYNC PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

HORIZONTAL SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

VERTICAL SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

DYNAMIC FOCUS SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

GEOMETRY CONTROL SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

MOIRE CANCELLATION SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

B+ SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

TYPICAL OUTPUT WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

I2C BUS ADDRESS TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

OPERATING DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1 GENERAL CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2

1.2 I C Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.3 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.4 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.5 Sync Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.6 Sync Identification Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.7 IC status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

1.8 Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

1.9 Sync Processor Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2 HORIZONTAL PART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.1 Internal Input Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.2 PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.3 PLL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.4 Output Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.5 X-RAY Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.6 Horizontal and Vertical Dynamic Focus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.7 Horizontal Moiré Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3 VERTICAL PART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.1 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.2 I2C Control Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.3 Vertical Moiré . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.4 Basic Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.5 Geometric Corrections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.6 E/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.7 Dynamic Horizontal Phase Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4 DC/DC CONVERTER PART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.1 Step-up Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.2 Step-down Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.3 Step-up and Step-down Configuration Comparison . . . . . . . . . . . . . . . . . . . . . . . . 32

2

INTERNAL SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2/43

STV6886

PIN CONNECTIONS

1

Name

H/HVIN

Function

TTL-compatible Horizontal sync Input (separate or composite)

TTL-compatible Vertical sync Input (for separated H&V)

2

VSYNCIN

3

HMOIRE/

HLOCK

Horizontal Moiré Output (to be connected to PLL2C through a resistor divider), HLock

Output

4

5

6

7

8

PLL2C

C0

Second PLL Loop Filter

Horizontal Oscillator Capacitor

Horizontal Oscillator Resistor

R0

PLL1F

HPOSITION

First PLL Loop Filter

Horizontal Position Filter (capacitor to be connected to HGND)

HFOCUS-

CAP

9

Horizontal Dynamic Focus Oscillator Capacitor

10

11

12

13

14

15

16

17

18

19

20

21

22

23

FOCUS OUT

HGND

Mixed Horizontal and Vertical Dynamic Focus Output

Horizontal Section Ground

HFLY

Horizontal Flyback Input (positive polarity)

HREF

Horizontal Section Reference Voltage (to be filtered)

B+ Error Amplifier Output for frequency compensation and gain setting

Feedback Input of B+ control loop

COMP

REGIN

I

Sensing of external B+ switching transistor current, or switch for step-down converter

Ground (related to B+ reference)

SENSE

B+GND

VBREATH

VGND

V Breathing Input Control (compensation of vertical amplitude against EHV variation)

Vertical Section Ground

VAGCCAP

Memory Capacitor for Automatic Gain Control in Vertical Ramp Generator

Vertical Section Reference Voltage (to be filtered to pin 19)

Vertical Sawtooth Generator Capacitor

V

REF

VCAP

VOUT

Vertical Ramp Output (with frequency-independent amplitude and S or C Corrections

if any). It includes vertical position and vertical moiré voltages.

24

25

26

27

28

29

30

31

32

EWOUT

XRAY

HOUT

GND

Pin Cushion (E/W) Correction Parabola Output

X-RAY protection input (with internal latch)

Horizontal Drive Output (NPN open collector)

General Ground

BOUT

B+ PWM Regulator Output (NPN open collector)

Supply Voltage(12V typ) (referenced to Pin 27)

V

CC

2

SCL

SDA

5V

I C Clock Input

2

I C Data Input

5V Supply Voltage

3/43

STV6886

QUICK REFERENCE DATA

Parameter

Value

YES

NO

Unit

Any polarity on H Sync & V Sync inputs

TTL or composite Syncs

Sync on Green

Horizontal Frequency

15 to 80

1 to 3.5 f0

NO

kHz

Horizontal Autosync Range (for given R0 and C0. Can be easily increased by application)

Control of free-running frequency

Frequency Generator for Burn-in

NO

2

Control of H-Position through I C

YES

30 to 65

NO

2

Control for H-Duty Cycle through I C

%

PLL1 Inhibition Possibility

Output for Horizontal Lock/Unlock

Dual Polarity H-Drive Outputs

YES

NO

Vertical Frequency

35 to 150

50 to 120

YES

NO

Hz

Vertical Autosync Range (for 150nF on Pin 22 and 470nF on Pin 20)

2

Vertical S-Correction (adapted to normal or super flat tube), controlled through I C

2

Vertical C-Correction, controlled through I C

2

Control of Vertical Amplitude through I C

2

Control of Vertical Position through I C

Input for Vertical Amplitude compensation versus EHV

E/W Correction Output (also known as Pin Cushion Output)

2

Horizontal Size Adjustment through I C control of E/W Output DC level

2

Control of E/W (Pincushion) Adjustment through I C

2

Control of Keystone (Trapezoïd) Adjustment through I C

2

Control of Corner Adjustment through I C

Fully integrated Dynamic Horizontal Phase Control

2

Control of Side Pin Balance through I C

2

Control of Parallelogram through I C

H/V composite Dynamic Focus Output

2

Control of Horizontal Dynamic Focus Amplitude through I C

2

Control of Horizontal Dynamic Focus Symmetry through I C

2

Control of Vertical Dynamic Focus Amplitude through I C

Tracking of Geometric Corrections and of Vertical focus with Vertical Amplitude and Position

2

Control of Horizontal and Vertical Moiré cancellations through I C

2

Optimisation of HMoiré frequency through I C

2

B+ Regulation, adjustable through I C

Stand-by function, disabling H and V scanning and B+

X-Ray protection, disabling H scanning and B+

Blanking Outputs

2

Fast I C Read/Write

400

kHz

2

I C indication of the presence of Syncs (biased from 5V alone)

YES

2

I C indication of the polarity and Type of Syncs

2

I C indication of Lock/Unlock, for both Horizontal and Vertical sections

4/43

STV6886

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

13.5

5.7

Unit

V

Supply Voltage (Pin 29)

Supply Voltage (Pin 32)

CC

DD

V

4.0

5.5

6.4

8.0

V

Max Voltage on

Pin 4

Pin 9

Pin 5

V_IN

Pins 6, 7, 8, 14, 15, 16, 20, 22

Pins 3, 10, 18, 23, 24, 25, 26, 28

Pins 1, 2

V

CC

V

DD

Pins 30, 31

5

V

ESD susceptibility

through 1.5kΩ

Human Body Model, 100pF Discharge

2

300

kV

V

VESD

EIAJ Norm, 200pF Discharge through 0Ω

T_stg

T_j

Storage Temperature

Junction Temperature

-40, +150

+150

°C

T_oper

Operating Temperature

0, +70

THERMAL DATA

Symbol

Parameter

Max. Junction-Ambient Thermal Resistance

Value

Unit

R_th(j-a)

65

°C/W

SUPPLY AND REFERENCE VOLTAGES

Electrical Characteristics (V = 12V, T

= 25°C unless otherwise indicated)

CC

Parameter

Supply Voltage

amb

Symbol

Test Conditions

Pin 29

Min.

10.8

4.5

Typ.

12

5

Max. Units

V

13.2

5.5

V

CC

DD

Supply Voltage

Pin 32

I

Supply Current

Pin 29

50

5

mA

V

CC

I

Supply Current

Pin 32

DD

V

Horizontal Reference Voltage

Vertical Reference Voltage

Pin 13, I = -2mA

Pin 21, I = -2mA

Pin 13

7.6

8.2

8.8

5

REF-H

REF-V

REF-H

REF-V

V

I

Max. Sourced Current on V

mA

REF-H

REF-V

Pin 21

5

6/43

STV6886

2

I C READ/WRITE

Electrical Characteristics (V_DD= 5V, T

= 25°C)

amb

Symbol

Parameter

Test Conditions

Min.

Typ.

Max. Units

2

(1)

I C PROCESSOR

Fscl

Tlow

Thigh

Vinth

Maximum Clock Frequency

Low period of the SCL Clock

Pin 30

400

kHz

µs

V

Pin 30

1.3

0.6

High period of the SCL Clock

SDA and SCL Input Threshold

Pin 30

Pins 30, 31

2.2

Acknowledged Output Voltage on SDA

input with 3mA

VACK

Pin 31

0.4

20

V

Leakage current into SDA and SCL with

no logic supply

V

= 0

µA

2

DD

I C leak

Pins 30, 31 = 5 V

2

Note:

1

See also I C Bus Address Table.

SYNC PROCESSOR

Operating Conditions (V_DD= 5V, V_CC= 12V, T

= 25°C)

amb

Symbol

Parameter

Test Conditions

Min.

Typ.

Max. Units

HSVR

Voltage on H/HVIN Input

Pin 1

0

5

V

Minimum Horizontal Input Pulses Dura-

tion

MinD

Pin 1

0.7

µs

Maximum Horizontal Input Signal Duty

Cycle

Mduty

25

5

%

VSVR

VSW

Voltage on VSYNCIN

Pin 2

0

5

V

µs

%

Minimum Vertical Sync Pulse Width

VSmD

Maximum Vertical Sync Input Duty Cycle Pin 2

15

Maximum Vertical Sync Width on TTL H/

Vcomposite

VextM

Pin 1

750

µs

Electrical Characteristics (V_DD= 5V, V_CC= 12V, T

= 25°C)

amb

Symbol

VINTH

RIN

Parameter

Test Conditions

Min.

Typ.

Max. Units

Horizontal and Vertical Input Logic Level High Level

(Pins 1, 2) Low Level

2.2

V

0.8

V

Horizontal and Vertical Pull-Up Resistor Pins 1, 2

Extracted Vsync Integration Time (% of

250

35

kΩ

VoutT

C0 = 820pF

26

%

(2)

T ) on H/VComposite

H

Note:

2

T

is the horizontal period.

H

7/43

STV6886

HORIZONTAL SECTION

Operating Conditions

Symbol

VCO

Parameter

Test Conditions

Min.

Typ.

Max. Units

I

Max Current from Pin 6

Pin 6

1.5

80

mA

0max

F(max.)

Maximum Oscillator Frequency

kHz

OUTPUT SECTION

I12m

Maximum Input Peak Current

Pin 12

5

mA

Horizontal Drive Output Maximum Cur-

rent

HOI

Pin 26, Sunk current

30

Electrical Characteristics (V_CC= 12V, T

= 25°C)

amb

Symbol

Parameter

Test Conditions

Min.

Typ.

Max. Units

1st PLL SECTION

Delay Time for detecting polarity

change

HpoIT

Pin 1

0.75

ms

(3)

V

= 8.2V

REF-H

Vvco

VCO Control Voltage (Pin 7)

VCO Gain (Pin 7)

f

= f

f (Max.)

1.4

4.9

V

H

0

f

H= H

R = 6.49kΩ,

C = 820pF

0

Vcog

Hph

Tbd

15.9

Tbd kHz/V

%

0

% of Horizontal

Period

(4)

Horizontal Phase Adjustment

±10

(4)

Horizontal Phase Setting Value (Pin 8)

Minimum Value

Typical Value

Sub-Address 01

Vbmi

Vbtyp

Vbmax

Byte

x1111111

x1000000

x0000000

2.9

3.5

4.2

V

Maximum Value

IPII1U

IPII1L

PLL1 Unlocked

PLL1 Locked

±140

±1

µA

mA

PLL1 Filter Charge Current

f

Free Running Frequency

R = 6.49kΩ, C = 820pF

Tbd

22.8

Tbd

kHz

o

0

Not including external

componant drift

(5)

dfo/dT

CR

Free Running Frequency Thermal Drift

-150

ppm/C

fH(Min.)

f +0.5

kHz

o

PLL1 Capture Range

(6)

fH(Max.)

3.5f

o

Sub-address 02

1xxx xxxx

0000 0000

DC level pin 3 when PLL1 is

unlocked

6

V

HUnlock

(7)

0.3

2.75

0111 1111

3

8/43

STV6886

Symbol

Parameter

Test Conditions

Min.

Typ.

Max. Units

2nd PLL SECTION AND HORIZONTAL OUTPUT SECTION

FBth

Hjit

Flyback Input Threshold Voltage (Pin 12)

0.65

0.75

70

V

(8)

Horizontal Jitter

At 31.4kHz

ppm

HDmin

HDmax

Horizontal Drive Output Duty-Cycle (Pin Sub-Address 00

(9)

26)

Byte x1111111

Byte x0000000

30

65

%

(10)

X-RAY Protection Input Threshold Volt-

age,

XRAYth

Vphi2

Pin 25, (see fig. 14)

7.6

8.2

8.8

0.4

V

Internal Clamping Levels on 2nd PLL

Loop Filter (Pin 4)

Low Level

High Level

1.6

4.2

V

Inhibition threshold (The condition V

<

CC

VSCinh

HDvd

VSCinh will stop H-Out, V-Out, B-Out and Pin 29

reset X-RAY)

7.5

V

Horizontal Drive Output (low level)

Pin 26, I

= 30mA

OUT

Note:

3

4

5

6

7

This delay is necessary to avoid a wrong detection of polarity change in the case of a composite sync.

See Figure 10 for explanation of reference phase.

These parameters are not tested on each unit. They are measured during our internal qualification.

A larger range may be obtained by application.

When at 0xxx xxxx, (HMoiré/HLock not selected), Pin 3 is a DAC with 0.3...2.75V range. When at 1xxx xxxx

(HMoiré/HLock selected) and PLL1 is locked, Pin 3 provides the waveform for HMoiré. See also Moiré

section.

6

8

9

Hjit = 10 x(Standard deviation/Horizontal period).

Duty Cycle is the ratio between the output transistor OFF time and the period. The scanning transistor is

controlled OFF when the output transistor is OFF.

10 Initial Condition for Safe Start Up.

9/43

STV6886

VERTICAL SECTION

Operating Conditions

Symbol

Parameter

Test Conditions

Pin 20

Min.

Typ.

Max. Units

Minimum Load for less than 1% Vertical

Amplitude Drift

R

65

MΩ

LOAD

Electrical Characteristics (V_CC= 12V, T

= 25°C)

amb

Symbol

Parameter

Test Conditions

Min.

Typ.

2.1

Max. Units

VRB

Voltage at Ramp Bottom Point

Pin 22

V

VRT

Voltage at Ramp Top Point (with Sync) Pin 22

5.1

Voltage at Ramp Top Point (without

Sync)

VRT-

0.1

VRTF

Pin 22

Pin 22, C = 150nF

V

VSTD

VFRF

ASFR

Vertical Sawtooth Discharge Time

70

µs

22

(12)

Vertical Free Running Frequency

Pin 22, C = 150nF

100

Hz

22

(13)

AUTO-SYNC Frequency

C

= 150nF ±5%

50

120

Hz

22

Ramp Amplitude Drift Versus Frequency

at Maximum Vertical Amplitude

C

= 150nF

ppm/

Hz

22

RAFD

Rlin

200

0.5

(11)

50Hz< f < 120Hz

(12)

Ramp Linearity on Pin 22

2.5V < V < 4.5V

%

27

Sub Address 06

Vertical Position Adjustment Voltage (Pin Byte 00000000

3.2

3.6

4.0

Tbd

V

VPOS

23 - VOUT mean value)

Byte 01000000

Byte 01111111

Tbd

Sub Address 05

Byte 10000000

Byte 11000000

Byte 11111111

Vertical Output Voltage

(peak-to-peak on Pin 23)

2.15

3.0

3.9

V

VOR

VOI

Vertical Output Maximum Current

(Pin 23)

±5

mA

Max Vertical S-Correction Amplitude (TV Sub Address 07

is the vertical period)

(0xxxxxxx inhibits S-CORR

11111111 gives max S-CORR)

Byte 11111111

∆V/V at TV/4

dVS

-3.5

+3.5

%

PP

∆V/V at 3TV/4

PP

Sub Address 08

∆V/V at TV/2

PP

Vertical C-Corr Amplitude

(0xxxxxxx inhibits C-CORR)

Ccorr

Byte 10000000

Byte 11000000

Byte 11111111

-3

0

+3

%

(14)

BRRANG

BRADj

DC Breathing Control Range

V

1

12

V

18

Vertical Output Variation versus DC

Breathing Control (Pin 23)

V

> V

0

-2.5

%/V

18

REF-V

1V<V < V

18

REF-V

Note: 11 These parameters are not tested on each unit. They are measured during our internal qualification procedure.

Note: 12 Set Register 07 at Byte 0xxxxxxx (S correction inhibited) and Register 08 at Byte 0xxxxxxx (C correction

inhibited), to obtain a vertical sawtooth with linear shape.

Note: 13 This is the frequency range for which the vertical oscillator will automatically synchronize, using a single

capacitor value on Pin22 and Pin 20, and with a constant ramp amplitude.

Note: 14 When not used, the DC breathing control pin must be connected to 12V.

10/43

STV6886

DYNAMIC FOCUS SECTION

Electrical Characteristics (V_CC= 12V, T

= 25°C)

amb

Symbol

Parameter

Test Conditions

Min.

Typ.

Max. Units

HORIZONTAL DYNAMIC FOCUS FUNCTION (seeFigure 15 on page 28)

Horizontal Dynamic Focus Sawtooth

Minimum Level

Maximum Level

Pin 9, capacitor on HFO-

CUSCAP and

HDFst

HDFdis

HDFstart

2.2

4.9

V

C0 = 820pF, T = 20µs

H

Horizontal Dynamic Focus Sawtooth

Discharge Width

Triggered by HDFstart

400

ns

Internal Phase Advance versus HFLY

middle

1

µs

(Independent of frequency)

HDFDC

TDFHD

Bottom DC Output Level

R

= 10kΩ, Pin 10

2.1

V

LOAD

(11)

DC Output Voltage Thermal Drift

200

ppm/C

Horizontal Dynamic Focus

Amplitude

Sub-Address 03,

Pin 10, fH = 50kHz,

Symmetric Wave Form

x1111111

x1000000

x0000000

HDFamp

Max Byte

Typ Byte

Max Byte

1

1.5

3.5

V

PP

Horizontal Dynamic FocusSymmetry

(For time reference, see Figure 15)

Max Phase Advance

Subaddress 04

HDFKeyst

x1111111 (decimal 127)

x0000000 (decimal 0)

16

%

Max Phase Delay

VERTICAL DYNAMIC FOCUS FUNCTION (see Figure 1)

Sub-Address 0F

Vertical Dynamic Focus Parabola (added

to horizontal) Amplitude with VAMP and

VPOS Typical

Min Byte x0000000

Typ Byte x1000000

Max Byte x1111111

0

0.5

1

V

PP

AMPVDF

VDFAMP

Parabola Amplitude Function of VAMP

(tracking between VAMP and VDF) with Byte

Sub-Address 05

x0000000

x1000000

x1111111

0.6

1

1.5

V

PP

VPOS Typ. (see Figure 1 on page 15,

Byte

(15)

and

)

Parabola Asymmetry Function of VPOS Sub-Address 06

Control (tracking between VPOS and

VDF) with VAMP Max.

VHDFKeyt

B/A Ratio

A/B Ratio

Byte

x0000000

x1111111

0.52

Note: 15 S and C correction are inhibited to obtain a linear vertical sawtooth.

11/43

STV6886

GEOMETRY CONTROL SECTION

Electrical Characteristics (V_CC= 12V, T

= 25°C)

amb

Symbol

Parameter

Test Conditions

Min.

Typ.

Max. Units

SYMMETRIC CONTROL THROUGH E/W OUTPUT (see Figure 2 on page 15 and Figure 4 on page 15)

VEWM

VEWm

Maximum E/W Output Voltage

Minimum E/W Output Voltage

Pin 24

6.5

V

1.8

For control of Horizontal size.

DC Output Voltage with:

-E/W Corner inhibited

-Keystone inhibited

Pin 24, see Figure 2

Subaddress 11

Byte x0000000

Byte x1000000

Byte x1111111

EW

2

3.25

4.2

V

DC

(16)

TDEW

DC Output Voltage Thermal Drift

See

100

ppm/C

DC

Parabola Amplitude with:

-VAMP max,

-VPOS typ.,

Subaddress 0A

Byte 11111111

Byte 11000000

Byte 10000000

1.4

0.7

0

V

PP

EWpara

EWtrack

-Keystone and Corner inhibited

Parabola Amplitude Function of VAMP

Control (tracking between VAMP & E/W):

-VPOS typ.

Subaddress 05

Byte 10000000

Byte 11000000

Byte 11111111

0.2

0.4

0.7

V

PP

-E/W Amplitude, Corner & Keystone in-

(17)

hibited

Keystone Adjustment Capability with: -

VPOS typ.

-E/W inhibited,

Subaddress 09

Byte 10000000

Byte 11111111

KeyAdj

0.4

V

PP

-Corner inhibited

-Vert. Amplitude max

(17)

(see

and Figure 4)

Corner Adjustment Capability with:

-VPOS typ,

-E/W inhibited

-Keystone inhibited

-Vertical Amplitude max.

Subaddress 10

Byte 11111111

Byte 11000000

Byte 10000000

+1.25

0

−1.25

V

PP

EW Corner

Intrinsic Keystone Function of VPOS

Control (tracking between VPOS & E/W):

- E/W Amplitude

Subaddress 06

KeyTrack

-Vertical Amplitude max

-Corner inhibited

B/A Ratio

A/B Ratio

Byte 00000000

Byte 01111111

0.52

12/43

STV6886

Symbol

Parameter

Test Conditions

Min.

Typ.

Max. Units

ASYMMETRIC CONTROL THROUGH INTERNAL DYNAMIC HORIZONTAL PHASE MODULATION (see Figure 3)

Side Pin Balance Parabola Amplitude

(Figure 3) with :

Subaddress 0D

SPBpara

SPBtrack

ParAdj

-VAMP max.,

-VPOS typ.

-Parallelogram inhibited

Byte 11111111

Byte 10000000

+2.8

-2.8

%T

H

(17 & 18)

Side Pin Balance Parabola Amplitude

function of VAMP Control (tracking be-

tween VAMP and SPB) with:

-SPB max.,

-VPOS typ.

-Parallelogram inhibited

Subaddress 05

Byte 10000000

Byte 11000000

Byte 11111111

1

1.8

2.8

%T

H

(17 & 18)

Parallelogram Adjustment Capability

with:

-VAMP max.,

-VPOS typ.

-SPB inhibited

Subaddress 0E

Byte 11111111

Byte 11000000

+2.8

-2.8

%T

H

(17 & 18)

Intrinsic Parallelogram Function of VPOS Subaddress 06

Control (tracking between VPOS and

DHPC) with :

-VAMP max.,

-SPB max.

Partrack

(17 & 18)

-Parallelogram inhibited

B/A Ratio

A/B Ratio

Byte x0000000

Byte x1111111

0.52

Note: 16 These parameters are not tested on each unit. They are measured during our internal qualification procedure.

Note: 17 With Register 07 at Byte 0xxxxxxx (S correction inhibited) and Register 08 at Byte 0xxxxxxx (C correction

inhibited), the sawtooth has a linear shape.

MOIRE CANCELLATION SECTION

Electrical Characteristics (V_CC= 12V, T

= 25°C)

amb

Symbol

Parameter

Test Conditions

Min.

Typ.

Max. Units

HORIZONTAL AND VERTICAL MOIRE

R

Minimum Output Resistor to GND

Pin 3

4.7

kΩ

MOIRE

R

= 4.7kΩ

MOIRE

sub-address 02

Byte 00000000

Byte 01000000

Byte 01111111

DC Voltage pin 3

DAC configuration

DacOut

0.3

1.1

2.75

V

3

R

= 4.7kΩ

MOIRE

Moiré pulse

(See also Hunlock in 1st PLL section)

H Frequency: Locked

Sub-address 02

Byte 10000000

Byte 11000000

Byte 11111111

HMOIRE

0

0.8

2.2

V

PP

Sub-address II:

0xxx xxxx

1xxx xxxx

T

Separate

Combined

HMOIRE

Preferred Scanning/EHT structure

Vertical Moiré

(measured on VOUT: Pin 23)

Sub-address 0C

Byte 11111111

VMOIRE

3

mV

Note: 18 T is the horizontal period.

H

13/43

STV6886

B+ SECTION

Operating Conditions

Symbol

Parameter

Test Conditions

Min.

Typ.

Max. Units

Resistor between Pins 15

and 14

FeedRes

Minimum Feedback Resistor

5

kΩ

Electrical Characteristics (V_CC= 12V, T

= 25°C)

amb

Symbol

Parameter

Test Conditions

Min.

Typ.

85

Max. Units

(19)

OLG

Error Amplifier Open Loop Gain

Unity Gain Bandwidth

At low frequency

dB

(19)

UGBW

See

6

MHz

Current sourced by Pin 15

(PNP base)

IRI

Feedback Input Bias Current

0.2

1.4

µA

Current sourced by Pin 14

Current sunk by

mA

EAOI

Error Amplifier Output Current

(20)

Pin 14

2

mA

CSG

Current Sense Input Voltage Gain

Pin 16

3

Max Current Sense Input Threshold Volt-

age

MCEth

Pin 16

1.3

V

Current sunk by Pin 16

(PNP base)

ISI

Current Sense Input Bias Current

1

µA

Maximum ON Time of the external power % of horizontal period,

Tonmax

B+OSV

100

%

V

(21)

transistor

f = 27kHz)

o

B+Output Saturation Voltage

V

with I = 10mA

0.25

28

On error amp (+)

input Subaddress OB:

Byte 1000000

IV

Internal Reference Voltage

5

V

REF

Internal Reference Voltage Adjustment

Range

Byte 01111111

Byte 00000000

+20

-20

%

V

REFADJ

Threshold for step-up/step-down selec-

PWMSEL

tion (step-up configuration if V < PWM- Pin 16

6

V

16

SEL)

t

Fall Time

Pin 28

100

ns

FB+

Note: 19 These parameters are not tested on each unit. They are measured during our internal qualification procedure

which includes characterization on batches coming from corners of our process and also temperature

characterization.

Note: 20 To make soft start possible, 0.5mA are sunk when B+ is disabled.

Note: 21 The external power transistor is OFF during 400ns of the HFOCUSCAP discharge

14/43

STV6886

Figure 1. Vertical Dynamic Focus Function

Figure 2. E/W Output

Figure 3. Dynamic Horizontal Phase Control

Figure 4. Keystone Effect on E/W Output (PCC Inhibited)

15/43

STV6886

TYPICAL OUTPUT WAVEFORMS

Sub

Address

Function

Byte

Specification

Effect on Screen

V

OUTDC

2.15V

3.9V

10000000

Vertical Size

05

23

V

OUTDC

11111111

00000000

01000000

01111111

V

= 3.2V

= 3.6V

= 4.0V

OUTDC

Vertical

Position

DC Control

V

06

23

V

OUTDC

0xxxxxxx:

Inhibited

Vertical

S

07

23

Linearity

∆V

V

11111111

PP

=

3.5%

V

PP

16/43

STV6886

Sub

Address

Function

Byte

Specification

Effect on Screen

0xxxxxxx :

Inhibited

Vertical

C

Linearity

∆V

08

23

10000000

11111111

V

PP

DV

=-3%

V

PP

V

PP

DV

=+3%

V

PP

x1111111

x0000000

4.2V

2V

Horizontal

Size

11

24

Horizontal

Dynamic

Focus with:

03

10

X000 0000 —

X111 1111 ---

Amplitude

Horizontal

Dynamic

Focus with:

X000 0000 —

X111 1111 ---

04

10

Symmetry

17/43

STV6886

Sub

Address

Function

Byte

Specification

Effect on Screen

(E/W + Corner Inhibited)

10000000

11111111

0.4V

EW

DC

Keystone

(Trapezoid)

Control

09

24

0.4V

DC

(Keystone + Corner Inhibited)

10000000

0V

EW

DC

E/W

(Pin

Cushion)

Control

0A

24

1.4V

11111111

EW

DC

(Keystone+ E/W Inhibited)

1.25V

11111111

EW

DC

Corner

Control

10

24

EW

DC

10000000

1.25V

(SPB

Inhibited)

Parallel-

ogram

Control

2.8% T

10000000

11111111

H

0E

2.8% T

H

18/43

STV6886

Sub

Address

Function

Byte

Specification

Effect on Screen

(Parallelogram

Inhibited)

Side Pin

Balance

Control

2.8% T

H

10000000

11111111

0D

H

X111 1111

2.1V

T

V

Vertical

Dynamic

Focus with

Horizontal

0F

10

X000 0000

0V

2.1V

T

V

19/43

STV6886

2

I C BUS ADDRESS TABLE

Slave Address (8C): Write Mode

Sub Address Definition

D8 D7 D6 D5 D4 D3 D2 D1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Horizontal Drive Selection/Horizontal Duty Cycle

X-ray Reset/Horizontal Position

Horizontal Moiré/H Lock

Sync. Priority/Horizontal Focus Amplitude

Refresh/Horizontal Focus Symmetry

Vertical Ramp Amplitude

Vertical Position Adjustment

S Correction

2

3

4

5

6

7

8

C Correction

9

E/W Keystone

A

B

C

D

E

F

E/W Amplitude

B+ Reference Adjustment

Vertical Moiré

Side Pin Balance

Parallelogram

Vertical Dynamic Focus Amplitude

E/W Corner

10

11

H. Moiré Frequency/Horizontal Size Amplitude

Slave Address (8D): Read Mode: No sub address needed.

20/43

STV6886

2

I C BUS ADDRESS TABLE (continued)

D8

D7

D6

D5

D4

D3

D2

D1

WRITE MODE

HDrive

0, off

[1], on

Horizontal Duty Cycle

00

01

[0]

[1]

[0]

Horizontal Phase Adjustment

[0] [0] [0]

Xray

1, reset

[0]

Horizontal Moiré Amplitude

[0] [0] [0]

HMoiré/HLock

1, on

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

[0]

[1]

[0]

[1]

[0]

[0], off

Horizontal Focus Amplitude

[0] [0] [0]

Sync

0, Comp

[1], Sep

Horizontal Focus Symmetry

[0] [0] [0]

Detect

Refresh

[0], off

Vertical Ramp Amplitude Adjustment

[0] [0] [0]

Vramp

0, off

[1], on

Vertical Position Adjustment

Test V

1, on

[0], off

[0]

S Correction

S Select

1, on

[0]

C Correction

C Select

1, on

[0]

E/W Keystone

E/W Key

0, off

[1]

[0]

E/W Amplitude

E/W Sel

0, off

[1]

[0]

B + Reference Adjustment

Test H

1, on

[0], off

[0]

Vertical Moiré Amplitude

V. Moiré

1, on

[0]

Side Pin Balance

SPB Sel

0, off

[1]

[0]

Parallelogram

Parallelo

0, off

[1]

[0]

21/43

STV6886

D8

Eq. Pulse

D7

D6

D5

D4

D3

D2

D1

Vertical Dynamic Focus Amplitude

0F 1, ignore T /2

H

[1]

[0]

[0], accept all

E/W Corner

Corner Sel

10

11

1, on

[0], off

[1]

[0]

H. Moiré

suited to

1 Combined

[0] Separate

scanning/EHT

Horizontal Size Amplitude

[0] [0] [0]

READ MODE

Polarity Detection

H/V pol V pol

[1], negative [1], negative [0], no det

Sync Detection

Hlock

0, on

[1], no

Vlock

0, on

[1], no

Xray

1, on

[0], off

Vext det

H/V det

V det

[0], no det

[x] at Power-on Reset value

Data is transferred with vertical sawtooth retrace.

We recommend setting the unspecified bits to [0] in order to ensure compatibility with future devices.

22/43

STV6886

OPERATING DESCRIPTION

1 GENERAL CONSIDERATIONS

1.1 Power Supply

dition is detected, the circuit increments automati-

cally by one the momentary subaddress in the

subaddress counter (auto-increment mode). So it

is possible to transmit immediately the following

data bytes without sending the IC address or sub-

address. This can be useful to reinitialize all the

controls very quickly (flash manner). This proce-

dure can be finished by a stop condition.

The typical values of the power supply voltages

V

and V are 12 V and 5 V respectively. Opti-

CC

DD

mum operation is obtained for V between 10.8

CC

and 13.2 V and V between 4.5 and 5.5 V.

DD

In order to avoid erratic operation of the circuit dur-

ing the transient phase of VCC switching on, or off,

the value of V is monitored: if V is less than

CC

The circuit has 18 adjustment capabilities: 3 for the

horizontal part, 4 for the vertical, 3 for the E/W cor-

rection, 2 for the dynamic horizontal phase control,

2 for the vertical and horizontal Moiré options, 3 for

the horizontal and the vertical dynamic focus and 1

for the B+ reference adjustment.

7.5 V typ., the outputs of the circuit are inhibited.

Similarly, before V reaches 4 V, all the I²C reg-

DD

ister are reset to their default value (see I²C Bus

Address Table).

In order to have very good power supply rejection,

the circuit is internally supplied by several voltage

references (typ. value: 8.2 V). Two of these volt-

age references are externally accessible, one for

the vertical and one for the horizontal part. They

18 bits are also dedicated to several controls (ON/

OFF, Horizontal Forced Frequency, Sync Priority,

Detection Refresh and XRAY reset).

1.4 Read Mode

can be used to bias external circuitry (if I

is

LOAD

less than 5 mA). It is necessary to filter the voltage

references by external capacitors connected to the

respective grounds, in order to minimize the noise

and consequently the “jitter” on vertical and hori-

zontal output signals.

During the read mode the second byte transmits

the reply information.

The reply byte contains the horizontal and vertical

lock/unlock status, the XRAY activation status,

and the horizontal and vertical polarity detection. It

also contains the sync detection status which is

used by the MCU to assign the sync priority. A

stop condition always stops all the activities of the

bus decoder and switches to high impedance both

the data and clock line (SDA and SCL).

1.2 I²C Control

2

STV6886 belongs to the I C-controlled device

family. Instead of being controlled by DC voltages

on dedicated control pins, each adjustment can be

done via the I²C Interface.

2

See I C Bus Address Table.

The I C bus is a serial bus with a clock and a data

input. The general function and the bus protocol

are specified in the Philips-bus data sheets.

1.5 Sync Processor

The internal sync processor allows the STV6886

to accept:

The inputs (Data and Clock) are comparators with

a 2.2 V threshold at 5 V supply. Spikes of up to 50

ns are filtered by an integrator and the maximum

clock speed is limited to 400 kHz.

– separated horizontal & vertical TTL-compatible

sync signal

– composite horizontal & vertical TTL-compatible

sync signal

The data line (SDA) can receive or transmit data.

In read-mode the IC sends reply information

(1 byte) to the micro-processor.

1.6 Sync Identification Status

The MCU can read (address read mode: 8D) the

status register via the I C bus, and then select the

sync priority depending on this status.

The bus protocol prescribes a full-byte transmis-

sion in all cases. The first byte after the start con-

dition is used to transmit the IC-address (hexa 8C

for write, 8D for read).

2

Among other data this register indicates the pres-

ence of sync pulses on H/HVIN, VSYNCIN and

(when 12 V is supplied) whether a Vext has been

extracted from H/HVIN. Both horizontal and verti-

cal sync are detected even if only 5 V is supplied.

1.3 Write Mode

In write mode the second byte is the subaddress of

the selected function to adjust (or controls to af-

fect) and the third byte the corresponding data

byte. It is possible to send more than one data byte

to the IC. If after the third byte no stop or start con-

23/43

STV6886

In order to choose the right sync priority the MCU

may proceed as follows (see I C Bus Address Ta-

ble):

ing horizontal sync. Its level goes to low when

locked. This information is also available on pin 3 if

sub-address 02 D8 is equal to 1. When PLL1 is un-

locked, pin 3 output voltage becomes higher than

6V. When it is locked, the HMoiré waveform is

available on pin 3 (max voltage: 3V).

2

– refresh the status register,

– wait at least for 20ms (Max. vertical period),

– read the status register.

Sync priority choice should be :

2 HORIZONTAL PART

Sync

Vextd H/V

V

det

priority

Subaddress

03 (D8)

Comment

Sync type

2.1 Internal Input Conditions

et

det

A digital signal (horizontal sync pulse or TTL com-

posite) is sent by the sync processor to the hori-

zontal input. It may be positive or negative (see

Figure 5).

No

Yes

No

1

Separated H&V

Composite TTL

H&V

Yes

0

Using internal integration, both signals are recog-

nized if Z/T < 25%. Synchronization takes place on

the leading edge of the internal sync signal.

Of course, when the choice is made, we can re-

fresh the sync detections and verify that the ex-

tracted Vsync is present and that no sync type

change has occurred. The sync processor also

gives sync polarity information.

The minimum value of Z is 0.7 µs.

Another integration is able to extract the vertical

pulse from composite sync if the duty cycle is high-

er than 25% (typically d = 35%),

1.7 IC status

The IC can inform the MCU about the 1st horizon-

tal PLL and vertical section status (locked or not)

and about the XRAY protection (activated or

not).Resetting the XRAY internal latch can be

(see Figure 6).

Figure 5.

done either by decreasing the V supply or di-

CC

2

rectly resetting it via the I C interface.

1.8 Sync Inputs

Both H/HVIN and VSYNCIN inputs are TTL com-

patible triggers with hysteresis to avoid erratic de-

tection. Both inputs include a pull up resistor con-

nected to V

.

DD

1.9 Sync Processor Output

The sync processor indicates on bit D8 of the sta-

tus register whether 1st PLL is locked to an incom-

Figure 6.

CSync

Integ.

d

VSyn

The last feature performed is the removal of these

equalization pulses which fall in the middle of a

line, to avoid parasitic pulses on the phase compa-

rator (which would be disturbed by missing or ex-

traneous pulses). This last feature is switched on/

off by sub-address 0F D8. By default [0], equaliza-

tion pulses will not be removed.

24/43

STV6886

2.2 PLL1

Figure 7.

The PLL1 consists of a phase comparator, an ex-

ternal filter and a voltage-controlled oscillator

(VCO).The phase comparator is a “phase/frequen-

cy” type designed in CMOS technology. This kind

of phase detector avoids locking on wrong fre-

quencies. It is followed by a “charge pump”, com-

posed of two current sources : sunk and sourced

(typically I =1 mA when locked and I = 140 µA

when unlocked). This difference between lock/un-

lock allows smooth catching of the horizontal fre-

quency by PLL1. This effect is reinforced by an in-

ternal original slow down system when PLL1 is

locked, avoiding the horizontal frequency chang-

ing too quickly. The dynamic behavior of PLL1 is

fixed by an external filter which integrates the cur-

rent of the charge pump. A “CRC” filter is generally

used (see Figure 7 on page 25).

PLL1F

7

1.8kΩ

10nF

The PLL1 is internally inhibited during extracted

vertical sync (if any) to avoid taking in account

missing pulses or wrong pulses on phase compa-

rator. Inhibition is obtained by stopping high and

low signals at the input of the charge pump block

(see Figure 8 on page 25).

Figure 8.

Lock/Unlock

Status

Extracted

VSync

PLL1F R0 C0

7

6

5

LOCKDET

PLL

INHIBITION

High

INPUT

INTERFACE

CHARGE

PUMP

1

VCO

OSC

COMP1

H/HVIN

Low

HPOSITION

Extracted

VSync

2

I C

HPOS

Adj.

PHASE

ADJUST

Figure 9.

I

0

I

2

0

6.4V

1.6V

RS

FLIP FLOP

PLL1F

7

(Loop Filter)

4 I

6

0

(1.4V<V <4.9V)

7

6.4V

1.6V

5

R0

C0

0

0.875 T

H

25/43

STV6886

The VCO uses an external RC network. It delivers

a linear sawtooth obtained by the charge and the

discharge of the capacitor, with a current propor-

tional to the current in the resistor. The typical

thresholds of the sawtooth are 1.6 V and 6.4 V.

Figure 11. PLL2 Timing Diagram

HOsc

7/8T

1/8 T

H

Sawtooth

H

The control voltage of the VCO is between 1.4 V

and 4.9 V (see Figure 9). The theoretical frequen-

cy range of this VCO is in the ratio of 1 to 3.5. The

effective frequency range has to be smaller due to

clamp intervention on the filter lowest value.

6.4V

4.0V

The sync frequency must always be higher than

the freerunning frequency. For example, when us-

ing a sync range between 25 kHz and 80 kHz, the

suggested free running frequency is 22 kHz.

1.6V

Flyback

PLL1 ensures the coincidence between the lead-

ing edge of the sync signal and a phase reference

REF1 obtained by comparison between the saw-

tooth of the VCO and an internal DC voltage Vb.

Vb is I C adjustable between 2.9 V and 4.2 V (cor-

responding to ±10 %) (see Figure 10).

Internally

shaped Flyback

2

HDrive

Ts

Duty Cycle

The STV6886 also includes a Lock/Unlock identifi-

cation block which senses in real time whether

PLL1 is locked or not on the incoming horizontal

sync signal. This information is available through

I²C, and also on pin 3 if HLock/Unlock option has

been set through Subaddress 02,D8.

The phase comparator of PLL2 is followed by a

charge pump (typical output current: 0.5 mA).

Figure 10. PLL1 Timing Diagram

The flyback input consists of an NPN transistor.

The input current must be limited to less than 5 mA

(see Figure 12).

H O

SC

Sawtooth

7/8 TH

1/8 TH

Figure 12. Flyback Input Electrical Diagram

6.4V

Ref. for H Position

Vb

(2.9V<Vb<4.2V)

1.6V

500Ω

Q1

12

HFLY

REF1

20kΩ

HSync

Phase REF1 is obtained by comparison between

the sawtooth and a DC voltage adjustable between

2.9 V and 4.2 V.

GND 0V

2

The PLL1 ensures the exact coincidence between the

The duty cycle is adjustable through I C from 30 %

to 65 %. For a safe start-up operation, the initial

duty cycle (after power-on reset) is 65% in order to

avoid having too long a conduction period of the

horizontal scanning transistor.

signal phase REF and HSYNC. A ±10% T phase

H

adjustment is possible around the 3.5V point.

2.3 PLL2

The maximum storage time (Ts Max.) is (0.44T -

H

PLL2 ensures a constant position of the shaped

flyback signal in comparison with the sawtooth of

the VCO, taking into account the saturation time

Ts (see Figure 11 on page 26)

T

/2). Typically, T /T is around 20 %, at

maximum frequency, which means that Ts max is

around 34 % of T .

FLY

H

26/43

STV6886

2.4 Output Section

Obviously the power scanning transistor cannot be

directly driven by the integrated circuit. An inter-

face has to be added between the circuit and the

power transistor either of bipolar or MOS type.

The H-drive signal is sent to the output through a

shaping stage which also controls the H-drive duty

2

cycle (I C adjustable) (see Figure 11). In order to

secure the scanning power part operation, the out-

put is inhibited in the following cases:

2.5 X-RAY Protection

The X-Ray protection is activated by application of

a high level on the X-Ray input (more than 8.2V on

Pin 25). It inhibits the H-Drive and B+ outputs.

– when V or V are too low

CC

DD

– when the XRAY protection is activated

– during the Horizontal flyback

This activation is internally delayed by 2 lines to

avoid erratic detection when short parasitics are

present .

2

– when the HDrive I C bit control is off.

The output stage consists of a NPN bipolar tran-

sistor. Only the collector is accessible (see

Figure 13).

This protection is latched; it may be reset either by

CC

page 28).

2

V

switch-off or by I C (see Figure 14 on

Figure 13.

2.6 Horizontal and Vertical Dynamic Focus

For dynamic focus adjustment, the STV6886 deliv-

ers the sum of two signals on pin 10:

– a parabolic waveform at horizontal frequency,

– a parabolic waveform at vertical frequency.

The horizontal parabola comes from a sawtooth in

phase advance with flyback pulse middle. The

phase advance versus horizontal flyback middle is

kept constant versus frequency (about 1µs). Sym-

2

metry and amplitude are I C adjustable (see

Figure 15 on page 28).

The vertical parabola is tracked with VPOS and

VAMP. Its amplitude can be adjusted. It is also af-

fected by S and C corrections.

This output stage is intended for “reverse” base

control, where setting the output NPN in off-state

will control the power scanning transistor in off-

state.

This positive signal once amplified is to be sent to

the CRT focusing grids.

Because the DC/DC converter is triggered by the

HFocus sawtooth, it is recommended to connect a

capacitor to pin 9, even if HFocus is not needed.

The capacitor value is critical only if Focus is used.

The maximum output current is 30mA, and the

corresponding voltage drop of the output V

0.4V Max.

is

CEsat

27/43

STV6886

Figure 14. Safety Functions Block Diagram

Figure 15. Phase of HFocus Parabola

Flyback pulse

1 µs

0.4 µs

H Focus sawtooth

0.6 µs

127

64

2

I C Code

(decimal)

H Focus parabola

45

0

0.475T

H

0.16T

H

0.16T

H

28/43

STV6886

2.7 Horizontal Moiré Output

If a synchronization pulse is applied, the internal

oscillator is synchronized immediately but with

wrong amplitude. An internal correction then ad-

justs it in less than half a second. The top value of

the ramp (Pin 22) is sampled on the AGC capaci-

tor (Pin 20) at each clock pulse and a transcon-

ductance amplifier modifies the charge current of

the capacitor so as to adjust the amplitude to the

right value.

The Horizontal Moiré output is intended to correct

a beat between the horizontal video pixel period

and the CRT pixel width.

The Moiré signal is a combination of the horizontal

and vertical frequency signals.

To achieve a Moiré cancellation, the Moiré output

has to be connected so as to modulate the hori-

zontal position. We recommend introducing this

“Horizontal Controlled Jitter” on the ground side of

PLL2 capacitor where this “controlled jitter” will di-

rectly affect the horizontal position.

The Read Status register provides the vertical

Lock-Unlock and the vertical sync polarity informa-

tion.

We recommend to use an AGC capacitor with low

leakage current. A value lower than 100nA is man-

datory.

2

The amplitude of the signal is I C adjustable. The

H-Moiré frequency can be chosen via the I C.

2

If H Scanning and EHT are separated, bit D8 in

subaddress 11 should be set to 0. If H Scanning

and EHT are combined, setting this bit to 1 will pro-

vide a better screen aspect.

A good stability of the internal closed loop is

reached with a 470nF ± 5% capacitor value on Pin

20 (VAGC).

2

3.2 I C Control Adjustments

The H-Moiré output is combined with the PLL1

horizontal unlock output.

S and C correction shapes can then be added to

this ramp. These frequency-independent S and C

corrections are generated internally. Their ampli-

If HMoiré/HLock is selected (bit 02D8 to 1):

2

tudes are adjustable by their respective I C regis-

– when PLL1 is unlocked, pin 3 output voltage

goes above 6V.

ters. They can also be inhibited by their select bits.

Finally, the amplitude of this S and C corrected

ramp can be adjusted by the vertical ramp ampli-

tude control register.

– when PLL1 is locked, the HMoiré signal (up to

2.2V peak) is present on pin 3.

If HMoiré/HLock is not selected, pin 3 can be used

as a 0....2.5V DAC.

The adjusted ramp is available on Pin 23 (V

drive an external power stage.

) to

OUT

The gain of this stage can be adjusted (± 25%) de-

pending on its register value.

3 VERTICAL PART

The mean value of this ramp is driven by its own

3.1 Function

2

I C register (vertical position). Its value is

When the synchronization pulse is not present, an

internal current source sets the free-running fre-

quency. For an external capacitor C

.

VPOS = 7/16 V

± 400mV.

REF-V

Usually V

is sent through a resistive divider to

= 150nF,

OUT

OSC

the inverting input of the booster. Since VPOS de-

rives from V , the bias voltage sent to the non-

the typical free running frequency is 100Hz.

REF-V

The typical free running frequency can be calculat-

inverting input of the booster should also derive

from V to optimize the accuracy (see Appli-

ed by:

1

REF-V

.

-5 .

fo(Hz) = 1.5 10

cation Diagram).

C

OSC

3.3 Vertical Moiré

A negative or positive TTL level pulse applied on

Pin 2 (VSYNC) as well as a TTL composite sync

on Pin 1 can synchronize the ramp in the range

[fmin, fmax] (See Figure 16 on page 30). This fre-

quency range depends on the external capacitor

connected on Pin 22. A 150nF (± 5%) capacitor is

recommended for 50Hz to 120Hz applications.

By using the vertical Moiré, VPOS can be modulat-

ed from frame to frame. This function is intended

to cancel the fringes which appear when the line to

line interval is very close to the CRT vertical pitch.

The amplitude of the modulation is controlled by

register VMOIRE on sub-address 0C and can be

switched-off via the control bit D8.

29/43

STV6886

Figure 16. AGC Loop Block Diagram

3.4 Basic Equations

3.5 Geometric Corrections

In first approximation, the amplitude of the ramp

The principle is represented in Figure 17 on

page 31.

on Pin 23 (VOUT) is:

.

V

- VPOS = (V

- V

) (1 + 0.3 (V

))

Starting from the vertical ramp, a parabola-shaped

current is generated for E/W correction (also

known as Pin Cushion correction), dynamic hori-

zontal phase control correction, and vertical dy-

namic focus correction.

OUT

OSC

DCMID

AMP

where:

V

= 7/16 V

(middle value of the ramp

REF

DCMID

on Pin 22, typically 3.6V)

V

= V (ramp with fixed amplitude)

OSC

22

The parabola generator is made by an analog mul-

tiplier, the output current of which is equal to:

= -1 for minimum vertical amplitude regis-

AMP

.

2

ter value and +1 for maximum

DI = k (V

- V

)

OUT

DCMID

VPOS is calculated by:

where V

is the vertical output ramp (typically

is 3.6V

OUT

between 2 and 5V) and V

VPOS = V

+ 0.4 V

P

DCMID

(for V

= 8.2V). The VOUT sawtooth is typical-

REF-V

where V = -1 for minimum vertical position reg-

P

ly centered on 3.6V. By changing the vertical posi-

ister value and +1 for maximum.

tion, the sawtooth shifts by ±0.4V.

The current available on Pin 22 is:

To provide good screen geometry for any end-

user adjustment, the STV6886 has the “geometry

tracking” feature which automatically adapts the

parabola shape, depending on the vertical position

and size.

3

8

.

I

=

V

x C

x f

OSC

REF

OSC

where C

f = synchronization frequency.

= capacitor connected on Pin 22 and

OSC

30/43

STV6886

Due to the large output stage voltage range (E/W

Pin Cushion, Keystone, E/W Corner), the combi-

nation of the tracking function, maximum vertical

amplitude, maximum or minimum vertical position

and maximum gain on the DAC control may lead

to output stage saturation. This must be avoided

Each of the three E/W components or the two dy-

namic horizontal phase control components may

2

be inhibited by their own I C select bit.

The E/W parabola is available on Pin 24 via an

emitter follower output stage which has to be bi-

ased by an external resistor (10kΩ to ground). Be-

ing stable in temperature, the device can be DC

coupled with external circuitry (mandatory to ob-

tain H Size control).

2

by limiting the output voltage with appropriate I C

register values.

For the E/W part and the dynamic horizontal

phase control part, a sawtooth-shaped differential

current in the following form is generated:

.

The vertical dynamic focus is combined with the

horizontal focus on Pin 10.

∆I’ = k’ (V

- V

)

OUT

DCMID

The dynamic horizontal phase control drives inter-

nally the H-position, moving the HFLY position on

Then ∆I and ∆I’ are added and converted into volt-

age for the E/W part.

the horizontal sawtooth in the range of ± 2.8 %T

both for side pin balance and parallelogram.

H

Figure 17. Geometric Corrections Principle

2

3.6 E/W

EWOUT = EW + K1 (V

K1 is adjustable by the keystone I C register.

2

- V ) +

DCMID

K2 is adjustable by the E/W amplitude I C register.

DC

OUT

2

4

K2 (V

- V

) + K3 (V

- V )

2

OUT

DCMID

OUT

DCMID

K3 is adjustable by the E/W corner I C register.

31/43

STV6886

3.7 Dynamic Horizontal Phase Control

4.2 Step-down Configuration

2

I

= K4 (V

- V

) + K5 (V

- V

2

)

In step-down configuration, the I

information

OUT

DCMID

OUT

DCMID

SENSE

is not used any more and therefore not sent to the

Pin16. This configuration is selected by connect-

ing this Pin16 to a DC voltage higher than 6V (for

K4 is adjustable by the parallelogram I C register.

2

K5 is adjustable by the side pin balance I C regis-

ter.

example V

).

REF-V

Instead of I

waveform the H-Focus Saw-

SENSE

tooth is used for comparison with the amplified er-

ror voltage. For that reason, the Step-down config-

uration can operate only if the H-Focus capacitor

is connected.

4 DC/DC CONVERTER PART

This unit controls the switch-mode DC/DC con-

verter. It converts a DC constant voltage into the

B+ voltage (roughly proportional to the horizontal

frequency) necessary for the horizontal scanning.

Operating Description

– The power MOS is switched ON as for the step-

up configuration.

This DC/DC converter can be configured either in

step-up or step-down mode. In both cases it oper-

ates very similarly to the well known UC3842.

– Thefeedback to the error amplifier is done as for

the step-up configuration.

4.1 Step-up Configuration

– The power MOS is switched OFF when the HFO-

CUSCAP voltage gets higher than the error am-

plifier output voltage.

Operating Description

– The power MOS is switched ON during the fly-

back (at the beginning of the positive slope of the

horizontal focus sawtooth).

Main Features

– Switching synchronized on the horizontal fre-

quency,

– The power MOS is switched OFF when its cur-

rent reaches a predetermined value. For this pur-

pose, a sense resistor is inserted in its source.

The voltage on this resistor is sent to Pin16

– B+ voltage always lower than the DC source,

– No current limitation.

(I

).

SENSE

4.3 Step-up and Step-down Configuration

Comparison

– The feedback (coming either from the EHV or

from the flyback) is divided to a voltage close to

5.0V and compared to the internal 5.0V refer-

In step-down configuration the control signal is in-

verted compared with the step-up mode.This, for

the following reason:

ence (I

). The difference is amplified by an

VREF

error amplifier, the output of which controls the

power MOS switch-off current.

– In step-up mode, the switch is a N-channel MOS

referenced to ground and made conductive by a

high level on its gate.

Main Features

– Switching synchronized on the horizontal fre-

quency,

– In step-down, a high-side switch is necessary. It

can be either a P- or a N-channel MOS.

– B+ voltage always higher than the DC source,

– Current limited on a pulse-by-pulse basis.

The DC/DC converter is disabled:

• For a P-channel MOS, the gate is controlled

directly from Pin 28 through a capacitor (this

allows to spare a Transformer). In this case,

a negative-going pulse is needed to make

the MOS conductive. Therefore it is

necessary to invert the control signal.

– when V or V are too low,

CC

DD

– when X-Ray protection is latched,

2

• For a N-channel MOS, a transformer is

needed to control the gate. The polarity of

the transformer can be easily adapted to the

negative-going control pulse.

– directly through I C bus.

When disabled, BOUT is driven to GND by a

0.5mA current source. This feature allows to im-

plement externally a soft start circuit.

32/43

STV6886

Figure 18. DC/DC Converter (represented: Step-Up configuration)

DAC

7bits

HDF Discharge

400ns

12V

Horizontal Dynamic

Focus Sawtooth

+

± I

adjust

A

BOUT

28

8.2V

C1

-

down

up

+

5V ±20%

85 dB

+

-

1/3

down

up

S

R

-

C2

Q

B

1.3V

+

C3

Inhibit.

1.3V

-

+

Command step-up/down

6V

C4

-

I

SENSE

REGIN

COMP

STV6886

15

14

16

1MΩ

L

22kΩ

EHV

Feedback

10nF

V

B+

33/43

STV6886

INTERNAL SCHEMATICS

Figure 19.

Figure 22.

12V

HREF

13

5V

CO

Pins 1-2

H/HVIN

5

200Ω

VSYNCIN

Figure 20.

Figure 23.

HREF

13

HREF

13

12V

6

R0

3

HMOIRE/HLOCK

Figure 21.

Figure 24.

12V

HREF

13

7

PLL1F

PLL2

4

34/43

STV6886

Figure 25.

Figure 28.

HREF

13

HREF

12V

8

HPOSITION

12

HFLY

Figure 26.

Figure 29.

HREF

13

12V

HFOCUS

CAP

9

14

COMP

Figure 27.

Figure 30.

12V

15

REGIN

10

HFOCUS

35/43

STV6886

Figure 31.

Figure 34.

12V

22

VCAP

I

16

SENSE

Figure 32.

Figure 35.

12V

BREATH 18

VOUT 23

Figure 33.

Figure 36.

12V

EWOUT 24

20

VAGCCAP

36/43

STV6886

Figure 37.

12V

XRAY 25

Figure 38.

V12

HOUT-BOUT

Pins 26-28

Figure 39.

Pins 30-31

SDA-SCL

37/43

STV6886

Figure 40. Demonstration Board

J16 J15

J14

1

2

3

4

C39

22pF

+5V

IC4

STV6886

L1

22µH

+12V

R39

4.7kΩ

R29

4.7kΩ 100Ω

R42

TP1

J11

TP13

C40

CC2

10µF

32

H/HVIN

R41

100Ω

22pF

1

2

3

4

5

6

+5V

PC1

47kΩ

C32

100nF

C30

100µF

TP16

SCL

SDA

TP17

J12

CC3

C45

10µF

VSYNCIN SDA

R49

22kΩ

31

47pF

13 14 15 16 17 18 19 20 21 22 23 24

-12V

TP10

CC1

100nF

16 15 14 13 12 11 10

9

HMOIRE/

HLOCK

SCL 30

+5V

C7 22nF

PLL2C

C0

29

+12V

V_CC

C6

100nF

C5

100µF

12 11 10

X1

9

8

7

6

5

4

3

2

1

C28

820pF 5%

1

2

3

4

5

6

7

8

TILT

J13

R43

10kΩ

CC4

47pF

B+OUT28

+12V

R23

6.49k

8MHz

+12V

R56

560kΩ

C42

1µF

R30

10kΩ

Ω

1%

C37

33pF

C43 +5V

47µF

PC2

47kΩ

C38

33pF

R10

10kΩ

C25

33pF

27

GND

R0

R53

1kΩ

D2

1N4148

R35

10kΩ

C13 10nF

C48

10µF

+12V

HOUT

PLL1F

7

8

9

HOUT 26

E/W POWER STAGE

C31 4.7µF R36 1.8kΩ

C49

100nF

HOUT

+12V

R37

27kΩ

R34

C36

1µF

R15

1kΩ

R17

43kΩ

R7 10kΩ

C22

33pF

R8

10kΩ

H

25

24

XRAY

R38

R19

J8

C17 1µF

POSITION

2.2Ω

J1

270kΩ

1kΩ

3W

R45 33kΩ

Q1

Q2

HFOCUS-

EWOUT

BC557 BC557

HFLY

J9

CAP

C11 220pF

C34

820pF 5%

R25

1kΩ

E/W

FOCUS

OUT

10

VOUT 23

V_CAP22

V_REF21

Q3

TIP122

R9

470Ω

R33

4.7kΩ

R18

10kΩ

+12V

DYN

FOCUS

L

R24

10kΩ

C12

47µH

R52

3.9kΩ

11 HGND

12 HFLY

150nF

C16 (*)

J19

C14

C9

J2

C3

47µF

470µF

100nF

+12V

-12V

TP3 J3

D1

1n400 1

C27

47µF

C33 HREF

100nF

1

2

C4

100nF

C15

TP6

TP7

C2

100nF

HREF

13

VAGCCAP20

VGND19

TP4

C10

100µF

35V

R2

5.6Ω

470nF

3

4

JP1

C51

100nF

J6

14 COMP

15 REGIN

CON4

C46

1nF

R40

36kΩ

R50

1

IC1

TDA817 2

C1

R3

1MΩ

R11

220Ω

0.5W

2

3

VYOKE

220nF 1.5Ω

R1

12kΩ

REGIN

18

BREATH

R57

82kΩ

C10

470µF

C8

100nF R5

5.6Ω

R51

1kΩ

J18

-12V

C41

470pF

R4

1Ω

I_SENSE

GND

16 I_SENSE

B+GND17

C47

100pF

0.5W

VERTIC AL DEFLECTION STAGE

Q4

BC557

R58

10Ω

J17

B+OUT

+12V

HOUT

Q5

BC547

R73

R75 1MΩ

10kΩ

L3

22µH

R74

10kΩ

TP8

EHT

COMP

C50

10µF

R76

47kΩ

P1

10kΩ

R77

15kΩ

C60

100nF

38/43

STV6886

Figure 41.

39/43

STV6886

Figure 42.

40/43

STV6886

PACKAGE MECHANICAL DATA

41/43

STV6886

PACKAGE MECHANICAL DATA

32 PINS - PLASTIC SHRINK

E

E1

C

Stand-off

e

B

B1

eA

eB

D

32

1

17

16

Millimeters

Dimensions

Inches

Typ.

Min.

3.556

0.508

3.048

0.356

0.762

.203

Typ.

Max.

Min.

0.140

0.020

0.120

0.014

0.030

0.008

1.080

0.390

0.300

Max.

A

A1

A2

B

3.759

5.080

0.148

0.200

3.556

0.457

1.016

0.254

27.94

10.41

8.890

1.778

10.16

4.572

0.584

1.397

0.356

28.45

11.05

9.398

0.140

0.018

0.040

0.010

1.100

0.410

0.350

0.070

0.400

0.180

0.023

0.055

0.014

1.120

0.435

0.370

B1

C

D

27.43

9.906

7.620

E

E1

e

eA

eB

L

12.70

3.810

0.500

0.150

2.540

3.048

0.100

0.120

42/43

STV6886

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no

responsibility for the consequences of use of such information nor for any infringement of patents or other

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型号：	STV6886
厂家：	ST
描述：	LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR 低成本I2C可控弯曲处理器的MultiSync显示器显示器消费电路商用集成电路偏转集成电路光电二极管监视器信息通信管理
文件：	总43页 (文件大小：486K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

STV6886 [STMICROELECTRONICS]

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