TPS43336QDAPQ1 [TI]
IC DUAL SWITCHING CONTROLLER, 600 kHz SWITCHING FREQ-MAX, PDSO38, GREEN, PLASTIC, HTSSOP-38, Switching Regulator or Controller;
| 型号： | TPS43336QDAPQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC DUAL SWITCHING CONTROLLER, 600 kHz SWITCHING FREQ-MAX, PDSO38, GREEN, PLASTIC, HTSSOP-38, Switching Regulator or Controller 开关 光电二极管 |
| 文件： | 总34页 (文件大小：1973K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS43335-Q1
TPS43336-Q1
www.ti.com
SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011
LOW IQ, SINGLE BOOST, DUAL SYNCHRONOUS BUCK
CONTROLLER
Check for Samples: TPS43335-Q1, TPS43336-Q1
1
FEATURES
•
•
•
Two Synchronous Buck Controllers
•
•
Sense Resistor or Inductor DCR Sensing
One Pre-Boost Controller
Out of Phase Switching between Buck
Channels
Input Range up to 40V, (transients up to 60V),
Operation Down to 2V when Boost is enabled
•
•
Peak Gate Drive Current 0.7 A
•
Low Power Mode IQ: 30µA (one Buck on), 35µA
(two Bucks on)
Thermally Enhanced Package – 38-Pin
HTSSOP (DAP) with PowerPadTM
•
•
•
•
Low Shutdown Current Ish < 4 µA
Buck Output Range 0.9V to 11V
Boost Output Selectable: 7V/10V/11V
•
Qualified for Automotive
APPLICATIONS
•
Automotive Start-Stop, Infotainment,
Navigation Instrument Cluster Systems
Programmable frequency and External
Synchronization Range 150kHz to 600kHz
•
Industrial/Automotive Multi-Rail DC Power
Distribution Systems and Electronic Control
Units
•
•
•
Separate Enable Inputs (ENA, ENB)
Frequency Spread Spectrum (TPS43336)
Selectable Forced Continuous Mode or
Automatic Low Power Mode at Light Loads
DESCRIPTION
The TPS43335-Q1/TPS43336-Q1 includes two current mode synchronous buck controllers and a voltage mode
boost controller. The part is ideally suited as pre-regulator stage with low Iq requirements and systems that need
to survive supply drops due to cranking events. The integrated boost controller allows the device to operate down
to 2V at the input without seeing a drop on the Buck regulator output stages. At light loads, the buck controllers
can be enabled to operate automatically in Low Power Mode consuming just 30µA of quiescent current.
The buck controllers have independent soft start capability and power good indicators. External MOSFET
protection is provided by current fold back in the buck controllers and cycle-by-cycle current limitation in the
boost controller. The switching frequency can be programmed over 150 kHz to 600 kHz or synchronized to an
external clock in the same range. Additionally, the TPS43336-Q1 offers frequency-hopping spread spectrum
operation.
spacer
VBAT
VBuckA
TPS43335-Q1/
TPS43336-Q1
VBuckB
2 V
Figure 1. Typical Application Diagram
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS43335-Q1
TPS43336-Q1
SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
TJ
OPTION
PACKAGE(2)
ORDERABLE PART NUMBER
TPS43335QDAPQ1
Frequency Hopping Spread Spectrum OFF
Frequency Hopping Spread Spectrum ON
-40ºC to 150ºC
DAP(3)
TPS43336QDAPQ1
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) The DAP package is available in tape and reel. Add the R suffix (TPS43335QDAPR, TPS43336QDAPR) to order.
space
ABSOLUTE MAXIMUM RATINGS(1)
MIN
–0.3
–0.3
–0.3
–0.7
–1.0
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–40
MAX
60
UNIT
V
Voltage
Input Voltage: VIN, VBAT
Enable Inputs: ENA, ENB
Bootstrap Inputs: CBA, CBB
Phase Inputs: PHA, PHB
60
V
68
V
60
V
Phase Inputs: PHA, PHB (for 150ns)
Feedback Inputs: FBA, FBB
Error amplifier outputs: COMPA, COMPB
High-Side MOSFET Driver: GA1-PHA, GB1-PHB
Low-Side MOSFET Drivers: GA2, GB2
Current Sense Voltage: SA1, SA2, SB1, SB2
Soft Start: SSA, SSB
V
13
13
V
V
Voltage
(Buck Function:
Buck A and Buck B)
8.8
8.8
13
V
V
V
13
V
Power Good Output: PGA, PGB
Power Good Delay: DLYAB
Switching Frequency Timing Resistor: RT
SYNC, EXTSUP
13
V
13
V
13
V
13
V
Low-Side MOSFET Driver: GC1
Error amplifier output: COMPC
Enable Input: ENC
8.8
13
V
V
Voltage
(Boost Function)
13
V
Current Limit Sense: DS
60
V
Output Voltage Select: DIV
P-Channel MOSFET Driver: GC2
P-Channel MOSFET Driver: VIN-GC2
Gate Driver Supply: VREG
Junction Temperature: TJ
8.8
60
V
V
Voltage
(PMOS Driver)
8.8
8.8
150
125
165
V
V
°C
°C
°C
kV
Temperature
Operating Temperature: TA
Storage Temperature: TS
–40
–55
Human Body Model (HBM)
Charged Device Model (CDM)
- FBA, FBB, RT, DLYAB
±2
±400
±750
±500
V
V
- VBAT, ENC, SYNC, VIN
- all other pins
Electrostatic Discharge
Ratings
Machine Model (MM)
- PGA, PGB
±150
±200
- all others
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to GND.
2
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Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): TPS43335-Q1 TPS43336-Q1
TPS43335-Q1
TPS43336-Q1
www.ti.com
SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
40
40
44
40
11
11
6
UNIT
V
Input Voltage: VIN, VBAT
Enable Inputs: ENA, ENB
Boot Inputs: CBA, CBB
4
4
V
4
V
Buck Function:
Phase Inputs: PHA, PHB
–0.6
0
V
Buck A and Buck B
Current Sense Voltage: SA1, SA2, SB1, SB2
Voltage
V
Power Good Output: PGA, PGB
Power Good Delay: DLYAB
SYNC, EXTSUP
0
V
0
V
0
9
V
Error amplifier output: COMPC
0
6
V
Enable Input: ENC
Boost Function
0
9
V
Voltage Sense: DS
40
6
V
DIV
0
28
V
(1)
Thermal Resistance Junction to Ambient, θJA
°C/W
°C/W
°C
(2)
Temperature Ratings
Thermal Resistance Junction to pad, θJC
10
Operating Temperature: TA
–40
125
(1) This assumes a JEDEC JESD 51-5 standard board with thermal vias – See Power Pad section and application note from Texas
Instruments SLMA002 for more information.
(2) This assumes junction to exposed pad.
Copyright © 2011, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Link(s): TPS43335-Q1 TPS43336-Q1
TPS43335-Q1
TPS43336-Q1
SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011
www.ti.com
MAX UNIT
DC ELECTRICAL CHARACTERISTICS
VIN = 8 V to 18 V, TJ = -40°C to 150°C (unless otherwise noted)
NO.
TEST(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
1.0
Input Supply
Boost Controller enabled, after initial start up
condition is satisfied
1.1
1.2
PT
PT
VBat
Supply Voltage
2
40
40
40
V
V
V
Input voltage required for device on initial start
up
Device Operating Range
6.5
VIN
Buck regulator operating range after initial start
up
4
VIN Falling
3.5
3.6
3.8
8.5
3.8
4
V
V
V
1.3
1.4
PT
PT
VIN UV
Buck Undervoltage Lockout
Boost unlock threshold
VIN Rising
VBAT-Off
VBAT Rising
8.2
8.8
VIN = 13V, BuckA: LPM, BuckB: off
VIN = 13V, BuckB: LPM, BuckA: off
VIN = 13V, BuckA, B: LPM
VIN = 13V, BuckA: LPM, BuckB: off
VIN = 13V, BuckB: LPM, BuckA: off
VIN = 13V, BuckA, B: LPM
Normal operation, SYNC = 5V
VIN = 13V, BuckA: CCM, BuckB: off
VIN = 13V, BuckB: CCM, BuckA: off
VIN = 13V, BuckA, B: CCM
Normal operation, SYNC = 5V
VIN = 13V, BuckA: CCM, BuckB: off
VIN = 13V, BuckB: CCM, BuckA: off
VIN = 13V, BuckA, B: CCM
BuckA, B: off, VBat = 13V
30
35
40
45
40
45
50
55
µA
µA
µA
µA
LPM Quiescent Current:
1.5
1.6
PT
PT
Iq_LPM_
TA = 25°C(2)
LPM Quiescent Current:
Iq_LPM
TA = 125°C(2)
Quiescent Current:
1.7
1.8
PT
PT
Iq_NRM
4.85
7
5.3
7.6
mA
mA
TA = 25°C(2)
Quiescent Current:
Iq_NRM
5
5.5
mA
TA = 125°C(2)
7.5
2.5
3
8
4
5
mA
µA
µA
1.9
1.10
2.0
PT
PT
Ibat_sh
Ibat_sh
Shutdown current ,TA = 25°C
Shutdown current ,TA = 125°C
BuckA, B: off, VBat = 13V
Input voltage VBAT - Undervoltage lock out
VBAT falling
VBAT rising
1.8
2.4
1.9
2.5
600
5
2
2.6
V
V
2.1
PT
VBATUV
Boost Input Undervoltage
2.2
2.3
3.0
PT
PT
UVLOHys
UVLOfilter
Hysteresis
Filter time
500
700
mV
µs
Input voltage VIN - Over voltage lock out
(based on VIN sense) Rising
Falling
45
43
1
46
44
2
47
45
3
V
V
3.1
PT
VOVLO
Overvoltage shutdown
3.2
3.3
4.0
4.1
PT
PT
OVLOHys
OVLOfilter
Hysteresis
Filter time
V
5
µs
Boost Controller
PT
PT
PT
PT
Info
Vboost7-VIN
Boost VOUT = 7V
DIV = low, VBAT = 2 V to 7 V
VBAT falling – Boost enable threshold
VBAT rising – Boost disable threshold
Hysteresis
7
8
V
V
V
V
V
V
V
V
V
7.5
8
8.5
9
Boost mode threshold
Boost VOUT = 7V
4.2
4.3
4.4
4.5
Vboost7-th
8.5
0.5
10
0.4
0.6
Vboost10-VIN
Vboost10-th
Vboost11-VIN
Boost VOUT = 10V
DIV = open, VBAT = 2 V to 10 V
VBAT falling – Boost enable threshold
VBAT rising – Boost disable threshold
Hysteresis
10.5
11
11
11.5
12
Boost mode threshold
Boost VOUT = 10V
11.5
0.5
11
0.4
0.6
Boost VOUT = 11V
DIV = VREG, VBAT = 2 V to 11 V
(1) PT = Production tested; CT = Characterization only, not production tested; Info = Information based on simulations and lab evaluation,
not production tested
(2) Quiescent current specification is non-switching current consumption without including the current in the external feedback resistor
divider.
4
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Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): TPS43335-Q1 TPS43336-Q1
TPS43335-Q1
TPS43336-Q1
www.ti.com
SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011
DC ELECTRICAL CHARACTERISTICS (continued)
VIN = 8 V to 18 V, TJ = -40°C to 150°C (unless otherwise noted)
NO.
TEST(1)
PARAMETER
TEST CONDITIONS
VBAT falling – Boost enable threshold
VBAT rising – Boost disable threshold
Hysteresis
MIN
11.5
12
TYP
12
MAX UNIT
12.5
13
V
V
V
Boost mode threshold
Boost VOUT = 11V
4.6
Info
Vboost11-th
12.5
0.5
0.4
0.6
Boost Switch current limit
4.7
4.8
PT
VDS
tDS
Current limit sensing
leading edge blanking
DS input with respect to PGNDA
0.175
0.2
0.225
V
Info
200
ns
Gate Driver for Boost Controller
4.9
Info
PT
IGC1 Peak
RDS(ON)
Gate driver peak current
Source and Sink driver
1.5
A
4.10
VREG = 5.8V, IGC1 current = 200mA
2
20
10
Ω
Gate Driver for PMOS
4.11
4.12
4.13
PT
PT
PT
RDS ON
PMOS OFF
10
5
Ω
mA
µs
IPMOS_ON
tdelay_ON
Gate current
Turn ON delay
VIN = 13.5V, Vgs = -5V
C = 10nF
10
Boost Controller Switching frequency
4.14
4.15
PT
PT
fsw-Boost
DBoost
Boost Switching Frequency
Boost duty cycle
fSW_Buck/2
90%
kHz
Error Amplifier (OTA) for Boost Converters
VBAT = 12V
VBAT = 5V
0.8
1.35
0.65
4.16
PT
GmBOOST
Forward Transconductance
mmho
0.35
5.0
5.1
Buck Controllers
PT
PT
VBuckA/B
Vref, NRM
Adjustable. output voltage range
0.9
0.792
-1%
11
0.808
+1%
V
V
Measure FBX pin
0.800
0.800
internal reference voltage in
normal mode
5.2
Info
PT
Internal tolerance on reference
Measure FBX pin
0.784
-2%
0.816
+2%
V
internal reference voltage in low
power mode
5.3
5.4
Vref, LPM
Info
Internal tolerance on reference
V sense for forward current limit in Maximum sense voltage FBx = 0.75V
CCM
PT
60
75
90
mV
(low duty cycles)
Vsense
V sense for reverse current limit in
CCM
5.5
5.6
5.7
PT
CT
Minimum sense voltage FBx = 1V
Sense voltage in foldback FBx = 0V
-65
17
-37.5
32.5
20
-23
48
mV
mV
ns
VI-Foldback
tdead
V sense for output short
shoot through delay, blanking
time
Info
CT
Info
CT
High side minimum on time
100
ns
5.8
5.9
DCNRM
DCLPM
Duty cycle
Maximum duty cycle (digitally controlled)
98.75%
Duty Cycle LPM
80%
LPM entry threshold load current
as fraction of maximum set load
current
ILPM_Entry
1%
The exit threshold is specified to be always
higher than entry threshold
5.10
Info
LPM exit threshold load current as
fraction of maximum set load
current
ILPM_Exit
10%
High Side external NMOS Gate Drivers for Buck Controller
5.11
5.12
Info
PT
IGX1_peak
RDS ON
Gate driver peak current
Source and Sink driver
0.7
0.7
A
VVREG = 5.8V, IGX1 current = 200mA
VREG = 5.8V, IGX2 current = 200mA
4
4
Ω
Low Side NMOS Gate Drivers for Buck Controller
5.13
5.14
Info
PT
IGX2_peak
RDS ON
Gate driver peak current
Source and sink driver
A
Ω
Error Amplifier (OTA) for Buck Converters
COMPA, COMPB = 0.8V,
source/sink = 5µA, Test in feedback loop
5.15
PT
PT
GmBUCK
Transconductance
0.72
50
1
1.35 mmho
5.16
6.0
IPULLUP_FBx
Pull-Up Current at FBx pins
FBx = 0V
100
200
nA
V
Digital Inputs: ENA, ENB, ENC, SYNC
PT Vih Higher threshold
6.1
VIN = 13V
1.7
Copyright © 2011, Texas Instruments Incorporated
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Product Folder Link(s): TPS43335-Q1 TPS43336-Q1
TPS43335-Q1
TPS43336-Q1
SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011
www.ti.com
MAX UNIT
DC ELECTRICAL CHARACTERISTICS (continued)
VIN = 8 V to 18 V, TJ = -40°C to 150°C (unless otherwise noted)
NO.
6.2
6.3
6.4
TEST(1)
PARAMETER
Lower threshold
Resistance
TEST CONDITIONS
MIN
TYP
PT
Vil
VIN = 13V
0.7
V
PT
Rih_SYNC
Ril_ENC
VSYNC = 5V, SYNC: pull down resistance
VENC = 5V, ENC: pull down resistance
500
500
kΩ
kΩ
PT
Resistance
VENx = 0V,
ENA, ENB: pull up current source
6.5
PT
Iil_ENx
pull-up current
0.5
2
µA
6
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Product Folder Link(s): TPS43335-Q1 TPS43336-Q1
TPS43335-Q1
TPS43336-Q1
www.ti.com
SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011
DC ELECTRICAL CHARACTERISTICS (continued)
VIN = 8 V to 18 V, TJ = -40°C to 150°C (unless otherwise noted)
NO.
TEST(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
7.0
Boost Output Voltage: DIV
Vreg-
0.2
7.1
PT
Vih_DIV
Higher threshold
VREG = 5.8V
V
7.2
7.3
8.0
8.1
8.2
8.3
8.4
8.5
9.0
PT
PT
Vil_DIV
Lower threshold
open
0.2
V
V
Voz_DIV
floating
Vreg/2
Switching Parameter – Buck DC-DC Controllers
PT
PT
PT
PT
PT
fSW_Buck
fSW_Buck
fSW_adj
fSYNC
Buck switching frequency
Buck switching frequency
Buck adjustable range
Buck synch. range
RT pin: GND
360
360
150
150
400
400
440
440
600
600
kHz
kHz
kHz
kHz
RT pin: 60kΩ external resistor
RT pin: using external resistor
External clock input
fSS
Spread Spectrum spreading
TPS43336-Q1 only
5%
Internal Gate Driver Supply
Internal regulated supply
Load Regulation
VIN = 8V to 18V, EXTSUP = 0V, SYNC = high
5.5
7.2
5.8V
0.2%
7.5
6.1
1%
7.8
1
V
9.1
PT
VREG
IVREG = 0mA to 100mA, EXTSUP = 0V,
SYNC = high
Internal Regulated supply
Load Regulation
EXTSUP = 8.5V
V
9.2
9.3
PT
PT
VREG-EXTSUP
IEXTSUP = 0mA to 125mA, SYNC = High
EXTSUP = 8.5V to 13V
0.2
%
VEXTSUP-
IVREG = 0mA to 100mA ,
EXTSUP ramping positive
Switch over voltage
4.4
4.6
4.8
V
VREG
9.4
9.5
PT
PT
VEXTSUP-Hys
IREG-Limit
Switch over hysteresis
Current Limit on VREG
150
100
250
400
mV
mA
EXTSUP = 0V, normal mode as well as LPM
IREG_EXTSUP- Current Limit on VREG when
IVREG = 0mA to 100mA,
EXTSUP = 8.5V, SYNC = High
9.6
PT
125
400
mA
using EXTSUP
Limit
10.0
10.1
11.0
11.1
12.0
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Soft Start
PT
ISSx
Soft Start source current
SSA and SSB = 0V
0.75
1
1.25
µA
Oscillator (RT)
PT
VRT
Oscillator reference voltage
1.2
V
Power Good / Delay
PT
PT
PT
PT
PT
PT
PT
PGpullup
PGth1
Pullup for A and B
Power Good Threshold
Hysteresis
internal pullup to Sx2
FBx falling
50
-7
kΩ
-5
-9
%
PGhys
PGdrop
2%
Voltage drop
IPGA = 5mA
450
100
1
mV
mV
µA
µs
IPGA = 1mA
PGleak
tdeglitch
Leakage
VSx2 = VPGx = 13V
Power Good deglitch
Deglitch Time
2
16
External capacitor = 1nF
VBUCKX < PGth1
12.8
PT
tdelay
Reset Delay
1
ms
12.9
12.10
12.11
13.0
PT
PT
PT
tdelay_fix
Fixed Reset Delay
No external capacitor, pin open
20
40
40
50
50
50
µs
µA
µA
Ioh
Iil
Activate current source
Activate current sink
Current to charge external capacitor
Current to discharge external capacitor
30
30
Over Temperature Protection
13.1
CT
CT
Tshutdown
Thys
shutdown threshold
Junction temperature
Hysteresis
150
165
15
°C
°C
13.2
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Product Folder Link(s): TPS43335-Q1 TPS43336-Q1
TPS43335-Q1
TPS43336-Q1
SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011
www.ti.com
DEVICE INFORMATION
DAP PACKAGE
(TOP VIEW)
1
2
3
4
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VBAT
DS
VIN
EXTSUP
DIV
GC1
GC2
VREG
CBB
5
6
7
8
CBA
GA1
GB1
PHA
PHB
GA2
GB2
9
PGNDA
SA1
PGNDB
SB1
10
11
SA2
SB2
12
13
14
15
FBA
FBB
COMPA
SSA
COMPB
SSB
PGA
ENA
PGB
16
17
18
AGND
RT
ENB
COMPC
ENC
DLYAB
SYNC
19
20
PIN FUNCTIONS
NO.
NAME
I/O
DESCRIPTION
Battery input sense for the boost controller. If the boost controller is enabled and the voltage at VBAT falls below
the boost threshold, the device will activate the boost controller and regulate the voltage at VIN to the
programmed boost output voltage.
1
VBAT
I
This input monitors the voltage on the external Boost converter low-side MOSFET for over current protection.
Alternatively, it can be connected to a sense resistor between the source of the low-side MOSFET and ground via
a filter network for better noise immunity.
2
3
4
DS
I
An external low-side N-channel MOSFET for the boost regulator can be driven from this output. This output
provides high peak currents to drive capacitive loads. The voltage swing on this pin is provided by VREG.
GC1
GC2
O
O
A floating output drive to control the external P-channel MOSFET is available at this pin. This MOSFET can be
used to bypass the boost rectifier diode or a reverse protection diode when the boost is not switching or disabled,
and thus reduce power losses.
A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate drive circuitry in the
buck controller BUCK A. When the buck is in a dropout condition, the device automatically reduces the duty cycle
of the high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to re-charge.
5
6
CBA
GA1
I
External high-side N-channel MOSFET for the buck regulator BUCK A can be driven from these output. The
output provides high peak currents to drive capacitive loads. The gate drive is referred to a floating ground
reference provided by the PHA and has a voltage swing provided by CBA.
O
Switching terminal of the buck regulator BUCK A, providing a floating ground reference for the high-side MOSFET
gate driver circuitry and is used to sense current reversal in the inductor when discontinuous mode operation is
desired.
7
8
PHA
GA2
O
O
External low-side N-channel MOSFET for the buck regulator BUCK A can be driven from this output. The output
provides high peak currents to drive capacitive loads. The voltage swing on this pin is provided by VREG.
9
PGNDA
SA1
O
I
Power ground connection to the source of the low-side N-channel MOSFETs of BUCK A.
10
High Impedance differential voltage inputs from the current sense element (sense resistor or inductor DCR) for
each buck controller. The current sense element should be chosen to set the maximum current through the
inductor based on the current limit threshold (subject to tolerances) and considering the typical characteristics
across duty cycle and VIN. (SA1 positive node, SA2 negative node).
11
SA2
I
8
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PIN FUNCTIONS (continued)
NO.
NAME
I/O
DESCRIPTION
Feedback voltage pin for BUCK A. The buck controller regulates the feedback voltage to the internal reference of
0.8V. A suitable resistor divider network between the buck output and the feedback pin sets the desired output
voltage.
12
FBA
I
Error amplifier output of BUCK A and compensation node for voltage loop stability. The voltage at this node sets
the target for the peak current through the respective inductor. This voltage is clamped on the upper and lower
ends to provide current limit protection for the external MOSFETs.
13
14
COMPA
O
O
Soft-start or tracking input for the buck controller BUCK A. The buck controller regulate the FBA voltage to the
lower of 0.8V or the SSA pin voltage. An internal pull-up current source of 1µA is present at the pin and an
appropriate capacitor connected here can be used to set the soft-start ramp interval. A resistor divider connected
to another supply can also be used to provide a tracking input to this pin.
SSA
Open drain power good indicator pin for BUCK A. An internal power good comparator monitors the voltage at the
feedback pin and pull this output low when the output voltage falls below 93% of the set value, or if either Vin or
Vbat drops below their respective undervoltage threshold.
15
16
PGA
ENA
O
I
Enable inputs for BUCK A (active high with an internal pull up current source). An input voltage higher than 1.5V
enables the controller while an input voltage lower than 0.7V disables the controller. When both ENA and ENB are
low, the device is shut down and consumes less than 4µA of current.
Enable inputs for BUCK B (active high with an internal pull up current source). An input voltage higher than 1.5V
enables the controller while an input voltage lower than 0.7V disables the controller. When both ENA and ENB are
low, the device is shut down and consumes less than 4µA of current.
17
18
19
ENB
COMPC
ENC
I
O
I
Error amplifier output and loop compensation node of the boost regulator.
This input enables and disables the boost regulator. An input voltage higher than 1.5V enables the controller.
Voltages lower than 0.7V disable the controller. When enabled, the controller will start switching as soon as VBAT
falls below the boost threshold depending upon the programmed output voltage.
If an external clock is present on this pin the device detects it and the internal PLL locks on to the external clock.
This overrides the internal oscillator frequency. The device can synchronize to frequencies from 150 kHz to 600
kHz. A high logic level on this pin ensures forced continuous mode operation of the buck controllers and inhibits
transition to low power mode. An open or low allows discontinuous mode operation and entry into low power
mode at light loads. On the TPS43336-Q1, a high level enables frequency-hopping spread spectrum while an
open or a low level disables it.
20
21
SYNC
I
The capacitor at the DLYAB pin sets the power good delay interval used to de-glitch the outputs of the power
good comparators. When this pin is left open, the power good delay is set to an internal default value of 20µsec
typical.
DLYAB
O
The operating switching frequency of the buck and boost controllers is set by connecting a resistor to ground on
this pin. A short circuit to ground on this pin defaults operation to 400 kHz for the buck controllers and 200 kHz for
the boost controller.
22
23
24
RT
O
O
O
AGND
PGB
Analog Ground Reference
Open drain power good indicator pin for BUCK B. An internal power good comparator monitors the voltage at the
feedback pin and pull this output low when the output voltage falls below 93% of the set value, or if either Vin or
Vbat drops below their respective undervoltage threshold.
Soft-start or tracking input for the buck controller BUCK B. The buck controller regulate the FBB voltage to the
lower of 0.8V or the SSB pin voltage. An internal pull-up current source of 1µA is present at the pin and an
appropriate capacitor connected here can be used to set the soft-start ramp interval. A resistor divider connected
to another supply can also be used to provide a tracking input to this pin.
25
SSB
O
Error amplifier output of BUCK B and compensation node for voltage loop stability. The voltage at this node sets
the target for the peak current through the respective inductor. This voltage is clamped on the upper and lower
ends to provide current limit protection for the external MOSFETs.
26
27
COMPB
FBB
O
I
Feedback voltage pin for BUCK B. The buck controller regulates the feedback voltage to the internal reference of
0.8V. A suitable resistor divider network between the buck output and the feedback pin sets the desired output
voltage.
28
29
SB2
SB1
I
I
High Impedance differential voltage inputs from the current sense element (sense resistor or inductor DCR) for
each buck controller. The current sense element should be chosen to set the maximum current through the
inductor based on the current limit threshold (subject to tolerances) and considering the typical characteristics
across duty cycle and VIN. (SB1 positive node, SB2 negative node).
30
31
PGNDB
GB2
O
O
Power ground connection to the source of the low-side N-channel MOSFETs of BUCK B.
External low-side N-channel MOSFETs for the buck regulator BUCK B can be driven from this output. The output
provides high peak currents to drive capacitive loads. The voltage swing on this pin is provided by VREG.
Switching terminal of the buck regulator BUCK B, providing a floating ground reference for the high-side MOSFET
gate driver circuitry and is used to sense current reversal in the inductor when discontinuous mode operation is
desired.
32
PHB
O
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PIN FUNCTIONS (continued)
NO.
NAME
I/O
DESCRIPTION
External high-side N-channel MOSFET for the buck regulator BUCK B can be driven from these output. The
output provides high peak currents to drive capacitive loads. The gate drive is referred to a floating ground
reference provided by the PHB and has a voltage swing provided by CBB.
33
GB1
O
A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate drive circuitry in the
buck controller BUCK B. When the buck is in a dropout condition, the device automatically reduces the duty cycle
of the high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to re-charge.
34
35
CBB
I
An external capacitor on this pin is required to provide a regulated supply for the gate drivers of the buck and
boost controllers. A capacitance in the order of 4.7uF is recommended. The regulator can be used such that it is
either powered from VIN or EXTSUP. This pin has a current limit protection and should not be used to drive any
other loads.
VREG
O
The status of this pin defines the output voltage of the boost regulator. A high input regulates the Boost converter
at 11V, a low input sets the value at 7V and a floating pin sets 10V.
36
37
38
DIV
EXTSUP
VIN
I
I
I
EXTSUP can be used to supply the VREG regulator from one of the TPS43335-Q1/TPS43336-Q1 buck regulator
rails to reduce power dissipation in cases where VIN is expected to be high. When EXTSUP is open or lower than
4.6V, the regulator is powered from VIN.
Main Input pin. This is the buck controller input pin as well as the output of the boost regulator. Additionally it
powers the internal control circuits of the device.
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5
Duplicate for second
Buck controller channel
CBA
Internal ref
(Band gap)
38
37
VIN
6
GA1
Gate Driver
Supply
EXTSUP
PWM logic
7
PHA
VREG
VREG 35
8
9
GA2
Internal
Oscillator
RT
22
PGNDA
Current sense
Amp
Slope Comp
SYNC &
LPM
+
10
11
12
PWM
comp
SA1
SA2
FBA
+
-
+
20
SYNC
-
OTA
-
gm
+
0.8V
+
SSA
Source/
Sink
Logic
4
13
15
GC2
COMPA
PGA
SA2
FBA
–
+
EN
VREF
Filter timer
1mA
VIN
14
SSA
ENA
VREF
40 mA
500 nA
16
ENA
21
DLYAB
40 mA
VREF
1mA
VIN
25
34
33
32
31
30
29
28
27
26
SSB
ENB
CBB
GB1
PHB
GB2
500 nA
17
ENB
18
COMPC
OTA
Second Buck Controller
Channel
1
-
VBAT
gm
+
PGNDB
SB1
36
DIV
Vref
OCP
2
DS
-
-
+
0.2V
SB2
+
VIN
PWM
comp
VREG
FBB
3
GC1
PWM
Logic
COMPB
PGNDA
19
ENC
24
PGB
23
AGND
Figure 2. Functional Block Diagram
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TYPICAL CHARACTERISTICS
EFFICIENCY ACROSS OUTPUT CURRENTS (BUCKS)
VIN = 12V, VOUT = 5V, SWITCHING FREQUENCY = 400kHz
INDUCTOR = 4.7µH, RSENSE = 10mW
10000
100
EFFICIENCY,
SYNC = LOW
90
80
70
60
50
40
30
20
10
0
1000
100
10
POWER LOSS,
SYNC = HIGH
POWER LOSS,
SYNC = LOW
1
EFFICIENCY,
SYNC = HIGH
0.1
0.0001
0.001
0.01
0.1
1
10
OUTPUT CURRENT (A)
Figure 3.
Figure 4.
SOFT-START OUTPUTS (BUCK)
VOUTA
VOUTB
1V/DIV
2ms/DIV
Figure 5.
Figure 6.
Figure 7.
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
EFFICIENCY ACROSS OUTPUT CURRENTS (BOOST)
VIN (BOOST OUTPUT) = 10V, SWITCHING FREQUENCY = 200kHz,
INDUCTOR = 1.0µH, RSENSE = 7.5mW
LOAD STEP RESPONSE (BOOST)
(0 TO 5A AT 2.5A/µs)
VBAT (BOOST INPUT) = 5V, VIN (BOOST OUTPUT) = 10V,
SWITCHING FREQUENCY = 200kHz, INDUCTOR = 1.0µH,
RSENSE = 7.5mW, CIN = 440µF, COUT = 660µF
100
90
VBAT = 8V
80
500mV/DIV
70
VIN (BOOST OUTPUT) AC-COUPLED
VBAT = 5V
60
VBAT = 3V
50
40
30
20
10
0
5A/DIV
IIND
0.01
1
10
2ms/DIV
OUTPUT CURRENT (A)
Figure 9.
Figure 10.
CRANKING PULSE BOOST RESPONSE
(12V to 4V IN 1ms AT BOOST DIRECT OUTPUT 25W)
CRANKING PULSE BOOST RESPONSE
(12V to 3V IN 1ms AT BUCK OUTPUTS 7.5W/11.5W)
VIN (BOOST OUTPUT) = 10V, BUCKA = 5V/1.5A, BUCKB = 3.3V/3.5A,
SWITCHING FREQUENCY = 200kHz, INDUCTOR = 1.0µH,
RSENSE = 7.5mOHM, CIN = 440µF, COUT = 660µF
VIN (BOOST OUTPUT) = 10V, BUCKA = 5V/1.5A, BUCKB = 3.3V/3.5A,
SWITCHING FREQUENCY = 200kHz, INDUCTOR = 1.0µH,
RSENSE = 7.5mOHM, CIN = 440µF, COUT = 660µF
VBAT (BOOST INPUT)
VBAT (BOOST INPUT)
5V/DIV
5V/DIV
0V
200mV/DIV
200mV/DIV
0V
VIN (BOOST OUTPUT)
VOUT BUCKA AC-COUPLED
VOUT BUCKB AC-COUPLED
5V/DIV
0V
10A/DIV
10A/DIV
0A
IIND
IIND
0A
20ms/DIV
20ms/DIV
Figure 11.
Figure 12.
INDUCTOR CURRENTS (BOOST)
VBAT (BOOST INPUT) = 5V, VIN (BOOST OUTPUT) = 10V,
SWITCHING FREQUENCY = 200kHz, INDUCTOR = 1.0µH,
RSENSE = 7.5mW, CIN = 440µF, COUT = 660µF
3A LOAD
5A/DIV
100mA LOAD
5A/DIV
2µs/DIV
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
BUCKx PEAK CURRENT LIMIT vs. COMPx VOLTAGE
NO-LOAD QUIESCENT CURRENT
ACROSS TEMPERATURE
75
62.5
50
60
50
40
30
20
10
0
37.5
25
BOTH BUCKS ON
12.5
0
SYNC = LOW
ONE BUCK ON
-12.5
-25
NEITHER BUCK ON
SYNC = HIGH
0.8 0.95
-37.5
0.65
1.1
1.25
1.4
1.55
-40 -15 10
35
60
85 110 135 160
COMPx VOLTAGE (V)
Temperature (°C)
Figure 14.
Figure 15.
FOLDBACK CURRENT LIMIT (BUCK)
CURRENT SENSE PINS INPUT CURRENT (BUCK)
0.9
80
70
60
50
40
30
20
10
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
150°C
25°C
-0.1
-0.2
-0.3
0
1
2
3
4
5
6
7
8
9
10 11 12
0
0.2
0.4
0.6
0.8
OUTPUT VOLTAGE (V)
FBx VOLTAGE (V)
Figure 16.
Figure 17.
REGULATED FBx VOLTAGE vs TEMPERATURE (BUCK)
CURRENT LIMIT VS DUTY CYCLE (BUCK)
805
804
803
802
801
800
799
798
797
796
795
80
70
60
50
40
30
20
10
0
VIN = 8V
VIN = 12V
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
-40 -15 10
35
60
85 110 135 160
TEMPERATURE (°C)
Figure 18.
Figure 19.
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SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011
DETAILED DESCRIPTION
Feedback Inputs
BUCK CONTROLLERS: NORMAL MODE
PWM OPERATION
The output voltage is set by choosing the right
resistor feedback divider network connected to the
FBx (feedback) pins. This is to be chosen such that
the regulated voltage at the FBx pin equals 0.8V. The
FBx pins have a 100nA pull up current source as a
protection feature in case the pins open up as a
result of physical damage.
Frequency Selection and External
Synchronization
The buck controllers operate using constant
frequency peak current mode control for optimal
transient behavior and ease of component choices.
The switching frequency is programmable between
150 kHz and 600 kHz depending upon the resistor
value at the RT pin. A short circuit to ground at this
pin sets the default switching frequency to 400 kHz.
The frequency can also be set by a resistor at RT
according to the formula:
Soft-Start Inputs
In order to avoid large inrush currents, both buck
controllers have independent programmable soft-start
timer. The voltage at the SSx pins acts as the
soft-start reference voltage. A 1µA pull-up current is
available at the SSx pins and by choosing a suitable
capacitor a ramp of the desired soft-start speed can
be generated. After start-up, the pull-up current
ensures that this node is higher than the internal
reference of 0.8V which then becomes the reference
for the buck controllers. The soft-start ramp time is
defined by:
X
f
=
(X=24kΩ×MHz)
SW
RT
9
10
f
=24×
SW
RT
Equation 1 Switching Frequency
For example,
I
×Δt
SS
C
=
(Farads)
SS
ΔV
600kHz requires 40kΩ
150kHz requires 160kΩ
Equation 2 SoftStart Ramp Time
Where,
It is also possible to synchronize to an external clock
at the SYNC pin in the same frequency range of 150
kHz to 600 kHz. The device detects clock pulses at
this pin and an internal PLL locks on to the external
clock within the specified range. The device can also
detect a loss of clock at this pin and when this is
detected it sets the switching frequency to the internal
oscillator. The two buck controllers operate at
identical switching frequencies 180 degrees out of
phase.
ISS = 1µA (typical)
∆V = 0.8V
CSS is the required capacitor for ∆t, the desired
soft-start time.
Alternatively the soft-start pins can be used as
tracking inputs. In this case, they should be
connected to the supply to be tracked via a suitable
resistor divider network.
Enable Inputs
Current Mode Operation
The buck controllers are enabled using independent
enable inputs from the ENA and ENB pins. These are
high voltage pins with a threshold of 1.5V for high
level and can be connected directly to the battery for
self-bias. The low threshold is 0.7V. Both these pins
have internal pull-up currents of 0.5µA (typical). As a
result, an open circuit on these pins enables the
respective buck controllers. When both buck
controllers are disabled, the device is shut down and
consumes a current less than 4µA.
Peak current-mode control regulates the peak current
through the inductor such that the output voltage is
maintained to its set value. The error between the
feedback voltage at FBx and the internal reference
produces a signal at the output of the error amplifier
(COMPx) which serves as target for the peak inductor
current. The current through the inductor is sensed as
a differential voltage at Sx1-Sx2 and compared with
this target during each cycle. A fall or rise in load
current produces a rise or fall in voltage at FBx
causing COMPx to fall or rise respectively, thus
increasing/decreasing the current through the
inductor until the average current matches the load.
In this way the output voltage is maintained in
regulation.
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The top N-channel MOSFET is turned on at the
beginning of each clock cycle and kept on until the
inductor current reaches its peak value. Once this
MOSFET is turned off, and after a small delay
(shoot-through delay) the lower N-channel MOSFET
is turned on until the start of the next clock cycle. In
dropout operation the high-side MOSFET stays on
100%. In every fourth clock cycle the duty cycle is
limited to 95% in order to charge the bootstrap
capacitor at CBx. This allows a maximum duty cycle
of 98.75% for the buck regulators. During dropout the
buck regulator switches at one-fourth of its normal
frequency.
Inductor L
TPS43335-Q1/
TPS43336-Q1
VBUCK X
DCR
R1
C1
Sx2
Sx1
VC
Figure 20. DCR Sensing Configuration
Slope Compensation
Current Sensing and Current Limit with Foldback
The maximum value of COMPx is clamped such that
the maximum current through the inductor is limited
to a specified value. When the output of the buck
regulator (and hence the feedback value at FBx) falls
to a low value due to a short circuit/over-current
condition, the clamped voltage at the COMPx
successively decreases, thus providing current fold
back protection. This protects the high-side external
MOSFET from excess current (forward direction
current limit).
Optimal slope compensation which is adaptive to
changes in input voltage and duty cycle allows stable
operation at all conditions. For optimal performance
of this circuit, the following condition must be satisfied
in the choice of inductor and sense resistor:
L×f
SW
=200
R
S
Equation 3 Inductor and Sense Resistor Choice
Where
Similarly, if due to a fault condition the output is
shorted to a high voltage and the low-side MOSFET
turns fully on, the COMPx node will drop low. It is
clamped on the lower end as well in order to limit the
maximum current in the low-side MOSFET (reverse
direction current limit).
L is the buck regulator inductor in Henry
RS is the sense resistor in Ohm
fsw is the buck regulator switching frequency in Hertz
The current through the inductor is sensed by an
external resistor. The sense resistor should be
chosen such that the maximum forward peak current
in the inductor generates a voltage of 75mV across
the sense pins. This value is specified at low duty
cycles only. At typical duty cycle conditions around
40% (assuming 5V output and 12V input), 50mV is a
more reasonable value, considering tolerances and
mismatches. the typical characteristics provide a
guide for using the correct current limit sense voltage.
Power Good Outputs and Filter Delays
Each buck controller has an independent power good
comparator monitoring the feedback voltage at the
FBx pins and indicating whether the output voltage
has fallen below a specified power good threshold.
this threshold has a typical value of 93% of the
regulated output voltage. the power good indicator is
available as an open drain output at the PGx pins. An
internal 50kΩ pull-up resistor to Sx2 is available or an
external resistor can be used. When a buck controller
is shut down, the power good indicator is pulled down
internally. Connecting the pull/up resistor to a rail
other than the output of that particular buck channel
will cause a constant current flow through the resistor
when the buck controller is powered down.
The current sense pins Sx1 and Sx2 are high
impedance pins with low leakage across the entire
output range. This allows DCR current sensing using
the DC resistance of the inductor for higher efficiency.
DCR sensing is shown in the below figure. Here the
series resistance (DCR) of the inductor is used as the
sense element. The filter components should be
placed close to the device for noise immunity. It
should be remembered that while the DCR sensing
gives high efficiency, it is inaccurate due to the
temperature sensitivity and a wide variation of the
parasitic inductor series resistance. Hence it may
often be advantageous to use the more accurate
sense resistor for current sensing.
In order to avoid triggering the power good indicators
due to noise or fast transients on the output voltage,
an internal delay circuit for de-glitching is used.
Similarly, when the output voltage returns to its set
value after a long negative transient, the power good
indicator will be asserted high (the open-drain pin
released) after the same delay. This can be used to
delay the reset to the circuits being powered from the
buck regulator rail. The delay of this circuit can be
programmed by using a suitable capacitor at the
DLYAB pin according to the equation:
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tDELAY
1 msec
1 nF
The TPS43335-Q1/TPS43336-Q1 can support the full
current load during low power mode until the
transition to normal mode takes place. The design
ensures the low power mode exit occurs at 10%
(typical) of full load current if the inductor and sense
resistor have been chosen as recommended.
Moreover, there is always a hysteresis between the
entry and exit thresholds to avoid oscillating between
the two modes.
=
CDLYAB
Equation 4 Power Good Indicator Delay
When the DLYAB pin is open the delay is set to a
default value of 20µsec typical. The power good
delay timing is common to both the buck rails but the
power good comparators and indicators function
independently.
In the event that both buck controllers are active, low
power mode is only possible when both buck
controllers have light loads that are low enough for
low power mode entry. When the boost controller is
enabled, low power mode is possible only if VBAT is
high enough to prevent the boost from switching and
if DIV is open or set to GND. If DIV is high (VREG),
low power mode is inhibited. .
Light Load PFM Mode
An external clock or a high level on the SYNC pin
results in forced continuous mode operation of the
bucks. When the SYNC pin is low or open, the buck
controllers will be allowed to operate in discontinuous
mode at light loads by turning off the low-side
MOSFET whenever a zero-crossing in the inductor
current is detected.
Boost Controller
In discontinuous mode, as the load decreases, the
duration of the clock period when both the high-side
as well the low-side MOSFET is turned off increases
(deep discontinuous mode). In case the duration
exceeds 60% of the clock period and VBAT > 8V, the
buck controller switches to a low power operation
mode. The design ensures that this typically occurs at
1% of the set full load current if the inductor and the
sense resistor have been chosen appropriately as
recommended in the slope compensation section.
The boost controller has a fixed frequency voltage
mode architecture and includes a cycle-by-cycle
current limit protection for the external N-channel
MOSFET. The switching frequency is derived from
and set to one half of the buck controller switching
frequency. The output voltage of the boost controller
at the VIN pin is set by an internal resistor divider
network and is programmable to 7V, 10V and 11V
based on the low, open and high status respectively
of the DIV pin. A change of the DIV-setting is not
recognized, while the device is in low power mode.
In Low Power PFM Mode the buck monitors the FBx
voltage and compares it with the 0.8V internal
reference. Whenever the FBx value falls below the
reference, the high-side MOSFET is turned on for a
pulse-duration inversely proportional to the difference
VIN-Sx2. At the end of this on-time, the high-side
MOSFET is turned off and the current in the inductor
decays until it becomes zero. The low-side MOSFET
is not turned on. The next pulse occurs the next time
FBx falls below the reference value. This results in a
constant volt-second Ton hysteretic operation with a
total device quiescent current consumption of 30µA
when a single buck channel is active and 35µA when
both channels are active.
The boost controller is enabled by the active-high
ENC pin and is active when the input voltage at the
VBAT pin has crossed the unlock threshold of 8.5V at
least once. After that, the boost controller is armed
and starts switching as soon as VIN falls below the
value set by the DIV pin and regulates the VIN
voltage. Thus, the boost regulator maintains a stable
input voltage for the buck regulators during transient
events such as cranking pulse at VBAT.
Whenever the voltage at the DS pin exceeds 200mV,
the boost external MOSFET is turned off by pulling
the GC1 pin low. By connecting the DS pin to the
drain of the MOSFET or to a sense resistor between
the MOSFET source and ground, cycle-by-cycle
over-current protection for the MOSFET can be
achieved. The on-resistance of the MOSFET or the
value of the sense resistor has to be chosen in such
a way that the on-state voltage at the DS does not
exceed 200mV at the maximum load and minimum
input voltage conditions. When sense resistor is
used , a filter network is recommended to be
connected between the DS pin and the sense resistor
for better noise immunity.
As the load increases, the pulse become more and
more frequent and move closer to each other until the
current in the inductor becomes continuous. At this
point, the buck controller returns to normal fixed
frequency current mode control. Another criteria to
exit the low power mode is when VIN falls low
enough to require higher than 80% duty cycle of the
high-side MOSFET.
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The boost output (VIN) can also be used to supply
other circuits in the system. However they should be
high-voltage tolerant. The boost output is regulated to
the programmed value only when VIN is low and so
VIN can reach battery levels.
Vbat
Vbat
VIN
TPS43335-Q1/
TPS43336-Q1
GC1
DS
RIFLT
VIN
CIFLT
DS
RISEN
TPS43335-Q1/
TPS43336-Q1
GC1
Figure 22. External Current Shunt Resistor
Figure 21. External Drain-Source Voltage Sensing
Frequency-Hopping Spread Spectrum (TPS43336-Q1 only)
The TPS43336-Q1 features a frequency-hopping pseudo-random spectrum spreading architecture. On this
device, whenever the SYNC pin is high, the internal oscillator frequency is varied from one cycle to the next
within a band of ±5% around the value programmed by the resistor at the RT pin. The implementation uses a
linear feedback shift register that changes the frequency of the internal oscillator based on a digital code. The
shift register is long enough to make the hops pseudo-random in nature and is designed in such a way that the
frequency shifts only by one step at each cycle to avoid large jumps in the buck and boost switching frequencies.
Table 1. Frequency Hopping Control
Sync
Terminal
Frequency Spread Spectrum (FSS)
Not active
Comments
Device in forced continuous mode, internal PLL locks into external clock
between 150kHz and 600kHz.
External clock
Device can enter discontinuous mode. Automatic LPM entry and Exit
depending on load conditions
Low or open
High
Not active
TPS43335-Q1: FSS not active
TPS43336-Q1: FSS active
Device in forced continuous mode
Table 2. Mode of Operation
ENABLE AND INHIBIT PINS
ENA ENB ENC SYNC
DRIVER STATUS
DEVICE STATUS
QUIESCENT CURRENT
~4 µA
BUCK CONTROLLERS
BOOST CONTROLLER
disabled
Low
Low
Low
X
Shutdown
Shutdown
Low
High
Low
High
Low
High
X
Buck B: LPM enabled
Buck B: LPM inhibited
Buck A: LPM enabled
Buck A: LPM inhibited
Buck A/B: LPM enabled
Buck A/B: LPM inhibited
Shutdown
~30µA (light loads)
mA range
Low
High
Low
Buck B running
Buck A running
disabled
disabled
~30µA (light loads)
mA range
High
Low
Low
~35µA (light loads)
mA range
High
Low
Low
High
Low
High
Low
Low
High
Buck A&B running
Shutdown
disabled
disabled
~4 µA
Low
High
Low
High
Low
High
Buck B: LPM enabled
Buck B: LPM inhibited
Buck A: LPM enabled
Buck A: LPM inhibited
Buck A/B: LPM enabled
Buck A/B: LPM inhibited
~50µA (no boost, light loads)
mA range
Boost running for VIN < set
Boost Output
Buck B running
~50µA (no boost, light loads)
mA range
Boost running for VIN < set
Boost Output
High
High
Low
High
High
Buck A running
~60µA (no boost, light loads)
mA range
Boost running for VIN < set
Boost Output
High
Buck A and B running
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Gate Driver Supply (VREG, EXTSUP)
scheme of reverse battery protection which may
require only a smaller sized diode to protect the
N-channel MOSFET as it conducts only for a part of
the switching cycle. Since it is not always in series
path, the system efficiency can be improved.
The gate drivers of the buck and boost controllers are
supplied from an internal linear regulator whose
output (5.8V typical) is available at the VREG pin and
should be decoupled using at least a 1µF ceramic
capacitor. This pin has an internal current limit
protection and should not be used to power any other
circuits.
R10
GC2
TPS43335-Q1/
D3
Q7
Q6
TPS43336-Q1
L3
Fuse (S1)
Vbat
VIN
DS
D1
D2
C17
C15
C16
C14
The VREG linear regulator is powered from VIN by
default when the EXTSUP voltage is lower than 4.6V
(typ.). In case VIN expected to go to high levels,
there can be excessive power dissipation in this
regulator, especially at high switching frequencies
and when using large external MOSFET's. In this
case, it is advantageous to power this regulator from
the EXTSUP pin which can be connected to a supply
lower than VIN but high enough to provide the gate
drive. When EXTSUP is connected to a voltage
greater than 4.6V, the linear regulator automatically
switches to EXTSUP as its input to provide this
advantage. Efficiency improvements are possible
when one of the switching regulator rails from the
TPS43335-Q1/TPS43336-Q1 or any other voltage
available in the system is used to power the
EXTSUP. The maximum voltage that should be
applied to EXTSUP is 13V.
GC1
COMPC
C13
R9
VBAT
Figure 23. Reverse Battery Protection Option for
Buck Boost Configuration
GC2
VBAT
VIN
Fuse
TPS43335-Q1/
TPS43336-Q1
DS
GC1
Using a large value for EXTSUP is advantageous as
it provides a large gate drive and hence better
on-resistance of the external MOSFET's. A 0.1µF
ceramic capacitor is recommended for decoupling the
EXTSUP pin when not being used.
COMPC
VBAT
Figure 24. Reverse Battery Protection Option for
Buck Boost Configuration
During low power mode, the EXTSUP functionality is
not available. The internal regulator operates as a
shunt regulator powered from VIN and has a typical
value of 7.5V. Current limit protection for VREG is
available in low power mode as well.
Undervoltage Lockout and Overvoltage
Protection
The TPS43335-Q1/TPS43336-Q1 starts up at a VIN
voltage of 6.5V (min). Once it has started up, the
device operates down to a VIN voltage of 3.6V, below
this voltage level the undervoltage lockout will disable
the device. A voltage of 46V at VIN triggers the
overvoltage comparator which shuts down the device.
In order to prevent that transient spikes shutting down
the device, the under and overvoltage protection
have filter times of 5µs (typical).
External P-Channel Drive (GC2) and Reverse
Battery Protection
The TPS43335-Q1/TPS43336-Q1 includes a gate
driver for an external P-channel MOSFET which can
be connected across the rectifier diode of the boost
regulator. This is useful to reduce power losses when
the boost controller is not switching. The gate driver
provides a swing of 6V typical below the VIN voltage
in order to drive a P-channel MOSFET. When VBAT
falls below the boost enable threshold, the gate driver
turns off the P-channel MOSFET and the diode is no
longer bypassed.
When the voltages return to the normal operating
region, the enabled switching regulators start
including
a new soft-start ramp for the buck
regulators.
When the boost controller is enabled, a voltage less
than 1.9V (typical) on VBAT triggers an undervoltage
lockout and pulls the boost gate driver (GC1) low. As
a result VIN will fall at a rate dependent on its
capacitor and load, eventually triggering VIN
The gate driver can also be used to bypass any
additional protection diodes connected in series as
shown in Figure 23. Figure 24 also shows a different
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undervoltage. A short falling transient at VBAT even
lower than 2V can thus be survived, if VBAT returns
to higher than 2.5V before VIN is discharged to the
undervoltage threshold. This detection has a filter
delay of 5µsec typical.
Thermal Protection
The TPS43335-Q1/TPS43336-Q1 protects itself from
overheating using an internal thermal shutdown
circuit. If the die temperature exceeds the thermal
shutdown threshold of 165 degrees Celsius due to
excessive power dissipation (e.g.: Due to fault
conditions such as a short circuit at the gate drivers
or VREG), the controllers are turned off and restarted
when the temperature has fallen by 15 degrees.
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APPLICATION INFORMATION
The following example illustrates the design process and component selection for the TPS43335-Q1. The design
goal parameters are given in Table 3.
Table 3.
PARAMETER
VBUCK A
VBUCK B
BOOST
VIN 6 V to 30 V
12 V - typ
VIN 6 V to 30 V
12 V - typ
VBAT - 5 V (cranking
pulse input) to 30V
Input voltage
Output voltage, VO
5 V
3 A
3.3 V
2 A
10 V
2.5 A
Max - output current, IO
Load step output tolerance, ∆VO
Current output load step, ∆IO
Converter switching frequency, fSW
±0.2 V
±0.12 V
0.1 A to 2 A
400 kHz
±0.5 V
0.1 A to 3 A
400 kHz
0.1 A to 2.5 A
200 kHz
This is a starting point and theoretical representation of the values to be used for the application, further
optimization of the components derived may be required to improve the performance of the device.
VIN
Boost Component Selection
A Boost converter operating in continuous conduction
C O
mode (CCM) has a right-half-plane (RHP) zero in its
7V
transfer function. The RHP zero is inversely related to
OTA-gmEA
the load current and inductor value and directly
COMPx
R ESR
-
related to the input voltage. The RHP zero limits the
maximum bandwidth achievable for the boost
10V
C 1
+
VREF
regulator. If the bandwidth is too close to the RHP
zero frequency, the regulator may become unstable.
C 2
R3
12V
Thus, for high power systems with low input voltages,
a low inductor value is chosen. This increases the
amplitude of the ripple currents in the N-channel
MOSFET, the inductor and the capacitors for the
boost regulator. They must be designed with the
ripple/RHP zero trade-off in mind and considering the
power dissipation effects in the components due to
parasitic series resistance.
Figure 25. Boost Compensation Components
This design is done assuming continuous conduction
mode. During light load conditions, the boost
converter will operate in discontinuous mode without
affecting stability. Hence the assumptions here cover
the worst case for stability.
A boost converter that operates in the discontinuous
mode does not contain the RHP-zero in its transfer
function. However, this needs an even lower inductor
value and has high ripple currents. Also, it must be
ensured that the regulator never enters the
continuous conduction mode otherwise it may
become unstable.
Boost Maximum Input Current IIN_MAX
The maximum input current is drawn at the minimum
input voltage and maximum load. the efficiency for
VBAT = 5V at 2.5A is 80% based on the typical
characteristics plot
Hence,
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Boost Inductor Selection, L
Allow input ripple current of 40% of IIN
VBAT = 5 V
at
max
V
BAT *TON
V
BAT
5V
L =
=
=
= 4.9 mH
I
IN max
I
IN max* 2 *fSW
2.52A * 2 * 200kHz
Choose a lower value of 4 µH in order to ensure a
high RHP-zero frequency while making a compromise
that expects a high current ripple. Also, this can make
the boost converter operate in discontinuous
conduction mode where it is easier to compensate.
The inductor saturation current needs to be higher
than the peak inductor current and some percentage
higher than the maximum current limit value set by
the external sensing resistive element.
Select CO = 660 µF.
This rating should be determined at the minimum
input voltage, maximum output current and maximum
core temperature for the application
This capacitor is usually aluminum electrolytic with
ESR in the 10s of mΩ. This is good for loop stability
since it provides a phase boost due to the ESR. The
output filter components LC create a double pole
(180 degree phase shift) at a frequency fLC and the
ESR of the output capacitor RESR creates a “zero“ for
the modulator at frequency fESR. These frequencies
can be determined by the following;
Inductor Ripple Current, IRIPPLE
Based on an Inductor value of 4 µH, the ripple current
is approximately 3.1 A.
Peak Current in Low Side FET, IPEAK
Based on this peak current value the external current
sense resistor RSENSE is calculated.
Select 20 mΩ allowing for tolerance
The filter component values RIFLT and CIFLT for
current sense are 1.5 kΩ and 1 nF respectively. This
allows for good noise immunity.
This satisfies fLC ≤ 0.1 fRHP
.
Bandwidth of Boost Converter, fC
Right Half Plane Zero RHP Frequency, fRHP
Use the following guidelines to set the frequency
poles, zeroes and crossover values for trade off
between stability and transient response:
fLC < fESR< fC< fRHP Zero
spacer
fC < fRHP Zero / 3
fC < fSW / 6
spacer
Output Capacitor, CO
fLC < fC / 3
To ensure stability, the output capacitor CO is chosen
such that
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Output Ripple Voltage Due to Load
Transients, ∆VO
Output Schottky Diode D1 Selection
A schottky diode with low forward conducting voltage
VF over temperature and fast switching
characteristics is required to maximize efficiency. The
reverse breakdown voltage should be higher than the
maximum input voltage and the component should
have low reverse leakage current. Additionally the
peak forward current should be higher than the peak
inductor current The power dissipation in the Schottky
diode is given by :
Since the boost converter is active only during brief
events such as a cranking pulse and the buck
converters are high-voltage tolerant,
a
higher
excursion on the boost output may be tolerable in
some cases. In such cases, smaller component
choices for the boost output may be used.
Since this is activated for low input voltage profile
related to crank pulse the duration is less than 25ms
Selection of Components for Type II
Compensation
Low-Side MOSFET (BOT_SW3)
The required loop gain for unity gain bandwidth
(UGB) is
The times tr and tf denote the rising and falling times
of the switching node and are related to the gate
driver strength of the TPS43335-Q1/TPS43336-Q1
and gate Miller capacitance of the MOSFET. The first
term denotes the conduction losses which are
minimized when the on-resistance of the MOSFET is
low. The second term denotes the transition losses
which arise due to the full application of the input
voltage across the drain-source of the MOSFET as it
turns on or off. They are higher at high output
currents and low input voltages (due to the large input
peak current) and when the switching time is low.
The boost converter error amplifier (OTA) has a Gm
that is proportional to the VBAT voltage. This allows a
constant loop response across the input voltage
range and makes it easier to compensate by
removing the dependency on VBAT
.
G
10
20
85 *10-6 *V
R3 =
C1=
C2 =
= 5.9kW
Note: The on resistance RDS(ON) has a positive
O
temperature
coefficient
which
produces
the
(TC=d*DeltaT) term that signifies the temperature
dependence.( Temperature coefficient d is available
as a normalized value from MOSFET data sheets
and can be assumed to be 0.005/degrees Celsius as
a starting value)
10
10
=
*R3 2p * 8kHz * 5.9kW
= 33nF
2p *f
C
C1
33nF
=
= 265pF
f
200kHz
2p *R3 *C1*( SW ) -1 2p * 5.9kW * 33nF *(
) -1
2
2
BUCKA Component Selection
Minimum ON Time, tON min
Input Capacitor, CI
The input ripple required is lower than 50 mV.
5
I
RIPPLE
416
DVC1 =
= 10mV
8 *fSW *C
1
This is higher than the min duty cycle specified (100
ns typ). Hence the minimum duty cycle is achievable
at this frequency.
DVESR = IRIPPLE *RESR = 40mV
Therefore our recommendation is 330µF with
10mOhm ESR.
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Current Sense Resistor RSENSE
Selection of Components for Type II
Compensation
Based on the typical characteristics for VSENSE limit
with VIN versus duty cycle, the sense limit is
approximately 65 mV (at VIN = 12V and duty cycle of
5V/12V = 0.416). Allowing for tolerances and ripple
currents choose VSENSE max of 50mV.
VO
RESR
R1
R2
VSENSE
RL
COMP
Type2A
gmea
CO
Vref
R3
R0
C2
Select 15 mΩ
C1
Inductor Selection L
Figure 26. Buck Compensation Components
As explained in the description of the buck
controllers, for optimal slope compensation and loop
response, the inductor should be chosen such that:
2p * f
C
*V
O
*CO
2p * 50kHz * 5 *100mF
R3 =
=
= 23.57kW
gm *KCFB *VREF
gm *KCFB *VREF
Use standard value of R3 = 24 kΩ
Where; VO = 5V, CO = 100uF, gm = 1ms, VREF = 0.8V
KFLR = Coil selection constant = 200
KCFB = 0.125 / RSENSE = 8.33 (0.125 is an internal
constant)
Choose a standard value of 8.2µH. For the buck
converter, the inductor saturation currents and core
should be chosen to sustain the maximum currents.
10
2p *R3 * fC 2p * 24kW * 50kHz
Use standard value of 1.5 nF
10
C1=
=
= 1.35nF
Inductor Ripple Current IRIPPLE
At nominal input voltage of 12V, this gives a ripple
current of 30% of IO max ≈ 1A.
Output Capacitor CO
The resulting bandwidth of Buck Converter fC
Select an output capacitance CO of 100µF with low
ESR in the range of 10mΩ. This give ∆VO(Ripple)
≈
15mV and ∆V drop of ≈ 180 mV during a load step,
which will not trigger the power good comparator and
is within the required limits.
Bandwidth of Buck Converter fC
This is close to the target bandwidth of 50 kHz
Use the following guidelines to set frequency poles,
zeroes and cross over values for trade off between
stability and transient response
The resulting zero frequency fZ1
•
Crossover frequency fC between fSW/6 and fSW/10
Assume fC = 50kHz
This is close to the fC/10 guideline of 5 kHz
•
•
Select the zero fz ≈ fC/10
Make the second pole fP2 ≈ fSW/2
The second pole frequency fP2
spacer
spacer
spacer
spacer
This is close to the fSW/2 guideline of 200 kHz. Hence
all requirements for a good loop response are
satisfied.
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10
10
Resistor Divider Selection for setting VO
Voltage
C1 =
=
2p * R3* fC 2p *30kW*50kHz
=1.2nF
C1
C2 =
2p * R3*C1*( fsw ) -1
Choose divider current through R1 and R2 to be 50
2
µA. Then
1.2nF
=
= 33pF
400kHz
2p *30kW*1.2nF *(
) -1
2
And
gm* R3* KCFB VREF
*
fC =
=
2p *CO
VO
Therefore, R2 = 16 kΩ and R1 = 84 kΩ
1ms*20kW*4.16*0.8
2p *100mF *3.3
fC =
= 48kHz
BUCKB Component Selection
Using the same method as VBUCKA, the following
parameters and components are realized
This close to the target bandwidth of 50 kHz
The resulting zero frequency fZ1
5
1
1
416
fZ1 =
=
2p * R3*C1 2p *30kW*1.2nF
= 4.4kHz
This is higher than the min duty cycle specified (100
ns typ)
This close to the fC guideline of 5kHz
The second pole frequency fP2
1
1
fP2 =
=
2p * R3*C2 2p *30kW*33pF
=160kHz
This close to the fSW/2 guideline of 200 kHz
Hence all requirements for a good loop response are
satisfied
∆Iripple current ≈ 0.4 A (approx.20% of IO max
)
Select an output capacitance CO of 100µF with low
ESR in the range of 10mΩ. This give ∆VO (Ripple) ≈
7.5mV and ∆V drop of ≈ 120 mV during a load step
Resistor Divider Selection for Setting VO
Voltage
Assume fC = 50kHz
2p * fC *VO *CO
R3 =
gm* KCFB *VREF
Choose divider current through R1 and R2 to be 50
µA. Then
2p *50kHz *3.3*100mF
=
= 30kW
1ms*4.16*0.8
Use standard value of R3 = 30kΩ
And
Therefore, R2 = 16 kΩ and R1 = 50 kΩ
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BUCKX High-Side and Low-Side N-Channel
MOSFETs
low. The second term denotes the transition losses
which arise due to the full application of the input
voltage across the drain-source of the MOSFET as it
turns on or off. They are lower at low currents and
when the switching time is low.
The gate drive supply for these MOSFET is supplied
by an internal supply which is 5.8V typical under
normal operating conditions. The output is a totem
pole allowing full voltage drive of VREG to the gate
with peak output current of 1.2 A. The High-Side
MOSFET is referenced to a floating node at the
phase terminal (PHx) and the Low-Side MOSFET is
referenced to power ground (PGx) terminal. For a
particular applications these MOSFET‘s should be
selected with consideration for the following
parameters Rds ON, gate charge Qg, drain to source
breakdown voltage BVDSS, Maximum DC current
IDC(max) and thermal resistance for the package.
P
BuckTOPFET =
V
I *I
(I
O
)2 *RDS(ON )(1+TC) *D + (
O ) *(t
r
+t ) *fSW
f
2
P
buckLOWERFET =
(I
O
)2 *RDS(ON )(1+TC)*(1-D) +V
F
*I
O
*(2*t )*fSW
d
In addition, during the dead time td when both the
MOSFETs are off, the body diode of the low-side
MOSFET conducts, increasing the losses. This is
denoted by the second term in the above equation.
Using external Schottky diodes in parallel to the
low-side MOSFETs of the buck converters helps to
reduce this loss.
The times tr and tf denote the rising and falling times
of the switching node and are related to the gate
driver strength of the TPS43335-Q1/TPS43336-Q1
and gate Miller capacitance of the MOSFET. The first
term denotes the conduction losses which are
minimized when the on-resistance of the MOSFET is
Note: The RDS(ON) has
a positive temperature
coefficient which is accounted for in the TC term for
RDS(ON). TC = d * delta T[°C]. The temperature
coefficient d is available as a normalized value from
MOSFET data sheets and can be assumed to be
0.005/degrees Celsius as a starting value
26
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SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011
Schematic
The following section summarize the previously calculated example and gives schematic + component proposals.
Table 3.
Table 4. Application Example 1
PARAMETER
VBUCK A
VBUCK B
BOOST
VIN 6 V to 30 V
12 V - typ
VIN 6 V to 30 V
12 V - typ
VBAT - 5 V (cranking
pulse input) to 30V
Input voltage
Output voltage, VO
5 V
3 A
3.3 V
2 A
10 V
2.5 A
Max - output current, IO
Load step output tolerance, ∆VO
Current output load step, ∆IO
Converter switching frequency, fSW
±0.2 V
±0.12 V
0.1 A to 2 A
400 kHz
±0.5 V
0.1 A to 3 A
400 kHz
0.1 A to 2.5 A
200 kHz
2.5V to 40V
VBAT
L1
D1
BOOST 10V, 25W
3.9µH
10µF
680µF
COUT1
CIN
330µF
TOP-SW3
1k
VIN
VBAT
DS
EXTSUP
0.1µF
BOT-SW3
0.02Ω
1.5k
1nF
GC1
DIV
GC2
CBA
VREG
1µF
0.1µF
CBB
TOP-SW2
L3
0.1µF
TOP-SW1
GA1
PHA
GA2
VBUCKA - 5V, 15W
0.015Ω
VBUCKB – 3.3V, 6.6W
GB1
PHB
GB2
L2
0.03Ω
8.2µH
15µH
100µF
COUT2
100µF
COUT3
BOT-SW2
BOT-SW1
TPS43335-Q1
or
TPS43336-Q1
PGNDB
SB1
PGNDA
SA1
84k
16k
50k
16k
SA2
FBA
SB2
FBB
COMPB
SSB
COMPA
SSA
47pF
33pF
1.5nF
20k 1.8nF
10nF
24k
10nF
PGA
PGB
5k
5k
ENA
ENB
AGND
RT
DLYAB
COMPC
ENC
270pF
5.6k
33nF
1nF
SYNC
Table 5. Application Example 1 - Component Proposals
Name
Component Proposal
Value
L1
L2
L3
D1
MSS1278T-392NL (Coilcraft)
4µH
8.2µH
15µH
MSS1278T-822ML (Coilcraft)
MSS1278T-153ML (Coilcraft)
SK103 (Micro Commercial Components)
IRF7416 (International Rectifier)
TOP_SW3
TOP_SW1, TOP_SW2 Si4840DY-T1-E3 (Vishay)
BOT_SW1, BOT_SW2 Si4840DY-T1-E3 (Vishay)
BOT_SW3
COUT1
COUT2,3
CIN
IRFR3504ZTRPBF (International Rectifier)
EEVFK1J681M (Panasonic)
ECASD91A107M010K00 (Murata)
EEEFK1V331P (Panasonic)
680µF
100µF
330µF
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TPS43335-Q1
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SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011
www.ti.com
Table 6. Application Example 2
PARAMETER
VBUCK A
VBUCK B
BOOST
VIN 5 V to 30 V
12 V - typ
VIN 6 V to 30 V
12 V - typ
VBAT - 5 V (cranking
pulse input) to 30V
Input voltage
Output voltage, VO
5 V
3 A
2.5 V
1 A
10 V
2 A
Max - output current, IO
Load step output tolerance, ∆VO
Current output load step, ∆IO
Converter switching frequency, fSW
±0.2 V
±0.12 V
0.1 A to 1 A
400 kHz
±0.5 V
0.1 A to 3 A
400 kHz
0.1 A to 2 A
200 kHz
5V to 30V
VBAT
L1
D1
BOOST 10V, 20W
3.9µH
CIN
330µF
10µF
470µF
COUT1
TOP-SW3
1k
VIN
VBAT
DS
EXTSUP
0.1µF
BOT-SW3
0.03Ω
1.5k
GC1
DIV
GC2
CBA
VREG
470pF
1µF
0.1µF
CBB
TOP-SW2
L3
0.1µF
TOP-SW1
GA1
PHA
GA2
VBUCKA - 5V, 15W
0.015Ω
VBUCKB – 2.5V, 2.5W
GB1
PHB
GB2
L2
0.045Ω
10uH
22uH
150µF
COUT2
100uF
COUT3
BOT-SW2
BOT-SW1
TPS43335-Q1
or
TPS43336-Q1
PGNDB
SB1
PGNDA
SA1
84k
16k
34k
16k
SA2
FBA
SB2
FBB
COMPB
SSB
COMPA
SSA
22pF
20pF
1nF
36k
10nf
1nF
39k
10nF
PGA
PGB
5k
5k
ENA
ENB
AGND
RT
DLYAB
COMPC
ENC
220pF
6.8k
24nF
1nF
SYNC
Table 7. Application Example 2 - Component Proposals
Name
Component Proposal
Value
L1
L2
L3
D1
MSS1278T-392NL (Coilcraft)
3.9µH
8.2µH
22µH
MSS1278T-822ML (Coilcraft)
MSS1278T-223ML (Coilcraft)
SK103 (Micro Commercial Components)
IRF7416 (International Rectifier)
TOP_SW3
TOP_SW1, TOP_SW2 Si4840DY-T1-E3 (Vishay)
BOT_SW1, BOT_SW2 Si4840DY-T1-E3 (Vishay)
BOT_SW3
COUT1
COUT2
COUT3
CIN
IRFR3504ZTRPBF (International Rectifier)
EEVFK1V471Q (Panasonic)
470µF
150µF
100µF
330µF
ECASD91A157M010K00 (Murata)
ECASD40J107M015K00 (Murata)
EEEFK1V331P (Panasonic)
28
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TPS43335-Q1
TPS43336-Q1
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SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011
Power Dissipation De-Rate Profile 32 pin HTTSOP package with power PAD
Figure 27. Power dissipation de rating profile based on high K Jedec PCB
PCB Layout Guidelines
Grounding and PCB Circuit Layout Considerations
Boost converter
1. The path formed from the input capacitor to the inductor and BOT_SW3 with low side current sense resistor
should have short leads and PC trace lengths. The same applies for the trace from the inductor to the
Schottky Diode D1 to the COUT1 capacitors. The negative terminal of the input capacitor and the negative
terminal of the sense resistor be connected together with short trace lengths.
2. The over current sensing shunt resistor may require noise filtering and this capacitor should be close to the
IC pin.
Buck Converter
1. Connect the drain of TOP_SW1 and TOP_SW2 together with positive terminal of the input capacitor COUT1.
The trace length between these terminals should be short.
2. Connect a local decoupling capacitor between Drain of TOP_SWx and Source of BOT_SWx.
3. The Kelvin current sensing for the shunt resistor should have minimum trace spacing and routed together.
Any filtering capacitors for noise should be placed near the IC pins.
4. The resistor divider for sensing output voltage is connected between the positive terminal of the respective
output capacitor and COUT2 or COUT3 and the IC signal ground. These components and the traces should
not be routed near any switching nodes or high current traces.
Other Considerations
1. PGNDx and AGND should be shorted to thermal pad. Use a star ground configuration if connecting to non
ground plane system. Use tie-ins for EXTSUP capacitor, compensation network ground and voltage sense
feedback ground networks to this start ground.
2. Connect compensation network between compensation pins and IC signal ground. Connect the oscillator
resistor (frequency setting) between the RT pin and IC signal ground. These sensitive circuits should NOT be
located near the dv/dt nodes; these include the gate drive outputs, phase pins and boost circuits (bootstrap).
3. Reduce the surface area of the high current carrying loops to a minimum, by ensuring optimal component
placement. Ensure the bypass capacitors are located as close as possible to their respective power and
ground pins.
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TPS43335-Q1
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SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011
www.ti.com
PCB Layout
POWER
INPUT
Power L ines
Connection to GND P lane ofPCB through vias
Connection to top /bottom ofPCB through vias
Vo ltage Ra ilOutputs
VBOOST
VBAT
DS
V IN
EXTSUP
D IV
GC1
GC2
CBA
VREG
CBB
GA1
PHA
GB1
PHB
GA2
PGNDA
SA1
GB2
PGNDB
SB1
SA2
SB2
FBA
FBB
COMPA
SSA
COMPB
SSB
PGA
ENA
PGB
AGND
RT
ENB
COMPC
ENC
DLYAB
SYNC
Exposed Pad
connected to GND
P lane
M icrocontro ller
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Dec-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS43335QDAPRQ1
TPS43336QDAPRQ1
ACTIVE
ACTIVE
HTSSOP
HTSSOP
DAP
DAP
38
38
2000
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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