V62/08620-03YE [TI]
增强型产品 Excaliber 低噪声高速精确四路运算放大器 | DW | 16 | -55 to 125;
| 型号： | V62/08620-03YE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 增强型产品 Excaliber 低噪声高速精确四路运算放大器 | DW | 16 | -55 to 125 放大器 运算放大器 放大器电路 |
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Document Number: MC34830
Rev. 1.0, 9/2008
Freescale Semiconductor
Product Preview
HD to SD Adjustable Bandwidth
Video Buffer with DC Restore
34830
The 34830 is a very high performance video buffer that can handle
HDTV bandwidths up to 1080p resolution. The integrated input clamp
works with all sync formats and all types of video signals. The 34830
includes an innovative capability to set the bandwidth to the optimum
trade-off of performance versus power dissipation. It can be adjusted
all the way from HD frequencies to SD frequencies while benefiting
from the lower power dissipation with lower bandwidths.
HD VIDEO BUFFER IC
Bottom
View
The 34830 can drive two standard video loads which are DC or AC
coupled. Input signals can be DC or AC coupled. For the DC coupled
case, the input sync should be close to ground. The 34830 can be
disabled, with shutdown current being 0.12μA.
EP SUFFIX (PB-FREE)
The 34830 is offered in an ultra thin UDFN package for space critical
applications. It operates on a single 3.0 to 5.5V supply over a -40°C to
85°C temperature range.
98ASA10819D
6-PIN UDFN
Features
ORDERING INFORMATION
Temperature
• 1080p / UXGA to 480i / VGA video buffer with 6dB gain
• Integrated input clamp
Device
Package
Range (T )
A
• Adjustable BW to save power
• Handles CV, Y, C, Pb, Pr, R, G, B signals
• Drives two video loads
PC34830EP/R2
-40°C to 85°C
6-UDFN
• Single supply operation
Applications
• 3.0 to 5.5V range
• Rail to rail output
• 0.3% dG / 0.3% dθ for SD
• 0.6% THD for HD
• 0.12μA shutdown current
•
•
•
•
•
Cellular phones
DVD players
Portable Game Players, Set-top boxes
Laptop PCs, Desktop PCs,
Projectors, Digital Cameras, Camcorders, Portable
Media Players, Security Systems
• Ultra thin UDFN package
• Pb-free packaging designated by suffix code EP
34830
VCC
ENABLE
Video cable
OUT
RFREQ
IN
GND
Figure 1. 34830 Simplified Application Diagram
*This document contains certain information on a product under development. Free-
scale reserves the right to change or discontinue this product without notice
© Freescale Semiconductor, Inc., 2008. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VCC
VCLAMP
ENABLE
6dB
IN
0dB
OUT
250mV
Levelshift
Bandwidth
Adjust
Bias
RFREQ
GND
Figure 2. 34830 Simplified Internal Block Diagram
34830
Analog Integrated Circuit Device Data
Freescale Semiconductor
2
PIN CONNECTIONS
PIN CONNECTIONS
VCC
1
EN
6
5
4
Transparent
Top View
OUT
IN
2
3
GND
RFREQ
Figure 3. 34830 Pin Connections
Table 1. 34830 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 10.
Pin Number Pin Name Pin Function
Formal Name
VCC
Definition
1
2
3
4
VCC
IN
Supply voltage input
Video Input
Power
Input
Video Input
Ground
GND
RFREQ
Ground return for the IC
Ground
Passive
Frequency Bandwidth Connection for the resistor to GND to set operating bandwidth
Set
5
6
OUT
EN
-
Video Output
Enable
Video output
Output
Input
Low = device disabled; High = device enabled
EP
Exposed Pad
Exposed pad for thermal dissipation. Connect the EP to GND or leave
floating. The EP is electrically connected to ground.
Passive
34830
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
Maximum Pin Voltage (Except as below)
All other pins -0.3V to Vcc + 0.3V
VCC
6.0
V
Maximum Current (into any pin)
THERMAL RATINGS
100
mA
Ambient Temperature Range
Operating Junction Temperature
Maximum Junction Temperature
Storage Temperature Range
TA
TJ
-40 to 85
-40 to 125
150
°C
°C
°C
°C
W
TJMAX
TSTORE
-40 to 150
Power Dissipation (UDFN package with EP soldered to ground plane)
TA = 25°C
TA = 70°C
1790
1140
Thermal Resistance (6-LD UDFN)
°C/W
°C
θJA
θJC
70
10
Peak Package Soldering Temperature During Reflow(2) (3)
,
TPPRT
260
Notes
1. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100pF, RZAP = 1500Ω), the Machine Model (MM)
(CZAP = 200pF, RZAP = 0Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0pF).
2. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
3. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
34830
Analog Integrated Circuit Device Data
Freescale Semiconductor
4
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions VCC = 3.0V to 5.5V, TA = -40°C to 85°C, RFREQ = 9.0kΩ, CIN = 0.1μF, RL = 150Ω, CL
= 5.0pF. Typical values are at TA = 27°C, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Input Voltage Range (inferred from gain)
VCC = 3V TO 3.4V
VINP
V
VINPCLAMP
VINPCLAMP
-
-
(VCC-1)/2
1.2
VCC = 3.4V TO 5.5V
Input Clamping Level(4)
VINPCLAMP
VOUTCLAMP
RFREQ
-50
400
9.0
0
500
-
+50
600
108
mV
mV
kΩ
Output Clamping Level(5)
Frequency Set Resistor Range
Supply Current measured with no load
RFREQ = 108kΩ
ICC
mA
-
-
4.5
17
8
RFREQ = 9kΩ
23
Supply Current in Shutdown Mode (EN = 0.0V)
Output Short-circuit Current (Output shorted to VCC or ground for <1s)
Input Leakage Current (VINP = 1.0V)
Line-Time Distortion (100 IRE, 18μs)
Field-Time Distortion (100 IRE, 18μs, field lines)
Logic Low Input Voltage
ICCSHUTDOWN
-
-
-
-
-
-
0.12
100
2.0
0.1
0.2
-
5.0
-
μA
mA
μA
%
ISC
IINP
5.0
0.2
0.4
HDIST
VDIST
VIL
%
0.3(VCC
)
V
Logic High Input Voltage
VIH
0.7(VCC
-
)
-
-
V
Logic Level Input Current (source and sink)
IILH
-
|1.0|
μA
Notes
4. Referenced to input. Input clamp not active for signals C, Pb, Pr, U, and V.
5. Establishes output sync level.
34830
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions VCC = 3.0V to 5.5V, TA = -40°C to 85°C, RFREQ = 9.0kΩ, CIN = 0.1μs, RL =150Ω, CL
= 5.0pF. Typical values are at TA = 27°C, unless otherwise noted.
Characteristic
Low Frequency Gain (@100kHz)
Symbol
Min
Typ
Max
Unit
A
1.9
2.0
2.1
V/V
Small-signal 1.0 dB Bandwidth
RFREQ = 108kΩ
BW1SS
MHz
25
85
37
RFREQ = 9kΩ)
130
Differential Gain (3-step measurement, RFREQ = 108kΩ, f = 4.0MHz)
Differential Phase (3-step measurement, RFREQ = 108kΩ, f = 4.0MHz)
Total Harmonic Distortion (VIN = 0.65V + 700mVP-P , 60MHz sine wave)
DC Group Delay (at 100kHz)
dG
dθ
-
-
0.3
0.3
0.65
2.8
0.5
450
4.0
65
1.0
%
deg
%
1.0
THD
tG
-
-
-
-
-
-
-
-
-
ns
Group Delay Deviation (f = 100kHz to 60 MHz)
ΔtG
SR
tS
-
ns
Slew Rate (VOUT = 2V step)
-
V/μs
ns
Settling Time to 10% (VOUT = 2VPP
)
-
Peak Signal to Noise Ratio (VOUT = 2.0Vp-p, f=100Hz to 200 MHz)
SNR
PSR
58
-
dB
dB
Power Supply Rejection (Measured at 100kHz with 100mVpp sinewave ripple
on VCC.)
40
ELECTRICAL PERFORMANCE CURVES
Plots are taken under conditions VCC = 4.0V, RFREQ = 9.0kΩ, RL =150Ω, TA = 27°C, unless otherwise noted.
145
135
125
115
105
95
10
5
RFREQ=9k
Ω
0
-5
RFREQ=108k
Ω
-10
-15
-20
-25
-30
-35
-40
85
75
65
55
45
35
25
0
10
20
30
40
50
60
70
80
90
100
110
120
0.1
1
10
100
1000
R,BANDWIDTHSETTINGRESISTOR(kΩ)
FREQ
FREQUENCY (MHz)
Figure 4. Frequency Response Magnitude
Figure 5. -1dB Bandwidth vs. RFREQ (kΩ)
34830
Analog Integrated Circuit Device Data
Freescale Semiconductor
6
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
20
18
16
14
12
10
8
20
18
16
14
12
10
8
RFREQ = 9kΩ
RFREQ = 108kΩ
6
6
4
4
2
0
20
40
60
80
100
120
0
RFREQ, BANDWIDTH SETTING RESISTOR (kΩ)
3
3.5
4
4.5
5
5.5
,SUPPLYVOLTAGE(V)
VCC
Figure 6. Supply Current vs. RFREQ (kΩ)
Figure 9. No Load Supply Current vs. Supply Voltage
0.53
0.527
0.524
0.521
4
3.5
3
0.518
2.5
2
RFREQ = 108kΩ
RFREQ=9k
Ω
0.515
0.512
RFREQ=108k
Ω
1.5
1
RFREQ = 9kΩ
0.509
0.506
0.503
0.5
0.5
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
VIN, INPUTVOLTAGE(V)
-40
-27.5
-15
-2.5
10
22.5
35
47.5
60
72.5
85
T, TEMPERATURE (°C)
Figure 10. Channel DC Shift vs. Temperature
Figure 7. DC Output Voltage vs. Input Voltage
20
18
16
14
12
10
8
RFREQ = 9kΩ
Set to 0.5V by key clamp
Input
gnd
Set to 1.5V
Output
RFREQ = 108kΩ
6
4
2
gnd
0
i/i
TIME (80ns/DIV)
-40
-27.5
-15
-2.5
10
22.5
35
47.5
60
72.5
85
T, TEMPERATURE (°C)
Figure 11. Sinusoidal Wave Response (External
resistors setting clamp level to 0.5V, VCC= 3V, RFREQ
Figure 8. Supply Current vs. Temperature
=
108kΩ for 5MHz sine input.)
34830
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
Input
Input
Set to 0 V by Sync tip clamp
gnd
Set to 0 V by Sync tip clamp
gnd
Output
Output
Set to 0.5 V
Set to 0.5 V
gnd
gnd
TIME (3.4μs/DIV)
TIME (9.5μs/DIV)
Figure 12. 480i Signal (RFREQ = 108kΩ)
Figure 15. 1080i Signal
Input
Input
gnd
gnd
Output
Output
gnd
gnd
TIME (25ns/DIV)
TIME (700ns/DIV)
Figure 16. 1080i 2T Response
Figure 13. 480i 2T and Modulated 12.5T Response
(RFREQ = 108kΩ)
OUTPUT
OUTPUT
INPUT
gnd
INPUT
gnd
gnd
TIME (0.8ms/DIV)
gnd
TIME (0.6ms/DIV)
Figure 17. 1080i Vertical/Horizontal Sync Levels
Figure 14. 480i Vertical/Horizontal Sync Levels (RFREQ
=
108kΩ)
34830
Analog Integrated Circuit Device Data
Freescale Semiconductor
8
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
8
7
6
5
4
3
2
1
0.5
0.4
0.3
0.2
0.1
0
RFREQ = 108kΩ
-0.1
-0.2
-0.3
-0.4
-0.5
0
1
2
3
4
5
6
0.1
1
10
100
1000
STEPS FROM 0.3 to 1.0V (140mV/STEP)
FREQUENCY (MHz)
Figure 18. Differential Gain (RFREQ = 108kΩ, measured
Figure 20. Group Delay Response
at 4.0MHz)
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
RFREQ = 108k
Ω
-0.1
-0.2
-0.3
-0.4
-0.5
RFREQ = 9k
Ω
3
3.25
3.5
3.75
4
4.25
4.5
4.75
5
5.25
5.5
VCC, SUPPLY VOLTAGE (V)
0
1
2
3
4
5
6
STEPS FROM 0.3 to 1.0V (140mV/STEP)
Figure 21. DC PSR vs. Supply Voltage
Figure 19. Differential Phase (RFREQ = 108kΩ, measured
at 4MHz)
34830
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
VCC
RFREQ
VCC is the power input terminal for the IC. A 0.1μF bypass
capacitor in series with a 4.7Ω resistor to ground should be
connected as close as possible to this pin to provide noise
immunity.
The operating bandwidth of the IC is set by the value of the
resistor between this terminal and ground. By selecting a
value for the RFREQ resistor between 9.0kΩ and 108kΩ,the
bandwidth can be set for video applications ranging from
1080p to 480i.
IN
OUT
IN is the video signal input terminal.
OUT is the video signal output terminal.
GND
EN
GND is the ground terminal for the IC.
EN is a logic level enable input for the IC. EN = 1 turns the
IC on, and EN = 0 turns it off.
34830
Analog Integrated Circuit Device Data
Freescale Semiconductor
10
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MC34830 - Functional Block Diagram
Signal Path/ Signal Channel
Input Clamp
Level Shifter
Output Buffer
Bias
Bandwidth Adjust
Shutdown
Voltage Bandgap
PTAT Current Generator
Constant Current Generator
Signal Path
Bias
Bandwidth Adjust
Shutdown
Figure 22. Functional Internal Block Diagram
BIAS CIRCUITRY
SIGNAL PATH/SIGNAL CHANNEL
The Bias Circuitry sets the operating points for the internal
INPUT CLAMP
blocks of the 34830. It consists of a bandgap voltage
reference, a PTAT current generator and a constant current
generator.
This sets the DC level of the signal at the input if the input
is AC-coupled.
BANDWIDTH ADJUST
LEVELSHIFTER
It consists of a variable PTAT current generator whose
current is set by an external resistor. Bias current variation is
inversely proportional to the external resistor value. By
varying the bias current for the level shifter and output buffer
we can adjust the channel bandwidth.
The Level Shifter provides +250mV DC shift to the input
signal. This positions the signal within the input compliance
of the output buffer.
OUTPUT BUFFER
It provides gain of two as well as the current to drive the
load.
SHUTDOWN
Shutdown enables/disables internal blocks of the 34830
based on the state of the enable input (EN).
34830
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
FUNCTIONAL DEVICE OPERATION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL DEVICE OPERATION
INTRODUCTION
The 34830 is a very high performance video buffer
designed for high-definition (HD) video applications. The
device features an innovative adjustable bandwidth circuitry
that allows the user to set the bandwidth of the device
through an external resistor connected to RFREQ. This
feature allows the 34830 to fit in a variety of video
applications giving it the flexibility to reduce power
consumption when full bandwidth is not required. In this way
the 34830 can support all video bandwidths, from standard
definition (SD) to high definition (HD), including the 1080i as
well as 1080p formats.
small (2.0μA) pull-down current to guarantee operation of the
clamp.
Key Clamp
The clamp works in this mode for C, Pb, Pr, U, and V
signals that are AC-coupled to the 34830 while DC bias is set
externally. In this configuration, ensure that the DC bias at the
input is such that the most negative level of the signal never
goes below 50mV, to avoid interference with the clamp. The
DC bias at the input can be set through a resistive voltage
divider after the AC-coupling capacitor (Figure 23). In order to
maximize the input signal swing, it is recommended to set the
input DC bias to 0.5V. This will also maximize the swing at the
output of the 34830.
The 34830 also features an internal input clamp that works
with all sync formats and types of video signals. The clamp
can work in three different modes and allows both AC- and
DC-coupled input signals.
Transparent Clamp
The 34830 is optimized to drive a single standard video
load while maintaining exceptional performance
characteristics. Two video loads can also be supported by the
device with a minimum tradeoff in performance
specifications. The 34830 supports both AC- and DC-
coupled outputs.
The clamp works in this mode for all DC-biased signals.
Ensure that the most negative level of the signal is above
50mV from ground. If this requirement is not met, the signal
source and clamp both try to set the level at the input,
resulting in signal distortion. The input clamp becomes
transparent for signals above 50mV and the signal passes
through unaffected.
The 34830 can be disabled with an ultra-low current
consumption of 0.12μA, by driving the EN input to ground.
The 34830 operates using a single supply from 3V to 5.5V,
and is designed to work in the extended temperature range
from -40°C to 85°C. The device is offered in a small UDFN
package ideal to fit into space-critical applications.
BIAS CIRCUITRY
The bias circuit sets the operating bias for 34830’s internal
blocks. It includes a bandgap voltage reference, a PTAT
current generator, as well as a constant current generator.
These reference currents and voltages are then distributed to
34830’s internal blocks to set their respective operating
points.
The signal path of the 34830 begins with the input clamp
that DC-restores the input. The signal is then shifted up by a
level shifter which brings it to the appropriate levels required
for the output buffer. The level shifter also provides isolation
between the very sensitive input clamp circuit and the input
stage of the output buffer. The signal is then channeled to the
output buffer which amplifies it with a gain of two and drives
the output loads. Both the level shifter and output buffer
blocks are biased through the bandwidth adjust circuitry
which allows the user to set the bandwidth and quiescent
power consumption according to the application at hand.
BANDWIDTH ADJUST
The 34830 features a bandwidth adjust circuit that sets the
bandwidth of the channel by adjusting quiescent supply
current. It consists of a PTAT current generator whose
current varies with the value of an external resistor (RFREQ).
This PTAT current is used to set the operating bias for the
level shifter and output buffer blocks. Increasing the external
resistor (RFREQ) lowers the bias current, and hence reduces
both supply current and bandwidth. Decreasing the value of
INPUT CLAMP
The function of the input clamp is to set the DC level of the
signal at the input. The clamp can be operated in three
modes.
RFREQ increases both supply current and bandwidth. Select
a value for RFREQ in the range between 9kΩ and 108kΩ, to
set the bandwidth between the upper and lower limits. Refer
to Figure 5.
Sync Tip Clamp
The clamp works in this mode for Y,CV, R, G, and B
signals that are AC-coupled to the 34830. In this mode, the
clamp senses the most negative level of the input signal and
clamps it to ground. The clamp circuit does this by injecting
current into the AC-coupling capacitor to make the voltage at
the input rise. The current is disabled once the voltage has
risen to the appropriate level. The clamp circuitry includes a
LEVEL-SHIFTER
After passing through the input clamp, which restores its
DC level to a known value, the signal is level-shifted up by
250mV. The level-shifting operation is done for two reasons.
The first is to isolate the input of the output buffer from the
sensitive clamp circuitry to prevent distortion. In this sense,
34830
Analog Integrated Circuit Device Data
Freescale Semiconductor
12
FUNCTIONAL DEVICE OPERATION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
the level-shifter acts simply as a buffer of gain one. The
second reason, is to bring the input signal into the proper
operating range of the output buffer. Shifting the signal up
allows the output buffer to work in its sweet spot. This also
prevents the output devices of the output buffer from going
into saturation.
R
× (V
– V
)
CLAMP
C1
CC
-------------------------------------------------------------------
R
=
C2
V
CLAMP
The values selected for RC1 should not be too small, The
bias current that flows through the resistor divider network
comes directly from VCC, and hence adds to power
consumption. A typical value for RC1 is 10kΩ.
Since the level-shifter needs to pass the signal without
affecting it, it really is a high-speed amplifier. The current that
biases this block comes from the bandwidth adjust section,
which allows for the power consumption to be decreased if
lower bandwidths are required. Refer to Figure 6.
The general relationship between input and output voltage
of the channel is given by the formula:
OUTPUT BUFFER
V
= 2 × (V + 250mV) 100mV
IN
The output buffer is a high-speed (800MHz open-loop
bandwidth), operational amplifier used in a non-inverting gain
of two configuration through resistive feedback. The amplifier
uses a class AB topology with a rail-to-rail output that
incorporates saturation protection as well as current-limiting.
In this way the 34830 is protected against excessive loads or
short-circuit conditions to both supply and ground and will
resume its normal operation as soon as the short-circuit or
overload condition is removed.
OUT
Where the 250mV term is the offset provided by the
internal level shifter. The 100mV term that is added to the
equation represents the worst case errors and offsets that
can be expected from the signal path, due to process and
temperature variations. The DC bias at the output is given by
the same formula substituting VCLAMP for VIN. Thus the DC
bias at the output for VCLAMP = 0.5V is around 1.5V.
The output buffer also uses PTAT current biasing that
varies with RFREQ. By increasing RFREQ, the buffer
bandwidth can be decreased, resulting in power consumption
savings.
The output buffer has been optimized to drive a standard
video load (150Ω) with up to 5pF of load capacitance, while
meeting all of the specifications listed in the electrical
characteristics table. The output buffer can also support two
standard video loads with a slight relaxation in the
specifications.
VCC
RC2
VCLAMP
MC34830
IN
AC coupling
capacitor
RC1
SHUTDOWN
The 34830 features an enable input (EN) that allows the
device to be placed in a low-supply-current shutdown state
when not required to pass a video signal. Driving EN high
puts the 34830 in its active mode. Driving EN low puts the
34830 in shutdown. In shutdown, the device has a supply
current of 120nA and its output becomes high impedance.
The shutdown feature makes the 34830 ideal for portable
applications where power consumption is critical.
Figure 23. Key Clamp DC Bias Configuration
SETTING BANDWIDTH
The bandwidth of the 34830 is set through an external
resistor connected from input RFREQ to ground. Increasing
the value of the resistor causes the quiescent current of the
device to decrease, which in turn decreases its bandwidth.
Decreasing the value of RFERQ has the opposite effect,
mainly to increase quiescent supply current and thus
bandwidth. Select the value of RFREQ in the range between
9kΩ and 108kΩ. Refer to Figure 5 for a relationship between
the value of RFREQ and the corresponding bandwidth of the
34830. To ensure that the channel bandwidth is greater than
the one needed for the application, after taking into account
process and temperature variation, multiply the value of
RFREQ obtained from the graph by 0.6. Use this number as
the value of the external resistor.
SETTING KEY CLAMP BIAS
For C, Pb, Pr, U, and V signals, use a resistor divider to set
the DC bias (VCLAMP) at the input of the 34830, as shown in
Figure 23. In this configuration.
RC1 × VCC
--------------------------
=
V
CLAMP
R
C1 + RC2
Ensure that VCLAMP is set to a value such that the most
negative value of the signal at the input to the 34830 is above
50mV. This prevents the internal clamp from turning on. To
maximize signal swing, set VCLAMP = 0.5V. The general
procedure for selecting the resistor values for RC1 and RC2
is to first select a value for VCLAMP and RC1, and then solve
for RC2 using the formula:
It is recommended to place a small capacitor (100pF) in
parallel with the external resistor at RFREQ. This capacitor
helps to filter any noise or signal that couples into the RFREQ
input, which may disturb the bias conditions of the device.
,
34830
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
FUNCTIONAL DEVICE OPERATION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
INPUT CONSIDERATIONS
V
= 2 × (V + 250mV) 100mV
IN
As explained in the Input Clamp section, the 34830
features an internal clamp that allows the device to work with
both AC as well as DC-coupled input signals. To AC-couple
the input signal, use a 0.1μF capacitor following the video
signal source. If the signal being AC-coupled has sync, then
the 34830’s clamp circuit ensures that the sync tip is detected
and positioned near ground (Sync Tip Clamp). If the signal
that is being AC-coupled does not have sync (Key Clamp),
care must be taken to ensure that its most negative portions
are not confused as being sync tips and clamped, resulting in
signal distortion. In order to prevent this from happening, the
user must set the DC bias at the input correctly. See the
SETTING KEY CLAMP BIAS section.
OUT
Where the 250mV term is the offset provided by the
internal level shifter. The 100mV term that is added to the
equation represents the worst case errors and offsets that
can be expected from the signal path, due to process and
temperature variations.
The 34830 has been optimized to drive a single standard
video load. A standard video load typically consists of a 75Ω
back-termination resistor, followed by a matched video cable
and a 75Ω load resistor. The 34830 can drive up to 5pF of
load capacitance in parallel with the video cable and load
resistor. Two video loads can be supported by the 34830 with
a minimum tradeoff in performance parameters.
When the input to the 34830 goes above 50mV, the clamp
circuit becomes transparent and does not have any effect on
the signal being passed. This allows the 34830 to work with
DC-coupled signals. To DC-couple the input signal, simply
connect the video source directly to the input of the 34830.
The output of the 34830 can be both AC or DC-coupled.
When the output is AC-coupled the AC-coupling capacitor
forms a high-pass filter with the load resistor. Ensure that the
value of the AC-coupling capacitor is such that the lowest
frequencies of the video signal are passed without
attenuation from this filter. A typical value for the output AC-
coupling capacitor is 220μF.
OUTPUT CONISDERATIONS
The relationship between input and output for the 34830
follows the equation:
Place the output termination resistor as close to the output
as possible to minimize parasitic inductance and capacitance
effects that tend to deteriorate signal quality.
34830
Analog Integrated Circuit Device Data
Freescale Semiconductor
14
TYPICAL APPLICATIONS
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
TYPICAL APPLICATIONS
V
CC
0.1μF
4.7Ω
VCC
EN
75Ω
EN
OUT
Video Cable
0.1μF
CV
OUT
CV
IN
IN
34830
75Ω
AC coupling
capacitor
RFREQ
GND
100pF
Figure 24. Composite Video Signal
V
CC
0.1μF
4.7Ω
0.1μF
VCC
EN
EN
OUT
Video Cable
100pF
Y
OUT
Y
IN
IN
34830
75Ω
75Ω
RFREQ
AC coupling
capacitor
GND
V
CC
0.1μF
4.7Ω
VCC
EN
EN
OUT
Video Cable
100pF
Rc
2
C
OUT
34830
0.1μF
75Ω
75Ω
C
RFREQ
IN
IN
GND
AC coupling
capacitor
Rc
1
Figure 25. S-Video Application
V
CC
0.1μF
4.7Ω
VCC
EN
OUT
EN
Video Cable
100pF
Y
/G
OUT OUT
34830
0.1μF
75Ω
75Ω
Y
/G
RFREQ
IN IN
IN
GND
AC coupling
capacitor
V
CC
P
only
P
bIN
0.1μF
4.7Ω
VCC
EN
EN
OUT
Video Cable
100pF
Rc
2
Pb
/B
OUT OUT
34830
0.1μF
75Ω
75Ω
/B
RFREQ
bIN IN
IN
GND
Rc
1
AC coupling
capacitor
V
CC
P
only
rIN
0.1μF
VCC
EN
OUT
EN
Video Cable
100pF
Rc
4.7Ω
Pr
/R
OUT OUT
2
34830
0.1μF
75Ω
75Ω
P
/R
RFREQ
rIN IN
IN
GND
AC coupling
capacitor
Rc
1
Figure 26. Component Video Application
34830
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
TYPICAL APPLICATIONS
BILL OF MATERIAL
VCC
VCC
R2
180
VCC
GND
EN
X1-2
C4
.1μF
C6
10μF
D1
2
1
R12
4.7
3
C3
220μF
R9
75
Output2
R10
49.9k
JP12
R11
100k
1
2
6
R8
EN
VCC
3V
.1μF
5.5V
75
R7
75
34830
JP9
JP6
5
4
JP8
JP5
IN
Input
OUT
C2
JP3
3
JP1
GND
RFREQ
JP2
C7
100pF
R6
75
1
2
R4
10k
C1
220μF
R3
75
NOPOP
49.9
Output1
R5
150k
3
R1
1k
Figure 27. 34830 Evaluation Board Schematic
BILL OF MATERIAL
Table 5. 34830 Bill of Material
Qty
Part Description
Part Number/Manufacturer
Install
Value/Rating
Item
UVZ1A221MED, Nichicon, radial,
electrolytic
Y
C1, C3
2
Capacitor
220μF, 10V
0603, ceramic, 03CER
Y
Y
C2
C4
1
1
Capacitor
Capacitor
.1μF, 25V
.1μF, 6.3V
0204, ceramic, Murata,
LLL153C80J104ME01B
1206, ceramic
C6
C7
1
1
2
Capacitor
Capacitor
10μF, 25V
0603, metal film chip
FIDICUAL_40
Y
N
Y
100pF, 50V
X1-2
HDR1X2, .1 Pitch straight for .062 BD.
JP1-3, JP5-6, JP8-9, JP12,
3.0V, 5.5V
1x2 Male header strip
10
HSMx-c670 HP 0805
N
Y
Y
N
Y
Y
Y
Y
Y
Y
N
D1
U1
1
1
1
1
5
1
1
1
1
1
LED
MC34830
Resistor
Resistor
Resistor
Resistor
Potentiometer
Resistor
Resistor
Resistor
Resistor
MC34830
0603, metal flip chip
R1
1.0kΩ, 1/10W, 1%
180Ω, 1/10W, 1%
75Ω, 1/10W, 1%
10kΩ, 1/10W, 1%
150kΩ
0603, metal flip chip
R2
0603, metal flip chip, Speer Electronics
0603, metal flip chip
R3, R6 - R9
R4
Bourns 3299Y-1-154L, trrimpot, 25 turn
Speer Electronics, 0603, metal flip chip
0603, metal flip chip
R5
R10
49.9kΩ, 1/10W, 1%
100kΩ, 1/10W, 1%
4.7Ω, 1/0W, 1%
49.9Ω, 1/10W, 1%
R11
0603, metal flip chip
R12
0603, metal flip chip, TTI
CRCW060349R9FT
NOPOP
1
3
Johnson, 142-0711-826, Edge Mount
Y
Input, Output 1-2
SMA Jack
SMA-PCB_EDGE_E
34830
Analog Integrated Circuit Device Data
Freescale Semiconductor
16
TYPICAL APPLICATIONS
Table 5. 34830 Bill of Material
Qty
Part Description
Part Number/Manufacturer
Install
Value/Rating
Item
SPDT, EG1218
Y
Y
EN
1
1
E-Switch
Switch SPDT
MKDSN1.5/2, 2 pin Terminal block 2 Diga-
key, 5.0mm, 90 deg wire to pin, Stock
number - 277-1236-ND
VCC
2POL254 Phoenix
Connector
Termblock2_MKD
Freescale does not assume liability, endorse, or warrant components from external manufacturers that are referenced in circuit drawings or
tables. While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to validate their application.
PCB LAYOUT CONSIDERATIONS
THERMAL CONSIDERATIONS
The 34830 is a high-speed amplifier, and as such requires
careful attention to be paid to the way in which boards are laid
out, in order to guarantee best performance. All high-speed
layout techniques should be followed including the following
points.
Make sure that the thermal dissipation ratings for the
34830 package are not violated in the application at hand.
The 34830 comes in a package with an exposed pad (EP).
The primary function of the EP is to serve as an effective way
to dissipate heat away from the inside of the package. Take
full advantage of this feature and connect the EP to a surface
or plane that can act as a heat sink. The EP is electrically
connected to ground. Make sure that the heat sink is also
connected to the same potential. If multiple heat generating
components are used in the application, distribute these
evenly throughout the board, so as not to create hot spots
with large temperature gradients that could violate power and
heat dissipation ratings.
1. Minimize all trace inductances by reducing trace
lengths. This is especially critical for the supply and
ground lines as well as for the output line. Boards with
multiple layers should have enough vias from the
ground plane to the chip ground connection to further
reduce inductance.
2. Make sure that a solid ground plane is available and
run all traces above it.
3. Avoid traces with 90 degree bends.
POWER DISSIPATION
4. Use a 0.1μF bypass capacitor in series with a 4.7Ω
Care must be taken not to exceed the maximum die
junction temperature of the 34830. The die junction
temperature can be calculated through the formula:
resistor as close to the VCC and GND pins of the 34830
as possible. Include a 10μF bypass capacitor at the
location on the board where VCC and GND are
connected to the external world.
T
= TA + PDISS × θJA
J
5. Try to refer all ground connections to the same point as
in a star ground configuration. Usually this point is the
middle point of the ground plane.
Where PDISS is the average power dissipation of the
device which can be calculated as PDISS = VCC*(ICC
+
VOUT(RMS)2/RLOAD).
34830
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.
EP SUFFIX (PB-FREE)
6-PIN
98ASA10819D
ISSUE A
34830
Analog Integrated Circuit Device Data
Freescale Semiconductor
18
PACKAGING
PACKAGE DIMENSIONS
EP SUFFIX (PB-FREE)
6-PIN
98ASA10819D
ISSUE A
34830
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
PACKAGING
PACKAGE DIMENSIONS
EP SUFFIX (PB-FREE)
6-PIN
98ASA10819D
ISSUE A
34830
Analog Integrated Circuit Device Data
Freescale Semiconductor
20
REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
• Initial Release
9/2008
1.0
34830
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
How to Reach Us:
Home Page:
www.freescale.com
Web Support:
http://www.freescale.com/support
USA/Europe or Locations Not Listed:
Freescale Semiconductor, Inc.
Technical Information Center, EL516
2100 East Elliot Road
Tempe, Arizona 85284
+1-800-521-6274 or +1-480-768-2130
www.freescale.com/support
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www.freescale.com/support
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters that may be
provided in Freescale Semiconductor data sheets and/or specifications can and do vary
in different applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer application by
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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners.
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© Freescale Semiconductor, Inc., 2008. All rights reserved.
MC34830
Rev. 1.0
9/2008
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