V62/09626-01YE [TI]
16-CHANNEL, 24-BIT ANALOG-TO-DIGITAL CONVERTER; 16通道， 24位模拟数字转换器
| 型号： | V62/09626-01YE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-CHANNEL, 24-BIT ANALOG-TO-DIGITAL CONVERTER |
| 文件： | 总57页 (文件大小：1040K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS1258-EP
www.ti.com
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
16-CHANNEL, 24-BIT ANALOG-TO-DIGITAL CONVERTER
Check for Samples: ADS1258-EP
1
FEATURES
APPLICATIONS
•
•
•
•
•
Medical, Avionics, and Process Control
Machine and System Monitoring
Fast Scan Multi-Channel Instrumentation
Industrial Systems
23
•
24 Bits, No Missing Codes
•
Fixed-Channel or Automatic Channel Scan
Fixed-Channel Data Rate: 125 kSPS
Auto-Scan Data Rate: 23.7 kSPS/Channel
Single-Conversion Settled Data
•
•
•
•
•
•
•
•
Test and Measurement Systems
16 Single-Ended or 8 Differential Inputs
Unipolar (5 V) or Bipolar (±2.5 V) Operation
Low Noise: 2.8 μVRMS at 1.8kSPS
0.0003% Integral Nonlinearity
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
DC Stability (typical):
0.02 μV/°C Offset Drift, 0.4 ppm/°C Gain Drift
Available in Military (–55°C/125°C) and
Industrial (–40°C/105°C) Temperature Ranges(1)
•
•
•
Open-Sensor Detection
Conversion Control Pin
•
•
•
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
Multiplexer Output for External Signal
Conditioning
•
On-Chip Temperature, Reference, Offset, Gain,
and Supply Voltage Readback
•
•
•
•
42-mW Power Dissipation
Standby, Sleep, and Power-Down Modes
8 General-Purpose Inputs/Outputs (GPIO)
32.768-kHz Crystal Oscillator or External Clock
(1) Custom temperature ranges available
DESCRIPTION
The ADS1258 is a 16-channel (multiplexed), low-noise, 24-bit, delta-sigma (ΔΣ) analog-to-digital converter (ADC)
that provides single-cycle settled data at channel scan rates from 1.8k to 23.7k samples per second (SPS) per
channel. A flexible input multiplexer accepts combinations of eight differential or 16 single-ended inputs with a
full-scale differential range of 5 V or true bipolar range of ±2.5 V when operating with a 5-V reference. The
fourth-order delta-sigma modulator is followed by a fifth-order sinc digital filter optimized for low-noise
performance.
The differential output of the multiplexer is accessible to allow signal conditioning prior to the input of the ADC.
Internal system monitor registers provide supply voltage, temperature, reference voltage, gain, and offset data.
An onboard PLL generates the system clock from a 32.768-kHz crystal, or can be overridden by an external
clock source. A buffered system clock output (15.7 MHz) is provided to drive a microcontroller or additional
converters.
Serial digital communication is handled via an SPI™ -compatible interface. A simple command word structure
controls channel configuration, data rates, digital I/O, monitor functions, etc.
Programmable sensor bias current sources can be used to bias sensors or verify sensor integrity.
The ADS1258 operates from a unipolar 5-V or bipolar ±2.5-V analog supply and a digital supply compatible with
interfaces ranging from 2.7 V to 5.25 V. The ADS1258 is available in QFN-48 and QFP-48 packages.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
SPI is a trademark of Motorola, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
ADS1258-EP
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
www.ti.com
AVDD
DVDD
VREF
GPIO[7:0]
GPIO
Internal
Monitoring
ADS1258
CS
1
DRDY
SCLK
DIN
Digital
Filter
SPI
Interface
24−Bit
ADC
16:1
Analog
Input
Analog Inputs
DOUT
MUX
START
RESET
PWDN
16
Oscillator
Control
AINCOM
AVSS
MUX
OUT
ADC
IN
Extclk
In/Out
DGND
32.768kHz
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
ORDERABLE PART
NUMBER
TOP-SIDE MARKING
TA
Package(2)
48/RTC
48/PHP
48/PHP
Tape & Reel of 250
Tray of 250
ADS1258MRTCTEP
ADS1258MPHPTEP
ADS1258IPHPREP
1258MEP
ADS1258MEP
ADS1258IEP
–55°C to 125°C
–40°C to 105°C
Tape & Reel 1000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted).(1)
ADS1258
–0.3 to 5.5
UNIT
V
AVDD to AVSS
AVSS to DGND
–2.8 to 0.3
V
DVDD to DGND
–0.3 to 5.5
V
Input Current
100, Momentary
10, Continuous
AVSS – 0.3 to AVDD + 0.3
–0.3 to DVDD + 0.3
150
mA
mA
V
Input Current
Analog Input Voltage
Digital Input Voltage to DGND
Maximum Junction Temperature
Storage Temperature Range
V
°C
°C
–60 to 150
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
2
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SBAS445C –MARCH 2009–REVISED DECEMBER 2009
ELECTRICAL CHARACTERISTICS
All specifications at TA = –55°C to 125°C, AVDD = 2.5 V, AVSS = –2.5 V, DVDD = 3.3 V, fCLK = 16 MHz (external clock) or fCLK = 15.729
MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, VREF = 4.096 V, and VREFN = –2.5 V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP(1)
MAX
UNIT
Analog Multiplexer Inputs
AIN0–AIN15,
AINCOM with respect to
DGND
AVSS –
100 mV
AVDD +
100mV
Absolute Input Voltage
V
On-Channel Resistance
Crosstalk
80
–110
1.5
24
Ω
fIN = 1 kHz
dB
SBCS[1:0] = 01
SBCS[1:0] = 11
Sensor Bias (Current Source)
μA
1.5 μA:24 μA Ratio Error
ADC Input
1
%
Full-Scale Input Voltage
Absolute Input Voltage
(VIN = ADCINP – ADCINN)
(ADCINP, ADCINN)
±1.0 6 VREF
V
V
AVSS –
100 mV
AVDD +
100mV
Differential Input Impedance
System Performance
65
kΩ
Resolution
No Missing Codes
Differential Input
24
Bits
Data Rate, Fixed-Channel Mode
Data Rate, Auto-Scan Mode
Integral Nonlinearity (INL)(2)
1.953
1.805
125
kSPS
kSPS
23.739
0.0010
0.0003
% of
FSR(3)
Chopping Off
Chopping On
20
1
Offset Error
Shorted
Inputs
TA = –40°C to 105°C
TA = –55°C to 125°C
10
μV
-650
-0.5
650
Chopping Off
Chopping On
0.5
Offset Drift
Gain Error
Gain Drift
Shorted Inputs
μV/°C
%
0.02
0.1
0.5
0.5
2
TA = –40°C to 105°C
TA = –55°C to 125°C
TA = –40°C to 105°C
TA = –55°C to 125°C
0.1
0.1
0.4
ppm/°C
0.4
Noise
(see Table 4)
Common-Mode Rejection
fCM = 60 Hz
fPS = 60 Hz
90
70
80
100
85
dB
dB
AVDD, AVSS
DVDD
Power-Supply Rejection
95
Voltage Reference Input
Reference Input Voltage
(VREF = VREFP – VREFN)
0.5
4.096
40
AVDD –
AVSS
V
Negative Reference Input (VREFN)
Positive Reference Input (VREFP)
Reference Input Impedance
System Parameters
AVSS – 0.1 V
VREFN + 0.5
VREFP – 0.5
AVDD + 0.1V
V
V
kΩ
External Reference Reading Error
Analog Supply Reading Error
1
3
3
%
%
1
Voltage
TA = 25°C
168
394
mV
Temperature Sensor Reading
Coefficient
μV/°C
Digital Input/Output
(1) TA = 25°C for typical parameters.
(2) Best straight line fit method.
(3) FSR = Full-scale range = 2.13 VREF
.
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ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = –55°C to 125°C, AVDD = 2.5 V, AVSS = –2.5 V, DVDD = 3.3 V, fCLK = 16 MHz (external clock) or
fCLK = 15.729 MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, VREF = 4.096 V, and VREFN =
–2.5 V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP(1)
MAX
DVDD
0.3 DVDD
DVDD
0.2 DVDD
10
UNIT
VIH
VIL
0.7 DVDD
DGND
V
V
Logic Levels
VOH
VOL
IOH = 2 mA
IOL = 2 mA
0.8 DVDD
DGND
V
V
Input Leakage
VIN = DVDD, GND
μA
MHz
%
Frequency
0.1
40
16
Master Clock Input (CLKIO)
Duty Cycle
60
Crystal Frequency
Clock Output Frequency
32.768
15.729
150
kHz
MHz
mS
Crystal Oscillator
(see the Crystal Oscillator
section)
Start-Up Time (Clock Output
Valid)
Clock Output Duty Cycle
40
60
%
Power Supply
DVDD
2.7
–2.6
5.25
V
V
V
AVSS
0
AVSS + 5.25
0.6
AVDD
AVSS + 4.75
External TA = –40°C to 105°C
Clock
Operation
0.25
0.25
mA
TA = –55°C to 125°C
0.75
Internal Oscillator Operation,
Clock Output Disabled
0.04
1.4
mA
mA
DVDD Supply Current
Internal Oscillator Operation,
Clock Output Enabled(4)
Power-Down(5)
Converting
Standby
1
25
12
µA
mA
mA
mA
µA
8.2
5.6
2.1
2
AVDD, AVSS Supply Current
Power Dissipation
Sleep
Power-Down
Converting
Standby
85
62
42
29
11
14
mW
mW
mW
μW
Sleep
Power-Down
(4) CLKIO load = 20 pF.
(5) No clock applied to CLKIO.
4
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SBAS445C –MARCH 2009–REVISED DECEMBER 2009
PIN CONFIGURATION
Top View
QFN
48 47 46 45 44 43 42 41 40 39 38 37
1
2
36
35
AIN3
AIN2
AIN12
AIN13
AIN1
3
34 AIN14
4
33
32
AIN0
AIN15
5
AVSS
AINCOM
AVDD
PLLCAP
XTAL1
XTAL2
PWDN
RESET
6
31 VREFP
ADS1258
7
30
29
VREFN
DGND
8
9
28 DVDD
10
11
27
26
CS
START
CLKSEL 12
25 DRDY
13 14 15 16 17 18 19 20 21 22 23 24
Top View
QFP
48 47 46 45 44 43 42 41 40 39 38 37
AIN3
AIN2
36
AIN12
1
2
35
34
33
32
31
30
29
28
27
26
25
AIN13
AIN14
AIN15
AINCOM
VREFP
VREFN
DGND
DVDD
CS
AIN1
3
AIN0
4
AVSS
5
AVDD
PLLCAP
XTAL1
XTAL2
PWDN
RESET
CLKSEL
6
ADS1258
7
8
9
10
11
12
START
DRDY
13 14 15 16 17 18 19 20 21 22 23 24
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PIN ASSIGNMENTS
ANALOG/DIGITAL
PIN #
NAME
AIN3
AIN2
AIN1
AIN0
INPUT/OUTPUT
Analog Input
Analog Input
Analog Input
Analog Input
DESCRIPTION
1
2
3
4
Analog Input 3: Single-Ended Channel 3, Differential Channel 1 (–)
Analog Input 2: Single-Ended Channel 2, Differential Channel 1 (+)
Analog Input 1: Single-Ended Channel 1, Differential Channel 0 (–)
Analog Input 0: Single-Ended Channel 0, Differential Channel 0 (+)
Negative Analog Power Supply: 0V for unipolar operation, –2.5 V for bipolar operation.
(Internally connected to exposed thermal pad of QFN package.)
5
AVSS
Analog
6
7
AVDD
PLLCAP
XTAL1
XTAL2
PWDN
RESET
Analog
Analog
Positive Analog Power Supply: 5 V for unipolar operation, 2.5 V for bipolar operation.
PLL Bypass Capacitor: Connect 22nF capacitor to AVSS when using crystal oscillator.
32.768-kHz Crystal Oscillator Input 1; see the Chrystal Oscillator section.
32.768-kHz Crystal Oscillator Input 2; see the Chrystal Oscillator section.
Power-Down Input: Hold low for minimum of two fCLK cycles to engage low-power mode.
Reset Input: Hold low for minimum of two fCLK cycles to reset the device.
8
Analog
9
Analog
10
11
Digital Input
Digital Input
Clock Select Input: Low = Activates Crystal Oscillator, fCLK output on CLKIO.
High = Disables Crystal Oscillator, apply fCLK to CLKIO.
12
CLKSEL
Digital Input
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
CLKIO
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
SCLK
Digital I/O
Digital I/O
System Clock Input/Output (See CLKSEL pin.)
General-Purpose Digital Input/Output 0
Digital I/O
General-Purpose Digital Input/Output 1
Digital I/O
General-Purpose Digital Input/Output 2
Digital I/O
General-Purpose Digital Input/Output 3
Digital I/O
General-Purpose Digital Input/Output 4
Digital I/O
General-Purpose Digital Input/Output 5
Digital I/O
General-Purpose Digital Input/Output 6
Digital I/O
General-Purpose Digital Input/Output 7
Digital Input
Digital Input
Digital Output
Digital Output
Digital Input
Digital Input
Digital
SPI Interface Clock Input: Data clocked in on rising edge, clocked out on falling edge.
SPI Interface Data Input: Data is input to the device.
SPI Interface Data Output: Data is output from the device.
Data Ready Output: Active low.
DIN
DOUT
DRDY
START
CS
Start Conversion Input: Active high.
SPI Interface Chip Select Input: Active low.
DVDD
DGND
VREFN
VREFP
AINCOM
AIN15
AIN14
AIN13
AIN12
AIN11
AIN10
AIN9
Digital Power Supply: 2.7 V to 5.25 V
Digital
Digital Ground
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Output
Analog Output
Analog Input
Analog Input
Analog Input
Analog Input
Reference Input Negative
Reference Input Positive
Analog Input Common: Common input pin to all single-ended inputs.
Analog Input 15: Single-Ended Channel 15, Differential Channel 7 (–)
Analog Input 14: Single-Ended Channel 14, Differential Channel 7 (+)
Analog Input 13: Single-Ended Channel 13, Differential Channel 6 (–)
Analog Input 12: Single-Ended Channel 12, Differential Channel 6 (+)
Analog Input 11: Single-Ended Channel 11, Differential Channel 5 (–)
Analog Input 10: Single-Ended Channel 10, Differential Channel 5 (+)
Analog Input 9: Single-Ended Channel 9, Differential Channel 4 (–)
Analog Input 8: Single-Ended Channel 8, Differential Channel 4 (+)
ADC Differential Input (–)
AIN8
ADCINN
ADCINP
MUXOUTN
MUXOUTP
AIN7
ADC Differential Input (+)
Multiplexer Differential Output (–)
Multiplexer Differential Output (+)
Analog Input 7: Single-Ended Channel 7, Differential Channel 3 (–)
Analog Input 6 : Single-Ended Channel 6, Differential Channel 3 (+)
Analog Input 5: Single-Ended Channel 5, Differential Channel 2 (–)
Analog Input 4: Single-Ended Channel 4, Differential Channel 2 (+)
AIN6
AIN5
AIN4
6
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SBAS445C –MARCH 2009–REVISED DECEMBER 2009
PARAMETER MEASUREMENT INFORMATION
CS(1)
tCSPW
tCSSC
tSCLK
tSPW
SCLK
DIN
tSPW
tDIST
tDIHD
tDOPD
Hi-Z
Hi-Z
tCSDO
DOUT
tDOHD
NOTE: (1) CS can be tied low.
Figure 1. Serial Interface Timing
SERIAL INTERFACE TIMING CHARACTERISTICS
At TA= –40°C to +105°C(1) and DVDD = 2.7 V to 5.25 V, unless otherwise noted.
SYMBOL
tSCLK
DESCRIPTION
SCLK Period
MIN
2
MAX
UNITS
(2)
τCLK
tSPW
SCLK High or Low Pulse Width (exceeding max resets SPI interface)
CS Low to First SCLK: Setup Time(4)
0.8
2.5
10
5
4096(3)
τCLK
τCLK
ns
tCSSC
tDIST
Valid DIN to SCLK Rising Edge: Setup Time
Valid DIN to SCLK Rising Edge: Hold Time
SCLK Falling Edge to Valid New DOUT: Propagation Delay(5)
SCLK Falling Edge to Old DOUT Invalid: Hold Time
CS High to DOUT Invalid (tri-state)
tDIHD
ns
tDOPD
tDOHD
tCSDO
tCSPW
20
5
ns
0
2
ns
τCLK
τCLK
CS Pulse Width High
(1) Ensured by characterization only.
(2) τCLK = master clock period = 1/fCLK
.
(3) Programmable to 256 τCLK
.
(4) CS can be tied low.
(5) DOUT load = 20 pF || 100kΩ to DGND.
tDRDY
tDDO
DRDY
DOUT
Figure 2. DRDY Update Timing
DRDY UPDATE TIMING CHARACTERISTICS
SYMBOL
t DRDY
DESCRIPTION
TYP
UNITS
τCLK
τCLK
DRDY High Pulse Width Without Data Read
Valid DOUT to DRDY Falling Edge (CS = 0)
1
tDDO
0.5
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ADS1258 48/RTC Package Operating Life Derating Chart
1 0 0 0
1 0 0
1 0
Wirebond Voiding Fail Mode
Electromigration Fail Mode
1
8 0
9 0
1 0 0
1 1 0
1 2 0
1 3 0
1 4 0
1 5 0
1 6 0
Continuous TJ (°C)
Figure 3.
Notes:
1. See datasheet for absolute maximum and minimum recommended operating conditions.
2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package
interconnect life).
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TYPICAL CHARACTERISTICS
At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal
clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise
noted.
READING HISTOGRAM
READING HISTOGRAM
3000
2500
2000
1500
1000
500
4500
4000
3500
3000
2500
2000
1500
1000
500
DRATE[1:0] = 11
16384 Points
DRATE[1:0] = 10
16384 Points
0
0
µ
µ
Offset ( V)
Offset ( V)
Figure 4.
READING HISTOGRAM
Figure 5.
READING HISTOGRAM
3500
3000
2500
2000
1500
1000
500
2500
2000
1500
1000
500
DRATE[1:0] = 00
16384 Points
DRATE[1:0] = 01
16384 Points
0
0
µ
µ
Offset ( V)
Offset ( V)
Figure 6.
Figure 7.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal
clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise
noted.
NOISE HISTOGRAM
NOISE vs INPUT VOLTAGE
20
15
10
5
20
15
10
5
50 units from two production lots.
DRATE[1:0] = 11
DRATE[1:0] = 11
DRATE[1:0] = 10
DRATE[1:0] = 01
DRATE[1:0] = 00
0
0
−
−
−
−
25
100
75
50
0
25
50
75
100
Input Voltage (%FS)
µ
RMS Noise ( V)
Figure 8.
Figure 9.
NOISE vs VREF
NOISE vs SUPPLY VOLTAGE
16
14
12
10
8
20
18
16
14
12
10
8
DRATE[1:0] = 11
DRATE[1:0] = 11
from DVDD
DRATE[1:0] = 10
6
from AVDD−AVSS
DRATE[1:0] = 01
DRATE[1:0] = 00
4
2
6
0
4
0.5
1.5
2.5
3.5
4.5
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VREF (V)
DVDD, AVDD−AVSS (V)
Figure 10.
Figure 11.
10
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal
clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise
noted.
NOISE AND OFFSET vs
NOISE vs TEMPERATURE
COMMON-MODE INPUT VOLTAGE
20
18
16
14
12
10
8
20
15
10
5
5
0
−
−
−
DRATE[1:0] = 11
OFFSET
CHOP = 1
5
NOISE
OFFSET
CHOP = 0
10
15
6
4
0
−
−
−
3
−
−
1
40
20
0
20
40
60
80
100
2
0
1
2
3
_
Temperature ( C)
Common−Mode Input Voltage (V)
Figure 12.
Figure 13.
OFFSET HISTOGRAM
OFFSET DRIFT HISTOGRAM
80
60
40
20
0
200
180
160
140
120
100
80
50 units from two
production lots.
311 units from one production lot.
CHOP = 1
_
Based on 20 C intervals
over the range of
−
_
_
40 C to +105 C.
CHOP = 1
60
40
20
0
µ
Offset ( V)
µ
_
Offset Drift ( V/ C)
Figure 14.
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal
clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise
noted.
OFFSET vs TEMPERATURE
OFFSET vs VREF
20
0
10
8
CHOP = 1, No Buffer
CHOP = 1
6
4
2
−
−
−
20
40
60
0
−
−
−
−
2
4
6
8
CHOP = 0, No Buffer
50 units from two production lots.
−
10
−
−
20
40
0
20
40
60
80
100
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VREF (V)
_
Temperature ( C)
Figure 16.
Figure 17.
OFFSET POWER-ON WARMUP
GAIN ERROR HISTOGRAM
10
8
80
60
40
20
0
Free−Air
320 units from one production lot.
6
4
2
0
−
−
−
−
2
4
6
8
−
10
0
10
20
30
40
50
60
Time After Power−On (s)
Absolute Gain Error (ppm)
Figure 18.
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal
clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise
noted.
GAIN DRIFT HISTOGRAM
GAIN ERROR vs TEMPERATURE
30
20
10
0
80
60
40
20
0
50 units from two production lots.
_
Based on 20 C intervals over the
−
_
_
range of 40 C to +105 C.
−
10
−
−
20
40
0
20
40
60
80
100
_
Temperature ( C)
_
Gain Drift (ppm/ C)
Figure 20.
Figure 21.
GAIN ERROR vs VREF
GAIN ERROR POWER-ON WARMUP
10
8
20
15
10
5
Free−Air
6
4
2
0
0
−
−
−
−
2
4
6
8
−
5
−
−
−
10
15
20
−
10
0
10
20
30
40
50
60
0.5 1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Time After Power−On (s)
VREF (V)
Figure 22.
INTEGRAL NONLINEARITY vs VREF
Figure 23.
INTEGRAL NONLINEARITY vs INPUT LEVEL
10
8
10
VREF = 5V
−
_
−
_
_
_
_
_
TA
=
40 C, 10 C, +25 C, +55 C, +85 C, +105 C
6
8
6
4
2
0
4
2
0
−
−
−
−
2
4
6
8
−
10
−
−
−
−
−
1
0.5 1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5
4
3
2
0
1
2
3
4
5
VREF (V)
VIN (V)
Figure 24.
Figure 25.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal
clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise
noted.
INTEGRAL NONLINEARITY vs TEMPERATURE
OUTPUT SPECTRUM
8
6
4
2
0
0
-20
f = 1kHz, -0.5dBFS
DRATE[1:0] = 11
65536 Points
-40
-60
-80
-100
-120
-140
-160
-180
−
−
20
40
0
20
40
60
80
100
120
1
10
100
1k
10k
100k
_
Temperature ( C)
Frequency (Hz)
Figure 26.
Figure 27.
TEMPERATURE SENSOR VOLTAGE vs TEMPERATURE
TEMPERATURE SENSOR READING HISTOGRAM
210
8
50 units from two production lots.
7
_
TA = +25 C
200
190
180
170
160
150
140
6
5
4
3
2
1
0
−
−
20
40
0
20
40
60
80
100
120
_
Temperature ( C)
_
Temperature Reading ( C)
Figure 28.
Figure 29.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal
clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise
noted.
SENSOR BIAS CURRENT SOURCE RATIO
HISTOGRAM
SENSOR BIAS CURRENT SOURCE RATIO
vs TEMPERATURE
18
17
16
15
14
25
20
15
10
5
50 units from two production lots.
0
−
−
20
40
0
20
40
60
80
100
120
_
Temperature ( C)
µ
µ
Ratio ( A/ A)
Figure 30.
Figure 31.
SUPPLY CURRENT vs TEMPERATURE
NOISE AND INL vs MASTER CLOCK
10
8
1.0
0.8
0.6
0.4
0.2
0
20
16
12
8
20
16
12
8
DRATE[1:0] = 11
AVDD, AVSS
Noise
6
4
2
4
4
DVDD
Linearity
0
0
0
−
−
20
40
0
20
40
60
80
100
120
0.1
1
10
100
_
Temperature ( C)
Master Clock (MHz)
Figure 32.
Figure 33.
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OVERVIEW
The ADS1258 is a flexible, 24-bit, low-noise ADC
optimized for fast multi-channel, high-resolution
measurement systems. The converter provides a
maximum channel scan rate of 23.7kSPS, providing a
complete 16-channel scan in less than 700μs.
VIN = (ADCINP – ADCINN), against the differential
reference input, VREF = (VREFP – VREFN). The
digital filter receives the modulator signal and
provides a low-noise digital output. The ADC channel
block controls the multiplexer Auto-Scan feature.
Channel Auto-Scan occurs at a maximum rate of
23.7kSPS. Slower scan rates can be used with
corresponding increases in resolution.
Figure 34 shows the block diagram of the ADS1258.
The input multiplexer selects the analog input pins
connected
to
the
multiplexer
output
pins
(MUXOUTP/MUXOUTN). External signal conditioning
can be used between the multiplexer output pins and
the ADC input pins (ADCINP/ADCINN) or the
multiplexer output can be routed internally to the ADC
inputs without external circuitry. Selectable current
sources within the input multiplexer can be used to
bias sensors or detect for a failed sensor. On-chip
system function readings provide readback of
temperature, supply voltage, gain, offset, and external
reference.
Communication is handled over an SPI-compatible
serial interface with a set of simple commands
providing control of the ADS1258. Onboard registers
store the various settings for the input multiplexer,
sensor detect bias, data rate selection, etc. Either an
external 32.768kHz crystal, connected to pins XTAL1
and XTAL2, or an external clock applied to pin CLKIO
can be used as the clock source. When using the
external crystal oscillator, the system clock is
available as an output for driving other devices or
controllers. General-purpose digital I/Os (GPIO)
provide input and output control of eight pins.
The ADS1258 converter comprises a fourth-order,
delta-sigma modulator followed by a programmable
digital
measures
filter.
the
The
differential
modulator
input signal,
AVDD
DVDD
PIO[7:0]
GPIO
G
CLKIO CLKSEL PLLCAP XTAL2
Clock Control
XTAL1
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
Sensor
Bias
CS
SCLK
DIN
SPI
Interface
DOUT
Supply Monitor
Temperature
DRDY
PWDN
RESET
START
AIN6
AIN7
Control
Logic
16−Channel
MUX
ADC Channel Control
AIN8
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
AINCOM
Internal Ref
Ext Ref Monitor
ADC
Digital Filter
OUTN
MUX
CINN VREFN VREFP
AD
M
UXOUTP
ADCINP
GND
AVSS
Figure 34. ADS1258 Block Diagram
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MULTIPLEXER INPUTS
A simplified diagram of the input multiplexer is
illustrated in Figure 36. The multiplexer connects one
of 16 single-ended external inputs, one of eight
differential external inputs, or one of the on-chip
internal variables to the ADC inputs. The output of the
channel multiplexer can be routed to external pins
and then to the input of the ADC. This flexibility
allows for use of external signal conditioning. See the
External Multiplexer Loop section.
AVDD
ESD
Diodes
VREFP
VREFN
Ω
Reff = 40k
3pF
(fCLK = 16MHz)
ESD diodes protect the analog inputs. To keep these
diodes from turning on, make sure the voltages on
the input pins do not go below AVSS by more than
100 mV, and likewise do not exceed AVDD by more
than 100 mV:
ESD
Diodes
AVSS – 100mV < (Analog Inputs) < AVDD + 100 mV.
AVSS
Overdriving the multiplexer inputs may affect the
conversions of other channels. See the Input
Overload Protection description in the Hardware
Considerations segment of the Applications section.
Figure 35. Simplified Reference Input Circuit
ESD diodes protect the reference inputs. To keep
these diodes from turning on, make sure the voltages
on the reference pins do not go below AVSS by more
than 100mV, and likewise do not exceed AVDD by
100mV, as described in Equation 1:
The converter supports two modes of channel access
through the multiplexer: the Auto-Scan mode and the
Fixed-Channel mode. These modes are selected by
the MUXMOD bit of register CONFIG0. The
Auto-Scan mode scans through the selected
channels automatically, with break-before-make
switching. The Fixed-Channel mode requires the user
to set the channel address for each channel
measured.
ǒ
Ǔ
AVSS * 100mV t VREFP or VREFN t AVDD ) 100mV
(1)
A high-quality reference voltage is essential for
achieving the best performance from the ADS1258.
Noise and drift on the reference degrade overall
system performance. It is especially critical that
special care be given to the circuitry that generates
the reference voltages and the layout when operating
in the low-noise settings (that is, with low data rates)
to prevent the voltage reference from limiting
performance. See the Reference Inputs description in
the Hardware Considerations segment of the
Applications section.
VOLTAGE REFERENCE INPUTS
(VREFP, VREFN)
The voltage reference for the ADS1258 ADC is the
differential voltage between VREFP and VREFN:
VREF = VREFP – VREFN. The reference inputs use a
structure similar to that of the analog inputs with the
circuitry on the reference inputs shown in Figure 35.
The load presented by the switched capacitor can be
modeled with an effective resistance (Reff) of 40 kΩ
for fCLK = 16 MHz. Note that the effective impedance
of the reference inputs loads an external reference
with a non-zero source impedance.
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VREFP
VREFN
Multiplexer
Reference/Gain Monitor
AIN0
AIN1
AIN2
Temperature Sensor Monitor
AVDD
AIN3
1x
2x
AIN4
AIN5
8x
1x
AIN6
AVSS
AIN7
Supply Monitor
AIN8
AVDD
AVSS
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
AINCOM
NOTE: ESD diodes not shown.
Internal
Reference
AVSS
ADC
−
(AVDD AVSS)/2
AVSS AVDD
Sensor Bias
Offset Monitor
Figure 36. Input Multiplexer
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ADC INPUTS
As with the multiplexer and reference inputs, ESD
diodes protect the ADC inputs. To keep these diodes
from turning on, make sure the voltages on the input
pins do not go below AVSS by more than 100 mV,
and likewise do not exceed AVDD by more than 100
mV.
The ADS1258 ADC inputs (ADCINP, ADCINN)
measure the input signal using internal capacitors
that are continuously charged and discharged. The
left side of Figure 38 shows a simplified schematic of
the ADC input circuitry; the right side of Figure 38
shows the input circuitry with the capacitors and
switches replaced by an equivalent circuit. Figure 37
shows the ON/OFF timings of the switches shown in
Figure 38. S1 switches close during the input
sampling phase. With S1 closed, CA1 charges to
ADCINP, CA2 charges to ADCINN, and CB charges to
(ADCINP – ADCINN). For the discharge phase, S1
opens first and then S2 closes. CA1 and CA2 discharge
to approximately AVSS + 1.3 V and CB discharges to
0V. This two-phase sample/discharge cycle repeats
tSAMPLE
ON
S1
OFF
ON
S2
OFF
with a period of tSAMPLE = 2/fCLK
.
Figure 37. S1 and S2 Switch Timing for Figure 38
The charging of the input capacitors draws a transient
current from the source driving the ADS1258 ADC
inputs. The average value of this current can be used
to calculate an effective impedance (Reff) where Reff
=
VIN/IAVERAGE. These impedances scale inversely with
fCLK. For example, if fCLK is reduced by a factor of
two, the impedances double.
AVSS + 1.3V
S2
AVSS + 1.3V
Ω
Ω
ReffA = 190k
CA1 = 0.65pF
S1
Equivalent
Circuit
ADCINP
ADCINN
ADCINP
ADCINN
Ω
ReffB = 78k
(fCLK = 16MHz)
CB = 1.6pF
S1
ReffA = 190k
CA2 = 0.65pF
S2
AVSS + 1.3V
RAIN = ReffB || 2ReffA
Reff = tSAMPLE/CX
AVSS + 1.3V
NOTE: ESD input diodes not shown.
Figure 38. Simplified ADC Input Structure
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MASTER CLOCK (fCLK
)
The ADS1258 oversamples the analog input at a high
rate. This requires a high-frequency master clock to
be supplied to the converter. As shown in Figure 39,
the clock comes from either an internal oscillator (with
external crystal), or an external clock source.
50
Ω
Clock Output
(15.729MHz)
CLKIO
0V to −2.5V
AVSS
CLKSEL XTAL1
XTAL2 PLLCAP
CLKENB
Bit
32.768kHz(1)
22nF
4.7pF
4.7pF
Internal Master Clock (fCLK
)
NOTE: (1) Parallel resonant type, C = 12.5pF, ESR = 35k (max).
Ω
L
Place the crystal and load capacitors as close as possible to the device pins.
MUX
CLKIO
Figure 40. Crystal Oscillator Connection
Table 1. System Clock Source
Oscillator
and PLL
CLKSEL
PIN
CLKENB
BIT
CLKSEL
XTAL1
XTAL2
PLL
CLOCK SOURCE
CLKIO FUNCTION
32.768 kHz
Crystal Oscillator
Disabled
(internally grounded)
0
0
Figure 39. Clock Generation Block Diagram
32.768 kHz
Crystal Oscillator
0
1
1
Output (15.729 MHz)
Input (16 MHz)
The CLKSEL pin determines the source of the
system clock, as shown in Table 1. The CLKIO pin
functions as an input or as an output. When the
CLKSEL pin is set to '1', CLKIO is configured as an
input to receive the master clock. When the CLKSEL
pin is set to '0', the crystal oscillator generates the
clock. The CLKIO pin can then be configured to
output the master clock. When the clock output is not
needed, it can be disabled to reduce device power
consumption.
External Clock Input
X
Table 2. Approved Crystal Vendors
VENDOR
Epson
CRYSTAL PRODUCT
C-001R
External Clock Input
When using an external clock to operate the device,
apply the master clock to the CLKIO pin. For this
mode, the CLKSEL pin is tied high. CLKIO then
becomes an input, as shown in Figure 41.
Crystal Oscillator
An on-chip oscillator and Phase-Locked Loop (PLL)
together with an external crystal can be used to
generate the system clock. For this mode, tie the
CLKSEL pin low. A 22nF PLL filter capacitor,
connected from the PLLCAP pin to the AVSS pin, is
required. The internal clock of the PLL can be output
to the CLKIO to drive other converters or controllers.
If not used, disable the clock output to reduce device
power consumption; see Table 1 for settings. The
clock output is enabled by a register bit setting
(default is ON). Figure 40 shows the oscillator
connections. Place these components as close to the
pins as possible to avoid interference and coupling.
Do not connect XTAL1 or XTAL2 to any other logic.
The oscillator start-up time may vary, depending on
the crystal and ambient temperature. The user should
verify the oscillator start-up time.
Ω
50
Clock Input
(16MHz)
CLKIO
2.7V
to 5V
DVDD
CLKSEL XTAL1 XTAL2 PLLCAP
No Connection
Figure 41. External Clock Connection
Make sure to use a clock source clean from jitter or
interference. Ringing or under/overshoot should be
avoided. A 50 Ω resistor in series with the CLKIO pin
(placed close to the source) can often help.
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ADC
rate—filter more for higher resolution, filter less for
higher data rate. The filter is comprised of two
sections, a fixed filter followed by a programmable
filter. Figure 42 shows the block diagram of the filter.
Data is supplied to the filter from the analog
modulator at a rate of fCLK/2. The fixed filter is a
fifth-order sinc filter with a decimation value of 64 that
outputs data at a rate of fCLK/128. The second stage
of the filter is a programmable averager (first-order
sinc filter) with the number of averages set by the
DRATE[1:0] bits.
The ADC block of the ADS1258 is composed of two
blocks: a modulator and a digital filter.
Modulator
The modulator converts the analog input voltage into
a Pulse Code Modulated (PCM) data stream. When
the level of differential analog input (ADCINP –
ADCINN) is near the level of the reference voltage,
the '1' density of the PCM data stream is at its
highest. When the level of the differential analog input
is near zero, the PCM '0' and '1' densities are nearly
equal. The fourth-order modulator shifts the
quantization noise to a high frequency (out of the
passband) where the digital filter can easily remove it.
The data rate depends upon the system clock
frequency (fCLK) and the converter configuration. The
data rate can be computed by Equation 2 or
Equation 3:
Data Rate (Auto-Scan):
The modulator continuously chops the input, resulting
in excellent offset and offset drift performance. It is
important to note that offset or offset drift originating
from the external circuitry is not removed by the
modulator chopping. These errors can be effectively
removed by using the external chopping feature of
the ADS1258 (see the External Chopping section).
fCLK
11b*DR
CHOP
(
)
) 4.265625 ) TD 2
128 4
(2)
(3)
Data Rate (Fixed-Channel Mode):
fCLK
11b*DR
CHOP
(
(
))
128 4
) CHOP 4.265625 ) TD 2
Where:
Digital Filter
DR = DRATE[1:0] register bits (binary).
CHOP = Chop register bit.
TD = time delay value given in Table 5 from the
DLY[2:0] register bits (128/fCLK periods).
The programmable low-pass digital filter receives the
modulator output and produces a high-resolution
digital output. By adjusting the amount of filtering,
tradeoffs can be made between resolution and data
Modulator Rate = fCLK/2
Data Rate = fCLK/128 Data Rate(1) = fCLK/(128 Num_Ave)
×
sinc5
Filter
Programmable
Averager
Analog
Modulator
Num_Ave
NOTE: (1) Data rate for Fixed−Channel Mode, Chop = 0, Delay = 0.
Figure 42. Block Diagram of Digital Filter
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Table 3 shows a listing of the averaging and data
rates for each of the four DRATE[1:0] register
settings for the Auto-Scan and Fixed-Channel modes,
with CHOP, DLY = 0. Note that the data rate scales
directly with fCLK. For example, reducing fCLK by 2x
reduces the maximum data rate by 2x.
Figure 44 shows the response with averaging set to 4
(DRATE[1:0]
=
10). 4-reading, post-averaging
produces three equally-spaced notches between
each main notch of the sinc5 filter. The frequency
response of DRATE[1:0] = 01 and 00 follows a similar
pattern, but with 15 and 63 equally-spaced notches
between the main sinc5 notches, respectively.
FREQUENCY RESPONSE
0
The low-pass digital filter sets the overall frequency
response for the ADS1258. The filter response is the
product of the responses of the fixed and
programmable filter sections and is given by
Equation 4:
Data Rate
Auto−Scan Mode
(23.739kSPS)
−
−
−
−
20
40
60
80
Data Rate
Fixed−Channel Mode
(125kSPS)
Ť
Ť
Ť
f Ť H
5
ǒf ǓŤ +
ǒ Ǔ
5 ǒ Ǔ
H f + ŤH
sinc
Averager
128p Num_Ave f
128p f
CLK
sinǒ Ǔ
sinǒ
Ǔ
ȧ
−
−
−
ȧ
ȧ
ȧ ȧ
100
120
140
f
f
CLK
ȧ ȧ
ȧ
ȧ
2p f ȧ ȧ
128p f ȧ
64 sinǒ Ǔ Num_Ave sinǒ Ǔ
f
f
ȧ
ȧ ȧ
ȧ
CLK
CLK
(4)
0
125
250
375
500
625
The digital filter attenuates noise on the modulator
output including noise from within the ADS1258 and
external noise present within the ADS1258 input
signal. Adjusting the filtering by changing the number
of averages used in the programmable filter changes
Frequency (kHz)
Figure 43. Frequency Response, DRATE[1:0] = 11
the filter bandwidth. With
a higher number of
averages, the bandwidth is reduced and more noise
is attenuated.
0
Data Rate
Auto−Scan Mode
(15.123kSPS)
−
−
−
−
20
40
60
80
The low-pass filter has notches (or zeros) at the data
output rate and multiples thereof. The sinc5 part of
the filter produces wide notches at fCLK/128 and
multiples thereof. At these frequencies, the filter has
zero gain. Figure 43 shows the response with no post
averaging. Note that in Auto-Scan mode, the data
rate is reduced while retaining the same frequency
response as in Fixed-Channel mode.
Data Rate
Fixed−Channel Mode
(31.25kSPS)
−
−
−
100
120
140
With programmable averaging, the wide notches
produced by the sinc5 filter remain, but a number of
narrow notches are superimposed in the response.
The number of the superimposed notches is
0
125
250
375
500
625
Frequency (kHz)
determined
by
the
number
of
readings
averaged (minus one).
Figure 44. Frequency Response, DRATE[1:0] = 10
Table 3. Data Rates(1)
DATA RATE AUTO-SCAN
MODE (SPS)(3)
DATA RATE FIXED-CHANNEL
MODE (SPS)
–3dB BANDWIDTH
(Hz)
DRATE[1:0]
Num_Ave(2)
11
10
01
00
1
4
23739
15123
6168
125000
31250
7813
25390
12402
3418
869
16
64
1831
1953
(1) fCLK = 16 MHz, Chop = 0, and Delay = 0.
(2) Num_Ave is the number of averages performed by the digital filter second stage.
(3) In Auto-Scan mode, the data rate listed is for a single channel; the effective data rate for multiple channels (on a per-channel basis) is
the value shown in Figure 43 and Figure 44 divided by the number of active channels in a scan loop.
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ALIASING
input. For most modes of operation, the analog input
must be stable for one complete conversion cycle to
provide settled data. In Fixed-Channel mode
(DRATE[1:0] = 11), the input must be stable for five
complete conversion cycles.
The digital filter low-pass characteristic repeats at
multiples of the modulator rate of fCLK/2. Figure 45
shows the response plotted out to 16MHz at the data
rate of 125 kSPS (Fixed-Channel mode). Notice how
the responses near DC, 8 MHz, and 16 MHz are the
same. The digital filter attenuates high-frequency
noise on the ADS1258 inputs up to the frequency
where the response repeats. However, noise or
frequency components present on the analog input
where the response repeats alias into the passband.
For most applications, an anti-alias filter is
Data Not Settled
1
Settled Data
2
DRDY
Step Input
recommended to remove the noise.
A simple
first-order input filter with a pole at 200kHz provides
–34dB rejection at the first image frequency.
Figure 46. Asynchronous Step-Input Settling
Time (DRATE[1:0] = 10, 01, 00)
0
DRATE[1:0] = 11
−
−
−
−
20
40
60
80
125kSPS
Fixed−Channel Mode
Data Not Settled
1
Settled Data
6
DRDY
2
Step Input
−
−
−
100
120
140
Figure 47. Asynchronous Step-Input Settling
Time (Fixed-Channel Mode, DRATE[1:0] = 11)
0
4
8
12
16
Frequency (MHz)
NOISE PERFORMANCE
Figure 45. Frequency Response Out to 16MHz
The ADS1258 offers outstanding noise performance
that can be optimized by adjusting the data rate. As
the averaging is increased by reducing the data rate,
Referring to Figure 43 and Figure 44, frequencies
present on the analog input above the Nyquist rate
(sample rate/2) are first attenuated by the digital filter
and then alias into the passband.
noise drops correspondingly. See Table
4 for
Input-Referred Noise, Noise-Free Resolution, and
Effective Number of Bits (ENOB). The noise
performance of low-level signals can be improved
substantially by using external gain. Note that when
Chop = 1, the data rate is reduced by 2x and the
noise is reduced by 1.4x.
SETTLING TIME
The design of the ADS1258 provides fully-settled
data when scanning through the input channels in
Auto-Scan mode. The DRDY flag asserts low when
the data for each channel is ready. It may be
necessary to use the automatic switch time delay
feature to provide time for settling of the external
buffer and associated components after channel
switching. When the converter is started (START pin
transitions high or Start Command) with stable inputs,
the first converter output is fully settled. When
applying asynchronous step inputs, the settling time
is somewhat different. The step-input settling time
diagrams (Figure 46 and Figure 47) show the
converter step response with an asynchronous step
ENOB is defined in Equation 5:
ǒ
Ǔ
ln FSRńRMS Noise
ENOB +
ln(2)
(5)
where FSR is the full-scale range.
The data for the Noise-Free Resolution (bits) is
calculated in the same way as ENOB, except
peak-to-peak noise is used.
As seen in the illustration of Noise vs VREF
(Figure 10), the converter noise is relatively constant
versus
the
reference
voltage.
Optimum
signal-to-noise ratio of the converter is achieved by
using higher reference voltages (VREF MAX = AVDD –
AVSS).
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Table 4. Noise Performance(1)
DATA RATE
EFFECTIVE
DATA RATE
AUTO-SCAN MODE
(SPS)
FIXED-CHANNEL
INPUT-REFERRED
NOISE
NOISE-FREE
RESOLUTION
(Bits)
NUMBER
OF BITS
(ENOB)
MODE
(SPS)
DRATE[1:0]
(µVRMS
)
11
10
01
00
23739
15123
6168
125000
31250
7813
12
16.8
17.4
18.2
18.9
19.5
20.1
20.9
21.6
7.9
4.5
1831
1953
2.8
(1) VREF = 4.096V, fCLK = 16MHz, Chop = 0, Delay = 0, Inputs shorted, and 2048 sample size.
Table 5. Effective Data Rates with Switch-Time Delay (Auto-Scan Mode)(1)
TIME DELAY
TIME DELAY
DLY[2:0]
000
(128/fCLK periods)
(μS)
DRATE[1:0] = 11
23739
DRATE[1:0] = 10
15123
DRATE[1:0] = 01
6168
DRATE[1:0] = 00
1831
0
1
0
001
8
19950
13491
5878
1805
010
2
16
17204
12177
5614
1779
011
4
32
13491
10191
5151
1730
100
8
64
9423
7685
4422
1639
101
16
32
48
128
256
384
5878
5151
3447
1483
110
3354
3104
2392
1247
111
2347
2222
1831
1075
(1) Time delay and data rates scale with fCLK. If Chop = 1, the data rates are half those shown. fCLK = 16MHz, Auto-Scan Mode.
Use of the switch time delay register reduces the
EXTERNAL MULTIPLEXER LOOP
effective channel data rate. Table 5 shows the actual
data rates derived from Equation 2, when using the
switch time delay feature.
The external multiplexer loop consists of two
differential multiplexer output pins and two differential
ADC input pins. The user may use external
components (buffering/filtering, single-ended to
When pulse converting, where one channel is
converted with each START pin pulse or each pulse
command, the application software may provide the
required time delay between pulses. However, with
Chop = 1, the switch time delay feature may still be
necessary to allow for settling.
differential conversion, etc.), forming
a
signal
conditioning loop. For best performance, the ADC
input should be buffered and driven differentially.
To bypass the external multiplexer loop, connect the
ADC input pins directly to the multiplexer output pins,
or select internal bypass connection (BYPASS = 0 of
CONFIG0). Note that the multiplexer output pins are
active regardless of the bypass setting.
In estimating the time delay that may be required,
Table 6 lists the time delay-to-time constant ratio (t/τ)
and the corresponding final settled data in % and
number of bits.
SWITCH TIME DELAY
Table 6. Settling Time
When using the ADS1258 in the Auto-Scan mode,
where the converter automatically switches from one
channel to the next, the settling time of the external
signal conditioning circuit becomes important. If the
channel does not fully settle after the multiplexer
channel is switched, the data may not be correct. The
ADS1258 provides a switch time delay feature which
automatically provides a delay after channel switching
to allow the channel to settle before taking a reading.
The amount of time delay required depends primarily
on the settling time of the external signal conditioning.
Additional consideration may be needed to account
for the settling of the input source arising from the
transient generated from channel switching.
FINAL SETTLING
(%)
FINAL SETTLING
(Bits)
t/τ(1)
1
63
95
2
5
3
5
99.3
7
7
99.9
10
14
20
24
10
15
17
99.995
99.9999
99.999994
(1) Multiple time constants can be approximated by:
(τ1 2 + τ2 2+…).
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SENSOR BIAS
The current source is connected to the output of the
multiplexer. For unselected channels, the current
source is not connected. This configuration means
that when a new channel is selected, the current
source charges stray sensor capacitance, which may
slow the rise of the sensor voltage. The automatic
switch time delay feature can be used to apply an
appropriate time delay before a conversion is started
to provide fully settled data (see the Switch Time
Delay section).
An integrated current source provides a means to
bias an external sensor (for example, a diode
junction); or, it verifies the integrity of a sensor or
sensor connection. When the sensor fails to an open
condition, the current sources drive the inputs of the
converter to positive full-scale. The biasing is in the
form of differential currents (programmable 1.5μA or
24μA), connected to the output of the multiplexer.
Figure 48 shows a simplified diagram of ADS1258
input structure with the external sensor modeled as a
resistance RS between two input pins. The two 80Ω
series resistors, RMUX, model the ADS1258 internal
resistances. RL represents the effective input
resistance of the ADC input or external buffer. When
the sensor bias is enabled, they source ISDC to one
selected input pin (connected to the MUXOUTP
channel) and sink ISDC from the other selected input
pin (connected to the MUXOUTN channel). The
signal measured with the biasing enabled equals the
total IR drop: ISDC[(2RMUX + RS)
׀׀
RL]. Note that when the sensor is a direct short (that is, RS = 0), there is
still a small signal measured by the ADS1258 when
the biasing is enabled: ISDC[2RMUX
׀׀
RL]. The time to charge the external capacitance is given
in Equation 6:
ISDC
C
dV
dt
+
(6)
It is also important to note that the low impedance
(65kΩ) of the direct ADC inputs or the impedance of
the external signal conditioning loads the current
sources. This low impedance limits the ability of the
current source to pull the inputs to positive full-scale
for open-channel detection.
OPEN-SENSOR DETECTION
For open-sensor detection, set the biasing to either
1.5μA or 24μA. Then select the channel and read the
output code. When a sensor opens, the positive input
is pulled to AVDD and the negative input is pulled to
AVSS. Because of this configuration, the output code
trends toward positive full-scale. Note that the
interaction of the multiplexer resistance with the
current source may lead to degradation in converter
linearity. It is recommended to enable the current
source only periodically to check for open inputs and
discard the associated data.
AVDD
ISDC
Ω
Ω
80
MUXOUTP
MUXOUTN
ADCINP
ADCINN
RS
RL
80
EXTERNAL DIODE BIASING
The current source can be used to bias external
diodes for temperature sensing. Scan the appropriate
channels with the current source set to 24µA.
Re-scan the same channels with the current source
set to 1.5µA. The difference in diode voltage readings
resulting from the two bias currents is directly
proportional to temperature.
ISDC
AVSS
Note that errors in current ratio, diode and cable
resistance, or the non-ideality factor of the diode can
lead to errors in temperature readings. These effects
can be compensated by characterization or by
calibrating the diode at known temperatures.
Figure 48. Sensor Bias Structure
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EXTERNAL CHOPPING
GPIO DIGITAL PORT (GPIOx)
The modulator of the ADS1258 incorporates a
chopping front-end which removes offset errors,
providing excellent offset and offset drift performance.
However, offset and offset drift originating from
external signal conditioning are not removed by the
modulator. The ADS1258 has an additional chopping
feature that removes external offset errors (CHOP =
1).
The ADS1258 has eight dedicated pins for
General-Purpose Digital I/O (GPIO). The digital I/O
pins are individually configurable as either inputs or
as outputs through the GPIOC (GPIO-Configure)
register. The GPIOD (GPIO-Data) register controls
the level of the pins. When reading the GPIOD
register, the data returned is the level of the pins,
whether they are programmed as inputs or outputs.
As inputs, a write to the GPIOD has no effect. As
outputs, a write to the GPIOD sets the output value.
With external chopping enabled, the converter takes
two readings in succession on the same channel. The
first reading is taken with one polarity and the second
reading is taken with the opposite polarity. The
converter averages the two readings, canceling the
offset, as shown in Figure 49. With chopping enabled,
the effective reading is reduced to half of the nominal
reading rate.
During Standby and Power-Down modes, the GPIO
remains active. If configured as inputs, they must be
driven (do not float). If configured as outputs, they
continue to drive the pins. The GPIO pins are set as
inputs after power-on or after a reset. Figure 50
shows the GPIO port structure.
Multiplexer
(chopping)
GPIO Data (read)
MUXOUTP
ADCINP
GPIO Pin
AINn
AINn
Optional
Signal
Conditioning
ADC
GPIO Data (write)
MUXOUTN
ADCINN
GPIO Control
Figure 49. External Chopping
Figure 50. GPIO Port Pin
Note that since the inputs are reversed under control
of the ADS1258, a delay time may be necessary to
provide time for external signal conditioning to fully
settle before the second phase of the reading
sequence starts (see the Switch time Delay section).
POWER-DOWN INPUT (PWDN)
The PWDN pin is used to control the power-down
mode of the converter. In power-down mode, all
internal circuitry is deactivated including the oscillator
and the clock output. Hold PWDN low for at least two
fCLK cycles to engage power-down. The register
settings are retained during power-down. When the
pin is returned high, the converter requires a wake-up
time before readings can be taken, as shown in the
Power-Up Timing section. Note that in power-down
mode, the inputs of the ADS1258 must still be driven
and the device continues to drive the outputs.
External chopping can be used to significantly reduce
total offset errors (to less than 10μV) and offset drift
over temperature (to less than 0.2μV/°C). Note that
chopping must be disabled (CHOP = 0) to take the
internal monitor readings.
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Table 7. Wake-Up Times
POWER-UP TIMING
tWAKE
When powering up the device or taking the PWDN
pin high to wake the device, a wake-up time is
required before readings can be taken. When using
the internal oscillator, the wake-up time is composed
of the oscillator start-up time and the PLL lock time,
and if the supplies are also being powered, there is a
reset interval time of 218 fCLK cycles. Note that CLKIO
is not valid during the wake-up period, as shown in
Figure 51.
INTERNAL
tWAKE
EXTERNAL CLOCK
CONDITION
PWDN or CLKSEL
AVDD – AVSS
OSCILLATOR(1)
tOSC
tOSC + 218/fCLK
2/fCLK
218/fCLK
POWER-UP SEQUENCE
The analog and digital supplies should be applied
before any analog or digital input is driven. The power
supplies may be sequenced in any order. The internal
master reset signal is generated from the analog
power supply (AVDD – AVSS), when the level
reaches approximately 3.2 V. The power-up master
reset signal is functionally the same as the Reset
Command and the RESET input pin.
CLKIO
tWAKE
PWDN
or
Reset Input (RESET)
CLKSEL
When RESET is held low for at least two fCLK cycles,
all registers are reset to their default values and the
digital filter is cleared. When RESET is released high,
the device is ready to convert data.
or
(1)
−
AVDD AVSS
Device Ready
3.2V, typical
Clock Select Input (CLKSEL)
NOTE: (1) Shown with DVDD stable.
This pin selects the source of the system clock: the
crystal oscillator or an external clock. Tie CLKSEL
low to select the crystal oscillator. When using an
external clock (applied to the CLKIO pin), tie CLKSEL
high.
Figure 51. Device Wake Time with
Internal Oscillator
When using the device with an external clock, the
wake-up time is 2/fCLK periods when waking up with
the PWDN pin and 218/fCLK periods when powering
the supplies, all after a valid CLKIO is applied, as
shown in Figure 52.
Clock Input/Output (CLKIO)
This pin serves either as a clock output or clock input,
depending on the state of the CLKSEL pin. When
using an external clock, apply the clock to this pin
and set the CLKSEL pin high. When using the
internal oscillator, this pin has the option of providing
a clock output. The CLKENB bit of register CONFIG0
enables the clock output (default is enabled).
tWAKE
CLKIO
Start Input (START)
PWDN,
CLKSEL
The START pin is an input that controls the ADC
process. When the START pin is taken high, the
converter starts converting the selected input
channels. When the START pin is taken low, the
conversion in progress runs to completion and the
converter is stopped. The device then enters one of
the two idle modes (see the Idle Modes section for
more details). See the Conversion Control section for
details of using the START pin.
or
AVDD AVSS(1)
−
Device Ready
3.2V, typical
NOTE: (1) Shown with DVDD stable.
Figure 52. Device Wake Time with External Clock
Table 7 summarizes the wake-up times using the
internal oscillator and the external clock operations.
(1) Wake-up times for the internal oscillator operation are typical
and may vary depending on crystal characteristics and layout
capacitance. The user should verify the oscillator start-up
times (tOSC = oscillator start-up time).
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Data Ready Output (DRDY)
DRDY is usually connected to an interrupt of a
controller, DSP, or connected to a controller port pin
for polling in a software loop. Channel data can be
read without the use of DRDY. Read the data using
the register format read and check the Status Byte
when the NEW bit = 1, which indicates new channel
data.
The DRDY pin is an output that asserts low to
indicate when new channel data is available to read
(the previous conversion data is lost). DRDY returns
high after the first falling edge of SCLK during a data
read operation. If the data is not read (no SCLK
pulses), DRDY remains low until new channel data is
available once again. DRDY then pulses high, then
low to indicate new data is available; see Figure 53.
Output Data Scaling and Over-Range
The ADS1258 is scaled such that the output data
code resulting from an input voltage equal to ±VREF
DRDY
has
a
margin of 6.6% before clipping. This
architecture allows operation of applied input signals
at or near full-scale without overloading the converter.
SCLK
Specifically, the device is calibrated so that:
1LSB = VREF/780000h,
DRDY with SCLK
and the output clips when:
tDRDYPLS
DRDY
|VIN| ≥ 1.06 × VREF
.
Table 8 summarizes the ideal output codes versus
input signals.
SCLK
DRDY without SCLK
1
tDRDYPLS
=
fCLK
Figure 53. DRDY Timing
(See Figure 2 for the DRDY Pulse)
Table 8. Ideal Output Code vs Input Signal
INPUT SIGNAL VIN
(ADCINP – ADCINN)
IDEAL OUTPUT CODE(1)
7FFFFFh
DESCRIPTION
≥ +1.06 VREF
Maximum Positive Full-Scale Before Output Clipping
+VREF
780000h
VIN = +VREF
+1.06 VREF/(223 – 1)
0
000001h
+1LSB
000000h
Bipolar Zero
–1.06 VREF/(223 – 1)
FFFFFFh
–1LSB
–VREF
87FFFFh
VIN = –VREF
≤ –1.06 VREF × (223/223 – 1)
800000h
Maximum Negative Full-Scale Before Output Clipping
(1) Excludes effects of noise, linearity, offset, and gain errors.
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INTERNAL SYSTEM READINGS
Analog Power-Supply Reading (VCC)
The scale factor of Equation 9 converts the code
value to external reference voltage:
Code
786432
( )
External Reference V +
(9)
The analog power-supply voltage of the ADS1258
can be monitored by reading the VCC register. The
supply voltage is routed internal to the ADS1258 and
is measured and scaled using an internal reference.
The supply readback channel outputs the difference
between AVDD and AVSS (AVDD – AVSS), for both
single and dual configurations. Note that it is required
to disable chopping (CHOP = 0) prior to taking this
reading.
This readback function can be used to check for
missing or an out-of-range reference. If the reference
input pins are floating (not connected), internal
biasing pulls them to the AVSS supply. This causes
the output code to tend toward '0'. Bypass capacitors
connected to the external reference pins may slow
the response of the pins when open. When reading
this register immediately after power-on, verify that
the reference has settled to ensure an accurate
reading. Note that it is required to disable chopping
(CHOP = 0) prior to taking this reading.
The scale factor of Equation 7 converts the code
value to volts:
Code
786432
( )
Total Analog Supply Voltage V +
(7)
Temperature Reading (TEMP)
When the power supply falls below the minimum
specified operating voltage, the full operation of the
ADS1258 cannot be ensured. Note that when the
total analog supply voltage falls to below
approximately 4.3 V the returned data is set to zero.
The SUPPLY bit in the status byte is then set. The bit
is cleared when the total supply voltage rises
approximately 50 mV higher than the lower trip point.
The ADS1258 contains an on-chip temperature
sensor. This sensor uses two internal diodes with one
diode having a current density of 16x of the other.
The difference in current densities of the diodes
yields a difference voltage that is proportional to
absolute temperature.
As a result of the low thermal resistance of the
package to the printed circuit board (PCB), the
internal device temperature tracks the PCB
temperature closely. Note also that self-heating of the
The digital supply (DVDD) may be monitored by
looping-back the supply voltage to an input channel.
A resistor divider may be required for bipolar supply
operation to reduce the DVDD level to within the
range of the analog supply.
ADS1258 causes
a
higher reading than the
temperature of the surrounding PCB. Note that it is
required to disable chopping (CHOP = 0) prior to
taking this reading.
Gain Reading (GAIN)
The scale factor of Equation 10 converts the
temperature reading to °C. Before using the equation,
the temperature reading code must first be scaled to
μV.
In this configuration, the external reference is
connected both to the analog input and to the
reference input of the ADC. The data from this
register indicates the gain of the device.
Temp Reading(mV) * 168, 000mV
Temperature(°C) + ƪ
ƫ) 25°C
The following scale factor (Equation 8) converts the
code value to device gain:
394mVń°C
(10)
Code
7864320
ǒ
Ǔ
Device Gain VńV +
(8)
Offset Reading (OFFSET)
To correct the device gain error, the user software
can divide each converter data value by the device
gain. Note that this corrects only for gain errors
originating within the ADC; system gain errors
because of an external gain stage error or because of
reference errors are not compensated. Note that it is
required to disable chopping (CHOP = 0) also prior to
taking this reading.
The differential output of the multiplexer is shorted
together and set to a common-mode voltage of
(AVDD – AVSS)/2. Ideally, the code from this register
function is 0h, but varies because of the noise of the
ADC and offsets stemming from the ADC and
external signal conditioning. This register can be used
to calibrate or track the offset of the ADS1258 and
external signal conditioning. The chop feature of the
ADC can automatically remove offset and offset drift
from the external signal conditioning; see the External
Chopping section.
Reference Reading (REF)
In this configuration, the external reference is
connected to the analog input and an internal
reference is connected to the reference of the ADC.
The data from this register indicates the magnitude of
the external reference voltage.
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Pulse Convert Command
CONVERSION CONTROL
Figure 55 also shows the start of conversions with the
rising edge of the START pin. If the START pin is
taken high, and then low prior to completion of the
conversion cycle (8 τCLK before DRDY asserts low),
only the current channel is converted and the device
enters the standby or sleep modes waiting for a new
start condition. Figure 56 shows the START pin to
DRDY timing. The same function of conversion
control is possible using the Pulse Convert command
(with the START pin low). In this operation, the data
from one channel is converted with each Pulse
Convert command. The Pulse convert command
takes effect when the command byte is completely
shifted in (eighth falling edge of SCLK). After
conversion, if more than one channel is enabled
(Auto-Scan mode), the converter indexes to the next
selected channel after completing the conversion.
The conversions of the ADS1258 are controlled by
the START pin. Conversions begin when the START
pin is taken high and conversions are stopped when
the START pin is taken low. For continuous
conversions, tie the START pin high. The START pin
can also be tied low and the conversions controlled
by the PULSE convert command. The PULSE
convert command converts one channel (only) for
each command sent. In this way, channel
conversions can be stepped without the need to
toggle the START pin.
START Pin
As shown in Figure 54, when the START pin is taken
high, conversions start beginning with the current
channel. The device continues to convert all of the
programmed channels, in a continuous loop, until the
START pin is taken low. When this occurs, the
conversion in process completes, and the device
enters the standby or sleep mode waiting for a new
start condition. When DRDY asserts low, the
conversion data is ready. Figure 56 shows the
START pin to DRDY timing. The order in which
channel data is converted is described in Table 10.
When the last selected channel in the program list
has been converted, the device continues
conversions starting with the highest priority channel.
If there is only one channel selected in the Auto-Scan
mode, the converter remains fixed on one channel. A
write operation to any of the multiplexer channel
select registers sets the channel pointer to the
highest priority channel (see Table 11). In
Fixed-Channel mode, the channel pointer remains
fixed.
Data Ready, Index to Next Channel
Converting
Idle
Converting
DRDY
START Pin
or
Pulse Convert
Command
Figure 55. Pulse Conversion, Auto-Scan Mode
tSDSU
DRDY
tDRHD
START Pin
Data Ready, Index to Next Channel
SYMBOL
DESCRIPTION
MIN UNIT
Idle Mode
Converting
Idle
START to DRDY Setup Time
to Halt Further Conversions
tSDSU
tCLK
8
8
DRDY
DRDY to START Hold Time
tDRHD
tCLK
START Pin
to Complete Current Conversion
Figure 56. START Pin and DRDY Timing
Figure 54. Conversion Control, Auto-Scan Mode
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GPIO Linked START Pin Control
OPERATING MODES
The START pin can be contolled directly by software
by connecting externally a GPIO port pin to the
START pin. (Note that an external pull-down resistor
is recommended to keep the GPIO from floating until
the GPIO is configured as an output). For this mode
of control, the START pin is effectively controlled by
writing to the GPIO Data Register (GPIOD), with the
write operation setting or resetting the appropriate bit.
The data takes effect on the eighth falling edge of the
data byte write. The START pin can then be
controlled by the serial interface.
The operating modes of the ADS1258 are defined in
three basic states: Converting Mode, Idle Mode, and
Power-Down mode. In Converting mode, the device
is actively converting channel data. The device power
dissipation is the highest in this mode. This mode is
divided into two sub-modes: Auto-Scan and
Fixed-Channel.
The next mode is the Idle mode. In this mode, the
device is not converting channel data. The device
remains active, waiting for input to start conversions.
The power consumption is reduced from that of the
Converting mode. This mode also has two
sub-modes: Standby and Sleep.
Initial Delay
As seen in Figure 57, when a start convert condition
occurs, the first reading from ADS1258 is delayed for
a number of clock cycles. This delay allows fully
settled data to occur at the first data read. Data reads
thereafter are available at the full data rate. The
number of clock cycles delayed before the first
reading is valid depends on the data rate setting, and
whether exiting the Standby or Sleep Mode. Table 9
lists the delayed clock cycles versus data rate.
The last mode is Power-Down mode. In this mode, all
functions of the converter are disabled to reduce
power consumption to a minimum.
CONVERTING MODES
The ADS1258 has two converting modes: Auto-Scan
and Fixed-Channel. In Auto-Scan mode, the channels
to be measured are pre-selected in the address
register settings. When a convert condition is present,
the converter automatically measures and sequences
through the channels either in a continuous loop or
pulse-step fashion, depending on the trigger
condition.
Fully−Settled Data
DRDY
In Fixed-Channel mode, the channel address is
selected in the address register settings prior to
acquiring channel data. When a convert condition is
present, the device converts a single channel, either
continuously or in pulse-step fashion, depending on
the trigger condition. The data rate in this mode is
higher than in Auto-Scan Mode since the input
channels are not indexed for each reading.
Initial Delay
Start
Condition
Figure 57. Start Condition to First Data
The selection of converting modes is set with bit
MUXMOD of register CONFIG0.
Table 9. Start Condition to DRDY Delay, Chop = 0, DLY[2:0] = 000
INITIAL DELAY (Standby Mode)
(fCLK cycles)
INITIAL DELAY (Sleep Mode)
(fCLK cycles)
DRATE[1:0]
Fixed-Channel
Auto-Scan
708
Fixed-Channel
866
Auto-Scan
772
11
10
01
00
802
1186
2722
8866
1092
1250
1156
2628
2786
2692
8772
8930
8836
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Auto-Scan Mode
register prior to converting a different channel. Note
that the AINCOM input and the internal system
registers cannot be referenced in this mode.
The ADS1258 provides 16 analog inputs, which can
be configured in combinations of eight differential
inputs or 16 single-ended inputs, and provides an
additional five internal system measurements. Taken
together, the device allows a total of 29 possible
channel combinations. The converter automatically
scans and measures the selected channels, either in
a continuous loop or pulse-step fashion, under the
control of the START pin or Start command software.
The channels are selected for measurement in
registers MUXDIF, MUXSG0, MUXSG1, and
SYSRED. When any of these registers are written,
the internal channel pointer is set to the channel
address with the highest priority (see Table 11).
Idle Modes
When the START pin is taken low, the device
completes the conversion of the current channel and
then enters one of the Idle modes, Standby or Sleep.
In the Standby mode, the internal biasing of the
converter is reduced. This state provides the fastest
wake-up response when re-entering the run state. In
Sleep mode, the internal biasing is reduced further to
provide lower power consumption than the Standby
mode. This mode has a slower wake-up response
when re-entering the Converting mode (see Table 9).
Selection of these modes is set under bit IDLMOD of
register CONFIG1.
DRDY asserts low when the channel data is ready;
see Figure 55 and Figure 54. At the same time, the
converter indexes to the next selected channel and, if
the START pin is high, starts a new channel
conversion. Otherwise, if pulse converting, the device
enters the Idle mode.
POWER-DOWN MODE
In power-down mode, both the analog and digital
circuitry are completely disabled.
For example, if channels 3, 4, 7, and 8 are selected
for measurement in the list, the ADS1258 converts
the channels in that order, skipping all other
channels. After channel 8 is converted, the device
starts over, beginning at the top of the channel list,
channel 3.
SERIAL INTERFACE
The ADS1258 is operated via an SPI-compatible
serial interface by writing data to the configuration
registers, using commands to control the converter
and finally reading back the channel data. The
interface consists of four signals: CS, SCLK, DIN,
and DOUT.
The following guidelines can be used when selecting
input channels for Auto-Scan measurement:
1. For differential measurements, adjacent input
pins (AIN0/AIN1, AIN2/AIN3, AIN4/AIN5, etc.) are
pre-set as differential pairs. Even number
channels from each pair represent the positive
input to the ADC and odd number channels within
a pair represent the negative input (for example,
AIN0/AIN1: AIN0 is the positive channel, AIN1 is
the negative channel.)
Chip Select (CS)
CS is an input that is used to select the device for
serial communication. CS is active low. When CS is
high, read or write commands in progress are aborted
and the serial interface is reset. Additionally, DOUT
tri-states and inputs on DIN are ignored. DRDY
indicates when data is ready, independent of CS.
2. For single-ended measurements use AIN0
through AIN15 as single-ended inputs and
AINCOM is the shared common input among
them. Note: AINCOM does not need to be at
ground potential. For example, AINCOM can be
tied to VREFP or VREFN; or any potential
between (AVSS – 100mV) and (AVDD + 100mV).
The converter may be operated using CS to actively
select and deselect the device, or with CS tied low
(always selected). CS must stay low for the entire
read or write operation. When operating with CS tied
low, the number of SCLK pulses must be carefully
controlled to avoid false command transmission.
3. Combinations of differential, single-ended inputs,
and internal system registers can be used in a
scan.
Serial Clock (SCLK) Operation
The serial clock (SCLK) is an input which is used to
clock data into (DIN) and out of (DOUT) the
ADS1258. This input is a Schmitt-trigger input that
has a high degree of noise immunity. However, it is
recommended to keep SCLK as clean as possible to
prevent glitches from inadvertently shifting the data.
Data is shifted into DIN on the rising edge of SCLK
and data is shifted out of DOUT on the falling edge of
SCLK. If SCLK is held inactive for 4096 or 256 fCLK
cycles (SPIRST bit of register CONFIG0), read or
Fixed-Channel Mode
In this mode, any of the 16 analog input channels
(AIN0–AIN15) can be selected for the positive ADC
input and any analog input channels can be selected
for the negative ADC input. New channel
configurations must be selected by the MUXSCH
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write operations in progress will terminate and the
SPI interface resets. This timeout feature can be
used to recover lost communication when a serial
interface transmission is interrupted or inadvertently
glitched.
may be read at any time without concern to DRDY.
The NEW bit of the STATUS byte indicates that the
data register has been refreshed with new converter
data since the last read operation. The data is shifted
out MSB first after the STATUS byte.
It should be noted that on system power-up, if the
ADS1258 interface signals are floating or undefined,
the interface could wake in an unknown state. This
condition is remedied by resetting the interface in
three ways: toggle the RESET pin low then high;
toggle the CS pin high then low; or hold SCLK
inactive for 218 + 4096 fCLK cycles.
Data Input (DIN) and Data Output (DOUT)
Operation
The data input pin (DIN) is used to input data to the
ADS1258. The data output pin (DOUT) is used to
output data from the ADS1258. Data on DIN is shifted
into the converter on the rising edge of SCLK while
data is shifted out on DOUT on the falling edge of
SCLK. DOUT is tri-stated when CS is high to allow
multiple devices to share the line.
Channel Data Read Direct
Channel data can be accessed from the ADS1258 in
two ways: Direct data read or data read with register
format. With Direct read, the DIN input pin is held
inactive (high or low) for at least the first three SCLK
transitions. When the first three bits are 000 or 111,
the device detects a direct data read and channel
data is output. After the device defects this read
format, commands are ignored until either CS is
toggled, an SPI timeout occurs or the device is reset.
The Channel Data Read command does not have
this requirement.
SPI Bus Sharing
The ADS1258 can be connected to a shared SPI bus.
DOUT tri-states when CS is deselected (high). When
the ADS1258 is connected to a shared bus, data can
be read only by the Channel Data Read command
format.
COMMUNICATION PROTOCOL
Communicating to the ADS1258 involves shifting data
into the device (via the DIN pin) or shifting data out of
the device (via the DOUT pin) under control of the
SCLK input.
Concurrent with the first SCLK transition, channel
data is output on the DOUT output pin. A total of 24
or 32 SCLK transitions complete the data read
operation. The number of shifts depend on whether
the status byte is enabled. The data must be
completely shifted out before the next occurrence of
DRDY or the remaining data will be corrupted. It is
recommended to monitor DRDY to synchronize the
start of the read operation to avoid data corruption.
Before DRDY asserts low, the MSB of the Status byte
or the MSB of the data is output on DOUT (CS = '0'),
as shown in Figure 58. In this format, reading the
data a second time within the same DRDY frame
returns data = 0.
Reading DATA
DRDY goes low to indicate that new conversion data
is ready. The data may be read via a direct data read
(Channel Data Read Direct) or the data may be read
in a register format (Channel Data Read Register). A
direct data read requires the data to be read before
the next occurrence of DRDY or the data will be
corrupted. This type of data read requires
synchronization with DRDY to avoid this conflict.
When reading data in the register format, the data
DRDY
CS
(3)
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
SCLK
DOUT
Status Byte(1)
Data Byte 1 (MSB)
Data Byte 3 (MSB)
DIN
(hold inactive)
(2)
NOTES: (1) Optional for Auto-Scan mode, disabled for Fixed-Channel mode. See Table 13, Status Byte.
(2) After the channel data read operation, CS must be toggled or an SPI timeout must occur before sending commands.
(3) No SCLK activity.
Figure 58. Channel Data Read Direct (No Command)
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COMMAND DESCRIPTION
SCLK falling edge (command byte completed), the
MSB of the channel data is restarted on DOUT. The
user clocks the data on the following rising edge of
SCLK. A total of 40 SCLK transitions complete the
data read operation. Unlike the direct read mode, the
channel data can be read during a DRDY transition
without data corruption. This mode is recommended
when DRDY is not used and the data is polled to
detect for the occurrence of new data or when CS is
tied low to avoid the necessity for an SPI timeout that
otherwise occurs when reading data directly. This
option avoids conflicts with DRDY, as shown in
Figure 59.
Commands may be sent to the ADS1258 with CS tied
low. However, after the Channel Data Read Direct
operation, it is necessary to toggle CS or an SPI
timeout must occur to reset the interface before
sending a command.
Channel Data Read Command
To read channel data in this mode (register format),
the first three bits of the command byte to be shifted
into the device are 001. The MUL bit must be set
because this command is a multiple byte read. The
remaining bits are don’t care but still must be clocked
to the device. During this time, ignore any data that
appear on DOUT until the command completes. This
data should be ignored. Beginning with the eighth
CS
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
SCLK
DIN
Command Byte 1
Don’t Care
Don’t Care
Data(2)
Don’t Care(1)
Data(2)
DOUT
NOTE: (1) After the prescribed number of registers are read, then one or more additional commands can be issued in succession.
(2) Four bytes for channel data register read. See Table 13, Status Byte. One or more bytes for register data read, depending on MUL bit.
Figure 59. Register and Channel Data (Register Format) Read
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Register Read Command
Beginning with the eighth SCLK rising edge
(command byte completed), the MSB of the data is
shifted in. The remaining seven SCLK rising edges
complete the write to a single register. If MUL = '1',
the data to the next register can be written by
supplying additional SCLKs. The operation terminates
when the last register is accessed (address = 09h),
as shown in Figure 60.
To read register data, the first three bits of the
command byte to be shifted into the device are 010.
These bits are followed by the multiple register read
bit (MUL). If MUL = '1', then multiple registers can be
read in sequence beyond the desired register. If
MUL = '0', only data from the addressed register can
be read. The last four bits of the command word are
the beginning register address bits. During this time,
the invalid data may appear on DOUT until the
command is completed. This data should be ignored.
Beginning with the eighth falling edge of SCLK
(command byte completed), the MSB of the register
data is output on DOUT. The remaining eight SCLK
transitions complete the read of a single register. If
MUL = '1', the data from the next register can be read
in sequence by supplying additional SCLKs. The
operation terminates when the last register is
accessed (address = 09h); see Figure 59.
CONTROL COMMANDS
Pulse Convert Command
(See Conversion Control section)
Reset Command
The Reset command resets the ADC. All registers
are reset to their default values. A conversion in
process continues but is invalid when completed
(DRDY low). This conversion data should be
discarded. Note that the SPI interface may require
reset for this command, or any command, to function.
To ensure device reset under a possible locked SPI
interface condition, do one of the following: 1) toggle
CS high then low and send the reset command; or 2)
hold SCLK inactive for 256/fCLK or 4096/fCLK and send
the reset command. The control commands are
illustrated in Figure 61.
Register Write Command
To write register data, the first three bits of the
command byte to be shifted into the device are 011.
These bits are followed by the multiple register read
bit (MUL). If MUL = '1', then multiple registers can be
written in sequence beyond the desired register. If
MUL = '0', only data to the addressed register can be
written. The remaining four bits of the command word
are the beginning register address bits. During this
time, the invalid data may appear on DOUT until the
command is completed. This data should be ignored.
CS
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
SCLK
DIN
(1)
(1)(2)
Register Data
Command Byte
Register Data
NOTE: (1) One or more bytes depending on MUL bit.
(2) After the prescribed number of registers are read, then one or more additional commands can be issued in succession.
Figure 60. Register Write Operation
CS
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
SCLK
DIN
(1)
(1)
Command 1
Command 2
Command 3
NOTE: (1) One or more commands can be issued in succession.
Figure 61. Control Command Operation
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CHANNEL DATA
The data read operation outputs either four bytes (one byte for status and three bytes for data), or three bytes for
data only. The selection of 4-byte or 3-byte data read is set by the bit STAT in register CONFIG0 (see Table 13,
Status Byte, for options). In the 4-byte read, the first byte is the status byte and the following three bytes are the
data bytes. The MSB (Data23) of the data is shifted out first.
Table 10. CHANNEL DATA FORMAT
BYTE
STATUS
BIT 7
NEW
BIT 6
OVF
BIT 5
SUPPLY
Data21
Data13
Data5
BIT 4
CHID4
Data20
Data12
Data4
BIT 3
CHID3
Data19
Data11
Data3
BIT 2
CHID2
Data18
Data10
Data2
BIT 1
CHID1
Data17
Data9
Data1
BIT 0
CHID0
Data16
Data8
Data0
1
2
3
4
MSB
MSB-1
LSB
Data23
Data15
Data7
Data22
Data14
Data6
STATUS BYTE
BIT STATUS.7, NEW
The NEW bit is set when the results of a Channel Data Read Command returns new channel data. The bit
remains set indefinitely until the channel data is read. When the channel data is read again before the converter
updates with new data, the previous data is output and the NEW bit is cleared. If the channel data is not read
before the next conversion update, the data from the previous conversion is lost. As shown in Figure 62, the
NEW bit emulates the operation of the DRDY output pin. To emulate the function of the DRDY output pin in
software, the user reads data at a rate faster than the converter's data rate. The user then polls the NEW bit to
detect for new channel data.
0 = Channel data has not been updated since the last read operation.
1 = Channel data has been updated since the last read operation.
DRDY
NEW Bit
Data Reads
(register format)
Figure 62. NEW Bit Operation
BIT STATUS.6 OVF
When this bit is set, this indicates the differential voltage applied to the ADC inputs have exceeded the range of
the converter |VIN| > 1.06 VREF. During over-range, the output code of the converter clips to either positive FS
(VIN ≥ 1.06 × VREF) or negative FS (VIN
≤
–1.06 × VREF). This bit, with the MSB of the data, can be used to
detect positive or negative over-range conditions. Note that because of averaging incorporated within the digital
filter, the absence of this bit does not assure that the modulator of the ADC has not saturated due to possible
transient input overload conditions.
BIT STATUS.5 SUPPLY
This bit indicates that the analog power-supply voltage (AVDD – AVSS) is below a preset limit. The SUPPLY bit
is set when the value falls below 4.3 V (typically) and is reset when the value rises 50mV higher (typically) than
the lower trip point. The output data of the ADC may not be valid under low power-supply conditions.
BITS CHID[4:0] CHANNEL ID BITS
The Channel ID bits indicate the measurement channel of the acquired data. Note that for Fixed-Channel mode,
the Channel ID bits are undefined. See Table 11 for the channel ID, the measurement priority, and the channel
description for Auto-Scan Mode.
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BITS DATA[23:0] OF DATA BYTES
The ADC output data are 24 bits wide (DATA[23:0]). DATA23 is the most significant bit (MSB) and DATA0 is the
least significant bit (LSB). The data is coded in binary twos complement format.
Table 11. Channel ID and Measurement Order (Auto-Scan Mode)
BITS CHID[4:0]
00h
PRIORITY
CHANNEL
DESCRIPTION
Differential 0
1 (Highest)
DIFF0 (AIN0–AIN1)
01h
2
DIFF1 (AIN2–AIN3)
Differential 1
02h
3
DIFF2 (AIN4–AIN5)
Differential 2
03h
4
DIFF3 (AIN6–AIN7)
Differential 3
04h
5
DIFF4 (AIN8– AIN9)
Differential 4
05h
6
DIFF5 (AIN10–AIN11)
Differential 5
06h
7
DIFF6 (AIN12–AIN13)
Differential 6
07h
8
DIFF7 (AIN14–AIN15)
AIN0
Differential 7
08h
9
Single-Ended 0
Single-Ended 1
Single-Ended 2
Single-Ended 3
Single-Ended 4
Single-Ended 5
Single-Ended 6
Single-Ended 7
Single-Ended 8
Single-Ended 9
Single-Ended 10
Single-Ended 11
Single-Ended 12
Single-Ended 13
Single-Ended 14
Single-Ended 15
OFFSET
09h
10
AIN1
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11
AIN2
12
AIN3
13
AIN4
14
AIN5
15
AIN6
16
AIN7
17
AIN8
11h
18
AIN9
12h
19
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
OFFSET
VCC
13h
20
14h
21
15h
22
16h
23
17h
24
18h
25
1Ah
1Bh
1Ch
1Dh
26
27
AVDD – AVSS Supplies
Temperature
TEMP
GAIN
28
Gain
29 (Lowest)
REF
External Reference
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COMMAND AND REGISTER DEFINITIONS
Commands are used to read channel data, access the configuration registers, and control the conversion
process. If the command is a register read or write operation, one or more data bytes follow the command byte.
If bit MUL = 1 in the command byte, then multiple registers can be read or written in one command operation
(see the MUL bit). Commands can be sent back-to-back without toggling CS; however, after a channel Data
Read Direct operation, CS must be toggled or an SPI timeout must occur before sending a command. The data
read by command does not require CS to be toggled.
The command byte consists of three fields: the Command Bits(C[2:0]), multiple register access bit (MUL), and
the Register Address Bits (A[3:0]); see the Command Byte register.
Command Byte
7
6
5
4
3
2
1
0
C2
C1
C0
MUL
A3
A2
A1
A0
Bits C[2:0] — Command Bits
These bits code the command within the command byte.
C[2:0]
000
001
010
011
100
101
110
111
DESCRIPTION
COMMENTS
Channel Data Read Direct (no command)
Channel Data Read Command (register format)
Register Read Command
Register Write Command
Pulse Convert Command
Reserved
Toggle CS or allow SPI timeout before sending command
Set MUL = 1; status byte always included in data
MUL, A[3:0] are don't care
Reset Command
MUL, A[3:0] don't care
Channel Data Read Direct (no command)
Toggle CS or allow SPI timeout before sending command
Bit 4 MUL: Multiple Register Access
0 = Disable Multiple Register Access
1 = Enable Multiple Register Access
This bit enables the multiple register access. This option allows writing or reading more than one register in a
single command operation. If only one register is to be read or written, set MUL = '0'. For multiple register
access, set MUL = '1'. The read or write operation begins at the addressed register. The ADS1258 automatically
increments the register address for each register data byte subsequently read or written. The multiple register
read or write operations complete after register address = 09h (device ID register) has been accessed.
The multiple register access is terminated in one of three ways:
1. The user takes CS high. This action resets the SPI interface.
2. The user holds SCLK inactive for 4096 fCLK cycles. This action resets the SPI interface.
3. Register address = 09h has been accessed. This completes the command and the ADS1258 is then ready
for a new command. Note for the Channel Data Read command, this bit must be set to read the four data
bytes (one status byte and three data bytes).
A[3:0] Register Address Bits
These bits are the register addresses for a register read or write operation; see Table 12.
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REGISTERS
Table 12. Register Map
ADDRESS REGISTER DEFAULT
Bits A[3:0]
NAME
CONFIG0
CONFIG1
MUXSCH
MUXDIF
MUXSG0
MUXSG1
SYSRED
GPIOC
VALUE
0Ah
83h
BIT 7
0
BIT 6
BIT 5
BIT 4
BYPAS
DLY0
AINP0
DIFF4
AIN4
BIT 3
CLKENB
SBCS1
AINN3
DIFF3
AIN3
BIT 2
CHOP
SBCS0
AINN2
DIFF2
AIN2
BIT 1
STAT
DRATE1
AINN1
DIFF1
AIN1
AIN9
0
BIT 0
0
00h
SPIRST MUXMOD
01h
IDLMOD
AINP3
DIFF7
AIN7
AIN15
0
DLY2
AINP2
DIFF6
AIN6
AIN14
0
DLY1
AINP1
DIFF5
AIN5
AIN13
REF
DRATE0
AINN0
DIFF0
AIN0
02h
00h
03h
00h
04h
FFh
FFh
00h
05h
AIN12
GAIN
CIO4
DIO4
ID4
AIN11
TEMP
CIO3
AIN10
VCC
AIN8
06h
OFFSET
CIO0
DIO0
ID0
07h
FFh
00h
CIO7
DIO7
ID7
CIO6
DIO6
ID6
CIO5
DIO5
ID5
CIO2
DIO2
ID2
CIO1
DIO1
ID1
08h
GPIOD
DIO3
09h
ID
8Bh
ID3
CONFIG0: CONFIGURATION REGISTER 0 (Address = 00h)
7
6
5
4
3
2
1
0
0
0
SPIRST
MUXMOD
BYPAS
CLKENB
CHOP
STAT
Default = 0Ah.
Bit 7
Bit 6
Must be 0 (default)
SPIRST SPI Interface Reset Timer
This bit sets the number of fCLK cycles in which SCLK is inactive the SPI interface will reset. This
places a lower limit on the frequency of SCLK in which to read or write data to the device. The SPI
interface only is reset and not the device itself. When the SPI interface is reset, it is ready for a new
command.
0 = Reset when SCLK inactive for 4096fCLK cycles (256µs, fCLK = 16MHz) (default).
1 = Reset when SCLK inactive for 256fCLK cycles (16µs, fCLK = 16MHz).
Bit 5
MUXMOD
This bit sets either the Auto-Scan or Fixed-Channel mode of operation.
0 = Auto-Scan Mode (default)
In Auto-Scan mode, the input channel selections are eight differential channels (DIFF0–DIFF7) and 16
single-ended channels (AIN0–AIN15). Additionally, five internal monitor readings can be selected.
These selections are made in registers MUXDIF, MUXSG0, MUXSG1, and SYSRED. In this mode,
settings in register MUXSCH have no effect. See the Auto-Scan Mode section for more details.
1 = Fixed-Channel Mode
In Fixed-Channel mode, any of the analog input channels may be selected for the positive
measurement and the negative measurement channels. The inputs are selected in register MUXSCH.
In this mode, registers MUXDIF, MUXSG0, MUXSG1, and SYSRED have no effect. Note that it is not
possible to select the internal monitor readings in this mode.
Bit 4
BYPAS
This bit selects either the internal or external connection from the multiplexer output to the ADC input.
0 = ADC inputs use internal multiplexer connection (default).
1 = ADC inputs use external ADC inputs (ADCINP and ADCINN).
Note that the Temperature, VCC, Gain, and Reference internal monitor readings automatically use the
internal connection, regardless of the BYPAS setting. The Offset reading uses the setting of BYPAS.
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Bit 3
CLKENB
This bit enables the clock output on pin CLKIO. The clock output originates from the device crystal
oscillator and PLL circuit.
0 = Clock output on CLKIO disabled.
1 = Clock output on CLKIO enabled (default).
Note: If the CLKSEL pin is set to '1', the CLKIO pin is a clock input only. In this case, setting this bit
has no effect.
Bit 2
CHOP
This bit enables the chopping feature on the external multiplexer loop.
0 = Chopping Disabled (default)
1 = Chopping Enabled
The chopping feature corrects for offset originating from components used in the external multiplexer
loop; see the External Chopping section.
Note that for Internal System readings (Temperature, VCC, Gain, and Reference), the CHOP bit must
be 0.
Bit 1
STAT Status Byte Enable
When reading channel data from the ADS1258, a status byte is normally included with the conversion
data. However, in some ADS1258 operating modes, the status byte can be disabled. Table 13, Status
Byte, shows the modes of operation and the data read formats in which the status byte can be
disabled.
0 = Status Byte Disabled
1 = Status Byte Enabled (default)
Table 13. Status Byte
CHANNEL DATA
READ COMMAND
CHANNEL DATA
READ DIRECT
MODE
Auto-Scan
Always Enabled
Enabled/Disabled by STAT Bit
Always Disabled
Fixed-Channel
Always Enabled (Byte is Undefined)
Bit 0
Must be 0
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CONFIG1: CONFIGURATION REGISTER 1 (Address = 01h)
7
6
5
4
3
2
1
0
IDLMOD
DLY2
DLY1
DLY0
SBCS1
SBCS0
DRATE1
DRATE0
Default = 83h.
Bit 7
IDLMOD
This bit selects the Idle mode when the device is not converting, Standby or Sleep. The Sleep mode
offers lower power consumption but has a longer wake-up time to re-enter the run mode; see the Idle
Modes section.
0 = Select Standby Mode
1 = Select Sleep Mode (default)
Bits
6–4
DLY[2:0]
These bits set the amount of time the converter will delay after indexing to a new channel but before
starting a new conversion. This value should be set large enough to allow for the full settling of
external filtering or buffering circuits used between the MUXOUTP, MUXOUTN, and ADCINP,
ADCINN pins; see the Switch Time Delay section. (default = 000)
Bits
3–2
SBCS[1:0]
These bits set the sensor bias current source.
0 = Sensor Bias Current Source Off (default)
1 = 1.5µA Source
3 = 24µA Source
Bits
1–0
DRATE[1:0]
These bits set the data rate of the converter. Slower reading rates yield increased resolution; see
Table 4. The actual data rates shown in the table can be slower, depending on the use of Switch Time
Delay or the Chop feature. See the Switch Time Delay section. The reading rate scales with the
master clock frequency.
DATA RATE
AUTO-SCAN MODE
(SPS)
DATA RATE
FIXED-CHANNEL MODE
(SPS)
DRATE[1:0]
11
10
01
00
23739
15123
6168
125000
31250
7813
1831
1953
fCLK = 16MHz, Chop = 0, Delay = 0.
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MUXSCH: MULTIPLEXER FIXED-CHANNEL REGISTER (Address = 02h)
7
6
5
4
3
2
1
0
AINP3
AINP2
AINP1
AINP0
AINN3
AINN2
AINN1
AINN0
Default = 00h.
This register selects the input channels of the multiplexer to be used for the Fixed-Channel mode. The MUXMOD
bit in register CONFIG0 must be set to '1'. In this mode, bits AINN[3:0] select the analog input channel for the
negative ADC input, and bits AINP[3:0] select the analog input channel for the positive ADC input. See the
Fixed-Channel Mode section.
MUXDIF: MULTIPLEXER DIFFERENTIAL INPUT SELECT REGISTER (Address = 03h)
7
6
5
4
3
2
1
0
DIFF7
DIFF6
DIFF5
DIFF4
DIFF3
DIFF2
DIFF1
DIFF0
Default = 00h.
MUXSG0: MULTIPLEXER SINGLE-ENDED INPUT SELECT REGISTER 0 (Address = 04h)
7
AIN7
6
5
4
3
2
1
0
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
AIN0
Default = FFh.
MUXSG1: MULTIPLEXER SINGLE-ENDED INPUT SELECT REGISTER 1 (Address = 05h)
7
6
5
4
3
2
1
0
AIN15
AIN14
AIN13
AIN12
AIN11
AIN10
AIN9
AIN8
Default = FFh.
SYSRED: SYSTEM READING SELECT REGISTER (Address = 06h)
7
6
5
4
3
2
1
0
0
0
REF
GAIN
TEMP
VCC
0
OFFSET
Default = 00h.
These four registers select the input channels and the internal readings for measurement in Auto-Scan mode.
For differential channel selections (DIFF0…DIFF7), adjacent input pins (AIN0/AIN1, AIN2/AIN3, etc.) are pre-set
as differential inputs. All single-ended inputs are measured with respect to the AINCOM input. AINCOM may be
set to any level within ±100 mV of the analog supply range. Channels not selected are skipped in the
measurement sequence. Writing to any of these four registers resets the internal channel pointer to the channel
with the highest priority (see Table 11). Note that the bits indicated as '0' must be set to 0.
0 = Channel not selected within a reading sequence.
1 = Channel selected within a reading sequence.
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GPIOC: GPIO CONFIGURATION REGISTER (Address = 07h)
7
CIO7
6
5
4
3
2
1
0
CIO6
CIO5
CIO4
CIO3
CIO2
CIO1
CIO0
Default = FFh.
This register configures the GPIO pins as inputs or as outputs. Note that the default configurations of the port
pins are inputs and as such they should not be left floating. See the GPIO Digital Port section.
0 = GPIO is an output; 1 = GPIO is an input (default).
CIO[7:0] GPIO Configuration
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CIO7, Digital I/O Configuration Bit for Pin GPIO7
CIO6, Digital I/O Configuration Bit for Pin GPIO6
CIO5, Digital I/O Configuration Bit for Pin GPIO5
CIO4, Digital I/O Configuration Bit for Pin GPIO4
CIO3, Digital I/O Configuration Bit for Pin GPIO3
CIO2, Digital I/O Configuration Bit for Pin GPIO2
CIO1, Digital I/O Configuration Bit for Pin GPIO1
CIO0, Digital I/O Configuration Bit for Pin GPIO0
GPIOD: GPIO DATA REGISTER (Address = 08h)
7
6
5
4
3
2
1
0
DIO7
DIO6
DIO5
DIO4
DIO3
DIO2
DIO1
DIO0
Default = 00h.
This register is used to read and write data to the GPIO port pins. When reading this register, the data returned
corresponds to the state of the GPIO external pins, whether they are programmed as inputs or as outputs. As
outputs, a write to the GPIOD sets the output value. As inputs, a write to the GPIOD has no effect. See the
GPIO Digital Port section.
0 = GPIO is logic low (default); 1 = GPIO is logic high.
DIO[7:0] GPIO Data
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DIO7, Digital I/O Data bit for Pin GPIO7
DIO6, Digital I/O Data bit for Pin GPIO6
DIO5, Digital I/O Data bit for Pin GPIO5
DIO4, Digital I/O Data bit for Pin GPIO4
DIO3, Digital I/O Data bit for Pin GPIO3
DIO2, Digital I/O Data bit for Pin GPIO2
DIO1, Digital I/O Data bit for Pin GPIO1
DIO0, Digital I/O Data bit for Pin GPIO0
ID: DEVICE ID REGISTER (Address = 09h)
7
6
5
4
3
2
1
0
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Default = 8Bh.
ID[7:0] ID Bits
Factory-programmed ID bits. Read-only.
APPLICATIONS
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HARDWARE CONSIDERATIONS
The following summarizes the design and layout
considerations when using the ADS1258:
AVDD
a. Power Supplies: The converter accepts a single
+5V supply (AVDD = 5 V and AVSS = AGND) or
dual, bipolar supplies (typically AVDD = 2.5 V,
BAT54SWTI
AINx
Ω
10k
Input
typ.
AVSS
=
–2.5 V). Dual supply operation
accommodates true bipolar input signals, within a
±2.5-V range. Note that the maximum negative
input voltage to the multiplexer is limited to AVSS
– 100 mV, and the maximum positive input
voltage is limited to AVDD + 100 mV. The range
for the digital power supply (DVDD) is 2.7 V to
5.25 V. For all supplies, use a 10-μF tantalum
AVSS
Figure 63. Input Overload Protection
d. ADC Inputs: The external multiplexer loop of the
ADS1258 allows for the inclusion of signal
conditioning between the output of the multiplexer
and the input of the ADC. Typically, an amplifier
is used to provide gain, buffering, and/or filtering
to the input signal. For best performance, the
ADC inputs should be driven differentially. A
capacitor, bypassed with
a 0.1-μF ceramic
capacitor, placed close to the device pins.
Alternatively, a single 10-μF ceramic capacitor
can be used. The supplies should be relatively
free from noise and should not be shared with
devices that produce voltage spikes (such as
relays, LED display drivers, etc.). If a switching
power supply is used, the voltage ripple should
be low (< 2 mV). The analog and digital power
supplies may be sequenced in any order.
differential
in/differential
out
or
a
single-ended-to-differential driver is recom-
mended. If the driver uses higher supply voltages
than the device itself (for example, ±15V),
attention should be paid to power-supply
sequencing and potential over-voltage fault
conditions. Protection resistors and/or external
clamp diodes may be used to protect the ADC
inputs. A 1-nF or higher capacitor should be used
directly across the ADC inputs.
b. Analog (Multiplexer) Inputs: The 16-channel
analog input multiplexer can accommodate 16
single-ended inputs, eight differential input pairs,
or combinations of either. These options permit
freedom in choosing the input channels. The
channels do not have to be used consecutively.
Unassigned channels are skipped by the device.
In the Fixed-Channel mode, any of the analog
inputs (AIN0 to AIN15) can be addressed for the
positive input and for the negative input. The
full-scale range of the device is 2.13 VREF, but the
absolute analog input voltage is limited to 100 mV
beyond the analog supply rails. Input signals
exceeding the analog supply rails (for example,
±10 V) must be divided prior to the multiplexer
inputs.
e. Reference Inputs: It is recommended to use a
10-μF tantalum with a 0.1-μF ceramic capacitor
directly across the reference pins, VREFP and
VREFN. The reference inputs should be driven
by
a
low-impedance source. For rated
performance, the reference should have less than
3μVRMS broadband noise. For references with
higher noise, external filtering may be necessary.
Note that when exiting the sleep mode, the
device begins to draw a small current through the
reference pins. Under this condition, the transient
response of the reference driver should be fast
enough to settle completely before the first
reading is taken, or simply discard the first
several readings.
c. Input Overload Protection: Overdriving the
multiplexer inputs may affect the conversions of
other channels. In the case of input overload,
external Schottky diode clamps and series
resistor are recommended, as shown in Figure
61.
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f. Clock Source: The ADS1258 requires a clock
signal for operation. The clock can originate from
either the crystal oscillator or from an external
clock source. The internal oscillator uses a PLL
circuit and an external 32.768-kHz crystal to
generate a 15.7-MHz master clock. The PLL
requires a 22-nF capacitor from the PLLCAP pin
to AVSS. The crystal and load capacitors should
be placed close to the pins as possible and kept
away from other traces with AC components. A
buffered output of the 15.7-MHz clock can be
used to drive other converters or controllers. An
external clock source can be used up to 16 MHz.
For best performance, the clock of the SPI
interface controller and the converter itself should
be on the same domain. This configuration
requires that the ratio of the SCLK to device clock
must be limited to 1,1/2,1/4, 1/8, etc.
for more details. The SPI interface can be
operated in a minimum configuration without the
use of CS (tie CS low; see the Serial Interface
and Communication Protocol sections).
j. GPIO: The ADS1258 has eight, user-
programmable digital I/O pins. These pins are
controlled by register settings. The register
setting is default to inputs. If these pins are not
used, tie them high or low (do not float input pins)
or configure them as outputs.
k. QFN Package: See Application Report SLUA271,
QFN/SON PCB Attachment for PCB layout
recommendations, available for download at
www.ti.com. The exposed thermal pad of the
ADS1258 should be connected electrically to
AVSS.
CONFIGURATION GUIDE
g. Digital Inputs: It is recommended to source
terminate the digital inputs and outputs of the
device with a 50-Ω (typical) series resistor. The
resistors should be placed close to the driving
end of the source (output pins, oscillator, logic
gates, DSP, etc). This placement helps to reduce
the ringing and overshoot on the digital lines.
Configuration of the ADS1258 involves setting the
configuration registers via the SPI interface. After the
device is configured for operation, channel data is
read from the device through the same SPI interface.
The following is
a
suggested procedure for
configuring the device:
1. Reset the SPI Interface: Before using the SPI
interface, it may be necessary to recover the SPI
interface. To reset the interface, set CS high or
disable SCLK for 4096 (256) fCLK cycles.
h. Hardware Pins: START, DRDY, RESET, and
PWDN. These pins allow direct pin control of the
ADS1258. The equivalent of the START and
DRDY pins is provided via commands through
the SPI interface; these pins may be left unused.
The device also has a RESET command. The
PWDN pin places the ADC into very low-power
2. Stop the Converter: Set the START pin low to
stop the converter. Although not necessary for
configuration, this command stops the channel
scanning sequence which then points to the first
channel after configuration.
state
where
the
device
is
inactive.
i. SPI Interface: The ADS1258 has an
SPI-compatible interface. This interface consists
of four signal lines: SCLK, DIN, DOUT, and CS.
When CS is high, the DIN input is ignored and
the DOUT output tri-states. See Chip Select (CS )
3. Reset the Converter: The reset pin can be
pulsed low or a Reset command can be sent.
Although not necessary for configuration, reset
re-initializes the device into a known state.
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4. Configure the Registers: The registers are
configured by writing to them either sequentially
or as a group. The user may configure the
software in either mode. Any write to the
Auto-Scan channel-select registers resets the
channel pointer to the channel of highest priority.
Convert command sent through the interface.
7. Read Channel Data: The DRDY asserts low
when data is ready. The channel data can be
read at that time. If DRDY is not used, the
updated channel data can be checked by reading
the NEW bit in the status byte. The status byte
also indicates the origin of the channel data. If
the data for a given channel is not read before
DRDY asserts low again, the data for that
channel is lost and replaced with new channel
data.
5. Verify Register Data: The register data may be
read
back
for
verification
of
device
communications.
6. Start the Converter: The converter can be
started with the START pin or with a Pulse
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DIGITAL INTERFACE CONNECTIONS
The ADS1258 SPI-compatible interface easily
connects to a wide variety of microcontrollers and
DSPs. Figure 64 shows the basic connection to TI's
MSP430 family of low-power microcontrollers.
Figure 65 shows the connection to microcontrollers
with an SPI interface such as the 68HC11 family, or
TI's MSC12xx family. Note that the MSC12xx
includes a high-resolution ADC; the ADS1258 can be
used to provide additional channels of measurement
or add higher-speed connections. Finally, Figure 66
shows how to connect the ADS1258 to a TMS320x
DSP.
ADS1258
TMS320R2811
DIN
DOUT
DRDY
SCLK
CS(1)
SPISIMO
SPISOMI
XINT1
SPICLK
SPISTA
(1) CS may be tied low.
Figure 66. Connection to a TMS320R2811 DSP
GPIO Connections
ADS1258
MSP430
DIN
P1.3
P1.2
P1.0
P1.6
P1.4
The ADS1258 has eight general purpose input/output
(GPIO) pins. Each pin can be configured as an input
or an output. Note that pins configured as inputs
should not float. The pins can be used to read key
pads, drive LED indicator, etc., by reading and writing
the GPIO data register (GPIOD). See Figure 67.
DOUT
DRDY
SCLK
CS(1)
(1) CS may be tied low.
3.3V
Figure 64. Connection to MSP430 Microcontroller
Ω
10k
ADS1258
GPIOx
(Input)
Key Pad
ADS1258
MSC12xx or
68HC11
3.3V
LED Indicator
DIN
MOSI
470
DOUT
DRDY
SCLK
CS(1)
MISO
INT
Ω
4.7k
GPIOx
(Output)
SCK
IO
(1) CS may be tied low.
Figure 67. GPIO Connections
Figure 65. Connection to Microcontrollers with an
SPI Interface
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ANALOG INPUT CONNECTIONS
When using Auto-Scan mode to sequence through
the channels, the switch time delay feature
(programmable by registers) can be used to provide
additional settling time of the external components.
Figure 68 shows the ADS1258 interfacing to
high-level ±10V inputs, commonly used in industrial
environments. In this case, bipolar power supplies are
used, avoiding the need for input signal level-shifting
otherwise required when a single supply is used. The
input resistors serve both to reduce the level of the
10V input signal to within the ADC range and also
protect the inputs from inadvertent signal over-voltage
up to 30V. The external amplifiers convert the
single-ended inputs to a fully differential output to
drive the ADC inputs. Driving the inputs differentially
maintains good linearity performance. The 2.2-nF
capacitor at the ADC inputs is required to bypass the
ADC sampling currents. The 2.5-V reference,
REF3125, is filtered and buffered to provide a
low-noise reference input to the ADC. The chop
feature of the ADC can be used to reduce offset and
offset drift of the amplifiers.
Figure 69 illustrates the ADS1258 interfacing to
multiple pressure sensors having a resistor bridge
output. Each sensor is excited by the 5-V single
supply that also powers the ADS1258 and likewise is
used as the ADS1258 reference input; the 6% input
overrange capability accommodates input levels at or
above VREF. The ratiometric connection provides
cancellation of excitation voltage drift and noise. For
best performance, the 5-V supply should be free from
glitches or transients. The 5-V supply input amplifiers
(two OPA365s) form a differential input/differential
output buffer with the gain set to 10. The chop feature
of the ADS1258 is used to reduce offset and offset
drift to very low levels. The 2.2-nF capacitor at the
ADC inputs is required to bypass the ADC sampling
currents. The 47-Ω resistors isolate the op-amp
outputs from the filter capacitor.
For ±1V input signals, the input resistor divider can
be removed and replaced with a series protection
resistor. For 20-mA input signals, the input resistor
divider is replaced by a 50-Ω resistor, connected from
each input to AINCOM.
−
2.5V
+2.5V
+
µ
µ
µ
µ
0.1 F
0.1
F
10
F
10
F
+
+2.5V
+2.5V
AVSS
AVDD
Ω
9.09k
Ω
Ω
OPA350
100
10k
±
±
10V
10V
AIN0
REFP
REFN
REF3125
µ
0.47
F
Ω
Ω
1k
+
+
µ
µ
F
µ
µ
0.1
F
10
−
100
F
0.1
F
2.5V
ADS1258
9.09k
AIN15
−
2.5V
Ω
1k
AINCOM
µ
NOTE: 0.1 F capacitors not shown.
2.2nF
Ω
Ω
47
+2.5V
Ω
10k
20mA Input
AINx
10k
+2.5V
OPA365
Ω
50
Ω
47
OPA365
−
2.5V
−
2.5V
Figure 68. Multichannel, ±10V Single-Ended Input, Bipolar Supply Operation
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+5V
+
RFI
0.1mF
10mF
2kW
2kW
AVSS
AVDD
RFI
RFI
AIN0
AIN1
REFP
+
10mF
0.1mF
REFN
2kW
2kW
ADS1258
RFI
RFI
RFI
AIN14
AIN15
AINCOM
+5V
2.2nF
47W
OPA365
R2
10kW
R1
2.2kW
R2
NOTE: G = 1 + 2R2/R1.
0.1mF supply bypass capacitor not shown.
10kW
47W
OPA365
Figure 69. Bridge Input, Single-Supply Operation
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Jan-2010
PACKAGING INFORMATION
Orderable Device
ADS1258IPHPREP
ADS1258IPHPREPG4
ADS1258MPHPTEP
ADS1258MPHPTEPG4
ADS1258MRTCTEP
V62/09626-01XE
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HTQFP
PHP
48
48
48
48
48
48
48
48
48
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
HTQFP
HTQFP
HTQFP
VQFN
PHP
PHP
PHP
RTC
RTC
PHP
PHP
PHP
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
VQFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
V62/09626-01YE
HTQFP
HTQFP
HTQFP
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
V62/09626-02XE
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
V62/09626-02YE
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADS1258-EP :
Catalog: ADS1258
•
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jan-2010
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
IMPORTANT NOTICE
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