SI7852DP-T1-E3
更新时间：2024-10-12 14:18:32
品牌：VISHAY
描述：TRANSISTOR 7.6 A, 80 V, 0.0165 ohm, N-CHANNEL, Si, POWER, MOSFET, ROHS COMPLIANT, POWERPAK, SOP-8, FET General Purpose Power
概述
规格参数
数据手册SI7852DP-T1-E3 概述
TRANSISTOR 7.6 A, 80 V, 0.0165 ohm, N-CHANNEL, Si, POWER, MOSFET, ROHS COMPLIANT, POWERPAK, SOP-8, FET General Purpose Power 功率场效应晶体管
SI7852DP-T1-E3 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Active | 零件包装代码： | SOT |
| 包装说明： | SMALL OUTLINE, R-XDSO-C5 | 针数： | 8 |
| Reach Compliance Code： | unknown | ECCN代码： | EAR99 |
| 风险等级： | 5.24 | 其他特性： | FAST SWITCHING |
| 外壳连接： | DRAIN | 配置： | SINGLE WITH BUILT-IN DIODE |
| 最小漏源击穿电压： | 80 V | 最大漏极电流 (Abs) (ID)： | 7.6 A |
| 最大漏极电流 (ID)： | 7.6 A | 最大漏源导通电阻： | 0.0165 Ω |
| FET 技术： | METAL-OXIDE SEMICONDUCTOR | JESD-30 代码： | R-XDSO-C5 |
| JESD-609代码： | e3 | 湿度敏感等级： | 1 |
| 元件数量： | 1 | 端子数量： | 5 |
| 工作模式： | ENHANCEMENT MODE | 最高工作温度： | 150 °C |
| 封装主体材料： | UNSPECIFIED | 封装形状： | RECTANGULAR |
| 封装形式： | SMALL OUTLINE | 峰值回流温度（摄氏度）： | 260 |
| 极性/信道类型： | N-CHANNEL | 最大功率耗散 (Abs)： | 5.2 W |
| 最大脉冲漏极电流 (IDM)： | 50 A | 认证状态： | Not Qualified |
| 子类别： | FET General Purpose Power | 表面贴装： | YES |
| 端子面层： | Matte Tin (Sn) | 端子形式： | C BEND |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | 40 |
| 晶体管应用： | SWITCHING | 晶体管元件材料： | SILICON |
| Base Number Matches： | 1 |
SI7852DP-T1-E3 数据手册
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Vishay Siliconix
www.vishay.com
N-Channel 80 V (D-S) MOSFET
FEATURES
• TrenchFET® power MOSFETs
• New low thermal resistance PowerPAK®
package with low 1.07 mm profile
PowerPAK® SO-8 Single
D
D
7
8
D
6
D
5
• PWM optimized for fast switching
• 100 % Rg tested
Available
• Material categorization: for definitions of
1
S
compliance please see www.vishay.com/doc?99912
2
3
S
S
APPLICATIONS
4
G
1
• Primary side switch for DC/DC applications
Top View
Bottom View
D
PRODUCT SUMMARY
VDS (V)
80
R
DS(on) max. () at VGS = 10 V
DS(on) max. () at VGS = 6 V
0.0165
0.0220
34
G
R
Qg typ. (nC)
D (A)
Configuration
I
12.5
S
Single
N-Channel MOSFET
ORDERING INFORMATION
Package
PowerPAK SO-8
Si7852DP-T1-E3
Si7852DP-T1-GE3
Lead (Pb)-free
Lead (Pb)-free and halogen-free
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
10 s
STEADY STATE
UNIT
Drain-source voltage
Gate-source voltage
VDS
80
80
20
V
VGS
20
TA = 25 °C
TA = 70 °C
12.5
10
7.6
6.1
50
Continuous drain current (TJ = 150 °C) a
ID
Pulsed drain current
IDM
IAS
IS
50
A
Avalanche current
Continuous source current (diode conduction) a
L = 0.1 mH
40
40
4.7
5.2
3.3
1.7
1.9
1.2
TA = 25 °C
TA = 70 °C
Maximum power dissipation a
PD
W
Operating junction and storage temperature range
Soldering recommendations (peak temperature) b, c
TJ, Tstg
-55 to +150
260
°C
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
RthJA
TYPICAL
MAXIMUM
UNIT
t 10 s
19
52
24
65
Maximum junction-to-ambient a
Steady state
Steady state
°C/W
Maximum junction-to-case (drain)
Notes
a. Surface mounted on 1" x 1" FR4 board
RthJC
1.5
1.8
b. See solder profile (www.vishay.com/doc?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper
(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not
required to ensure adequate bottom side solder interconnection
c. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components
S09-0268-Rev. E, 16-Feb-09
Document Number: 71627
1
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si7852DP
Vishay Siliconix
www.vishay.com
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Gate threshold voltage
Gate-body leakage
VGS(th)
IGSS
VDS = VGS, ID = 250 μA
2
-
-
-
V
VDS = 0 V, VGS
=
20 V
-
100
nA
VDS = 80 V, VGS = 0 V
VDS = 80 V, VGS = 0 V, TJ = 55 °C
VDS 5 V, VGS = 10 V
VGS = 10 V, ID = 10 A
-
-
-
1
Zero gate voltage drain current
On-state drain current a
IDSS
ID(on)
μA
A
-
5
50
-
-
-
0.0135
0.0175
25
0.0165
0.0220
-
Drain-source on-state resistance a
RDS(on)
VGS = 6 V, ID = 8 A
-
Forward transconductance a
Diode forward voltage a
Dynamic b
gfs
VDS = 15 V, ID = 10 A
-
S
V
VSD
IS = 2.8 A, VGS = 0 V
-
0.75
1.1
Total gate charge
Gate-source charge
Gate-drain charge
Gate resistance
Qg
Qgs
Qgd
Rg
-
-
34
7.5
11
0.6
17
11
40
31
45
41
-
V
DS = 40 V, VGS = 10 V, ID = 10 A
nC
-
-
0.1
-
1
Turn-on delay time
Rise time
td(on)
tr
td(off)
tf
25
17
60
45
75
-
VDD = 40 V, RL = 40
ID 1 A, VGEN = 10 V, Rg = 6
Turn-off delay time
Fall time
-
ns
-
Source-drain reverse recovery time
trr
IF = 2.8 A, di/dt = 100 A/μs
-
Notes
a. Pulse test; pulse width 300 μs, duty cycle 2 %
b. Guaranteed by design, not subject to production testing
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
S09-0268-Rev. E, 16-Feb-09
Document Number: 71627
2
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si7852DP
Vishay Siliconix
www.vishay.com
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
50
20
16
12
8
V = 40 V
DS
V
GS
= 10 V thru 6 V
I
D
= 10 A
40
30
20
10
0
5 V
4
3 V, 4 V
0
0
2
4
6
8
10
0
15
30
45
60
Q
- Total Gate Charge (nC)
V
DS
- Drain-to-Source Voltage (V)
g
Output Characteristics
Gate Charge
50
40
30
20
10
0
100
10
T
= 150 °C
J
T
= 125 °C
C
1
T
= 25 °C
J
0.1
25 °C
-55 °C
5
0.01
0
1
2
3
4
6
0.0
0.2
0.4
0.6
0.8
1.0
1.2
V
SD
- Source-to-Drain Voltage (V)
V
GS
- Gate-to-Source Voltage (V)
Transfer Characteristics
Source-Drain Diode Forward Voltage
0.04
0.03
0.02
0.01
0.00
3000
2500
2000
1500
1000
500
C
iss
V
GS
= 6 V
V
GS
= 10 V
C
rss
C
oss
0
0
10
20
30
40
50
0
20
40
60
80
I
D
- Drain Current (A)
V
DS
- Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current
Capacitance
S09-0268-Rev. E, 16-Feb-09
Document Number: 71627
3
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si7852DP
Vishay Siliconix
www.vishay.com
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
1.0
0.5
2.5
V
D
= 10 V
GS
= 10 A
I
2.0
1.5
1.0
0.5
0.0
I
D
= 250 µA
0.0
-0.5
-1.0
-1.5
-50
-25
0
25
50
75
100 125 150
-50
-25
0
25
50
75
100 125 150
T
- Temperature (°C)
J
T
- Junction Temperature (°C)
J
On-Resistance vs. Junction Temperature
Threshold Voltage
0.08
0.06
0.04
0.02
0.00
100
10
I
= 10 A
D
T = 25 °C
T = 125 °C
1
0.1
10
-5
-4
-3
-2
-1
0
2
4
6
8
10
10
10
10
10
1
10
V
GS
- Gate-to-Source Voltage (V)
Time (s)
On-Resistance vs. Gate-to-Source Voltage
Avalanche Current vs. Time
100
80
60
40
20
0
0.1
0.001
0.01
1
10
Time (s)
Single Pulse Power, Junction-to-Ambient
S09-0268-Rev. E, 16-Feb-09
Document Number: 71627
4
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si7852DP
Vishay Siliconix
www.vishay.com
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
2
1
Duty cycle = 0.5
0.2
Notes:
0.1
0.1
P
DM
0.05
t
1
t
2
t
t
1
2
1 .Duty cycle, D =
0.02
2. Per unit base = R
= 52 °C/W
thJA
(t)
3 . T - T = P
JM
Z
A
DM thJA
Single pulse
0.01
4. Surface mounted
-4
-3
-2
-1
10
10
10
10
1
10
100
600
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
2
1
Duty cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single pulse
0.01
-4
-3
-2
-1
10
10
10
10
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Case
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?71627.
S09-0268-Rev. E, 16-Feb-09
Document Number: 71627
5
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
PowerPAK® SO-8, (Single/Dual)
L
H
E2
K
E4
W
1
1
2
3
4
Z
2
3
4
D
L1
E3
A1
Backside View of Single Pad
L
H
K
E2
E4
2
E1
E
Detail Z
1
2
3
4
D1
D2
Notes
1. Inch will govern.
E3
2
Dimensions exclusive of mold gate burrs.
Backside View of Dual Pad
3. Dimensions exclusive of mold flash and cutting burrs.
MILLIMETERS
INCHES
NOM.
0.041
DIM.
MIN.
NOM.
1.04
MAX.
1.12
0.05
0.51
0.33
5.26
5.00
3.91
1.68
MIN.
0.038
0
MAX.
0.044
0.002
0.020
0.013
0.207
0.197
0.154
0.066
A
A1
b
0.97
-
-
0.33
0.23
5.05
4.80
3.56
1.32
0.41
0.013
0.009
0.199
0.189
0.140
0.052
0.016
c
0.28
0.011
D
5.15
0.203
D1
D2
D3
D4
D5
E
4.90
0.193
3.76
0.148
1.50
0.059
0.57 typ.
3.98 typ.
6.15
0.0225 typ.
0.157 typ.
0.242
6.05
5.79
3.48
3.68
6.25
5.99
3.84
3.91
0.238
0.228
0.137
0.145
0.246
0.236
0.151
0.154
E1
E2
E3
E4
e
5.89
0.232
3.66
0.144
3.78
0.149
0.75 typ.
1.27 BSC
1.27 typ.
-
0.030 typ.
0.050 BSC
0.050 typ.
-
K
K1
H
0.56
0.51
0.51
0.06
0°
-
0.022
0.020
0.020
0.002
0°
-
0.61
0.71
0.71
0.20
12°
0.024
0.028
0.028
0.008
12°
L
0.61
0.024
L1
0.13
0.005
-
-
W
M
0.15
0.25
0.36
0.006
0.010
0.014
0.125 typ.
0.005 typ.
ECN: S17-0173-Rev. L, 13-Feb-17
DWG: 5881
Revison: 13-Feb-17
Document Number: 71655
1
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VISHAY SILICONIX
www.vishay.com
Power MOSFETs
Application Note AN821
PowerPAK® SO-8 Mounting and Thermal Considerations
by Wharton McDaniel
PowerPAK SO-8 SINGLE MOUNTING
MOSFETs for switching applications are now available with
die on resistances around 1 m and with the capability to
handle 85 A. While these die capabilities represent a major
advance over what was available just a few years ago, it is
important for power MOSFET packaging technology to keep
pace. It should be obvious that degradation of a high
performance die by the package is undesirable. PowerPAK
is a new package technology that addresses these issues.
In this application note, PowerPAK’s construction is
described. Following this mounting information is presented
including land patterns and soldering profiles for maximum
reliability. Finally, thermal and electrical performance is
discussed.
The PowerPAK single is simple to use. The pin arrangement
(drain, source, gate pins) and the pin dimensions are the
same as standard SO-8 devices (see figure 2). Therefore, the
PowerPAK connection pads match directly to those of the
SO-8. The only difference is the extended drain connection
area. To take immediate advantage of the PowerPAK SO-8
single devices, they can be mounted to existing SO-8 land
patterns.
THE PowerPAK PACKAGE
The PowerPAK package was developed around the SO-8
package (figure 1). The PowerPAK SO-8 utilizes the same
footprint and the same pin-outs as the standard SO-8. This
allows PowerPAK to be substituted directly for a standard
SO-8 package. Being a leadless package, PowerPAK SO-8
utilizes the entire SO-8 footprint, freeing space normally
occupied by the leads, and thus allowing it to hold a larger
die than a standard SO-8. In fact, this larger die is slightly
larger than a full sized DPAK die. The bottom of the die
attach pad is exposed for the purpose of providing a direct,
low resistance thermal path to the substrate the device is
mounted on. Finally, the package height is lower than the
standard SO-8, making it an excellent choice for
applications with space constraints.
Standard SO-8
PowerPAK SO-8
Fig. 2
The minimum land pattern recommended to take full
advantage of the PowerPAK thermal performance see
Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs. Click on the PowerPAK SO-8 single in the index
of this document.
In this figure, the drain land pattern is given to make full
contact to the drain pad on the PowerPAK package.
This land pattern can be extended to the left, right, and top
of the drawn pattern. This extension will serve to increase
the heat dissipation by decreasing the thermal resistance
from the foot of the PowerPAK to the PC board and
therefore to the ambient. Note that increasing the drain land
area beyond a certain point will yield little decrease
in foot-to-board and foot-to-ambient thermal resistance.
Under specific conditions of board configuration, copper
weight and layer stack, experiments have found that
more than about 0.25 in2 to 0.5 in2 of additional copper
(in addition to the drain land) will yield little improvement in
thermal performance.
Fig. 1 PowerPAK 1212 Devices
Revision: 16-Mai-13
Document Number: 71622
1
For technical questions, contact: powermosfettechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Application Note AN821
www.vishay.com
Vishay Siliconix
PowerPAK® SO-8 Mounting and Thermal Considerations
For
the
lead
(Pb)-free
solder
profile,
see
PowerPAK SO-8 DUAL
www.vishay.com/doc?73257.
The pin arrangement (drain, source, gate pins) and the pin
dimensions of the PowerPAK SO-8 dual are the same as
standard SO-8 dual devices. Therefore, the PowerPAK
device connection pads match directly to those of the SO-8.
As in the single-channel package, the only exception is the
extended drain connection area. Manufacturers can likewise
take immediate advantage of the PowerPAK SO-8 dual
devices by mounting them to existing SO-8 dual land
patterns.
To take the advantage of the dual PowerPAK SO-8’s
thermal performance, the minimum recommended land
pattern can be found in Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click on the
PowerPAK 1212-8 dual in the index of this document.
The gap between the two drain pads is 24 mils. This
matches the spacing of the two drain pads on the
PowerPAK SO-8 dual package.
Fig. 3 Solder Reflow Temperature Profile
Ramp-Up Rate
+ 3 °C /s max.
120 s max.
REFLOW SOLDERING
Temperature at 150 - 200 °C
Temperature Above 217 °C
Maximum Temperature
Vishay Siliconix surface-mount packages meet solder reflow
reliability requirements. Devices are subjected to solder
60 - 150 s
255 + 5/- 0 °C
reflow as
a
test preconditioning and are then
reliability-tested using temperature cycle, bias humidity,
HAST, or pressure pot. The solder reflow temperature profile
used, and the temperatures and time duration, are shown in
figures 3 and 4.
Time at Maximum
Temperature
30 s
Ramp-Down Rate
+ 6 °C/s max.
30 s
260 °C
3 °C(max)
6 °C/s (max.)
217 °C
150 - 200 °C
150 s (max.)
60 s (min.)
Reflow Zone
Pre-Heating Zone
Maximum peak temperature at 240 °C is allowed.
Fig. 4 Solder Reflow Temperatures and Time Durations
Revision: 16-Mai-13
Document Number: 71622
2
For technical questions, contact: powermosfettechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Application Note AN821
www.vishay.com
Vishay Siliconix
PowerPAK® SO-8 Mounting and Thermal Considerations
THERMAL PERFORMANCE
Introduction
Because of the presence of the trough, this result suggests
a minimum performance improvement of 10 °C/W by using
a PowerPAK SO-8 in a standard SO-8 PC board mount.
A basic measure of a device’s thermal performance
is the junction-to-case thermal resistance, RthJC, or the
junction-to-foot thermal resistance, RthJF This parameter is
measured for the device mounted to an infinite heat sink and
is therefore a characterization of the device only, in other
words, independent of the properties of the object to which
the device is mounted. Table 1 shows a comparison of
the DPAK, PowerPAK SO-8, and standard SO-8. The
PowerPAK has thermal performance equivalent to the
DPAK, while having an order of magnitude better thermal
performance over the SO-8.
The only concern when mounting a PowerPAK on a
standard SO-8 pad pattern is that there should be no traces
running between the body of the MOSFET. Where the
standard SO-8 body is spaced away from the pc board,
allowing traces to run underneath, the PowerPAK sits
directly on the pc board.
Thermal Performance - Spreading Copper
Designers may add additional copper, spreading copper, to
the drain pad to aid in conducting heat from a device. It is
helpful to have some information about the thermal
performance for a given area of spreading copper.
TABLE 1 - DPAK AND POWERPAK SO-8
EQUIVALENT STEADY STATE
PERFORMANCE
Figure 6 shows the thermal resistance of a PowerPAK SO-8
device mounted on a 2-in. 2-in., four-layer FR-4 PC board.
The two internal layers and the backside layer are solid
copper. The internal layers were chosen as solid copper to
model the large power and ground planes common in many
applications. The top layer was cut back to a smaller area
and at each step junction-to-ambient thermal resistance
measurements were taken. The results indicate that an area
above 0.3 to 0.4 square inches of spreading copper gives no
PowerPAK
SO-8
Standard
SO-8
DPAK
Thermal
Resistance RthJC
1.2 °C/W
1 °C/W
16 °C/W
Thermal Performance on Standard SO-8 Pad Pattern
Because of the common footprint, a PowerPAK SO-8
can be mounted on an existing standard SO-8 pad pattern.
The question then arises as to the thermal performance
of the PowerPAK device under these conditions. A
characterization was made comparing a standard SO-8 and
a PowerPAK device on a board with a trough cut out
underneath the PowerPAK drain pad. This configuration
restricted the heat flow to the SO-8 land pads. The results
are shown in figure 5.
additional
thermal
performance
improvement.
A
subsequent experiment was run where the copper on the
back-side was reduced, first to 50 % in stripes to mimic
circuit traces, and then totally removed. No significant effect
was observed.
R
th
vs. Spreading Copper
(0 %, 50 %, 100 % Back Copper)
56
51
46
41
36
Si4874DY vs. Si7446DP PPAK on a 4-Layer Board
SO-8 Pattern, Trough Under Drain
60
50
40
Si4874DY
30
100 %
Si7446DP
0 %
20
50 %
10
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Spreading Copper (sq in)
0
Fig. 6 Spreading Copper Junction-to-Ambient Performance
0.0001
0.01
1
10000
100
Pulse Duration (sec)
Fig. 5 PowerPAK SO-8 and Standard SO-0 Land Pad Thermal
Path
Revision: 16-Mai-13
Document Number: 71622
3
For technical questions, contact: powermosfettechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Application Note AN821
www.vishay.com
Vishay Siliconix
PowerPAK® SO-8 Mounting and Thermal Considerations
Suppose each device is dissipating 2.7 W. Using the
SYSTEM AND ELECTRICAL IMPACT OF
PowerPAK SO-8
junction-to-foot thermal resistance characteristics of the
PowerPAK SO-8 and the standard SO-8, the die
temperature is determined to be 107 °C for the PowerPAK
(and for DPAK) and 148 °C for the standard SO-8. This is a
2 °C rise above the board temperature for the PowerPAK
and a 43 °C rise for the standard SO-8. Referring to figure 7,
a 2 °C difference has minimal effect on RDS(on) whereas a
In any design, one must take into account the change in
MOSFET RDS(on) with temperature (figure 7).
On-Resistance vs. Junction Temperature
1.8
43 °C difference has a significant effect on RDS(on)
.
V
= 10 V
= 23 A
GS
1.6
1.4
1.2
1.0
0.8
0.6
I
D
Minimizing the thermal rise above the board temperature by
using PowerPAK has not only eased the thermal design but
it has allowed the device to run cooler, keep rDS(on) low, and
permits the device to handle more current than the same
MOSFET die in the standard SO-8 package.
CONCLUSIONS
PowerPAK SO-8 has been shown to have the same thermal
performance as the DPAK package while having the same
footprint as the standard SO-8 package. The PowerPAK
SO-8 can hold larger die approximately equal in size to the
maximum that the DPAK can accommodate implying no
sacrifice in performance because of package limitations.
-50
-25
0
25
50
75
100 125 150
T
J
- Junction Temperature (°C)
Recommended PowerPAK SO-8 land patterns are provided
to aid in PC board layout for designs using this new
package.
Fig. 7 MOSFET RDS(on) vs. Temperature
A MOSFET generates internal heat due to the current
passing through the channel. This self-heating raises the
junction temperature of the device above that of the PC
board to which it is mounted, causing increased power
dissipation in the device. A major source of this problem lies
in the large values of the junction-to-foot thermal resistance
of the SO-8 package.
Thermal considerations have indicated that significant
advantages can be gained by using PowerPAK SO-8
devices in designs where the PC board was laid out for
the standard SO-8. Applications experimental data gave
thermal performance data showing minimum and
typical thermal performance in a SO-8 environment, plus
information on the optimum thermal performance
obtainable including spreading copper. This further
emphasized the DPAK equivalency.
PowerPAK SO-8 minimizes the junction-to-board thermal
resistance to where the MOSFET die temperature is very
close to the temperature of the PC board. Consider two
devices mounted on a PC board heated to 105 °C by other
components on the board (figure 8).
PowerPAK SO-8 therefore has the desired small size
characteristics of the SO-8 combined with the attractive
thermal characteristics of the DPAK package.
PowerPAK SO-8
Standard SO-8
107 °C
148 °C
0.8 °C/W
PC Board at 105 °C
16 C/W
Fig. 8 Temperature of Devices on a PC Board
Revision: 16-Mai-13
Document Number: 71622
4
For technical questions, contact: powermosfettechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR PowerPAK® SO-8 Single
0.260
(6.61)
0.150
(3.81)
0.024
(0.61)
0.026
(0.66)
0.050
(1.27)
0.032
(0.82)
0.040
(1.02)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Document Number: 72599
Revision: 21-Jan-08
www.vishay.com
15
Legal Disclaimer Notice
www.vishay.com
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
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including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
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© 2017 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED
Revision: 08-Feb-17
Document Number: 91000
1
SI7852DP-T1-E3 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| SI7852DP-T1-GE3 | VISHAY | N-Channel 80-V (D-S) MOSFET | 获取价格 |
|
| SI7856ADP-T1 | VISHAY | Power Field-Effect Transistor, N-Channel, Metal-oxide Semiconductor FET, | 获取价格 |
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| SI7856ADP-T1-E3 | VISHAY | TRANSISTOR 15 A, 30 V, 0.0037 ohm, N-CHANNEL, Si, POWER, MOSFET, ROHS COMPLIANT, LEADLESS, POWERPAK, SOP-8, FET General Purpose Power | 获取价格 |
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| SI7856ADP-T1-GE3 | VISHAY | TRANSISTOR 15 A, 30 V, 0.0037 ohm, N-CHANNEL, Si, POWER, MOSFET, HALOGEN FREE AND ROHS COMPLIANT, LEADLESS, POWERPAK, SOP-8, FET General Purpose Power | 获取价格 |
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|
| SI7858ADP-T1-E3 | VISHAY | TRANSISTOR 20 A, 12 V, 0.0026 ohm, N-CHANNEL, Si, POWER, MOSFET, ROHS COMPLIANT, LEADLESS, POWERPAK, SOP-8, FET General Purpose Power | 获取价格 |
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| SI7858ADP-T1-GE3 | VISHAY | TRANSISTOR 20 A, 12 V, 0.0026 ohm, N-CHANNEL, Si, POWER, MOSFET, HALOGEN FREE AND ROHS COMPLIANT, LEADLESS, POWERPAK, SOP-8, FET General Purpose Power | 获取价格 |
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