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SI7858DP

更新时间：2025-06-30 02:10:26
品牌：VISHAY
描述：N-Channel 12-V (D-S) MOSFET

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SI7858DP 概述

N-Channel 12-V (D-S) MOSFET N通道12 -V （D -S ）的MOSFET 功率场效应晶体管

SI7858DP 规格参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Transferred零件包装代码：SOT
包装说明：,针数：8
Reach Compliance Code：unknown风险等级：5.29
Is Samacsys：N配置：Single
最大漏极电流 (Abs) (ID)：18 AFET 技术：METAL-OXIDE SEMICONDUCTOR
JESD-609代码：e0工作模式：ENHANCEMENT MODE
最高工作温度：150 °C极性/信道类型：N-CHANNEL
最大功率耗散 (Abs)：5.4 W子类别：FET General Purpose Power
表面贴装：YES端子面层：Tin/Lead (Sn/Pb)
Base Number Matches：1

SI7858DP 数据手册

通过下载SI7858DP数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。

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SPICE Device Model Si7858DP  
Vishay Siliconix  
N-Channel 12-V (D-S) MOSFET  
CHARACTERISTICS  
• N-Channel Vertical DMOS  
• Macro Model (Subcircuit Model)  
• Level 3 MOS  
• Apply for both Linear and Switching Application  
• Accurate over the −55 to 125°C Temperature Range  
• Model the Gate Charge, Transient, and Diode Reverse Recovery  
Characteristics  
DESCRIPTION  
The attached spice model describes the typical electrical  
characteristics of the n-channel vertical DMOS. The subcircuit  
model is extracted and optimized over the −55 to 125°C  
temperature ranges under the pulsed 0-to-5V gate drive. The  
saturated output impedance is best fit at the gate bias near the  
threshold voltage.  
A novel gate-to-drain feedback capacitance network is used to model  
the gate charge characteristics while avoiding convergence difficulties  
of the switched Cgd model. All model parameter values are optimized  
to provide a best fit to the measured electrical data and are not  
intended as an exact physical interpretation of the device.  
SUBCIRCUIT MODEL SCHEMATIC  
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate  
data sheet of the same number for guaranteed specification limits.  
Document Number: 71024  
20-May-02  
www.vishay.com  
1
SPICE Device Model Si7858DP  
Vishay Siliconix  
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)  
Simulated  
Data  
Measured  
Data  
Parameter  
Symbol  
Test Conditions  
Unit  
Static  
Gate Threshold Voltage  
On-State Drain Currenta  
VGS(th)  
ID(on)  
0.91  
1265  
0.0019  
0.0031  
142  
V
A
VDS = VGS, ID = 250µA  
V
DS ≥ 5V, VGS = 4.5V  
VGS = 4.5V, ID = 25A  
VGS = 2.5V, ID =20A  
VDS = 6V, ID = 25A  
IS = 2.9A, VGS = 0V  
0.0024  
0.0031  
130  
Drain-Source On-State Resistancea  
rDS(on)  
Ω
Forward Transconductancea  
Diode Forward Voltagea  
gfs  
S
V
VSD  
0.76  
0.75  
Dynamicb  
Total Gate Charge  
Gate-Source Charge  
Gate-Drain Charge  
Turn-On Delay Time  
Rise Time  
Qg  
Qgs  
Qgd  
td(on)  
tr  
42  
6.7  
9.2  
41  
40  
6.7  
9.2  
40  
VDS = 6V, VGS = 4.5V, ID = 25A  
nC  
ns  
58  
40  
VDD = 6V, RL = 6Ω  
I
D ≅ 1A, VGEN = 4.5V, RG = 6Ω  
Turn-Off Delay Time  
Fall Time  
td(off)  
tf  
66  
140  
70  
118  
39  
Source-Drain Reverse Recovery Time  
trr  
50  
IF = 2.9A, di/dt = 100 A/µs  
Notes  
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.  
b. Guaranteed by design, not subject to production testing.  
www.vishay.com  
2
Document Number: 71024  
20-May-02  
SPICE Device Model Si7858DP  
Vishay Siliconix  
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)  
Document Number: 71024  
20-May-02  
www.vishay.com  
3

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