ICS8402 [ICSI]
350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER; 350MHZ ，水晶- TO- LVCMOS / LVTTL频率合成器
| 型号： | ICS8402 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER |
| 文件： | 总15页 (文件大小：248K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8402
Integrated
Circuit
Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-LVCMOS / LVTTL
F
REQUENCY
SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS8402 is a general purpose, Crystal-to- • 2 LVCMOS/LVTTL outputs
ICS
LVCMOS/LVTTL High Frequency Synthesizer and
• Selectable crystal oscillator interface
or LVCMOS/LVTTL TEST_CLK
HiPerClockS™
a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8402 has a selectable TEST_CLK or crystal
• Output frequency range: 15.625MHz to 350MHz
• Crystal input frequency range: 12MHz to 40MHz
• VCO range: 250MHz to 700MHz
inputs. The VCO operates at a frequency range of 250MHz
to 700MHz.TheVCO frequency is programmed in steps equal
to the value of the input reference or crystal frequency. The
VCO and output frequency can be programmed using the
serial or parallel interfaces to the configuration logic. The low
phase noise characteristics of the ICS8402 make it an ideal
clock source for Gigabit Ethernet and SONET applications.
• Parallel or serial interface for programming counter
and output dividers
• RMS period jitter: 8ps (typical)
• Cycle-to-cycle jitter: 40ps (typical)
• Full 3.3V or mixed 3.3V core/2.5V output supply voltage
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
OE0
OE1
VCO_SEL
XTAL_SEL
32 31 30 29 28 27 26 25
M5
M6
M7
M8
N0
N1
nc
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
XTAL2
TEST_CLK
0
TEST_CLK
XTAL_SEL
VDDA
XTAL1
1
OSC
ICS8402
XTAL2
S_LOAD
S_DATA
S_CLOCK
MR
PLL
GND
PHASE DETECTOR
9
10 11 12 13 14 15 16
÷2
÷4
0
1
MR
VCO
Q0
Q1
÷8
÷16
÷ M
32-Lead LQFP
7mm x 7mm x 1.4mm package body
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
Y Package
Top View
CONFIGURATION
INTERFACE
LOGIC
TEST
32-Lead VFQFN
M0:M8
N0:N1
5mm x 5mm x 0.75mm package body
K Package
Top View
8402AY
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 6, 2004
1
ICS8402
Integrated
Circuit
Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-LVCMOS / LVTTL
F
REQUENCY
SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes op- put divider to a specific default state that will automatically
eration using a 25MHz crystal. Valid PLL loop divider values occur during power-up. The TEST output is LOW when op-
for different crystal or input frequencies are defined in the erating in the parallel input mode. The relationship between
Input Frequency Characteristics, Table 5, NOTE 1.
the VCO frequency, the crystal frequency and the M divider
is defined as follows: fVCO = fxtal x M
The ICS8402 features a fully integrated PLL and therefore
requires no external components for setting the loop band- The M value and the required values of M0 through M8 are
width. A fundamental crystal is used as the input to the on- shown in Table 3B, Programmable VCO Frequency Function
chip oscillator.The output of the oscillator is fed into the phase Table.Valid M values for which the PLL will achieve lock for a
detector. A 25MHz crystal provides a 25MHz phase detector 25MHz reference are defined as 10 ≤ M ≤ 28.The frequency
reference frequency. The VCO of the PLL operates over a out is defined as follows: FOUT = fVCO = fxtal x M
N
N
range of 250MHz to 700MHz. The output of the M divider is
also applied to the phase detector.
Serial operation occurs when nP_LOAD is HIGH and
S_LOAD is LOW. The shift register is loaded by sampling
The phase detector and the M divider force the VCO output the S_DATA bits with the rising edge of S_CLOCK. The con-
frequency to be M times the reference frequency by adjusting tents of the shift register are loaded into the M divider and N
the VCO control voltage. Note that for some values of M (either output divider when S_LOAD transitions from LOW-to-HIGH.
too high or too low), the PLL will not achieve lock.The output of The M divide and N output divide values are latched on the
the VCO is scaled by a divider prior to being sent to each of HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH,
the LVCMOS output buffers. The divider provides a 50% out- data at the S_DATA input is passed directly to the M divider
put duty cycle.
and N output divider on each rising edge of S_CLOCK. The
serial mode can be used to program the M and N bits and
The programmable features of the ICS8402 support two in- test bits T1 and T0. The internal registers T0 and T1 deter-
mine the state of the TEST output as follows:
put modes to program the M divider and N output divider.
The two input operational modes are parallel and serial. Fig-
ure 1 shows the timing diagram for each mode. In parallel
mode, the nP_LOAD input is initially LOW. The data on in-
puts M0 through M8 and N0 and N1 is passed directly to the
M divider and N output divider. On the LOW-to-HIGH transi-
tion of the nP_LOAD input, the data is latched and the M
divider remains loaded until the next LOW transition on
nP_LOAD or until a serial event occurs. As a result, the M
and N bits can be hardwired to set the M divider and N out-
T1 T0
TEST Output
LOW
0
0
1
1
0
1
0
1
Shift Register Output
Output of M divider
CMOS Fout
S
ERIAL
L
OADING
S_CLOCK
T1
T0
*NULL
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
S_DATA
S_LOAD
nP_LOAD
t
t
H
S
t
S
P
ARALLEL LOADING
M, N
M0:M8, N0:N1
nP_LOAD
t
t
H
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
S
*NOTE: The NULL timing slot must be observed.
8402AY
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 6, 2004
2
ICS8402
Integrated
Circuit
Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-LVCMOS / LVTTL
F
REQUENCY
SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pullup
Description
1
M5
Input
Input
M divider inputs. Data latched on LOW-to-HIGH transition
of nP_LOAD input. LVCMOS / LVTTL interface levels.
2, 3, 4,
28, 29,
30, 31, 32
M6, M7, M8,
M0, M1,
M2, M3, M4
Pulldown
Pulldown
Determines output divider value as defined in Table 3C,
Function Table. LVCMOS / LVTTL interface levels.
5, 6
N0, N1
Input
7
nc
Unused
Power
No connect.
8, 16
GND
Power supply ground.
Test output which is ACTIVE in the serial mode of operation. Output
driven LOW in parallel mode. LVCMOS / LVTTL interface levels.
9
TEST
VDD
Output
Power
10
Core supply pin.
Output enable. When logic HIGH, the outputs are enabled (default).
When logic LOW, the outputs are in Tri-State. See Table 3D,
OE Function Table. LVCMOS / LVTTL interface levels.
11, 12
OE1, OE0
Input
Pullup
13
VDDO
Power
Output
Output supply pin.
14, 15
Q1, Q0
Clock outputs. LVCMOS / LVTTL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the outputs to go low. When logic LOW, the
17
MR
Input
Pulldown internal dividers and the outputs are enabled. Assertion of MR
does not effect loaded M, N, and T values.
LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of
S_CLOCK. LVCMOS / LVTTL interface levels.
18
19
S_CLOCK
S_DATA
Input
Input
Pulldown
Pulldown
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
20
21
S_LOAD
VDDA
Input
Pulldown
Power
Analog supply pin.
Selects between crystal or test inputs as the PLL reference source.
22
XTAL_SEL
Input
Pullup
Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW.
LVCMOS / LVTTL interface levels
23
TEST_CLK
Input
Input
Pulldown Test clock input. LVCMOS / LVTTL interface levels.
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
24, 25
XTAL2, XTAL1
Parallel load input. Determines when data present at M8:M0 is
Pulldown loaded into M divider, and when data present at N1:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
26
nP_LOAD
Input
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS / LVTTL interface levels.
27
VCO_SEL
Input
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
8402AY
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REV. B OCTOBER 6, 2004
3
ICS8402
Integrated
Circuit
Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-LVCMOS / LVTTL
F
REQUENCY
SYNTHESIZER
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
pF
pF
KΩ
KΩ
Ω
VDD, VDDA, VDDO = 3.465V
VDD, VDDA = 3.465V, VDDO = 2.625V
13
11
51
51
7
Power Dissipation Capacitance
(per output)
CPD
RPULLUP
Input Pullup Resistor
RPULLDOWN Input Pulldown Resistor
ROUT Output Impedance
5
12
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
Inputs
Conditions
MR nP_LOAD
M
N
S_LOAD S_CLOCK S_DATA
H
X
X
X
X
X
X
Reset. Forces outputs LOW.
Data on M and N inputs passed directly to the M
L
L
Data Data
Data Data
X
X
X
divider and N output divider. TEST output forced LOW.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
L
L
L
↑
L
L
↑
X
↑
L
X
H
H
X
X
X
X
Data
Data
L
L
L
H
H
H
X
X
X
X
X
X
↓
L
L
X
↑
Data
X
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
H
Data
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓= Falling edge transition
8402AY
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REV. B OCTOBER 6, 2004
4
ICS8402
Integrated
Circuit
Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-LVCMOS / LVTTL
F
REQUENCY
SYNTHESIZER
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
256
M8
0
128
M7
0
64
M6
0
32
M5
0
16
M4
0
8
4
M2
0
2
1
M0
0
VCO Frequency
(MHz)
M Divide
M3
1
1
•
M1
1
1
•
250
275
•
10
11
•
0
0
0
0
0
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
650
675
700
26
27
28
0
0
0
0
1
1
1
1
0
1
1
0
0
0
0
0
0
1
0
1
0
0
0
0
1
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency
of 25MHz.
TABLE 3D. OUTPUT ENABLE & CLOCK ENABLE FUNCTION TABLE
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Output Frequency
Inputs
Control Inputs
Output
(MHz)
N Divider Value
OE0
OE1
Q0
Q1
N1
0
N0
0
Minimum Maximum
0
0
1
1
0
1
0
1
Hi-Z
Hi-Z
2
4
125
62.5
350
175
Hi-Z
Enabled
Hi-Z
0
1
Enabled
Enabled
1
0
8
31.25
15.625
87.5
43.75
Enabled
1
1
16
8402AY
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REV. B OCTOBER 6, 2004
5
ICS8402
Integrated
Circuit
Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-LVCMOS / LVTTL
F
REQUENCY
SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
Inputs, VI
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Charac-
teristics is not implied.Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
Outputs, VO
Package Thermal Impedance, θJA
32 Lead LQFP
47.9°C/W (0 lfpm)
34.8°C/W (0 lfpm)
32 Lead VFQFN
Storage Temperature, TSTG
-65°C to 150°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.465
3.465
3.465
125
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
3.135
3.3
3.135
3.3
V
mA
mA
mA
IDDA
IDDO
18
10
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VCO_SEL, XTAL_SEL, MR,
S_LOAD, nP_LOAD, S_DATA,
S_CLOCK, OE0, OE1,
N0:N1, M0:M8
2
VDD + 0.3
VDD + 0.3
0.8
V
V
V
Input
VIH
High Voltage
TEST_CLK
2
VCO_SEL, XTAL_SEL, MR,
S_LOAD, nP_LOAD, S_DATA,
S_CLOCK, OE0, OE1,
N0:N1, M0:M8
-0.3
-0.3
Input
VIL
Low Voltage
TEST_CLK
1.3
V
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
S_DATA, S_LOAD, nP_LOAD
M5, OE0, OE1,
VDD = VIN = 3.465V
VDD = VIN = 3.465V
150
µA
Input
IIH
High Current
5
µA
µA
XTAL_SEL, VCO_SEL
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
S_DATA, S_LOAD, nP_LOAD
VDD = 3.465V,
VIN = 0V
-5
Input
IIL
Low Current
V
DD = 3.465V,
IN = 0V
M5, OE0, OE1,
XTAL_SEL, VCO_SEL
-150
2.6
µA
V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
V
0.5
NOTE 1: Outputs terminated with 50Ω to VDDO/2.
8402AY
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 6, 2004
6
ICS8402
Integrated
Circuit
Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-LVCMOS / LVTTL
F
REQUENCY
SYNTHESIZER
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V 5%, VDDO = 2.5V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.465
3.465
2.625
125
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
3.135
3.3
2.375
2.5
V
mA
mA
mA
IDDA
IDDO
18
10
TABLE 4D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V 5%, VDDO = 2.5V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VCO_SEL, XTAL_SEL, MR,
S_LOAD, nP_LOAD, S_DATA,
S_CLOCK, OE0, OE1,
N0:N1, M0:M8
2
VDD + 0.3
VDD + 0.3
0.8
V
V
V
Input
VIH
High Voltage
TEST_CLK
2
VCO_SEL, XTAL_SEL, MR,
S_LOAD, nP_LOAD, S_DATA,
S_CLOCK, OE0, OE1,
N0:N1, M0:M8
-0.3
-0.3
Input
VIL
Low Voltage
TEST_CLK
1.3
V
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
S_DATA, S_LOAD, nP_LOAD
M5, OE0, OE1,
VDD = VIN = 3.465V
150
µA
Input
IIH
High Current
VDD = VIN = 3.465V
5
µA
µA
XTAL_SEL, VCO_SEL
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
S_DATA, S_LOAD, nP_LOAD
VDD = 3.465V,
VIN = 0V
-5
Input
IIL
Low Current
VDD = 3.465V,
M5, OE0, OE1,
XTAL_SEL, VCO_SEL
-150
1.8
µA
VIN = 0V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
V
0.5
NOTE 1: Outputs terminated with 50Ω to VDDO/2.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
TEST_CLK; NOTE 1
12
12
40
40
50
MHz
MHz
MHz
fIN
Input Frequency XTAL1, XTAL2; NOTE 1
S_CLOCK
NOTE 1: For the input crystal and TEST_CLK frequency range, the M value must be set for the VCO to operate within
the 250MHz to 700MHz range. Using the minimum input frequency of 12MHz, valid values of M are 21 ≤ M ≤ 58.
Using the maximum frequency of 40MHz, valid values of M are 7 ≤ M ≤ 17.
8402AY
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REV. B OCTOBER 6, 2004
7
ICS8402
Integrated
Circuit
Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-LVCMOS / LVTTL
F
REQUENCY
SYNTHESIZER
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Fundamental
Frequency
12
40
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance (CO)
pF
TABLE 7A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
Output Frequency
15.625
350
80
MHz
ps
ps
ps
ns
ns
ns
ns
ns
ns
ns
%
tjit(cc)
tjit(per)
tsk(o)
tR / tF
Cycle-to-Cycle Jitter; NOTE 1, 3
Period Jitter, RMS; NOTE 1
Output Skew; NOTE 2, 3
Output Rise/Fall Time
40
8
20
60
20% to 80%
0.3
5
1.1
M, N to nP_LOAD
tS
Setup Time S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
5
M, N to nP_LOAD
5
tH
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
5
odc
Output Duty Cycle
PLL Lock Time
40
60
1
tLOCK
ms
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 7B. AC CHARACTERISTICS, VDD = VDDA = 3.3V 5%, VDDO = 2.5V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
Output Frequency
15.625
350
80
MHz
ps
ps
ps
ns
ns
ns
ns
ns
ns
ns
%
tjit(cc)
tjit(per)
tsk(o)
tR / tF
Cycle-to-Cycle Jitter; NOTE 1, 3
Period Jitter, RMS; NOTE 1
Output Skew; NOTE 2, 3
Output Rise/Fall Time
40
8
15
60
20% to 80%
0.3
5
1.0
M, N to nP_LOAD
tS
Setup Time S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
5
M, N to nP_LOAD
5
tH
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
5
odc
Output Duty Cycle
PLL Lock Time
40
60
1
tLOCK
ms
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
8402AY
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REV. B OCTOBER 6, 2004
8
ICS8402
Integrated
Circuit
Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-LVCMOS / LVTTL
F
REQUENCY
SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
1.65V 5%
1.25V 5%
2.05V 5%
SCOPE
SCOPE
,
,
VDD
VDD
,
VDDA
VDDO
VDDA
VDDO
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-1.65V 5%
-1.25V 5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
VOH
VREF
VDDO
Qx
Qy
2
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
VDDO
2
Histogram
Reference Point
(Trigger Edge)
tsk(o)
Mean Period
(First edge after trigger)
PERIOD JITTER
OUTPUT SKEW
VDDO
2
VDDO
2
VDDO
2
80%
80%
tR
Q0, Q1
➤
➤
20%
20%
tcycle n+1
tcycle n
➤
➤
Clock
Outputs
tF
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
CYCLE-TO-CYCLE JITTER
OUTPUT RISE/FALL TIME
VDDO
2
Q0, Q1
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
Output Duty Cycle/tPERIOD
8402AY
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REV. B OCTOBER 6, 2004
9
ICS8402
Integrated
Circuit
Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-LVCMOS / LVTTL
F
REQUENCY
SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS8402 provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VDDA pin.
3.3V
VDD
.01µF
.01µF
10Ω
VDDA
10µF
FIGURE 2. POWER SUPPLY FILTERING
CRYSTAL
I
NPUT NTERFACE
I
were chosen to minimize the ppm error. The optimum C1 and C2
values can be slightly adjusted for different board layouts.
The ICS8402 has been characterized with 18pF parallel resonant
crystals.The capacitor values, C1 and C2, shown in Figure 3 below
were determined using a 25MHz, 18pF parallel resonant crystal and
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p
ICS8402
Figure 3. CRYSTAL INPUt INTERFACE
8402AY
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 6, 2004
10
ICS8402
Integrated
Circuit
Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-LVCMOS / LVTTL
F
REQUENCY
SYNTHESIZER
RELIABILITY INFORMATION
TABLE 8A. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θ
JA by Velocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE 8B. θJAVS. AIR FLOW TABLE FOR A 32 LEAD VFQFN
θ
JA 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
34.8C/W
TRANSISTOR COUNT
The transistor count for ICS8402 is: 3784
8402AY
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 6, 2004
11
ICS8402
Integrated
Circuit
Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-LVCMOS / LVTTL
F
REQUENCY
SYNTHESIZER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 9A. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
8402AY
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REV. B OCTOBER 6, 2004
12
ICS8402
Integrated
Circuit
Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-LVCMOS / LVTTL
F
REQUENCY
SYNTHESIZER
PACKAGE OUTLINE - K SUFFIX FOR A 32 LEAD VFQFN
TABLE 9B. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
VHHD-2
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
0.80
0
1.00
0.05
A1
A3
b
--
0.25 Ref.
0.25
0.18
0.30
8
ND
NE
D
8
5.00 BASIC
2.25
D2
E
1.25
1.25
0.30
3.25
3.25
0.50
5.00 BASIC
2.25
E2
e
0.50 BASIC
0.40
L
Reference Document: JEDEC Publication 95, MO-220
8402AY
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 6, 2004
13
ICS8402
Integrated
Circuit
Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-LVCMOS / LVTTL
F
REQUENCY
SYNTHESIZER
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS8402AY
ICS8402AYT
ICS8402AK
ICS8402AKT
ICS8402AY
ICS8402AY
ICS8402AK
ICS8402AK
32 Lead LQFP
250 per tray
1000
32 Lead LQFP on Tape and Reel
32 Lead MLF
490 per tray
2500
32 Lead MLF on Tape and Reel
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-
mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use
in life support devices or critical medical instruments.
8402AY
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 6, 2004
14
ICS8402
Integrated
Circuit
Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-LVCMOS / LVTTL
F
REQUENCY
SYNTHESIZER
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
7A
8
3.3V AC Characteristics Table, changed Output Rise/Fall Time 1.4ns max.
to 1.1ns max.
B
8/1/03
7B
3.3V/2.5V AC Characteristics Table, changed Output Rise/Fall Time
1.4ns max. to 1.0ns max.
8
Pin Description Table - corrected OE0 and OE1 pin name to correspond with
the pin number.
Pin Description Table - corrected placement of Q0, Q1 pins to correspond with
Pin Assignment.
B
B
T1
T1
3
3
11/4/03
8/10/04
1
6
11
13
14
Pin Assignment - added 32 Lead VFQFN package.
AMR - added 32 Lead VFQFN Package Thermal Impedance.
Added 32 Lead VFQFN Thermal Resistance.
Add 32 Lead VFQFN Package Outline & Dimensions.
Ordering Information Table - added 32 Lead VFQFN ordering information
B
T8B
T9B
T10
10/6/04
8402AY
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REV. B OCTOBER 6, 2004
15
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