ICS9250-11 [ICSI]
Frequency Timing Generator for PENTIUM II/III Systems; 频率时序发生器奔腾II / III系统
| 型号： | ICS9250-11 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Timing Generator for PENTIUM II/III Systems |
| 文件： | 总8页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9250-11
Frequency Timing Generator for PENTIUM II/III Systems
General Description
Features
The ICS9250-11 is a main clock synthesizer chip for Pentium
II based systems using Rambus Interface DRAMs. This chip
provides all the clocks required for such a system when used
with a Direct Rambus Clock Generator (DRCG) chip such as
the ICS9212-01, 02, 03 and a PCI buffer 9112-17.
Generates the following system clocks:
- 6 - CPU Clocks 100/133MHz (2.5V).
- 2 - CPU/2 output for synchronous memory
reference (2.5V).
- 4 - fixed frequency Clocks @ 66.6MHz (3.3V).
- 2 - fixed frequency Clocks @ 33.3MHz (3.3V).
- 6 - IOAPIC Clocks @ ¼ of CPUCLK or 16.667MHz,
synchronous to CPU Clock (2.5V)
- 1 - 48MHz Clock (3.3V)
Spread Spectrum may be enabled by driving the SPREAD#
pin active. Spread spectrum typically reduces system EMI by
8dB to 10dB. This simplifies EMI qualification without
resorting to board design iterations or costly shielding. The
ICS9250-11 employs a proprietary closed loop design, which
tightly controls the percentage of spreading over process and
temperature variations.
- 2 - REF Clocks @ 14.31818MHz
0.5% typical down spread modulation on CPU, PCI,
IOAPIC, 3V66 and CPU/2 output clocks.
The CPU/2 clocks are inputs to the DRCG.
Uses external 14.318MHz crystal.
Block Diagram
X1
REF (0:1)
OSC
2
X2
Pin Configuration
CPUCLK (0:5)
IOAPIC(0:5)
6
PLL
Spread
Spectrum
SPREAD#
/ 2
/ 3
/ 4
/ 2
C
o
n
t
6
2
SEL 133/100#
SEL(0:1)
r
o
l
CPU/2 (0:1)
3V66 (0:3)
/ 2
/ 3
/ 2
4
2
/ 2
3V33 (0:1)
48MHz
PLL2
Power Groups:
VDDREF, GNDREF = REF, X1, X2
VDD66, GND66 = 3V66
VDD33, GND33 = 3V33
VDD48, GND48 = 48MHz
56-pin SSOP
VDDCOR, GNDCOR = PLL Core
VDDLCPU, GNDLCPU = CPUCLK
VDDLCPU/2 , GNDLCPU/2 = CPU/2
VDDLAPIC, GNDAPIC = IOAPIC
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the
latest version of all device data to verify that any information being relied
upon by the customer is current and accurate.
9250-11 Rev C 3/20/00
Third party brands and names are the property of their respective owners.
ICS9250-11
Pin Descriptions
Pin number
1, 52, 53
Pin name
GNDLAPIC
Type
PWR
Description
Ground pin for the IOAPIC outputs.
2.5V clock outputs running divide synchronous with the CPU
(Host bus) clock frequency. The default APIC is running at ¼ of
CPUCLK frequency.
2, 3, 50, 51, 54, 55 IOAPIC (0:5)
OUT
When FREQ_APIC is strapped low, the APIC is running at fixed
16.67 MHz.
If CPU = 133 MHz, APIC = CPU/8
If CPU = 100 MHz, APIC = CPU/6
4, 49, 56
5, 11
VDDLAPIC
VDDREF
X1
PWR
PWR
IN
Power pin for the IOAPIC outputs. 2.5V.
Power pin for REF clocks
XTAL_IN 14.318MHz crystal input
6
7
X2
OUT
XTAL_OUT Crystal output
3.3V 14.318 MHz clock output. APIC clock strapping option for
fixed 16.67 MHz APIC clock outputs.
If FREQ_APIC# = 0, APIC Clock = 16.67 MHz
If FREQ_APIC# = Open, APIC Clock = CPU/4
3.3V 14.318MHz clock output.
TEST# is sampled low (external with 10k pulldown). All clock
outputs are Tri-State.
power pin for the 3V66 clocks.
REF0
OUT
9
FREQ_APIC#
REF1
OUT
OUT
OUT
PWR
OUT
10
TEST#
12, 19
VDD66
66MHz outputs at 3.3V. These outputs are stopped when
CPU_STOP# is driven active..
13, 14, 17, 18
3V66[0:3]
8, 15, 16, 23, 24
GND
3V33MHz
VDDCOR
GND48
48MHz
VDD48
PWR
OUT
PWR
PWR
OUT
PWR
Ground pin for 3V outputs.
3.3V Fixed 33MHz clock output.
3.3V power for PLL core.
Ground pin for the 48MHz output
Fixed 48MHz clock output. 3.3V
Power pin for the 48MHz output.
21, 22
25
26
27
28
This selects the frequency for the CPU and CPU/2 outputs. High =
133MHz, Low=100MHz
29
SEL 133/100#
SEL[0:1]
IN
IN
30, 31
Function select pins. See truth table for details.
Enables spread spectrum when active(Low). modulates all the CPU,
PCI, IOAPIC, 3V66 and CPU/2 clocks. Does not affect the REF and
48MHz clocks. 0.5% down spread modulation.
Power pin for the CPU/2 clocks. 2.5V
2.5V clock outputs at 1/2 CPU frequency. 66MHz or50MHz
depending on the state of the SEL 133/100# input pin.
Ground pin for the CPU/2 clocks.
32
SPREAD#
IN
33
VDDLCPU/2
CPU/2[0:1]
PWR
OUT
34, 35
36
37, 44, 45
38, 39, 42, 43, 46,
47
GNDLCPU/2
GNDLCPU
PWR
PWR
Ground pin for the CPUCLKs
Host bus clock output at 2.5V. 133MHz or 100MHz depending on
the state of the SEL 133/100MHz.
CPUCLK[0:5]
VDDLCPU
OUT
PWR
40, 41, 48
Power pin for the CPUCLKs. 2.5V
2
ICS9250-11
Frequency Select:
SEL
133/100#
CPU
MHz
CPU/2
MHz
3V66
MHz
3V33
MHz
48
MHz
REF
MHz
SEL1 SEL0
IOAPIC MHz
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Tristate Tristate
Tristate Tristate Tristate Tristate
Tristate
N/A
N/A
100
100
N/A
50.00
50.00
N/A
66.6
66.6
N/A
33.3
33.3
N/A
OFF
48
N/A
14.318 ¼ CPUCLK/16.67
14.318 ¼ CPUCLK/16.67
TCLK/2 TCLK/4 TCLK/4 TCLK/8 TCLK/2 TCLK
TCLK/16
N/A
N/A
133.3
133.3
N/A
66.6
66.6
N/A
66.6
66.6
N/A
33.3
33.3
NA
OFF
48
N/A
14.318 ¼ CPUCLK/16.67
14.318 ¼ CPUCLK/16.67
Power Management Features:
SEL 133/100#
SEL1
0
SEL0
Function
0
0
0
1
All outputs Tri-State
Reserved
00
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
Active 100 MHz, 48 MHz PLL inactive
Active 100 MHz, 48 MHz PLL active
Test Mode
Reserved
Active 133 MHz, 48 MHz PLL inactive
Active 133 MHz, 48 MHz PLL active
3
ICS9250-11
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V+/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
CONDITIONS
MIN
2
TYP
MAX
VDD+0.3
0.8
UNITS
V
IH
V
V
V
IL
V -0.3
SS
IIH
IIL1
IIL2
V = VDD
5
A
µ
IN
V = 0 V; Inputs with no pull-up resistors
-5
IN
Input Low Current
A
µ
V = 0 V; Inputs with pull-up resistors
200
IN
CL = Max loads; Select @ 100 MHz
160
mA
mA
IDD3.3OP
IDD.25OP
Operating Supply
Current
CL = Max loads; Select @ 133 MHz
CL = Max loads; Select @ 100 MHz
160
75
CL = Max loads; Select @ 133 MHz
90
IDD3.3PD CL = Max loads
200
100
Powerdown Current
µA
IDD.25PD Input address VDD or GND
Input Frequency
Pin Inductance1
Fi
VDD = 3.3 V
14.318
18
MHz
Lpin
CIN
7
5
nH
pF
pF
pF
ms
Logic Inputs
Input Capacitance1
COUT
CINX
Ttrans
Output pin capacitance
X1 & X2 pins
6
13.5
22.5
3
Transition time1
Clk Stabilization1
To 1st crossing of target frequency
TSTAB
From VDD = 3.3 V to 1% target frequency
3
8
ms
ns
ns
ns
ns
ns
t
t
PZH,tPZL Output enable delay (all outputs)
PHZ,tPLZ Output disable delay (all outputs)
1
1
Delay1
8
TCPU-3V66 CPU @ 1.25V, 3V66 @ 1.5V
T3V66-3V33 3V66 @ 1.5V, 3V33 @ 1.5V
0
1.5
3.5
3.0
Skew1
1.5
1.0
TCPU-IOAPIC
CPU @ 1.25V, IOAPIC @ 1.25V
1Guaranteed by design, not 100% tested in production.
4
ICS9250-11
Electrical Characteristics - CPU
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
VOH2B
CONDITIONS
MIN
2
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
IOH = -12 mA
IOL = 12 mA
VOL2B
0.4
V
V
OH @ MIN = 1.0 V
OH @ MAX = 2.375 V
OL @ MIN = 1.2 V
OL @ MAX = 0.3 V
-27
27
Output High Current
IOH2B
IOL2B
mA
V
-27
V
Output Low Current
mA
V
30
1.6
1.6
55
Rise Time1
Fall Time1
Duty Cycle1
Skew window1
tr2B
tf2 B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
0.4
0.4
45
ns
ns
%
ps
ps
dt2B
tsk2B
VT = 1.25 V
175
150
Jitter, cycle-to-cycle1
tjcyc-cyc2B VT = 1.25 V
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPU/2
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
VOH2B
CONDITIONS
MIN
2
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
IOH = -12 mA
IOL = 12 mA
VOL2B
0.4
V
V
OH @ MIN = 1.0 V
OH @ MAX = 2.375 V
OL @ MIN = 1.2 V
OL @ MAX = 0.3 V
-27
27
Output High Current
IOH2B
mA
V
-27
V
Output Low Current
IOL2B
tr2B
mA
V
30
1.6
1.6
55
Rise Time1
Fall Time1
Duty Cycle1
Skew window1
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
0.4
0.4
45
ns
ns
%
ps
ps
tf2 B
dt2B
tsk2B
VT = 1.25 V
175
250
Jitter, cycle-to-cycle1
tjcyc-cyc2B VT = 1.25 V
1Guaranteed by design, not 100% tested in production.
5
ICS9250-11
Electrical Characteristics - 3V33
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
IOH = -14.5 mA
IOL = 9.4 mA
VOL1
0.4
V
V
OH @ MIN = 1.0 V
OH @ MAX = 3.135 V
OL @ MIN = 1.95 V
OL @ MAX = 0.4 V
-33
30
Output High Current
IOH1
IOL1
mA
V
-33
V
Output Low Current
mA
V
38
2.0
2.0
55
Rise Time1
Fall Time1
Duty Cycle1
Skew window1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.5
0.5
45
ns
ns
%
ps
ps
dt1
tsk1
VT = 1.5 V
250
250
Jitter, cycle-to-cycle1
tjcyc-cyc1 VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
IOH = -14.5 mA
IOL =9 mA
VOL1
0.4
V
V
OH @ MIN = 1.0 V
OH @ MAX = 3.135 V
OL @ MIN = 1.95 V
OL @ MAX = 0.4 V
-33
30
Output High Current
IOH1
IOL1
mA
V
-33
V
Output Low Current
mA
V
38
2.0
2.0
55
Rise Time1
Fall Time1
Duty Cycle1
Skew window1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.5
0.5
45
ns
ns
%
ps
ps
dt1
tsk1
VT = 1.5 V
250
500
Jitter, cycle-to-cycle1
tjcyc-cyc1 VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
6
ICS9250-11
Electrical Characteristics - REF, 48MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.4
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
IOH = -16 mA
IOL = 9 mA
VOL5
0.4
V
V
OH @ MIN = 1.0 V
OH @ MAX = 3.135 V
OL @ MIN = 1.95 V
OL @ MAX = 0.4 V
-29
29
Output High Current
IOH5
mA
V
-23
V
Output Low Current
IOL5
tr5
mA
V
27
4.0
Rise Time1
Fall Time1
Duty Cycle1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.0
1.0
45
ns
ns
%
ps
ps
tf5
4.0
dt5
55
Jitter, cycle-to-cycle1
Jitter, cycle-to-cycle1
tjcyc-cyc5 VT = 1.5 V, Fixed clocks
tjcyc-cyc5 VT = 1.5 V, Ref clocks
500
1000
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
VOH2B
CONDITIONS
MIN
2
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
IOH = -12 mA
IOL = 12 mA
VOL2B
0.4
V
V
OH @ MIN = 1.0 V
OH @ MAX = 2.375 V
OL @ MIN = 1.2 V
OL @ MAX = 0.3 V
-27
27
Output High Current
IOH2B
IOL2B
mA
V
-27
V
Output Low Current
mA
V
30
1.6
1.6
55
Rise Time1
Fall Time1
Duty Cycle1
Skew window1
tr2B
tf2 B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
0.4
0.4
45
ns
ns
%
ps
ps
dt2B
tsk2B
VT = 1.25 V
250
250
Jitter, cycle-to-cycle1
tjcyc-cyc2B VT = 1.25 V
1Guaranteed by design, not 100% tested in production.
7
ICS9250-11
Pin 1
.093
DIA. PIN (Optional)
D/2
Index
Area
E/2
PARTING LINE
H
L
DETAIL “A”
TOP VIEW
BOTTOM VIEW
-e-
B
A2
c
A
C
.004
SEE
DETAIL “A”
-E-
SEATING
PLANE
-D-
-C-
END VIEW
A1
SIDE VIEW
SYMBOL
COMMON DIMENSIONS
VARIATIONS
D
N
MIN.
.095
.008
.087
.008
.005
NOM.
.102
.012
.090
MAX.
.110
.016
.094
.0135
.010
MIN.
.720
NOM.
.725
MAX.
.730
A
A1
A2
B
AD
56
-
-
c
D
E
e
H
h
L
See Variations
.295
0.025 BSC
“For current dimensional specifications, see JEDEC 95.”
Dimensions in inches
.291
.299
.395
.010
.020
-
.420
.016
.040
.013
-
N
See Variations
0°
-
8°
56 Pin 300 mil SSOP Package
Ordering Information
ICS9250yF-11-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
PackageType
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the
latest version of all device data to verify that any information being relied
upon by the customer is current and accurate.
8
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