PHD63NQ03LT [NXP]
TrenchMOS logic level FET; 的TrenchMOS逻辑电平FET
| 型号： | PHD63NQ03LT |
| 厂家： | 
NXP |
| 描述： | TrenchMOS logic level FET |
| 文件： | 总14页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PHP/PHB/PHD63NQ03LT
TrenchMOS™ logic level FET
Rev. 01 — 14 June 2002
Product data
1. Product profile
1.1 Description
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™ technology.
Product availability:
PHP63NQ03LT in SOT78 (TO-220AB)
PHB63NQ03LT in SOT404 (D2-PAK)
PHD63NQ03LT in SOT428 (D-PAK).
1.2 Features
■ Logic level compatible
■ Low gate charge
1.3 Applications
■ DC to DC converters
■ Switched mode power supplies
1.4 Quick reference data
■ VDS = 30 V
■ Ptot = 111 W
■ ID = 68.9 A
■ RDSon ≤ 13 mΩ
2. Pinning information
Table 1:
Pinning - SOT78, SOT404, SOT428 simplified outline and symbol
Pin Description
Simplified outline
Symbol
1
2
3
gate (g)
mb
mb
d
s
mb
[1]
drain (d)
source (s)
g
mb mounting base,
connected to drain (d)
MBB076
2
2
1
3
1
3
Top view
MBK091
MBK116
MBK106
1
2 3
SOT78 (TO-220)
SOT404 (D2-PAK)
SOT428 (D-PAK)
[1] It is not possible to make connection to pin 2 of the SOT404 or SOT428 packages.
PHP/PHB/PHD63NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
3. Limiting values
Table 2:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
30
Unit
V
VDS
VDGR
VGS
VGSM
ID
drain-source voltage (DC)
25 °C ≤ Tj ≤ 175 °C
-
drain-gate voltage (DC)
gate-source voltage (DC)
peak gate-source voltage
drain current (DC)
25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ
-
30
V
-
±20
±25
68.9
48.7
240
111
+175
+175
V
tp ≤ 50 µs; pulsed; duty cycle = 25 %
Tmb = 25 °C; VGS = 10 V; Figure 2 and 3
Tmb = 100 °C; VGS = 10 V; Figure 2
Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3
Tmb = 25 °C; Figure 1
-
V
-
A
-
A
IDM
Ptot
Tstg
Tj
peak drain current
-
A
total power dissipation
storage temperature
junction temperature
-
W
°C
°C
−55
−55
Source-drain diode
IS
source (diode forward) current (DC) Tmb = 25 °C
-
-
68.9
48.7
A
A
ISM
peak source (diode forward) current Tmb = 25 °C; pulsed; tp ≤ 10 µs
9397 750 09822
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 June 2002
2 of 14
PHP/PHB/PHD63NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
03aa16
03aa24
120
120
P
der
(%)
I
der
(%)
80
80
40
40
0
0
0
50
100
150
200
( C)
0
50
100
150
200
°
T
mb
°
( C)
T
mb
Ptot
ID
Pder
=
× 100%
Ider
=
× 100%
-----------------------
-------------------
P
I
°
°
tot(25 C)
D(25 C)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
Fig 2. Normalized continuous drain current as a
function of mounting base temperature.
03ai84
3
10
I
D
(A)
t
p
= 10 µs
Limit R
= V
/ I
DS D
DSon
2
10
100 µs
DC
10
1 ms
1
1
10
10
V
(V)
DS
Tmb = 25 °C; IDM is single pulse; VGS = 10V.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 09822
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 June 2002
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PHP/PHB/PHD63NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
4. Thermal characteristics
Table 3: Thermal characteristics
Symbol Parameter
Conditions
Min Typ Max Unit
Rth(j-mb) thermal resistance from junction to mounting base Figure 4
-
-
1.35 K/W
Rth(j-a)
thermal resistance from junction to ambient
SOT78
vertical in still air
-
-
60
75
-
-
K/W
K/W
SOT428
SOT428 minimum footprint;
mounted on a PCB
SOT404 and SOT428
SOT404 minimum footprint;
mounted on a PCB
-
50
-
K/W
4.1 Transient thermal impedance
03ai83
10
Z
th(j-mb)
(K/W)
1
δ = 0.5
0.2
0.1
-1
t
10
p
P
0.05
δ =
T
0.02
t
t
p
single pulse
T
-2
10
10
-5
-4
10
-3
10
-2
10
-1
10
t
p
(s)
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
9397 750 09822
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Product data
Rev. 01 — 14 June 2002
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PHP/PHB/PHD63NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
5. Characteristics
Table 4:
Characteristics
Tj = 25 °C unless otherwise specified
Symbol Parameter
Conditions
Min Typ Max Unit
Static characteristics
V(BR)DSS drain-source breakdown voltage
ID = 250 µA; VGS = 0 V
Tj = 25 °C
30
27
-
-
-
-
V
V
V
V
V
V
Tj = −55 °C
VGS(th)
gate-source threshold voltage
drain-source leakage current
ID = 1 mA; VDS = VGS; Figure 9
Tj = 25 °C
1
1.9
2.5
-
Tj = 175 °C
0.6
-
-
-
Tj = −55 °C
2.9
IDSS
VDS = 30 V; VGS = 0 V
Tj = 25 °C
-
-
-
0.05
-
1
µA
Tj = 175 °C
500 µA
IGSS
gate-source leakage current
VGS = ±20 V; VDS = 0 V
VGS = 5 V; ID = 25 A; Figure 7 and 8
Tj = 25 °C
10
100 nA
RDSon
drain-source on-state resistance
-
-
-
15
24
11
17.7 mΩ
28.3 mΩ
Tj = 175 °C
VGS = 10 V; ID = 25 A; Figure 7 and 8
13
mΩ
Dynamic characteristics
Qg(tot)
Qgs
Qgd
Ciss
Coss
Crss
td(on)
tr
total gate charge
gate-source charge
gate-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
ID = 50 A; VDD = 15 V; VGS = 5 V; Figure 13
VGS = 0 V; VDS = 25 V; f = 1 MHz; Figure 11
VDD = 15 V; ID = 25 A; VGS = 4.5 V; RG = 5.6 Ω
-
-
-
-
-
-
-
-
-
-
9.6
4
-
-
-
-
-
-
-
-
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
3.2
920
275
110
12
140
10.5
14
td(off)
tf
turn-off delay time
fall time
Source-drain diode
VSD
trr
source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 12
-
-
-
0.95 1.2
V
reverse recovery time
recovered charge
IS = 10 A; dIS/dt = −100 A/µs; VGS = 0 V
23
12
-
-
ns
nC
Qr
9397 750 09822
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 June 2002
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PHP/PHB/PHD63NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
03ai85
03ai87
80
80
°
T = 25
C
j
I
I
V
> I x R
DS D DSon
10 V 6 V 5.5 V 5 V
D
D
(A)
(A)
60
60
4.5 V
4 V
°
175 C
°
= 25 C
T
j
40
20
0
40
20
0
3.5 V
= 3 V
V
GS
0
0.4
0.8
1.2
1.6
0
2
4
6
V
(V)
V
(V)
GS
DS
Tj = 25 °C
Tj = 25 °C and 175 °C; VDS > ID x RDSon
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values.
Fig 6. Transfer characteristics: drain current as a
function of gate-source voltage; typical values.
03ai86
03af18
30
2
°
T = 25
j
C
V
= 4.5 V
GS
a
R
DSon
(mΩ)
1.5
20
5 V
5.5V
6 V
1
0.5
0
10 V
10
0
0
20
40
60
I
80
-60
0
60
120
180
(A)
°
T ( C)
D
j
Tj = 25 °C
RDSon
a =
----------------------------
RDSon(25 C)
°
Fig 7. Drain-source on-state resistance as a function
of drain current; typical values.
Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature.
9397 750 09822
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 June 2002
6 of 14
PHP/PHB/PHD63NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
03ai29
03ai28
-1
3.2
10
I
D
V
GS(th)
(V)
(A)
-2
-3
-4
-5
-6
10
max
typ
2.4
1.6
0.8
0
10
10
10
10
min
typ
max
min
-60
0
60
120
180
0
0.8
1.6
2.4
3.2
°
T ( C)
V
(V)
j
GS
ID = 1 mA; VDS = VGS
Tj = 25 °C; VDS = 5 V
Fig 9. Gate-source threshold voltage as a function of
junction temperature.
Fig 10. Sub-threshold drain current as a function of
gate-source voltage.
03ai89
4
10
C
(pF)
3
10
C
iss
C
C
oss
rss
2
10
10
-1
2
10
10
1
10
V
(V)
DS
VGS = 0 V; f = 1 MHz
Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values.
9397 750 09822
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 June 2002
7 of 14
PHP/PHB/PHD63NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
03ai88
03ai90
80
10
V
I
= 50 A
V
= 0 V
GS
GS
(V)
D
I
S
(A)
T = 25 ˚C
j
8
6
4
2
0
60
V
= 15 V
DD
40
20
0
°
°
C
175
C
T = 25
j
0
0.4
0.8
1.2
1.6
0
5
10
15
20
V
(V)
Q
(nC)
SD
G
Tj = 25 °C and 175 °C; VGS = 0 V
ID = 50 A; VDD = 15 V
Fig 12. Source (diode forward) current as a function of
source-drain (diode forward) voltage; typical
values.
Fig 13. Gate-source voltage as a function of gate
charge; typical values.
9397 750 09822
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Product data
Rev. 01 — 14 June 2002
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PHP/PHB/PHD63NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
6. Package outline
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB
SOT78
E
p
A
A
1
q
mounting
base
D
1
D
(1)
L
L
2
1
Q
b
1
L
1
2
3
b
c
e
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
b
L
max.
(1)
2
e
A
b
D
E
L
D
L
1
A
c
UNIT
p
q
Q
1
1
1
4.5
4.1
1.39
1.27
0.9
0.7
1.3
1.0
0.7
0.4
15.8
15.2
6.4
5.9
10.3
9.7
15.0
13.5
3.30
2.79
3.8
3.6
3.0
2.7
2.6
2.2
mm
3.0
2.54
Note
1. Terminals in this zone are not tinned.
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
SC-46
00-09-07
01-02-16
SOT78
3-lead TO-220AB
Fig 14. SOT78 (TO-220AB).
9397 750 09822
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 June 2002
9 of 14
PHP/PHB/PHD63NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
2
Plastic single-ended surface mounted package (Philips version of D -PAK); 3 leads
(one lead cropped)
SOT404
A
A
E
1
mounting
base
D
1
D
H
D
2
L
p
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
D
E
A
A
b
UNIT
c
D
e
L
H
Q
1
1
p
D
max.
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
1.60
1.20
10.30
9.70
2.90 15.80 2.60
2.10 14.80 2.20
mm
11
2.54
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
99-06-25
01-02-12
SOT404
Fig 15. SOT404 (D2-PAK)
9397 750 09822
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 June 2002
10 of 14
PHP/PHB/PHD63NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads
(one lead cropped)
SOT428
seating plane
y
A
A
E
A
2
A
b
E
1
1
2
mounting
base
D
1
D
H
E
L
2
2
L
1
L
1
3
b
b
w
M
A
c
1
e
e
1
0
10
20 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
D
L
y
1
1
A
A
A
b
D
E
E
H
UNIT
b
b
c
e
e
1
L
L
w
2
1
2
1
E
1
2
max.
min.
min.
0.65
0.45
0.89
0.71
0.9
0.5
2.38
2.22
0.93
0.73
1.1
0.9
5.46
5.26
0.4 6.22
0.2 5.98
6.73
6.47
10.4 2.95
9.6
2.55
4.81
4.45
mm
4.57
0.2
0.2
4.0
2.285
0.5
Note
1. Measured from heatsink back to lead.
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
JEITA
99-09-13
01-12-11
SOT428
TO-252
SC-63
Fig 16. SOT428 (D-PAK)
9397 750 09822
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 June 2002
11 of 14
PHP/PHB/PHD63NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
7. Revision history
Table 5:
Revision history
CPCN
Rev Date
Description
01 20020614
-
Product data; initial version
9397 750 09822
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 June 2002
12 of 14
PHP/PHB/PHD63NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
8. Data sheet status
Data sheet status[1]
Product status[2]
Definition
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips Semiconductors
reserves the right to change the specification in any manner without notice.
Preliminary data
Product data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be published at a
later date. Philips Semiconductors reserves the right to change the specification without notice, in order to
improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the right to
make changes at any time in order to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change Notification (CPCN) procedure
SNW-SQ-650A.
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
9. Definitions
10. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Right to make changes — Philips Semiconductors reserves the right to
make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve
design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
11. Trademarks
TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
13 of 14
9397 750 09822
Product data
Rev. 01 — 14 June 2002
PHP/PHB/PHD63NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
1.4
2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 1
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Transient thermal impedance . . . . . . . . . . . . . . 4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 13
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
4
4.1
5
6
7
8
9
10
11
© Koninklijke Philips Electronics N.V. 2002.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 14 June 2002
Document order number: 9397 750 09822
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