CXD2412AQ [SONY]
Timing Generator for LCD Panels; 时序发生器，用于LCD面板
| 型号： | CXD2412AQ |
| 厂家： | 
SONY CORPORATION |
| 描述： | Timing Generator for LCD Panels |
| 文件： | 总36页 (文件大小：1948K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXD2412AQ
Timing Generator for LCD Panels
Description
100 pin QFP (Plastic)
The CXD2412AQ is a timing signal generator for
LCD panel drivers.
Features
• Generates the LCX007 drive pulse.
• Supports NTSC/PAL.
(With PAL, a video signal on which scanning line
conversion has been performed is used.)
• Supports WIDE.
• Supports HD (20 MHz band).
• Supports Muse-NTSC conversion signal (MNDC).
• Supports up/down and/or right/left inversion.
• Supports three-panel projector.
• Generates timing signal of external sample-and-
hold circuit.
• Generates line inversion and field inversion
signals.
• AC drive for LCD panel during no signal.
• AFC circuit supporting static and dynamic
fluctuations.
Applications
LCD projectors
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings (Ta = 25 °C)
• Supply voltage
• Input voltage
• Output voltage
VDD
VSS–0.5 to +7.0
V
VI VSS – 0.5 to VDD + 0.5 V
VO VSS – 0.5 to VDD + 0.5 V
• Operating temperature Topr
• Storage temperature Tstg
–20 to +75
°C
°C
–55 to +150
Recommended Operating Conditions
•
•
Supply voltage
VDD
5.0 ± 0.5
V
Operating temperature Topr
–20 to +75
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E94Y04-ST
CXD2412AQ
Block Diagram
RPD1
RPD2
RPD3
FPD1
9
86
94
6
7
84
95
8
PEO1
PEO2
PEO3
PWM1
LOOP
FILTER
FPD2 83
FPD3 97
85 PWM2
96 PWM3
48 N.C.
51 N.C.
52 N.C.
55 N.C.
56 N.C.
57 N.C.
PHASE
COMPARATOR
TC1
5
TC2 82
TC3 98
PLL-COUNTER
HSYNC 16
N.C.
N.C.
2
1
H-SYNC
DETECTOR
H-SKEW
HALF-H
KILLER
CKI1 12
CKI2 89
N.C.
58
DETECTOR
59 N.C.
60 N.C.
75 SLFR
32 RGT
47 DWN
33 XRGT
CKI3 92
CKO1 11
CKO2 88
CKO3 91
VSYNC 17
TST6 14
FIELD & LINE
CONTROLLER
61
18
19
FRP
HP1
HP2
V-SYNC
SEPERATER
(NOISE SHAPE)
TST1
24
TST2 25
TST3 26
TST4 27
TST5 30
20 HP3
21 HP4
22 HP5
XCLR
23
HP6
31
VP1 49
VP2 50
74 PCGW
71 SLSH1
V-TIMING
PULSE GENERATOR
VST 46
72
81
SLSH2
SLSH3
CP1
SLAUX 73
VSS0
VSS1
4
99
100
10
CP2
VSS2 13
36 HCK1A
37
H-TIMING
PULSE
GENERATOR
VSS3
VSS4
15
29
HCK2A
38 HCK1B
39 HCK2B
34 HSTA
41 HSTB
42 CLR
VSS5 40
VSS6
54
VSS7 65
VSS8
79
43
VSS10 87
VSS11 90
VSS12 93
ENB
44 VCK
45
PCG
62 XCLP1
63
VDD0
VDD1
3
XCLP2
64 PRG
28
VDD2 35
66
67
68
69
VDD3
VDD4
VDD5
SH1
SH2
SH3
SH4
53
70
78
76 NTPL
77 XWD
80
XHD
– 2 –
CXD2412AQ
Pin Description
Input pin for open
status
Pin No. Symbol I/O
Description
N.C.
—
—
—
—
I
Not connected
Not connected
Power supply
GND
1
N.C.
2
VDD0
VSS0
3
4
TC1
FPD1 pin pulse width adjustment
5
FPD1
PEO1
PWM1
RPD1
VSS1
O
O
I
Phase comparator output B-1 (for NTSC/PAL)
6
Loop filter integrator output 1
7
Loop filter integrator input 1
8
O
—
O
I
Phase comparator output A-1 (for NTSC/PAL)
9
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
CKO1
CKI1
VSS2
NTSC/PAL oscillation cell output
NTSC/PAL oscillation cell input
—
I
GND
TST6
VSS3
Test
L
—
I
GND
HSYNC
VSYNC
HP1
Hsync input (negative polarity)
I
Vsync input (negative polarity)
I
Switches for the horizontal display start position
L
L
L
L
L
H
L
L
L
L
HP2
I
Switches for the horizontal display start position
HP3
I
Switches for the horizontal display start position
HP4
I
Switches for the horizontal display start position
HP5
I
Switches for the horizontal display start position
HP6
I
Switches for the horizontal display start position
TST1
TST2
TST3
TST4
VDD1
VSS4
I
Test
I
Test
I
Test
I
Test
—
—
I
Power supply
GND
TST5
XCLR
RGT
Test
H
H
H
I
Cleared at 0 V
I
Right/left inversion identification signal input
Right/left inversion identification signal output
H start pulse A
XRGT
HSTA
VDD2
HCK1A
HCK2A
O
O
—
O
O
Power supply
H clock pulse 1A
H clock pulse 2A
– 3 –
CXD2412AQ
Input pin for open
status
I/O
Pin No. Symbol
Description
HCK1B
HCK2B
VSS5
HSTB
CLR
H clock pulse 1B
H clock pulse 2B
GND
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
O
O
—
O
O
O
O
O
O
I
H start pulse B
Clear pulse
ENB
Enable pulse
V clock pulse
Precharge pulse
V start pulse
VCK
PCG
VST
DWN
N.C.
Up/down inversion identification signal input
Not connected
H
—
I
VP1
Switches for the vertical display start position
Switches for the vertical display start position
Not connected
L
VP2
I
H
N.C.
—
—
—
—
—
—
—
—
—
—
O
O
O
O
—
O
O
O
O
—
I
N.C.
Not connected
VDD3
VSS6
N.C.
Power supply
GND
Not connected
N.C.
Not connected
N.C.
Not connected
N.C.
Not connected
N.C.
Not connected
N.C.
Not connected
FRP
AC drive inversion timing output
Video signal pedestal clamp pulse 1
Video signal pedestal clamp pulse 2
Precharge signal pulse
GND
XCLP1
XCLP2
PRG
VSS7
SH1
Sample-and-hold pulse 1
Sample-and-hold pulse 2
Sample-and-hold pulse 3
Resample-and-hold pulse
Power supply
SH2
SH3
SH4
VDD4
SLSH1
SLSH2
SLAUX
PCGW
Switches SH
L
L
Switches SH
I
Switches free-running identification line number
Switches PCG
I
H
H
I
– 4 –
CXD2412AQ
Input pin for open
status
Pin No. Symbol
I/O
I
Description
Switches between H inversion and F inversion
(H: H inversion / L: F inversion)
75
SLFR
H
H
H
I
I
Switches mode
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
NTPL
XWD
VDD5
Switches mode
—
—
I
Power supply
GND
VSS8
H
L
Switches mode
XHD
I
Switches SH
SLSH3
TC2
I
FPD2 pin pulse width adjustment
Phase comparator output B-2 (for WIDE)
Loop filter integrator output 2
Loop filter integrator input 2
Phase comparator output A-2 (for WIDE)
GND
FPD2
PEO2
PWM2
RPD2
VSS10
CKO2
CKI2
O
O
I
O
—
O
I
WIDE oscillation cell output
WIDE oscillation cell input
GND
VSS11
CKO3
CKI3
—
O
I
HD/MNDC oscillation cell output
HD/MNDC oscillation cell input
GND
VSS12
RPD3
PEO3
PWM3
FPD3
TC3
—
O
O
I
Phase comparator output A-3 (for HD/MNDC)
Loop filter integrator output 3
Loop filter integrator input 3
Phase comparator output B-3 (for HD/MNDC)
FPD3 pin pulse width adjustment
Switches pedestal clamp position
Switches pedestal clamp position
O
I
H
L
CP1
I
CP2
I
– 5 –
CXD2412AQ
Electrical Characteristics
1. DC characteristics
(Temperature = 25°C, Vss = 0V)
Typ.
Symbol
Conditions
Item
Max. Unit
Min.
4.5
VDD
VIH
VIL
5.5
V
V
Supply voltage
Input voltage
TTL input cell
2.2
TTL input cell
0.8
V
Input voltage
VIH
VIL
CMOS input cell
CMOS input cell
V
Input voltage
0.7VDD
0.3VDD
0.4
V
Input voltage
VOH
VOL
VOH
VOL
VOH
VOL
IIL
IOH = –4mA (HCKl, SHm)
V
Output voltage
Output voltage
Output voltage
Output voltage
Output voltage
Output voltage
Input leak current
Input leak current
Output leak current
Current consumption
VDD
– 0.8
IOL = 8mA (HCKl, SHm)
V
IOH = –3mA (CKOn, CKIn)
V
VDD/2
IOL = 3mA (CKOn, CKIn)
VDD/2
V
IOH = –2mA (other than the above)
IOL = 4mA (other than the above)
Pull-up resistor connected
V
VDD
– 0.8
0.4
–240
240
40
V
–100
100
µA
µA
µA
mA
–40
–40
–40
IIH
Pull-down resistor connected
RPDn, FPDn (at high impedance state)
HD mode, VDD = 5.0V (at no load)
ILZ
IDD
75
2. AC characteristics
Item
(VDD = 5.0 ± 10%)
Typ.
Applicable pins
CKIn
Conditions
Max.
Symbol
Min.
22
Unit
ns
ns
ns
ns
ns
ns
ns
Clock input cycle
∆t
CL = 30pF
CL = 30pF
CL = 30pF
CL = 30pF
CL = 30pF
CL = 30pF
10
10
20
15
25
15
Cross point time difference
Cross point time difference
Output rise delay
HCK1A, HCK2A
HCK1B, HCK2B
HCKl, SHm
∆t
tpr
tpf
Output fall delay
HCKl, SHm
tpr
Output rise delay
Other than HCK1 and SHm
Other than HCK1 and SHm
tpf
Output fall delay
dt1
CL = 30pF 0.05
CL = 30pF
CL = 30pF 0.1
0.25 ns
HCK1, SH1 delay time difference HCK1A, HCK1B, SH1
HCK1, SH1 delay time difference HCK1A, HCK1B, SH1
HCK2, SH1 delay time difference HCK2A, HCK2B, SH1
HCK2, SH1 delay time difference HCK2A, HCK2B, SH1
dt2
1
5
0.5
5
ns
ns
ns
%
dt1
dt2
CL = 30pF
CL = 30pF
CL = 30pF
1
tH/tH + tL
tH/tH + tL
45
45
52
52
HCK1 Duty
HCK2 Duty
HCK1A, HCK1B
HCK2A, HCK1B
%
Note) l = 1A, 1B, 2A, 2B
n = 1, 2, 3
m = 1, 2, 3, 4
– 6 –
CXD2412AQ
Timing Definition
VDD
0V
CK1
VDD
Output
0V
tpr
tpf
VDD
Output
0V
VDD
HCK1A
(HCK2A)
50%
50%
0V
VDD
HCK1B
(HCK2B)
50%
50%
0V
∆t
∆t
t
t
CK1
HCK1A
1B
50%
50%
50%
2A
2B
t1
t2
tH
tL
SH1
50%
50%
dt1
dt2
– 7 –
CXD2412AQ
– 8 –
CXD2412AQ
– 9 –
CXD2412AQ
Input Signal Specifications
1. Horizontal sync signal
• With NTSC, NTSC WIDE, PAL, PAL+, and MNDC, the standard signal is doubled in speed, and a 1/2 cycle,
1/2 width horizontal sync signal (H.SYNC) is input.
• With HD, a signal derived by cutting off the lower part of 3-value sync is input.
• Negative polarity input is used.
2. Vertical sync signal
• V.sync separated by synchronizing separation circuit and not doubled in speed is input as the vertical sync
signal.
• Negative polarity input is used.
• With this TG, the phase relationship between VSYNC and HSYNC is as follows;
(1) NTSC/NTSC WIDE/MNDC
Phase reference
HSYNC
(Double-speed H.sync)
VSYNC
(2) PAL/PAL+
Phase reference
HSYNC
(Double-speed H.sync )
VSYNC
The video signal has a 487-line effective period due to scanning line conversion.
(3) HD
ODD FIELD
HSYNC
VSYNC
Phase reference
EVEN FIELD
HSYNC
VSYNC
– 10 –
CXD2412AQ
Mode Selection
Mode selection is performed by means of three pins, as shown in the table.
NTPL
XWD
XHD
H
Mode
NTSC
H
L
H
H
L
H
PAL
H
L
H
NTSC WIDE
PAL+
L
H
L
X
X
L
HD
H
L
MNDC
– 11 –
CXD2412AQ
SH Pulse Switching
The phase relationship between HCK1A, HCK1B and SH1, SH2, SH3, SH4 is switched by SLSH1, SLSH2,
SLSH3.
SLSH1 = L
SLSH2 = L
SLSH3 = L
SLSH1 = H
SLSH2 = L
SLSH3 = L
SLSH1 = L
SLSH2 = H
SLSH3 = L
SLSH1 = H
SLSH2 = H
SLSH3 = L
Right scan driver
RGT = H
HCK1A
(HCK1B)
SH1
SH2
SH3
SH4
Left scan driver
RGT = L
HCK1A
(HCK1B)
SH1
SH2
SH3
SH4
– 12 –
CXD2412AQ
SLSH1 = L
SLSH2 = L
SLSH3 = H
SLSH1 = H
SLSH2 = L
SLSH3 = H
SLSH1 = H
SLSH2 = H
SLSH3 = H
SLSH1 = L
SLSH2 = H
SLSH3 = H
Right scan driver
RGT = H
HCK1A
(HCK1B)
SH1
SH2
SH3
SH4
Left scan driver
RGT = L
HCK1A
(HCK1B)
SH1
SH2
SH3
SH4
– 13 –
CXD2412AQ
Right/Left Inversion and Up/Down Inversion
The LCD panel is arranged in a delta pattern, where an identical signal line is 1.5-dot offset for every horizontal
line. For this reason, a 1.5-bit offset is made to the horizontal start pulse HST of the LCD between lines. HCK
and S/H (sample and hold) are also 1.5-bit offset in a similar manner.
When the panel is driven with right/left inversion or up/down inversion, this offset relationship becomes inverted
for even and odd lines. Moreover, since the dot arrangement is asymmetrical, the HST position is also offset.
Right/left inversion and up/down inversion are supported by the TG as follows.
(1) Two types of output pulses for right scan (A output) and left scan (B output) are prepared for HST, HCK to
allow right/left inversion present/absent mixed three-panel LCDs to be driven simultaneously. In addition,
XRGT (RGT inverse output) is prepared for the left scan panel. SH1 and SH3 connections to the driver are
reversed for sample-and-hold.
(2) Left scan pulses are output to the A output by setting the right/left inversion input pin RGT to low. Also,
XRGT is driven high by setting RGT to low.
(3) The A and B outputs output up scan pulses by setting the up/down inversion input pin DWN to low.
Right scan
Left scan
Right/left inversion compatible SH wiring diagram
SH1
SH2
SH3
SH4
A output
driver
H SCANNER
SH1
SH2
SH3
SH4
TG
Down scan
Up scan
Display area
SH1
SH2
SH3
SH4
B output
driver
The relationship between the output pins and switches is summarized below.
TG input pin
B output HST, HCK
A output HST, HCK
(Three-panel LCD auxiliary output)
DWN
RGT
H
For right scan, down scan
For left scan, down scan
For right scan, up scan
For left scan, up scan
For left scan, down scan
For right scan, down scan
For left scan, up scan
For right scan, up scan
H
H
L
L
H
L
L
– 14 –
CXD2412AQ
Horizontal Output Pulses
The HST pulses are offset for each line in accordance with the dot arrangement.
Video start
MCK
–2fh
16 : 9, right, down scan, odd line
16 : 9, left, down scan, odd line
16 : 9, right, up scan, even line
16 : 9, left, up scan, even line
HSTn
n = A.B
–3.5fh
16 : 9, right, down scan, even line
16 : 9, right, up scan, odd line
–0.5fh
16 : 9, left, down scan, even line
16 : 9, left, up scan, odd line
–5fh
4 : 3, right, down scan, odd line
4 : 3, left, down scan, odd line
4 : 3, right, up scan, even line
4 : 3, left, up scan, even line
–6.5fh
4 : 3, right, down scan, even line
4 : 3, right, up scan, odd line
–3.5fh
4 : 3, left, down scan, even line
4 : 3, left, up scan, odd line
– 15 –
CXD2412AQ
The phase relationship between the horizontal pulses is shown in the figure below.
The display start position can be changed by means of the HP pin while maintaining this relationship.
HSYNC
HSTn
n = A.B
VCK
FRP
1µs
PCG
1.2µs
0.7µs
FRP
PRG
ENB
0.4µs
CLR
3.1µs
XCLP1
XCLP2
0.55µs
1.2µs
2µs
0.15µs
– 16 –
CXD2412AQ
XCLP Pulse Switching
The phase relationship between HSYNC and XCLP1, XCLP2 is switched by means of CP1 and CP2.
–250ns
550ns
1350ns
2150ns
–650ns
150ns
950ns
1750ns
2550ns
HSYNC
XCLP1
CP1 = L; CP2 = L
CP1 = H; CP2 = L
CP1 = L; CP2 = H
CP1 = H; CP2 = H
CP1 = L; CP2 = L
CP1 = H; CP2 = L
CP1 = L; CP2 = H
CP1 = H; CP2 = H
Central value
XCLP2
Central value
– 17 –
CXD2412AQ
Vertical Output
The vertical display position is varied as shown below.
VP2
L
VP1
L
After 2H
After 1H
L
H
H
L
Central value
1H before
H
H
LCD Panel AC Driving for No Signal
With no signal, also, provision is made as follows for AC driving of the LCD panel.
Horizontal pulses The PLL is set to the free-running state.
Therefore, the horizontal pulse frequency depends on the PLL free-running frequency.
Vertical pulses
The number of lines is counted by an internal counter, and VST and FRP are output in a
specific cycle.
VST Cycle with No Signal
SLAUX = L
NTSC
NTSC-WIDE
MNDC
545H
PAL
PAL+
641H
577H
HD
SLAUX = H
All modes
769H
Note) This TG determines there to be no signal if there is no VSYNC input during the above cycle.
– 18 –
CXD2412AQ
– 19 –
CXD2412AQ
– 20 –
CXD2412AQ
– 21 –
CXD2412AQ
– 22 –
CXD2412AQ
– 23 –
CXD2412AQ
– 24 –
CXD2412AQ
– 25 –
CXD2412AQ
– 26 –
CXD2412AQ
– 27 –
CXD2412AQ
– 28 –
CXD2412AQ
– 29 –
CXD2412AQ
– 30 –
CXD2412AQ
– 31 –
CXD2412AQ
– 32 –
CXD2412AQ
– 33 –
CXD2412AQ
– 34 –
CXD2412AQ
Application Circuit
N . C .
N . C .
T S T 5
S S V
D D V
T S T 4
D D V
S S V
N . C .
T S T 3
T S T 2
T S T 1
H P 6
N . C .
N . C .
N . C .
N . C .
N . C .
F R P
H P 5
H P 4
H P 3
X C L P 1
X C L P 2
P R G
S S V
H P 2
H P 1
V S Y N C
H S Y N C
S H 1
S H 2
S H 3
S H 4
S S V
T S T 6
S S V
C K I 1
D D V
C K O 1
S L S H 1
S S V
S L S H 2
S L A U X
P C G W
S L F R
R P D 1
P W M 1
P E O 1
F P D 1
T C 1
N T P L
X W I D
S S V
D D V
N . C .
N . C .
D D V
S S V
X H D
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 35 –
CXD2412AQ
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
+ 0.1
0.15 – 0.05
23.9 ± 0.4
+ 0.4
20.0 – 0.1
A
0.65
+ 0.35
2.75 – 0.15
±0.12
M
0.15
0° to 15°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
EPOXY RESIN
SOLDER PLATING
QFP-100P-L01
SONY CODE
QFP100-P-1420-A
EIAJ CODE
LEAD MATERIAL
COPPER / 42 ALLOY
1.4g
PACKAGE WEIGHT
JEDEC CODE
– 36 –
相关型号：
©2020 ICPDF网 联系我们和版权申明