CXD2422R [SONY]
CCD Camera Timing Generator; CCD相机时序发生器
| 型号： | CXD2422R |
| 厂家： | 
SONY CORPORATION |
| 描述： | CCD Camera Timing Generator |
| 文件： | 总22页 (文件大小：1041K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXD2422R
CCD Camera Timing Generator
Description
64 pin LQFP (Plastic)
The CXD2422R generates the timing pulses
required for driving and signal processing CCDs with
480,000 pixels (EIA, effective pixels) and CCDs with
570,000 pixels (CCIR, effective pixels).
Features
• EIA and CCIR compatible
• Compatible with component digital and composite
digital recording format
• Compatible with field/frame accumulation modes
Absolute Maximum Ratings
• Supply voltage
• Input voltage
• Output voltage
VDD
VI
VSS – 0.5 to +7.0
VSS – 0.5 to VDD + 0.5
VSS – 0.5 to VDD + 0.5
V
V
V
Applications
CCD cameras
VO
• Operating temperature
Structure
Silicon gate CMOS IC
Topr
• Storage temperature
Tstg
–20 to +75
°C
°C
–55 to +150
Applicable CCD Image Sensors
ICX062/063AL
Recommended Operating Conditions
• Supply voltage
VDD
4.5 to 5.5
V
• Operating temperature
Block Diagram
Topr
–20 to +75
°C
51
1
2
3
4
5
6
39
XSG1
SD 30
Shift
Register
SC
31
38 XSG2
V latch
13
32
LD
Latch
4
44
43
XV1
XV2
9
Shutter data
42 XV3
41
35 XSUB
HTSG
FLD/FRM
EIA/CCIR
58
61
62
63
XV4
Output
F.F.
Pulse Generation Circuit
HCLP1
HCLP2
VCLP
26
22
21
MODE
Reset
XH gate
Internal clock
High-speed
Pulse
Generation
Circuit
CLKI
33
PBLK
28
27
PBLKON
7
14 15
16
18 19
20 54 53 52 37 36
34
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E94Y30-ST
CXD2422R
Pin Configuration
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
LD
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC 49
SC
50
51
52
53
54
55
NC
SDO
BCO
BCI
SD
TEST7
PBLK
PBLKON
HCLP1
TEST6
VDD
XRG
VSS
VDD 56
NC
57
58
VSS
HTSG
HCLP2
RST 59
VCLP
BBO
BBI
60
61
TEST12
FLD/FRM
EIA/CCIR 62
SHD
NC
63
64
MODE
TEST13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
– 2 –
CXD2422R
Pin Description
Pin No.
1
Symbol
I/O
O
O
O
O
I
Description
D0
Extended I/O output.
Extended I/O output.
Extended I/O output.
Extended I/O output.
D1
2
D2
3
D3
4
VD
Vertical sync signal input. (With pull-up resistor)
Horizontal sync signal input. (With pull-up resistor)
Two frequency divider output of Pin 33.
5
HD
6
I
CLK
7
O
—
I
VSS
8
TEST1
TEST2
TEST3
TEST4
TEST5
SHP
BAI
Test input (normally Low). (With pull-down resistor)
Test input (normally Low). (With pull-down resistor)
Test input (normally Low). (With pull-down resistor)
Test input (normally Low). (With pull-down resistor)
Test input (normally Low). (With pull-down resistor)
CCD output precharge level sampling pulse output.
Buffer input (for phase adjustment of SHP). (With pull-up resistor)
Non-inversed output of BAI.
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
I
I
I
I
O
I
BAO
(NC)
SHD
BBI
O
—
O
I
CCD output signal level sampling pulse output.
Buffer input (for phase adjustment of SHD). (With pull-up resistor)
Non-inversed output of BBI.
BBO
VCLP
HCLP2
VSS
O
O
O
—
—
I
Vertical clamp pulse output.
Horizontal (dummy bit block) clamp pulse output.
VDD
TEST6
HCLP1
PBLKON
PBLK
TEST7
SD
Test input (normally High). (With pull-up resistor)
Horizontal (OPB block) clamp pulse output.
Output ON/OFF of PBLK. (High: ON) (With pull-up resistor).
Preblanking pulse output.
O
I
O
I
Test input (normally High). (With pull-up resistor)
Serial data input for electronic shutter control. (With pull-up resistor)
Clock input for electronic shutter control. (With pull-up resistor)
Latch pulse input for electronic shutter control. (With pull-up resistor)
Clock input.
I
SC
I
LD
I
CLKI
CLKO
XSUB
XH2
I
Inversed output of CLKI.
O
O
O
O
Substrate pulse output for electronic shutter.
Clock output for horizontal register drive.
XH1
Clock output for horizontal register drive.
– 3 –
CXD2422R
Pin No.
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Symbol
XSG2
I/O
O
O
—
O
O
O
O
O
O
O
O
—
—
O
O
I
Description
Sensor charge readout pulse output.
XSG1
VSS
Sensor charge readout pulse output.
XV4
Clock output for vertical register drive.
Clock output for vertical register drive.
Clock output for vertical register drive.
Clock output for vertical register drive.
Test output (normally open).
XV3
XV2
XV1
TEST8
TEST9
TEST10
TEST11
(NC)
Test output (normally open).
Test output (normally open).
Test output (normally open).
(NC)
SDO
BCO
BCI
Serial data output for electronic shutter control.
Non-inversed output of BCI.
Buffer input (for phase adjustment of XRG). (With pull-up resistor)
Reset gate pulse output of output block.
XRG
VSS
O
—
—
—
I
VDD
(NC)
HTSG
RST
Readout pulse (XSG1, 2) ON/OFF. (High: OFF) (With pull-down resistor)
Test input (normally High). (With pull-up resistor)
I
TEST12
Test input (normally Low). (With pull-up resistor)
I
High: Field accumulation mode, Low: Frame accumulation mode.
(With pull-up resistor)
FLD/FRM
EIA/CCIR
MODE
61
62
63
64
I
I
I
I
High: EIA, Low: CCIR. (With pull-up resistor)
High: Component digital mode, Low: Composite digital mode.
(With pull-up resistor)
TEST13
Test input (normally Low). (With pull-up resistor)
Note) TEST12 and TEST13 have a built-in pull-up resistor.
Be sure to fix them at Low.
– 4 –
CXD2422R
Electrical Characteristics
1) DC characteristics
(VDD = 4.5 to 5.5V, Topr = –20 to +75°C)
Conditions
Min.
4.5
Typ.
5.0
Max. Unit
Item
Symbol
Supply voltage
VDD
5.5
V
V
V
V
V
V
Input/Output voltages VI, VO
VSS
VDD
VIH
0.7VDD
Input voltage
VIL
0.3VDD
VOH
Output voltage
VOL
IOH = –2mA
IOL = 4mA
VDD – 0.8
40k
0.4
Pull-up/
RPU,
RPD
VIL = 0V, VIH = VDD
100k
250k
Ω
Pull-down resistors
2) AC characteristics
2)-1. Pulses for electronic shutter control (SD, SC, LD)
SD
ts1
tH1
SC
tw1
ts2
tH2
LD
tw2
Symbol
ts1
Item
Min.
20ns
20ns
20ns
20ns
20ns
20ns
SD set-up time, activated by the rising edge of SC
SD hold time, activated by the rising edge of SC
SC pulse width
tH1
tw1
ts2
SC set-up time, activated by the rising edge of LD
SC hold time, activated by the rising edge of LD
LD pulse width
tH2
tw2
– 5 –
CXD2422R
2)-2. HD/VD take-in characteristics
HD, VD
1.6V
1.6V
0.7VDD
ts3
CLK
th3
(VDD = 4.5 to 5.5V, Topr = –20 to +75°C)
Symbol
Definition
Min.
4
Typ.
Max. Unit
ts3
th3
HD/VD set-up time, activated by CLK
HD/VD hold time, activated by CLK
ns
ns
0
2)-3. Field discrimination characteristics
1.6V
1.6V
VD
HD
VD
HD
tpd1
tpd1
When the HD logic level is Low tpd1 after
VD falls, the field is discriminated as an
ODD (EVEN with CCIR) field.
When the HD logic level is High tpd1 after
VD falls, the field is discriminated as an
EVEN (ODD with CCIR) field.
(VDD = 4.5 to 5.5V, Topr = –20 to +75°C)
Definition
Min.
890
Typ.
Max. Unit
ns
Symbol
tpd1
Field discriminating clock phase, activated by the falling edge of VD
– 6 –
CXD2422R
2)-4. CLKO, CLK, XH1, XH2, XRG, SHP, SHD phase characteristics
CLKI
tpd3
CLKO
tpd2
tpd5
CLK
tpd4
tpd7
XH1
tpd6
tpd8
XH2
tpd9
tpd11
XRG
tpd10
tpd12
SHP
tpd13
tpd15
SHD
tpd14
(VDD = 4.5 to 5.5V, Topr = –20 to +75°C, load capacitance = 10pF)
Symbol
tpd2
Definition
Min.
3.5
4.0
5.2
6.5
5.2
6.4
5.7
5.3
4.7
5.2
8.1
7.9
7.9
8.6
Typ.
6.2
Max. Unit
CLKO falling delay time against CLKI
CLKO rising delay time against CLKI
CLK2 falling delay time against CLKI
CLK2 rising delay time against CLKI
XH1 falling delay time against CLKI
XH1 rising delay time against CLKI
XH2 rising delay time against CLKI
XH2 falling delay time against CLKI
XRG falling delay time against CLKI
XRG rising delay time against CLKI
SHP rising delay time against CLKI
SHP falling delay time against CLKI
SHD falling delay time against CLKI
SHD rising delay time against CLKI
12.1
14.1
18.3
22.8
17.2
22.4
20.3
18.5
16.5
18.1
28.3
27.6
27.6
29.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tpd3
7.2
tpd4
9.3
tpd5
11.6
8.8
tpd6
tpd7
11.4
10.2
9.4
tpd8
tpd9
tpd10
tpd11
tpd12
tpd13
tpd14
tpd15
8.4
9.2
14.4
14.1
14.1
15.2
– 7 –
CXD2422R
Phases of SHP, SHD, and XRG pulses can be adjusted using on-chip buffers.
Internal CXD2422R
R
SHP
15
C
BAI
16
17
BAO
SHP
Delay times of SHP, SHD, and XRG can be adjusted with C and R.
Delay characteristics of on-chip buffers (VDD = 4.5 to 5.5V, Topr = –20 to +75°C, load capacitance = 10pF)
Symbol
tpd16
tpd17
tpd18
tpd19
tpd20
tpd21
Definition
Rising delay time from BAI to BAO
Min.
4.0
2.8
4.0
3.0
4.3
3.4
Typ.
7.1
5.5
7.0
5.4
7.6
6.0
Max. Unit
13.9
10.7
13.8
10.7
15.0
11.7
ns
ns
ns
ns
ns
ns
Falling delay time from BAI to BAO
Rising delay time from BBI to BBO
Falling delay time from BBI to BBO
Rising delay time from BCI to BCO
Falling delay time from BCI to BCO
3) I/O pin capacitances
Item
(VDD = VI = 0V, f = 1MHz)
Min. Typ. Max. Unit
Symbol
CIN
Input pin capacitance
Output pin capacitance
9
pF
pF
COUT
11
– 8 –
CXD2422R
Description of Operation
1) Mode setting
Symbol
Pin No.
62
Low
CCIR
High
EIA
EIA/CCIR
Composite digital mode
Component digital mode
Clock (CLKI) input
Clock (CLKI) input
MODE
63
EIA 35.79545MHz
(2275fH = 10fsc)
EIA 36MHz
(2288fH)
CCIR 35.46895MHz
CCIR 36MHz
(2304fH)
(2270+8/625fH = 8fsc)
FLD/FRM
HTSG
61
58
27
Frame accumulation
Field accumulation
XSG1 and XSG2 pulses are output.
XSG1 and XSG2 pulses are fixed at
High. (Readout suspended)
PBLKON
PBLK is fixed at High.
PBLK pulse is output.
– 9 –
CXD2422R
2) Inputting serial data
The accumulation time of the electronic shutter is controlled by external serial data.
Input pins (SD, SC, and LD) are used to input serial data.
SD: Serial data input
SC: Clock input
LD: Latch pulse input
The following is the serial data timing chart.
SD
D3
D2
D1
D0
S8
S7
S6
S5
S4
S3
S2
S1
S0
SC
LD
D3 to D0: Not related to the accumulation time of the electronic shutter. Data are output to D3 to D0 pins
after converted into parallel data and being latched at LD.
S8 to S0: Sdata is set in 9-bit binary with S8 as MSB (High: 1, Low: 0). ON/OFF of the electronic shutter
and the accumulation time are determined by Sdata.
The calculation on the next page is for the accumulation time in each mode.
The data for SD are input to the internal 13-bit shift register, and the data can be retrieved as serial data at
SDO pin.
Note) The electronic shutter might operate from turning power on to inputting serial data. To prevent this
operation, process RST and LD pins as shown in the following figures. Be careful, however, as serial
data cannot be received before the voltage at RST rises.
VDD
RST
LD
32
59
(with pull-up resistor)
(with pull-up resistor)
4.7k
1000p
– 10 –
CXD2422R
Accumulation time of electronic shutter
EIA/
Sdata
CCIR
Accumulation time (s)
0
to
261
{(261 – Sdata)/15734} + 1/25678 (Component digital mode)
{(261 – Sdata)/15734} + 1/25532 (Composite digital mode)
EIA
262
Input prohibited
263
to
Electronic shutter OFF
511
0
to
311
{(311 – Sdata)/15625} + 1/25678 (Component digital mode)
{(311 – Sdata)/15625} + 1/25299 (Composite digital mode)
312
CCIR
Input prohibited
313
to
Electronic shutter OFF
511
The Sdata values corresponding to representative shutter speeds are listed below.
Sdata
Shutter speed
EIA
CCIR
1/100
1/125
1/250
1/500
1/1000
1/2000
104 (068h) 155 (09Bh)
136 (088h) 187 (0BBh)
199 (0C7h) 249 (0F9h)
230 (0E6h) 280 (118h)
246 (0F6h) 296 (128h)
254 (0FEh) 304 (130h)
– 11 –
CXD2422R
3) Latch pulse timing
Various mode switchings and shutter data are taken in by field. The latch pulse timing is as follows
(The broken lines show timing in the EVEN FIELD.):
EIA
VD
HD
VLT1
VLT2
IT
VLT3
XSG1,2
CCIR
VD
HD
VLT1
VLT2
IT
VLT3
XSG1,2
Latch pulse
VLT1
Latched data
EIA/CCIR, MODE, HTSG
VLT2
Shutter data (S8 to S0)
FLD/FRM
VLT3
– 12 –
CXD2422R
Example of System Configuration
36MHz (Component digital)
35.79545MHz (Composite digital, EIA)
35.56895MHz (Composite digital, CCIR)
Phase
Comparator
LPF
VCO
EXTfH
INTfH
Electronic shutter serial data
External sync
signal
19
20
33
fH
fV
Separation
of
fH and fV
15
SYNC
XH1, 2
XRG
1/2
Frequency
Division
14
13
HD
VD
To each
driver
XSUB
XV1 to 4
Pulse
26
MODE1
Generation
Circuit
XSG1, 2
CLK
38
7
SHP, SHD
HCLP1, 2
VCLP
HD
VD
Frequency Division/
Pulse Generation Circuit
To signal
processing
circuit
41
42
6
5
PBLK
CXD8302Q
CXD2422R (TG)
Note) 1. Either SYNC or VD/HD is used as external sync signal. When SYNC is used (SYNC synchronous
mode), fix MODE1 to High; when VD/HD is used (VD/HD Synchronous mode), fix MODE1 to Low.
2. Be sure to do phase comparison of the falling edge of EXTfH and INTfH for SYNC synchronous
mode.
– 13 –
CXD2422R
2 8 5
2 8 0
2 7 5
2 7 0
2 6 5
2 6 0
2 0
1 5
1 0
5
( 5 2 5 ) 0
5 2 0
– 14 –
CXD2422R
3 3 5
3 3 0
3 2 5
3 2 0
3 1 5
3 1 0
2 5
2 0
1 5
1 0
5
1
( 6 2 5 ) 0
6 2 0
– 15 –
CXD2422R
1 7 0
1 6 0
1 5 0
1 4 0
1 3 0
1 2 0
1 1 0
1 0 0
9 0
8 0
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0 ( 1 1 4 4 )
– 16 –
CXD2422R
1 7 0 . 5
1 6 0 . 5
1 5 0 . 5
1 4 0 . 5
1 3 0
1 2 0
1 1 0
1 0 0
9 0
8 0
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0 ( 1 1 3 7 . 5 )
– 17 –
CXD2422R
1 7 0
1 6 0
1 5 0
1 4 0
1 3 0
1 2 0
1 1 0
1 0 0
9 0
8 0
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0 ( 1 1 5 2 )
– 18 –
CXD2422R
1 7 0
1 6 0
1 5 0
1 4 0
1 3 0
1 2 0
1 1 0
1 0 0
9 0
8 0
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0 ( 1 1 3 5 )
– 19 –
CXD2422R
– 20 –
CXD2422R
Timing Chart (8) High-speed pulse timing
CLK
XH1
XH2
XRG
SHP
SHD
– 21 –
CXD2422R
Package Outline
Unit: mm
64PIN LQFP (PLASTIC)
12.0 ± 0.2
10.0 ± 0.1
48
33
49
64
32
A
17
(0.22)
16
1
+ 0.08
0.18 – 0.03
+ 0.05
0.127 – 0.02
0.5 ± 0.08
+ 0.2
1.5 – 0.1
0.1
0.1 ± 0.1
0° to 10°
NOTE: Dimension “ ” does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
EPOXY / PHENOL RESIN
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
SOLDER PLATING
LQFP-64P-L01
SONY CODE
EIAJ CODE
QFP064-P-1010-A
42 ALLOY
0.3g
JEDEC CODE
PACKAGE WEIGHT
– 22 –
相关型号：
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