CXD2403AR_技术文档

CXD2403AR

Timing Generator for Color Liquid Crystal Panel

Description

48 pin LQFP (Plastic)

The CXD2403AR is a timing signal generator for

color liquid crystal panel drivers.

Features

• Generates the LCX003, LCX004 and LCX005

drive pulses

• Supports line inversion and field inversion

• AC drive for liquid crystal panel during no signal

(NTSC/PAL)

Absolute Maximum Ratings (5V system)

(Ta = +25°C, VSS1 = 0V)

• Generates timing signal of external sample-and-

hold circuit

• Supply voltage

• Input voltage

• Output voltage

VCC

VI

–0.3 to +7.0

–0.3 to VDD +0.3

–20 to +75

V

• AFC circuit supporting static and dynamic

fluctuations

VO

V

• Operating temperature Topr

• Storage temperature Tstg

°C

• Pulse driver for liquid crystal panel driver (12.0V)

–55 to +125

Applications

Absolute Maximum Ratings (12V system)

Color liquid crystal viewfinders

(Ta = +25°C, VSS3 = 0V)

• Supply voltage

• Output voltage

VEE

VO

–0.3 to +20.0

–0.3 to VEE +0.3

–20 to +75

V

Structure

Silicon gate CMOS IC

• Operating temperature Topr

• Storage temperature Tstg

°C

–55 to +125

Recommended Operating Conditions (5V system)

• Supply voltage

VDD

2.7 to 5.5

V

• Operating temperature Topr

–20 to +75

°C

Recommended Operating Conditions (12V system)

• Supply voltage

VEE

11.5 to 12.5

–20 to +75

V

• Operating temperature Topr

°C

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication

or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony

cannot assume responsibility for any problems arising out of the use of these circuits.

E94421-TE

–1–

CXD2403AR

Block Diagram

Master CK

CKO

CKI

TST0

TST1

TST2

39

40

7

8

9

RPD

PLL Phase Comparator

37

XCLR

PLNT

SLCK

3

2

6

XCLP

35

H-SYNC

Detector

H-SKEW

Detector

36 HD

SYNC

27

Half-H

Killer

PLL

Counter

38

41

1

VDD1

VSS1

VDD2

N.C.

5

25 VSS2

VEE

13

24

10

N.C.

VSS3

11

12

14

15

V-SYNC

Separator

(Noise Shape)

HP1

HP2

HP3

HP4

45

46

47

48

16 CLR

26

28

N.C.

FLDI

H-Timing

Pulse

Generator

HST

21

HCK1

HCK2

SH1

23

22

31

42

43

N.C.

SH2

32

33

44

V-Timing

Pulse Generator

SH3

EN

VST

17

18

19

20

29

30

PAL Pulse

Eliminator

VCK1

VCK2

FLDO

VD

SLFR

4

Field & Line

Controller

34 FRP

–2–

CXD2403AR

Pin Description

(H: Pull Up, L: Pull Down)

Input Pin for

Open Status

Symbol

No.

I/O

Description

1

VDD2

PLNT

XCLR

SLFR

N.C.

SLCK

TST0

TST1

TST2

N.C.

VEE

I

5V system power supply

2

Switches between PAL (High) and NTSC (Low)

Reset at 0V

L

3

H

4

Switches between field inversion (High) and line inversion (Low)

No connected

L

5

—

L

6

I

Switches between LCX003/004 (Low) and LCX005 (High)

Test

7

L

8

I

Test

L

9

I

Test

L

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

—

I

No connected

—

No connected

12V system power supply

N.C.

CLR

EN

—

O

I

No connected

CLR pulse output (positive polarity)

EN pulse output (negative polarity)

V start pulse output (positive polarity)

V clock pulse 1 output (positive polarity)

V clock pulse 2 output (positive polarity)

H start pulse output (positive polarity)

H clock pulse 2 output (positive polarity)

H clock pulse 1 output (positive polarity)

12V system GND

VST

VCK1

VCK2

HST

HCK2

HCK1

VSS3

VSS2

N.C.

SYNC

FLDI

FLDO

VD

I

5V system GND

—

I

No connected

Composite sync input (positive polarity)

Field identification signal input ODD (High)/EVEN (Low)

Field identification signal output

VD pulse output (positive polarity)

Sample-and-hold pulse output (positive polarity)

AC drive timing pulse output

Burst position clamp pulse output (negative polarity)

HD pulse output (positive polarity)

Phase comparator output

I

O

I

SH1

SH2

SH3

FRP

XCLP

HD

RPD

VDD1

CKO

CKI

5V system power supply

O

I

Oscillation cell (output)

Oscillation cell (input)

–3–

CXD2403AR

No.

Input Pin for

Open Status

Symbol

I/O

Description

41

42

43

44

45

46

47

48

VSS1

N.C.

HP1

HP2

HP3

HP4

I

—

I

5V system GND

No connected

—

H

L

Switches for the horizontal display start position

I

L

I

H

Electrical Characteristics 1

DC Characteristics (VDD = 5.0V ± 10%)

Applicable

Measurement

Conditions

Item

Pins

Symbol

Min.

Typ.

Max.

Unit

V

Input

VIH

VIL

IOH

IOL

IOH

IOL

IOH

IOL

II

0.7*VDD

VSS

5.5

0.3*VDD

–2.0

SYNC

voltage

VOH = VDD–0.8V

VOL = 0.4V

Other than CKO and RPD

Output

4

VOH = VDD–0.8V

VOL = 0.4V

–2

RPD

current

2

–18

3.0

–2

mA

µA

VOH = VDD/2

VOL = VDD/2

VIN = VSS or VDD

VIN = VSS

–3.0

18

CKO

Normal input pins

2

Input leak

Pull-up resistor connected

IIL

–240

10

–10

240

40

current

Pull-down resistor connected

IIH

VIN = VDD

Output leak

IO2

VIN = VSS or VDD

–40

RPD (at high imedance state)

current

VOH

VOL

IOH

IOUT = –20µA

IOUT = 20µA

VOH = 11.5V (VEE=

12V)

11.9

—

12.0

0.0

—

0.1

Output

V

12V system output pins

voltage

–1.0

Output

mA

12V system output pins

current

Measurement

Item

Symbol

Min.

Typ.

Max.

Unit

mA

Conditions

Note 1)

IDD

IEE

25.0

2.0

Current

5V system

Note 1)

consumption

12V system

Note:

1. Master clock frequency FCKI = 12MHz, input conditions VIH = VDD, VIL = VSS, no output load.

–4–

CXD2403AR

AC Characteristics (VDD = 5.0V ± 10%)

5V System

Applicable

Pins

Measurement

Conditions

Item

Clock input cycle

Symbol

Min. Typ. Max. Unit

tck

tw (H)

tw (L)

tr (ck)

tf (ck)

tr

83

30

High level pulse width

Low level pulse width

Clock rise time

CKI

Note 4)

10

20

70

Clock fall time

ns

Output rise time

SH1, SH2

SH3

CL = 10pF

CL = 20pF

Output fall time

tf

Output rise delay time

Output fall delay time

5V system

output pins

tpr

tpf

12V System

tr

tf

CL = 10pF

CL = 40pF

CL = 10pF

CL = 40pF

CL = 10pF

CL = 40pF

CL = 10pF

CL = 40pF

CL = 10pF

CL = 40pF

(HCK1, HCK2)

CL = 20pF

(SH1) Note 5)

CL = 40pF

50

80

Output rise time

12V system all

Output pins

Note 3)

50

Output fall time

80

Cross point time difference

Note 2)

VCK1, 2

HCK1, 2

∆t

15

tpLH

160

Output rise delay time

Output fall delay time

12V system all

ouput pins

Note 3)

180 ns

160

tpHL

dt1

180

HCK1

SH1

80

90

125

HCK1, SH1 delay time difference

HCK2, SH2 delay time difference

HCK delay time difference

Notes:

HCK2

SH1

dt2

130

40

HCK1

HCK2

tH–tL

–30

2. Applicable to the relationships between HCK1 and HCK2, and VCK1 and VCK2.

3. 12V system output pins : HST, HCK1, HCK2, VST, VCK1, VCK2, EN, CLR.

4. CKI input voltage conditions : The input signal must have the full swing amplitude.

5.

Master clock frequency fCKI=8MHz.

–5–

CXD2403AR

Electrical Characteristics 2

DC Characteristics (VDD = 2.7V to 3.6V)

Applicable

Measurement

Conditions

Item

Pins

Symbol

Min.

Typ.

Max.

Unit

Input volt-

VIH

VIL

IOH

IOL

IOH

IOL

II

0.7*VDD

VSS

5.5

0.3*VDD

–1.1

V

SYNC

age Note) 4

VOH = VDD–0.8V

VOL = 0.4V

Other than CKO

Output

1.0

–8.0

0.75

–2

mA

current

CKO

VOH = VDD/2

VOL = VDD/2

VIN = VSS or VDD

VIN = VSS

–0.7

8.0

2

Normal input pins

Input leak

Pull-up resistor connected

IIL

–240

5

–3

current

Pull-down resistor connected

IIH

VIN = VDD

240

40

µA

Output leak

IO2

VIN = VSS or VDD

–40

RPD (at high imedance state)

current

VOH

VOL

IOH

IOL

IOUT = –20µA

11.9

—

12.0

0.0

—

0.1

V

Output

12V system output pins

voltage

IOUT = 20µA

VOH = 11.5V (VEE=

VOL = 0.5V 12V)

–1.0

mA

Output

12V system output pins

current

1.0

Measurement

Conditions

Item

Symbol

Min.

Typ.

Max.

Unit

mA

Current

5V system

IDD

IEE

Note 1)

25.0

2.0

consumption

12V system

Notes:

1. Master clock frequency FCKI = 12MHz, input conditions VIH = VDD, VIL = Vss, no output load.

4. CKI input voltage conditions : The input signal must have the full swing amplitude.

–6–

CXD2403AR

AC Characteristics (VDD = 2.7V to 3.6V)

5V System

Applicable

Pins

Measurement

Conditions

Item

Symbol

Min. Typ. Max. Unit

tck

tw (H)

tw (L)

tr (ck)

tf (ck)

tr

83

30

Clock input cycle

High level pulse width

Low level pulse width

Clock rise time

CKI

Note 4)

10

ns

Clock fall time

CL = 10pF

CL = 20pF

30

Output rise time

SH1, SH2

SH3

tf

30

Output fall time

tpr

200

Output rise delay time

Output fall delay time

5V system

output pins

tpf

12V System

tr

tf

CL = 10pF

CL = 40pF

CL = 10pF

CL = 40pF

CL = 10pF

CL = 40pF

CL = 10pF

CL = 40pF

CL = 10pF

CL = 40pF

(HCK1, HCK2)

CL = 20pF

(SH1) Note 5)

CL = 40pF

50

80

Output rise time

12V system all

Output pins

Note 3)

50

Output fall time

80

Cross point time difference

Note 2)

VCK1, 2

HCK1, 2

∆t

15

tpLH

200

Output rise delay time

12V system all

ouput pins

Note 3)

250 ns

200

tpHL

dt1

Output fall delay time

250

HCK1

SH1

80

90

145

HCK1, SH1 delay time difference

HCK2, SH2 delay time difference

HCK delay time difference

HCK2

SH1

dt2

145

40

HCK1

HCK2

tH–tL

–30

Notes:

2. Applicable to the relationships between HCK1 and HCK2, and VCK1 and VCK2.

3. 12V system output pins : HST, HCK1, HCK2, VST, VCK1, VCK2, EN, CLR.

4. CKI input voltage conditions : The input signal must have the full swing amplitude.

5. Master clock frequency fCKI = 8MHz.

–7–

CXD2403AR

Timing Definition for 5V System Pins

VDD

0V

Data input

tCK

tW (H)

100%

VDD

0V

CKI

0%

tW (L)

tr (CK)

tf (CK)

VDD

90%

5V system output

10%

0V

tr

tpr

VDD

90%

5V system output

10%

0V

tf

tpf

–8–

CXD2403AR

Timing Definition for 12V System Pins

VDD

0V

CKI

VEE

90%

12V system output

10%

0V

tr

tPLH

VEE

90%

12V system output

10%

0V

tf

tPHL

VEE

50%

VCK1

(HCK1)

0V

VCK2

(HCK2)

VEE

50%

0V

Dt

t

CKI

t – tL = 2(t – t1)

tH = t – t1 + t2

tL = t – t2 + t1

tH – tL = 2(t2 – t1)

50%

HCK1

(HCK2)

t1

t2

tH

tL

SH1

50%

dt1

dt2

–9–

CXD2403AR

Description of Functions

The structure of liquid crystal panel driven by this IC is shown below.

Liquid Crystal Panel Structure

Gate SW

B

R

B

R

B

R

B

R

B

G

R

G

R

G

R

B

G

B

G

B

G

B

G

B

G

B

R

480

2

473

5

LCX003

Basic Specifications

Total number of horizontal pixels

Number of horizontal display pixels

(A line) :

(B line) :

(A line) :

(B line) :

:

479H

480H

473H

230H

218H

Total number of vertical pixels

Number of vertical display pixels

:

Total number of pixels

:

110285

103114

Number of display pixels

–10–

CXD2403AR

Liquid Crystal Panel Structure

Gate SW

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

480

473

2

5

LCX004

Basic Specifications

Total number of horizontal pixels

Number of horizontal display pixels

(A line) :

(B line) :

(A line) :

(B line) :

:

479H

480H

473H

268H

260H

Total number of vertical pixels

Number of vertical display pixels

:

Total number of pixels

:

128506

122980

Number of display pixels

–11–

CXD2403AR

Liquid Crystal Panel Structure

Gate SW

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

B

R

G

B

R

G

B

R

B

R

G

B

R

G

B

G

R

B

G

R

G

R

G

B

R

525

3

1

521

LCX005

Basic Specifications

Total number of horizontal pixels

:

525H

521H

Number of horizontal display pixels :

Total number of vertical pixels

Number of vertical display pixels

:

222H

218H

Total number of pixels

:

116550

113578

Number of display pixels

–12–

CXD2403AR

Horizontal Direction Output Pulse

The picture display timing of horizontal direction is as

follows.

The horizontal start position is offset by two clocks in

16 different ways with the HP1 to 4 pins.

Effective Pixel Display Timing (for the LCX003)

10.9µs

(110fH)

52.6

(528fH)

63.5µs

(638fH)

4.76µs

(48fH)

SYNC

BLK

Effective interval

1.5µs

(15fH)

9µs

(90.5fH)

HST

Picture display interval

47.1µs

(473fH)

2.75µs

(27.5fH)

2.75µs

(27.5fH)

Horizontal Start Position Concept

Horizontal scan interval

63.5µs = 638ffH

Interval from sync signal to picture display

Picture display starts (528–473)/2 = 27.5fH later

from the end of BLK. Therefore, picture

display starts 11 – 15 + 27.5 = 122.5fH later.

Blanking and SYNC

47.6µs

SYNC

(48fH)

BLK

10.9µs

BLK

110fH

473fH

110fH

(Picture display interval)

1.5µs (15fH)

27.5fH

Interval from HST to picture display

Picture display interval

First two bits are masked.

5fH

47.1µs = 473fH

2

HST

HCK1

HCK2

473

2

4

Therefore, the interval between HST and display

start is 6 clocks.

Display

interval

218

Black mask

10

Interval from the center of sync signal to HST.

Add time delayed four bits of sync separation circuit.

110-15-26+27.5-6-4=90.5fH (9.0µs)µs

–13–

CXD2403AR

Variable Range from the Center of Sync Signal to Hst Rise Timing

HP1 to HP4 pins can be used to vary the

HP4

0

HP3

0

HP2

0

HP1

0

1

108CLK (10.7µs)

106CLK

104CLK

interval from the center of sync signal to HST

rise as shown in the left table.

0

1

0

1

102CLK

0

1

0

100CLK

0

1

0

1

0

1

0

1

0

98CLK

96CLK

94CLK (9.4µs)

92CLK

90CLK

Internal preset:

NTSC (typ.):

PAL (typ.):

1001 (90CLK)

1000 (92CLK)

1

0

1

0

1

0

88CLK

1

0

1

86CLK

1

0

84CLK

1

0

1

82CLK

1

0

80CLK

1

78CLK (7.8µs)

Liquid Crystal Panel Driving Pulse Generation

HST, HCK1, HCK2, VST, VCK1, and VCK2 (EN, CLR

in LCX005 mode only) are generated for the liquid

crystal panel driver.

Low. Polarity is not specified for each field. The point is

changed from VCK1 and VCK2 pulse change points

after 1 clock.

HD-Clamp Pulse Generation

HD pulse is output during horizontal BLK in order to

drive the backlight (fluorescent tube). Even during no

signal, raster screen with no screen noise can be

created synchronizing to the free running frequency.

XCLP is output for BF timing clamp pulse.

External Sample-and-Hold Pulse Generation

Timing pulses of external sample-and-hold circuit

SH1, SH2, and SH3 are generated.

AC Driving Pulse Generation

FRP is output for liquid crystal AC driving. Field

inverts when F/H input pin is High and line inverts when

SYNC

BLK

4.7µs

1.5µs

10.9µs

2.7µs

HD

6.5µs

XCLP

2µs

6.1µs

1.3µs

1.4µs

–14–

CXD2403AR

Pulse Timing Chart (for the LCX003)

Clock

(638fH)

Display start

HST

HCK1

HCK2

VCK1,2

SH1

SH2

SH3

RESET position

FRP

* In accordance with the layout of picture elements on LCD panel, timings between the adjacent lines and

fields are offset accordingly.

1.5 bit offset pulse

1 bit offset pulse

→ HST, HCK1, HCK2, SH1, SH2, SH3, CLR

→ VCK1,VCK2, FRP, EN

–15–

CXD2403AR

LCX003/004 Horizontal Direction Timing Chart — NTSC, PAL (HPOS-1001)

–16–

CXD2403AR

LCX003 Vertical Direction Timing Chart — NTSC

Note) The second row of the timing chart 'VD' is a pulse indicated as a reference and is not a pulse output from pins.

–17–

CXD2403AR

LCX004 Vertical Direction Timing Chart — PAL

Note) The second row of the timing chart 'VD' is a pulse indicated as a reference and is not a pulse output from pins.

–18–

CXD2403AR

LCX005 Holizontal Direction Timing Chart — NTSC, PAL (HP=1001)

–19–

CXD2403AR

LCX005 Vertical Direction Timing Chart — NTSC

Note) The second row of the timing chart 'VD' is a pulse indicated as a reference and is not a pulse output from pins.

–20–

CXD2403AR

LCX005 Vertical Direction

Timing Chart — PAL

–21–

CXD2403AR

Driving for No Signal

The period of the V counter is 269H for NTSC and

321H for PAL, and if there is no VSYNC during

269H/321H, it is assumed to be a no signal state.

The RPD pin is kept at high impedance so that the

AFC circuit does not cause phase errors by phase

comparison.

HST, HCK1, HCK2, FRP, VCK1, VCK2, XCLP, HD,

VD, and VST are made to run free so that the liquid

crystal panel is AC driven even when there is no

composite sync from the SYNC pin.

The PLL counter is made to run free because the

HSYNC separation circuit stops. In addition, the

auxiliary V counter is used to create the reference pulse

for generating VD and VST because the VSYNC

separation circuit is also stopped.

AFC Circuit (638/702 fh clock generation)

A fully synchronized AFC circuit is built in. PLL error

detection signal is generated at the following timing.

SYNC

4.7µs

5V

2.5V

RPD

Center of SYNC

0V

The phase comparison output of the entire bottom of

SYNC and the internal H counter becomes RPD. RPD

output is converted to DC error with the lag-lead filter.

Then the outputs change the vari-cap capacitance and

the oscillating frequency is stabilized at 638 fh in

LCX003/1004 or 702 fh in LCX005.

Example of PLL Related Peripheral Circuit

1k

37 RPD

3.3µ 10k

L value

+

LCX003/004 → 8.2µ

LCX005

→ 6.8µ

3300pF

33k

1000pF

+12V

100k

40

39

CKI

*The parameters of the elements are reference.

1T369

0.01µ

L

10k

CKO

100pF

Parts : Vari-cap

1T369 (Sony), MA365 (Matsushita)

Concretely, adjust so that the RPD rise is at the center

Adjustment Method

of HSYNC.

1. Adjust the voltage for vari-cap with the variable

resistor connected to 12V power supply while checking

HSYNC and RPD waveforms with an oscilloscope.

2. When PLL is still not locked, change the L of the LC

oscillations.

–22–

CXD2403AR

HSYNC Separation

HSYNC is separated from the composite sync input.

Noise is eliminated with the counter and equivalent

pulse is eliminated with the half H killer.

HSYNC jumping detection and address management

when jumping occurs frequently (matching the number

of H in a field) are also performed.

PLL

H-DET

Noise Elimination

SYNC

Half H-Kill

H Control

Circuit

AFH

H Counter

(Internal pulse)

(Matching the number of H)

SKEW DET

V. SYNC Separation

V-RESET

Pulse

Generate

Noise

Shape

V-Reset pulse

(internal pulse)

SYNC

V-SYNC Separation Circuit

a V sync having different pulse width from normal one is

input, it can be separated when the width of serration

pulse is narrower than 2~3 µsec or less which is

positioned right after the V sync having 0.5H width

during A~F period.

V. sync is separated from the composite sync input

connected to SYNC connector. The serration pulses

are removed as noise. When considerable pulse width

is detected, the V reset pulse is output to notify V sync

input and to synchronize timing of output signals. When

V-SYNC Period

190µs

A

B

C

D

E

F

SYNC

NOISE SHAPE START

NOISE SHAPE END

NOISE SHAPE MODE

Recovery period 15µs

Tolerance ± 0 to 1.0µs

NOISE

SHAPED

PULSE

V-SYNC

Decision Period

When the pulse enters in this

period, twice the pulse time

width is added.

125µs

V-RESET

PULSE

V-SYNC Input Time Axis Specification

–23–

CXD2403AR

Application Circuit

(for driving the liquid crystal panel LCX003)

+

3.3µ

+

10k

1k

VSS2

HCK1

HCK2

HST

RPD

VDD

24

23

22

21

20

19

18

17

16

15

14

13

37

38

39

40

41

3300pF

0.01µ

33k

CKO

CKI

LCD panel

1000pF

VSS

VCK2

VCK1

VST

10k

N.C.

HP1

HP2

HP3

HP4

N.C. 42

8.2µ

43

44

45

46

47

48

100k

N.C.

EN

N.C.

100pF

CLR

N.C.

VDD2

+

+5.0V

PAL

NT

+

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems

arising out of the use of these circuits or for any infringement of third party and other right due to same.

–24–

CXD2403AR

Package Outline Unit : mm

48PIN LQFP (PLASTIC)

9.0 }0.2

* 7.0 }0.1

+0.2

1.5-0.1

0.1

36

25

24

37

48

A

13

1

12

0.5 }0.1

+0.08

0.18-0.03

M

0.08

0.1 }0.1

NOTE Dimension g hdoes notinclude mold protrusion.

0 K-10 K

DETAIL A

PACKAGESTRUCTURE

EPOXY RESIN

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

SONYCODE

EIAJCODE

LQFP-48P-L121

SOLDER PLATING

LQFP048-P-0707-AX

42ALLOY

0.2

JEDEC CODE

PACKAGEWEIGHT

–25–


型号：	CXD2403AR
厂家：	SONY CORPORATION
描述：	Timing Generator for Color Liquid Crystal Panel 时序发生器彩色液晶板
文件：	总25页 (文件大小：1287K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CXD2403AR [SONY]

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