CXD2401R [SONY]
Electronic Iris Control IC; 电子光圈控制IC
| 型号： | CXD2401R |
| 厂家： | 
SONY CORPORATION |
| 描述： | Electronic Iris Control IC |
| 文件： | 总21页 (文件大小：319K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXD2401R
Electronic Iris Control IC
Description
48 pin LQFP (Plastic)
The CXD2401R is an IC which performs electronic
iris control by applying a CCD electronic shutter.
Features
• Electronic iris control drive
• Generates system clocks in response to the
CXA1390AR series
• Generates timing pulses to drive the 510H system
CCD image sensor
•
H driver for CCD (5V direct drive for Type 1/3 CCD)
Applications
CCD monitoring cameras
Absolute Maximum Ratings
• Supply voltage
• Input voltage
• Output voltage
VDD
VSS – 0.5 to +7.0
V
Structure
VI VSS – 0.5 to VDD + 0.5V
VO VSS – 0.5 to VDD + 0.5V
Silicon gate CMOS IC
•
Operating temperature Topr
–20 to +75
°C
°C
Applicable CCD Image Sensors
510H system SONY CCD
• Storage temperature Tstg
–55 to +150
• ICX054BK (Type 1/3 NTSC CCD)
• ICX055BK (Type 1/3 PAL CCD)
Recommended Operating Conditions
• Supply voltage
VDD
4.75 to 5.25
–20 to +75
V
•
Operating temperature Topr
°C
Pin Configuration
35
33 32 31
30
29 28
25
36
34
27
26
37
38
39
40
41
42
43
44
45
46
VSS4
SPUPV
IRIN
24 XV2
23
22
21
20
19
18
17
16
15
XDL2
XDL1
XSP2
XSP1
XSHP
VSS2
XSHD
VDD2
CLP2
BFG
SPDNV
Vreg
VDD4
CXD2401R
ENB
IRENB
PS
LIMIT1
LIMIT2 47
48
14
13
NTSC
ID
1
2
3
4
5
6
7
8
9
10
11 12
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E94620D9X
CXD2401R
Pin Description
Pin
Symbol
No.
I/O
Description
1
OSCI
OSCO
CK
I
Inverter input for oscillation. (NTSC: 1820fH, PAL: 1816fH)
Inverter output for oscillation. (NTSC: 1820fH, PAL: 1816fH)
Input for main clock in IC. (NTSC: 1820fH, PAL: 1816fH)
IC test input. Fixed at GND in normal operation. (With pull-down resistor)
CK/2 clock output. NTSC: 910fH = 4fsc, PAL: 908fH
GND
2
O
I
3
4
TEST
CL
I
5
O
—
I
6
VSS1
VD
7
Vertical sync signal input.
8
HD
I
Horizontal sync signal input.
9
VDD1
CLP4
CLP1
PBLK
ID
—
O
O
O
O
O
O
—
O
—
O
O
O
O
O
O
O
O
O
O
O
O
—
O
O
O
5V power supply.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Clamping pulse for CCD dummy output.
Clamping pulse for CCD optical black.
Cleaning pulse for vertical/horizontal blanking.
Vertical direction line identification signal.
Burst flag gate pulse.
BFG
CLP2
VDD2
XSHD
VSS2
XSHP
XSP1
XSP2
XDL1
XDL2
XV2
Clamping pulse in horizontal blanking.
5V power supply.
CCD data level sample-and-hold pulse output.
GND
CCD precharge level sample-and-hold pulse output.
Color separation sample-and-hold pulse output.
Color separation sample-and-hold pulse output.
Clock output for CCD DL (Delay Line).
Clock output for CCD DL (Delay Line).
CCD vertical clock output.
XV1
CCD vertical clock output.
XSG1
XV3
Clock output for CCD sensor readout.
CCD vertical clock output.
XSG2
XV4
Clock output for CCD sensor readout.
CCD vertical clock output.
XSUB
VSS3
H1
Clock output for CCD electronic shutter.
GND
CCD horizontal clock output.
H2
CCD horizontal clock output.
RG
CCD reset gate pulse output.
– 2 –
CXD2401R
Pin
No.
Symbol
I/O
Description
35
36
37
VDD3
—
I
5V power supply.
Used for GND connection.
GND
GM
VSS4
—
When set in electronic iris mode: Shutter speedup reference voltage input
When set in serial mode of electronic shutter: Strobe input
38
39
40
SPUPV
IRIN
I
I
I
When set in electronic iris mode: Iris signal input
When set in serial mode of electronic shutter: Clock input
When set in electronic iris mode: Shutter speed-down reference voltage input
When set in serial mode of electronic shutter: Data input
SPDNV
41
42
43
44
45
46
47
48
Vreg
—
Current source for comparator. Connected to 5V power supply via 33kΩ resistor.
5V power supply.
VDD4
—
ENB
I
I
I
I
I
I
Generation/halt switching of electronic shutter pulse (Pin 30). (With pull-up resistor)
Electronic iris/electronic shutter switching. (With pull-up resistor)
Parallel/serial input switching of electronic shutter speed data. (With pull-up resistor)
Selecting limit value of max. shutter speed. (With pull-down resistor)
Selecting limit value of max. shutter speed. (With pull-down resistor)
NTSC/PAL switching. (With pull-down resistor)
IRENB
PS
LIMIT1
LIMIT2
NTSC
Electrical Characteristics
DC Characteristics
Item
(Within recommended operating range)
Pin No.
Symbol
Conditions
Min.
4.75
1.9
Typ.
5.0
Max.
5.25
VDD
Unit
V
Supply voltage 1 9, 16, 35, 42
VDD
Input voltage 1
Input voltage 2
38, 40 (Electronic iris mode) VIN1
V
39 (Electronic iris mode)
VIN2
VIH3
VSS
VDD
V
4, 7, 8, 36, 38, 39, 40, 43,
44, 45, 46, 47, 48 (Pins 38,
39 and 40 are when set in
electronic shutter mode)
0.7VDD
V
V
Input voltage 3
VIL3
0.3VDD
IOH = –4mA
IOL = 8mA
VOH1
VOL1
VOH2
VOL2
VOH3
VOL3
VOH4
VOL4
VDD – 0.8
VDD – 0.8
VDD – 0.8
VDD – 0.8
V
V
V
V
V
V
V
V
Output voltage 1 5, 10, 11
0.4
0.4
0.4
IOH = –8mA
IOL = 8mA
15, 17, 19, 20, 21,
22, 23, 34
Output voltage 2
IOH = –20mA
IOL = 20mA
IOH = –2mA
IOL = 4mA
Output voltage 3 32, 33
12, 13, 14, 24, 25,
26, 27, 28, 29, 30
Output voltage 4
0.4
75
Pull-up
resistance value
VIL = 0V
43, 44, 45
RPU
RPD
25
25
50
50
kΩ
kΩ
Pull-down
resistance value
VIH = VDD
4, 36, 46, 47, 48
75
Pins 7 and 8 do not have a protective diode at the power supply side.
– 3 –
CXD2401R
Comparator Characteristics
(Within recommended operating range)
Item
Pin No. Symbol
Conditions
Min.
Typ.
1.1
Max.
50
Unit
mV
ns
Input offset voltage
Vos
tpd +
tpd –
IDD
Response time when a step
input of 100mV amplitude/
5mV overdrive is applied.
Rise
140
Response
time
Fall
190
ns
38, 39,
40
Current consumption
In-phase input voltage range
Indefinite region
98
140
±10
µA
V
VICR
Vf
1.9 to 5
mW
Bias current source for comparator. Pin No.: 41. Connected to power supply via 33kΩ resistor.
Note) 1. Input offset voltage and indefinite region
5.0V
Input offset voltage and indefintie region are
Indefinite region
existed in the comparator which builds in this IC
10mV
10mV
Pins 40 and 38
(SPDNV and SPUPV)
as shown right figure. Note that this when
designing external circuit.
50mV
50mV
Input offset voltage
Input offset voltage
2. Pins 40 and 38 for electronic iris mode
Use it in this state of Pin 40 (SPDNV) > Pin 38
(SPUPV).
10mV
10mV
Indefinite region
GND
Oscillating Inverter I/O Characteristics
(Within recommended operating range)
Item
Logical Vth
Pin No. Symbol
LVth
Conditions
Min.
0.7VDD
VDD/2
Typ.
Max.
Unit
V
VDD/2
VIH
VIL
VOH
VOL
RFE
f
V
1
Input voltage
0.3VDD
V
IOH = –12mA
V
2
Output voltage
IOL = 12mA
VDD/2
2.5M
30
V
VIN = VDD or Vss
250k
20
1M
Ω
1 to 2
Feedback resistor
MHz
Oscillator frequency
Duty Control Inverter Input Characteristics
(Within recommended operating range)
Item
Logical Vth
Pin No. Symbol
Conditions
Min.
Typ.
Max.
Unit
V
LVth
VDD/2
VIH
0.7VDD
V
Input voltage
VIL
0.3VDD
2.5M
V
3
VIN
fmax = 50MHz sine wave
VIN = VDD or Vss
0.5
Vpp
Ω
Input amplification
Feedback resistor
RFE
250k
1M
Note) The input voltage is the input voltage characteristics for an external direct power input, and input
amplification is the input amplification characteristics for input through capacitor.
– 4 –
CXD2401R
Electrical Characteristics
AC Characteristics
1) AC characteristics among serial communication clocks (SPDNV (ED2), IRIN (ED1), SPUPV (ED0))
0.7VDD
SPDNV (ED2)
IRIN (ED1)
0.3VDD
0.7VDD
0.7VDD
ts2
th2
0.7VDD
SPUPV (ED0)
0.3VDD
tw0
ts1
ts0
(Within recommended operating range)
Symbol
ts2
Definition
Min.
20ns
20ns
Typ.
Max.
SPDNV (ED2) set-up time, activated by the rising edge of IRIN (ED1)
SPDNV (ED2) hold time, activated by the rising edge of IRIN (ED1)
th2
IRIN (ED1) rising set-up time, activated by the rising edge of SPUPV
(ED0)
20ns
20ns
20ns
ts1
tw0
ts0
SPUPV (ED0) pulse width
50µs
SPUPV (ED0) rising set-up time, activated by the rising edge of IRIN
(ED1)
2) Microcomputer communication clock → IC take-in characteristics
Example: NTSC/ODD field
VD
HD
XSG1
Magnification
HD
0.3VDD
0.3VDD
XSG1
NTSC mode: 63.5µs, PAL mode: 63.9µs
SEN logic level is to be High for this period.
Note) During the 1H period for generating XSG1, the phase against AVD differs according to each mode.
Please always maintain the SEN logic level at High for "the 1H period when XSG1 varies."
– 5 –
CXD2401R
3) HD/VD take-in characteristics
HD
VD
0.3VDD
0.7VDD
0.3VDD
CL
ts4
th4
(Within recommended operating range, Load capacity of CL = 30pF)
Symbol
Definition
Min.
5
Typ.
Max. Unit
ns
ns
ts4
th4
HD/VD set-up time, activated by CL
HD/VD hold time, activated by CL
7
4) Phase discrimination characteristics by VD/HD input
NTSC: ODD field
PAL: EVEN field
NTSC: EVEN field
PAL: ODD field
VD
VD
HD
0.3VDD
0.3VDD
tpd2
tpd2
HD
When the HD logic level is Low tpd2 after VD falls,
the phase is discriminated as an ODD field (NTSC).
When the HD logic level is High tpd2 after VD falls,
the phase is discriminated as an EVEN field (NTSC).
(Within recommended operating range)
Symbol
tpd2
Definition
Field discriminating clock phase, activated by the falling edge of VD
Min.
700
Typ.
Max. Unit
1000 ns
– 6 –
CXD2401R
5) Phase characteristics of H1, RG, XSHP, XSHD, XSP1, XSP2, XDL1, XDL2, and CL
tCK
Vpp/2
CK
H1
tpd3
0.7VDD
0.7VDD
tpd4
tpd6
tpd5
0.3VDD
0.7VDD
RG
0.3VDD
tpd7
tpd8
XSHP
XSHD
tpd10
tpd9
0.3VDD
0.7VDD
tpd11
tpd12
0.3VDD
0.7VDD
XSP1
XSP2
tpd13
tpd14
0.3VDD
tpd15
tpd16
0.7VDD
0.3VDD
0.7VDD
XDL1
XDL2
0.3VDD
0.7VDD
tpd17
0.3VDD
tpd18
tpd20
0.3VDD
0.7VDD
tpd19
CL
(Within recommended operating range)
CK-duty = within 50 ± 4%, Load capacity of H1 = 150pF, Load capacity of CL = 30pF, Load capacity of RG,
XSHP, XSHD, XSP1, XSP2, XDL1, and XDL2 = 10pF
Symbol
Definition
Min.
Typ.
35
29
31
36
33
28
28
27
26
26
27
27
27
26
27
26
27
27
26
Max. Unit
ns
CK cycle
tCK
16.22
17.25
20.18
18.61
15.86
15.76
14.92
14.76
14.79
15.05
15.09
15.29
14.49
15.05
14.46
14.92
15.33
14.71
56.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
H1 falling delay, activated by the falling edge of CK
H1 rising delay, activated by the rising edge of CK
RG falling delay, activated by the falling edge of CK
RG rising delay, activated by the rising edge of CK
XSHP falling delay, activated by the rising edge of CK
XSHP rising delay, activated by the falling edge of CK
XSHD falling delay, activated by the falling edge of CK
XSHD rising delay, activated by the rising edge of CK
XSP1 falling delay, activated by the rising edge of CK
XSP1 rising delay, activated by the rising edge of CK
XSP2 falling delay, activated by the rising edge of CK
XSP2 rising delay, activated by the rising edge of CK
XDL1 rising delay, activated by the rising edge of CK
XDL1 falling delay, activated by the falling edge of CK
XDL2 rising delay, activated by the rising edge of CK
XDL2 falling delay, activated by the falling edge of CK
CL falling delay, activated by the falling edge of CK
CL rising delay, activated by the falling edge of CK
– 7 –
tpd3
60.38
70.58
65.32
55.59
55.32
52.26
51.62
51.74
52.58
52.82
53.54
50.79
52.67
50.65
52.47
53.01
51.58
tpd4
tpd5
tpd6
tpd7
tpd8
tpd9
tpd10
tpd11
tpd12
tpd13
tpd14
tpd15
tpd16
tpd17
tpd18
tpd19
tpd20
CXD2401R
6) Waveform characteristics of H1 and RG
0.9VDD
H1
0.1VDD
trH1
tfH1
0.9VDD
RG
0.1VDD
trRG
tfRG
VDD = 5.0V, Topr = 25°C, Load capacity of H1 = 150pF, Load capacity of RG = 10pF
Symbol
trH1
Definition
H1 rise time
Min.
Typ.
Max. Unit
7
7
3
3
ns
ns
ns
ns
H1 fall time
RG rise time
RG fall time
tfH1
trRG
tfRG
I/O Pin Capacitances
Item
Symbol
Min.
Typ.
Max.
Unit
pF
Input pin capacitance
CIN
9
Output pin capacitance COUT
I/O pin capacitance
11
11
pF
CI/O
pF
– 8 –
CXD2401R
Description of Operation
The operations of the CXD2401R are described below.
Control pin
Detailed description
Low: The CXD2401R performs control drive in accordance with NTSC. In this case, the
CXD2401R operates by assuming the signals input to Pin 7 (VD) and Pin 8 (HD) are
NTSC sync signals.
High: The CXD2401R performs control drive in accordance with PAL. In this case, the
CXD2401R operates by assuming the signals input to Pin 7 (VD) and Pin 8 (HD) are PAL
sync signals.
NTSC
(Pin 48)
Refer to the "Timing Chart" for the control drive pulse for either NTSC or PAL.
Low: Pin 30 (XSUB) is always High. That is, the electronic iris and electronic shutter to which
XSUB pulses are applied suspend operation (electronic iris and electronic shutter OFF).
High: Pin 30 (XSUB) outputs control pulses for the electronic iris and electronic shutter.
(electronic iris and electronic shutter ON).
ENB
(Pin 43)
Low: Realizes the electronic shutter control.
High: Realizes the electronic iris control.
IRENB
(Pin 44)
The control pins (SPUPV, IRIN, and SPDNV) are used in common for both electronic shutter
control and electronic iris control. The operations of these pins differ depending on the state of
IRENB pin.
This pin is valid when the operation of electronic shutter is assigned (IRENB = Low).
Low: Electronic shutter speed can be controlled by inputting serial data into SPUPV, IRIN, and
SPDNV pins.
High: Electronic shutter speed can be controlled by inputting parallel data into SPUPV, IRIN,
and SPDNV pins.
PS
(Pin 45)
Note) The PS pin is invalid when IRENB = High, and the CXD2401R does not accept data,
whether PS is Low or High.
– 9 –
CXD2401R
Control pin
Detailed description
The operations of SPUPV, IRIN, and SPDNV pins differ according to the mode (IRENB control)
of the electronic iris and electronic shutter. The operations are described below for each case.
IRENB = Low: When the operation of electronic shutter is assigned
SPUPV : Strobe input pin
IRIN
: Clock input pin
PS = Low: When inputting serial data is assigned
SPDNV : Data input pin
SPUPV
(Pin 38)
IRIN
SPDNV (ED2)
IRIN (ED1)
D7
D6
D5
D4
D3
D2
D1
D0
(Pin 39)
SPDNV
(Pin 40)
SPUPV (ED0)
MSB
LSB
D7
0
D6
1
D5
1
D4
0
D3
D2
D1
0
D0
0
Ld : Shutter speed data
Ex.: Ld = 100 [decimal]
0
1
<Shutter speed calculation formula> Shutter speed = 1/n [s]
PAL: NTSC (Pin 48) = H
n = 1/m × 106
NTSC: NTSC (Pin 48) = L
Ld
(decimal)
Ld
(decimal)
n = 1/m × 106
m
m
255 to 248 [261 – {(255 – Ld) × 7 + 2}] × 63.56 + 31
247 to 241 [261 – {(247 – Ld) × 5 + 58}] × 63.56 + 31
240 to 232 [261 – {(240 – Ld0 × 4 + 93}] × 63.56 + 31
231 to 220 [261 – {(231 – Ld) × 3 + 129}] × 63.56 + 31
219 to 202 [261 – {(219 – Ld) × 2 + 165}] × 63.56 + 31
201 to 151 [261 – {(201 – Ld) × 1 + 201}] × 63.56 + 31
[311 – {(255 – Ld) × 10 + 2}] × 64 + 30.77
[311 – {(250 – Ld) × 7 + 52}] × 64 + 30.77
[311 – {(242 – Ld) × 5 + 108}] × 64 + 30.77
[311 – {(235 – Ld) × 4 + 143}] × 64 + 30.77
[311 – {(226 – Ld) × 3 + 179}] × 64 + 30.77
[311 – {(214 – Ld) × 2 + 215}] × 64 + 30.77
[311 – {(196 – Ld) × 1 + 251}] × 64 + 30.77
255 to 251
250 to 243
242 to 236
235 to 227
226 to 215
214 to 197
196 to 146
145 to 109
108 to 102
101 to 93
92 to 81
150 to 114 [875 – {(150 – Ld)
113 to 107 [875 – {(113 – Ld)
106 to 98 [875 – {(106 – Ld)
×
11 + 253}]
5 + 660}]
4 + 695}]
×
0.978 + 0.047
0.978 + 0.047
0.978 + 0.047
×
×
[923 – {(145 – Ld)
[923 – {(108 – Ld)
[923 – {(101 – Ld)
×
×
×
11 + 303}] × 0.987 + 0.721
×
×
5 + 710}] 0.987 + 0.721
×
97 to 86 [875 – {(97 – Ld)
85 to 69 [875 – {(85 – Ld)
×
3 + 731}]
×
×
×
0.978 + 0.047
0.978 + 0.047
0.978 + 0.047
4 + 745}] × 0.987 + 0.721
×
×
2 + 767}]
1 + 801}]
[923 – {(92 – Ld)
[923 – {(80 – Ld)
[923 – {(63 – Ld)
×
3 + 781}]
2 + 817}]
1 + 851}]
×
×
×
0.987 + 0.721
0.987 + 0.721
0.987 + 0.721
68 to 0
[875 – {(68 – Ld)
×
×
80 to 64
63 to 0
– 10 –
CXD2401R
Control pin
Detailed description
IRENB = Low: When the operation of electronic shutter is assigned
PS = High: When inputting parallel data is assigned
Shutter Speed Compatibility Chart
Shutter speed (s)
SPUPV
IRIN
SPDNV
NTSC(Pin 48) = L NTSC(Pin 48) = H
H
L
H
H
L
H
H
H
H
L
1/100
1/250
1/120
1/250
H
L
1/500
1/500
L
1/1000
1/2000
1/5000
1/10000
1/100000
1/1000
1/2000
1/5000
1/10000
1/110000
H
L
H
H
L
L
H
L
L
L
L
IRENB = High: When the operation of electronic iris is assigned
SPUPV
(Pin 38)
IRIN
CXD2401R
(Pin 39)
SPDNV
(40Pin)
Comp1
SPDNV
Shutter Speed Cont
IRIN
DECODE
Comp2
SPUPV
Comp 1 Truth Table
DECODE Truth Table
SPDNV
IRIN
Comp1
Comp1
Comp2
Shutter Speed Cont
L
H
L
H
L
L
L
L
H
L
Shutter speed; Faster
Shutter speed; Hold
Shutter speed; Hold
Shutter speed; Slower
H
H
H
Comp 2 Truth Table
H
IRIN
L
SPUPV
Comp2
H
L
L
H
H
In the electronic iris control operation, the electronic shutter speed is controlled according to
the logic above. The variations of shutter speed by each control are the same as those shown
in <Shutter speed calculation formula> for "electronic shutter; inputting serial data".
– 11 –
CXD2401R
Control pin
Detailed description
LIMIT1 and LIMIT2 pins function only when IRENB = High (when the operation of electronic iris
is assigned).
(Inputs from LIMIT1 and LIMIT2 are not accepted when IRENB = Low: when the operation of
electronic shutter is assigned.)
Maximum Electronic Shutter Speed
Max. shutter speed (s)
LIMIT1 LIMIT2
Purpose
NTSC (Pin 48) = L NTSC (Pin 48) = H
Reduces flickers caused by an
indoor fluorescent lamp.
LIMIT1
(Pin 46)
LIMIT2
(Pin 47)
L
L
L
1/200
1/200
Intermediate mode between
indoor and outdoor applications.
H
1/2000
1/2000
H
H
L
1/20000
1/90000
1/20000
Reduces CCD smear outdoors.
Secures dynamic range of iris.
H
1/100000
Electronic iris control of the CXD2401R is realized by applying functions of the electronic shutter.
The electronic shutter has a dynamic range from 1/60s when Pin 48 (NTSC) = Low or from 1/50s
when Pin 48 (NTSC) = High up to the maximum shutter speed in the table above.
Select one of the four dynamic ranges of the electronic iris, according to the application
conditions of the CXD2401R. The dynamic range is also determined by also taking into
consideration the influence of the electronic shutter on image quality, as shown in the table
above.
– 12 –
CXD2401R
– 13 –
CXD2401R
– 14 –
CXD2401R
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CXD2401R
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CXD2401R
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CXD2401R
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CXD2401R
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CXD2401R
Application Circuit
ICX055AK
ICX054AK
CXL1518N
IRIS GC = 4.1V
IRIS LEVEL = 3.0V
DET LEVEL = 5.0V
ICX027CK
ICX026CK
CXA1391R/Q
CXA1390AQ/AR
CXA1392R/Q
CCD
CXD1267N
3.9K
XV2, XV3, XV4
XSG1, XSG2
H1
H2
CXD2401R
RG
30P
OSCI
XSUB
IRIS/SHUTTER
CK GEN
OSCO
GATE
Timing Generator
CK
27P
1000P
CK
COUNTER
ENB
WND
D
CL
VD
HD
SELECTOR
IRENB
CXD1159Q
SELECTOR
SUBTRACTION
DECODE
DECODE
ED2 ED1
PS
ED0
NTSC
VSS4
UP/DOWN
ADDER
VSS3
VSS2
VSS1
Vreg
LIMIT1 LIMIT2
GM VDD1VDD2VDD3 VDD4
33K
6.8K
2.2K
IRIN
3.9K
2.3V
2.8V
33µ/16V
SPUPV
SPDNV
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
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CXD2401R
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 ± 0.2
7.0 ± 0.1
36
25
24
37
48
A
13
(0.22)
12
1
+ 0.05
0.127 – 0.02
0.5 ± 0.08
+ 0.2
+ 0.08
1.5 – 0.1
0.18 – 0.03
0.1
0.1 ± 0.1
0° to 10°
NOTE: Dimension “ ” does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SOLDER/PALLADIUM
LQFP-48P-L01
SONY CODE
EIAJ CODE
PLATING
LQFP048-P-0707
42/COPPER ALLOY
0.2g
JEDEC CODE
PACKAGE MASS
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相关型号：
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