CXD2411AR_技术文档

CXD2411AR

Timing Generator for Color LCD Panels

For the availability of this product, please contact the sales office.

Description

48 pin LQFP (Plastic)

The CXD2411AR is a timing signal generator for

color LCD panel drivers.

Features

• Generates the LCX005BK/BKB and

LCX009AK/AKB drive pulse.

• Supports right/left inverse display.

• Supports 16:9 wide display.

• Supports CSYNC and Separate SYNC (XHD, XVD)

input.

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage

• Input voltage

• Output voltage

V^DD

VSS – 0.5 to +7.0

V

• Supports line inversion and field inversion.

• AC drive for LCD panel during no signal

(NTSC/PAL).

VI

VSS – 0.5 to VDD + 0.5

VO VSS – 0.5 to VDD + 0.5

• Operating temperature

• Generates timing signal of external sample-and-

hold circuit.

Topr

• Storage temperature

Tstg

–20 to +85

°C

• AFC circuit supporting static and dynamic

fluctuations.

–55 to +150

Recommended Operating Conditions

Applications

• Supply voltage

V^DD

2.7 to 5.5

V

• Color LCD viewfinder

• Operating temperature

• Single-panel and three-panel projectors

Topr

–20 to +85

°C

Structure

Silicon gate CMOS IC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by

any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the

operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E95Z14-ST

CXD2411AR

Block Diagram and Pin Configuration

41

42

master ck

CKO

CKI

RPD

39

PLL PHASE COMPARATOR

XCLR

PLNT

SLCK

3

2

1

35

36

XCLP

HD

H-SYNC

DETECTOR

H-SKEW

XHD

XVD

27

45

HALF-H

KILLER

DETECTOR

PLL-COUNTER

6

VSS

VDD

VSS

VDD

VSS

19

31

43

40

TST0

TST1

TST2

7

8

9

V-SYNC

TST3 11

SEPERATOR

(NOISE SHAPE)

HP1

HP2

12

15

26

37

44

46

47

TST4

TST5

TST6

48 HP3

HP4

TST7

TST8

38

10

22

14

24

23

RGT

HST1

H-TIMING

PULSE

GENERATOR

HST2

HCK1

HCK2

32 SH1

33 SH2

V-TIMING

PULSE GENERATOR

EN

VD

17

25

18

21

20

29

5

SH3

SH4

CLR

34

30

16

VST

PAL PULSE

ELIMINATOR

VCK1

VCK2

FLDO

SBLK

WIDE

13

28

SLFR

FRP

FIELD & LINE

CONTROLLER

4

– 2 –

CXD2411AR

Pin Description

Input pin for

open status

Symbol I/O

No.

Description

Switches between LCX005BK (H) and LCX009 (L)

Switches between PAL (H) and NTSC (L)

Cleared at 0V

1

2

3

4

5

6

7

8

9

SLCK

PLNT

XCLR

WIDE

SBLK

V^SS

I

L

I

H

L

Switches between 16:9 display (H) and 4:3 display (L)

Black signal pulse output (during WIDE MODE) (positive polarity)

GND

I

O

—

I

—

Leave this open.

TST0

TST1

TST2

—

H

Leave this open.

Switches between Normal scan (H) and Reverse scan (L)

Leave this open.

10 RGT

11 TST3

12 TST4

13 SLFR

14 HST2

15 TST5

16 CLR

17 EN

—

I

—

L

Leave this open.

Switches between field inversion (H) and line inversion (L)

H start pulse 2 (positive polarity)

Leave this open.

O

—

O

—

O

—

I

—

CLR pulse output (positive polarity)

EN pulse output (negative polarity)

V start pulse (positive polarity)

Power supply

18 VST

19 VDD

V clock pulse 2

20 VCK2

21 VCK1

22 HST1

23 HCK2

24 HCK1

25 VD

—

V clock pulse 1

H start pulse 1 (positive polarity)

H clock pulse 2

H clock pulse 1

VD pulse output (positive polarity)

Leave this open.

26 TST6

27 XHD

28 FRP

29 FLDO

30 SH4

31 VSS

XHD (negative polarity)/Composite sync (positive polarity) input

AC drive timing pulse output

Field identification signal output

Sample-and-hold pulse (positive polarity)

GND

O

—

O

—

Sample-and-hold pulse (positive polarity)

Burst position clamp pulse output (negative polarity)

HD pulse output (positive polarity)

Leave this open.

32 SH1

33 SH2

34 SH3

35 XCLP

36 HD

—

37 TST7

– 3 –

CXD2411AR

Input pin for

open status

No.

Symbol I/O

Description

HP4

RPD

VSS

Switches for the horizontal display position

Phase comparator output

GND

38

39

40

41

42

43

44

45

46

47

48

I

O

—

O

I

H

—

CKO

CKI

Oscillation cell (output)

—

Oscillation cell (input)

VDD

Power supply

—

I

TST8

XVD

HP1

HP2

HP3

Leave this open.

—

L

XVD (negative polarity) input

Switches for the horizontal display position

I

L

I

L

I

L

(H: Pull up, L: Pull down)

Note) The CXD2411AR processes CSYNC and Separate SYNC inputs with the same pins. Therefore, care

should be given to the following points when using the CXD2411AR.

1) During CSYNC input, the XVD input pin should be set to L or left open.

2) During Separate SYNC input (XHD, XVD), the XVD width specification is from 2H to 10H.

– 4 –

CXD2411AR

Electrical Characteristics

1. DC characteristics

(Temperature = 25°C, VSS = 0V)

Item

Symbol

Conditions

Min.

2.7

2.2

1.8

Typ.

Max.

5.5

Unit

V

Supply voltage

Input voltage

VDD

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

VOH

VOL

IL

TTL input cell (5V ±10%)

TTL input cell (3.0V ±10%)

TTL input cell

V

Input voltage

V

Input voltage

0.8

0.3VDD

0.4

V

Input voltage

CMOS input cell

0.7VDD

VDD – 0.8

VDD/2

V

Input voltage

CMOS input cell

V

Output voltage

Input leak current

Output leak current

Current consumption

IOH = –4mA (HCKn, VCKn)

IOL = 8mA (HCKn, VCKn)

IOH = –3mA (CKO, CKI)

IOL = 3mA (CKO, CKI)

IOH = –2mA (other than the above)

IOL = 4mA (other than the above)

Normal input pin

V

VDD/2

V

VDD – 0.8

V

0.4

10

V

–10

–12

12

µA

mA

IIL

With pull-up resistor

–100

100

–240

240

40

IIH

With pull-down resistor

RPDn, FPDn (at high impedance state)

VDD = 5.0V

ILZ

–40

IDD

25

2. AC characteristics

(VDD = 2.7 to 5.5V)

Conditions Min. Typ. Max. Unit

Symbol

Item

Applicable pins

Clock input cycle

CKI

60

ns

Cross-point time difference HCK1, HCK2

Cross-point time difference VCK1, VCK2

∆t

CL = 30pF

10

30

25

40

22

Output rise delay

Output fall delay

Output rise delay

Output fall delay

HCKn, VCKn

tpr

tpf

Other than HCKn and VCKn tpr

Other than HCKn and VCKn tpf

HCK1, SH1 delay time

difference

HCK1, SH1

HCK2, SH1

dt1

dt2

dt1

dt2

CL = 30pF 60

85

95

85

95

ns

HCK1, SH1 delay time

difference

HCK2, SH1 delay time

difference

HCK2, SH1 delay time

difference

HCK1 Duty

HCK2 Duty

HCK1

HCK2

tH/tH + tL

CL = 30pF 46

52

%

Note) n = 1, 2

– 5 –

CXD2411AR

Timing Definition

VDD

0V

CKI

VDD

Output

0V

tpr

tpf

VDD

0V

VDD

VCK1

(HCK1)

50%

0V

VDD

VCK2

(HCK2)

50%

0V

∆t

t

tH – tL = 2 (t – t1)

CKI

tH = t – t1 + t2

tL = t – t2 + t1

tH – tL = 2 (t2 – t1)

HCK1

(HCK2)

50%

t1

t2

tH

tL

SH1

50%

dt1

dt2

– 6 –

CXD2411AR

LCX005BK/BKB and LCX009AK/AKB Color Coding Diagram

The delta arrangement is used for the color coding in the LCD panels with which this IC is compatible. Note

that the shaded region within the diagram is not displayed.

LCX005BK/BKB pixel arrangement

HSW1

HSW2

HSW3

HSW174

HSW175

dummy2 to 5

dummy1

dummy2

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

Photo-shielding area

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

Vline1

Vline2

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

Vline3

Display area

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

Vline217

Vline218

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

B

G

B

R

G

B

R

G

B

R

G

B

G

dummy3

dummy4

R

3

G

B

R

521

13

537

Basic specifications

Total horizontal dots

Horizontal display dots

:

537H

521H

Total vertical dots

Vertical display dots

:

222H

218H

Total dots

Display dots

:

119,214H

113,578H

– 7 –

CXD2411AR

LCX009AK/AKB pixel arrangement

dummy1 to 4

HSW1

HSW2

HSW267

HSW268

dummy5 to 8

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

dummy1

dummy2

Photo-shielding area

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

Vline1

Vline2

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

Vline3

Display area

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

R

Vline224

G

R

G

B

R

G

B

R

G

B

R

G

B

R

G

B

Vline225

dummy3

R

14

800

13

827

Basic specifications

Total horizontal dots

Horizontal display dots

:

827H

800H

Total vertical dots

Vertical display dots

:

228H

225H

Total dots

Display dots

:

188,556H

180,000H

– 8 –

CXD2411AR

Description of Mode Selection Switch (SLCK, PLNT, WIDE)

MODE

SLCK PLNT WIDE

H

L

H

L

LCX005BK/BKB, NTSC, NORMAL

LCX005BK/BKB, NTSC, WIDE

LCX005BK/BKB, PAL, NORMAL

LCX005BK/BKB, PAL, WIDE

LCX009AK/AKB, NTSC, NORMAL

LCX009AK/AKB, NTSC, WIDE

LCX009AK/AKB, PAL, NORMAL

LCX009AK/AKB, PAL, WIDE

H

L

H

L

H

L

H

L

H

NORMAL (4:3 display), WIDE (16:9 display)

SLFR

SLFR is the selector switch for the AC drive timing pulse (FRP). This switch selects field inversion when H and

line inversion when L. Normally, line inversion (L) is used. The transition point is one clock cycle after the

transition point of the VCK1 and VCK2 pulses.

FRP

1H inversion

(2H cycle)

1H

1F inversion

(2F cycle)

1Field

FRP polarity is not specified.

– 9 –

CXD2411AR

HP1, 2, 3, 4

These are selector switches for the horizontal display position. The HST timing can be set at 2fh intervals in 16

different ways by using the four HST position bits. The picture center is set at internal preset value: HP1/2/3/4:

LLLH. However, actually, because there is a difference between the RGB signal and the drive pulse delays,

the picture center may not match the design center. In this case, adjust with these switches.

The HST timing (from SYNC termination to the rising edge of HST) for even lines is shown below.

LCX005BK/BKB (NTSC, PAL)

HST1 (NTSC/PAL)

HST2 (NTSC/PAL)

74.5fh (6.74/6.79µs)

72.5fh

HP4

0

HP3

0

HP2

0

HP1

0

72fh (6.51/6.56µs)

0

1

70fh

0

1

0

68fh

70.5fh

0

1

66fh

68.5fh

0

1

0

64fh

66.5fh

0

1

0

1

62fh

64.5fh

0

1

0

60fh

62.5fh

0

1

58fh

60.5fh

1

0

56fh (5.06/5.11µs)

58.5fh (5.29/5.33µs)

56.5fh

1

0

1

54fh

1

0

1

0

52fh

54.5fh

1

0

1

50fh

52.5fh

1

0

48fh

50.5fh

1

0

1

46fh

48.5fh

1

0

44fh

46.5fh

1

42fh (3.80/3.83µs)

44.5fh (4.02/4.06µs)

The HST1 and 2 timing for odd lines is 1.5fh delayed and 1.5fh advanced respectively from the above

timings. (Refer to the Timing Charts for details.)

– 10 –

CXD2411AR

LCX009AK/AKB (NTSC, PAL)

HP4

0

HP3

0

HP2

0

HP1

HST1 (NTSC/PAL)

HST2 (NTSC/PAL)

93.5fh (5.66/5.70µs)

91.5fh

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

91fh (5.51/5.55µs)

0

89fh

0

1

87fh

89.5fh

0

1

85fh

87.5fh

0

1

0

83fh

85.5fh

0

1

0

81fh

83.5fh

0

1

79fh

81.5fh

0

1

77fh

79.5fh

1

0

75fh (4.54/4.57µs)

77.5fh (4.69/4.72µs)

75.5fh

1

0

73fh

1

0

1

71fh

73.5fh

1

0

1

69fh

71.5fh

1

0

67fh

69.5fh

1

0

65fh

67.5fh

1

63fh

65.5fh

1

61fh (3.69/3.72µs)

63.5fh (3.84/3.87µs)

The HST1 and 2 timing for odd lines is 1.5fh delayed and 1.5fh advanced respectively from the above

timings. (Refer to the Timing Charts for details.)

– 11 –

CXD2411AR

Right/Left Inversion

The LCD panel is arranged in a delta pattern, where identical signal line has 1.5-dot offset at adjoining vertical

lines. For this reason, a 1.5-bit offset is attached to the horizontal start pulse (HST) between odd lines and

even lines. HCK and SH are also 1.5-bit offset in a similar manner.

When the panel is driven with left scan (Reverse scan), this offset relationship becomes inverted for even and

odd lines. Moreover, since the dot arrangement is asymmetrical, the HST position is also changed. The

CXD2411AR deals with this inversion as follows.

Right scan

Left scan

(Normal scan)

(Reverse scan)

H SCANNER

Display area

When using single-panel

(1) When the right/left inversed-identification pin (RGT) goes L, the relationship concerning HCK output

switches between odd and even lines. In this case, use HST1 for the horizontal direction start pulse.

When RGT is H:

Right scan mode is on. The right scan drive pulse is output by the timing generator and is supplied to

the panel.

When RGT is L:

Left scan mode is on. The left scan drive pulse is output by the timing generator and is supplied to the

panel.

When using three-panels

(1) In order to be able to simultaneously drive three panels, with a mixture of right/left inversion on and off,

output two pulses regarding HST pulse: HST1 for right scan (Normal scan) and HST2 for left scan

(Reverse scan).

In addition, left and right scan outputs are necessary for the RGT signal as well. However, since this timing

generator does not have an RGT (right/left inversed-identification) output pin for left scan, external

measures must be taken. Similarly, external measures are also taken for HCK1 and 2.

Regarding SH, the wiring of SH1 and SH4 to the driver IC.

(2) When the right/left inversed-identification pin (RGT) goes L, the relationship concerning HCK output

switches between odd and even lines for each output switches.

When RGT is H:

Right scan mode is on. The right scan (A) and left scan (B) drive pulses are output by the timing

generator and are supplied to panels 1 and 2 and panel 3, respectively.

When RGT is L:

Left scan mode is on and (A) and (B) outputs are switched. Accordingly, panels 1 and 2 are used for

left scan and panel 3 changes to right scan.

– 12 –

CXD2411AR

Application Circuit (Three-panel LCD drive)

SH1

SH2

SH3

SH4

Right scan driver

32

33

34

30

SH1

SH2

SH3

SH4

TG

SH1

SH2

SH3

SH4

Left scan driver

Signal Driver

Panel 1

TG

(Right scan)

SH1

SH2

SH3

SH4

32

33

34

30

22

Signal Driver

Right scan output

(A)

Panel 2

HST1

(Right scan)

SH1

SH2

32

33

34

30

14

Signal Driver

SH3

Left scan output

(B)

SH4

Panel 3

HST2

(Left scan)

HCK1

HCK2

RGT

VST

24

23

10

18

21

20

17

16

RGT IN

(common)

VCK1

VCK2

EN

(To all panels)

CLR

The facing of the three panels is the same.

– 13 –

CXD2411AR

SH Pulse and HCK Phase Relationship

The phase relationship between the SH pulse and HCK changes according to switching between right scan

(Normal scan) and left scan (Reverse scan).

In the present timing, SH3 is the re-sampling pulse.

RGT = H (Normal scan)

RGT = L (Reverse scan)

HCK1

SH1

SH2

SH3

SH4

– 14 –

CXD2411AR

WIDE Mode

Setting the WIDE pin (Pin 4) to H, shifts the unit to WIDE mode. In this mode, the aspect ratio is converted

through pulse eliminator processing, allowing 16:9 quasi-WIDE display.

During WIDE mode, vertical pulse eliminator scanning of 1/4 for NTSC and 1/2 and 1/4 for PAL, are

performed, and the video signal is compressed to achieve a 16:9 aspect ratio. In addition, in areas outside the

display area, black is displayed by performing high-speed scanning. The timing during high-speed scanning is

a 2H cycle pulse consisting of normal drive (1H) and quadruple-speed drive (1H) and black signals are written

in 28 and 27 lines, respectively of the upper and lower side of this display area. During this time, FRP is

changed to a 4H cycle, HST to a 2H cycle, and EN and CLR are not output.

In addition, the SBLK output, which is the black signal generation timing pulse, becomes H.

(For example, black display in the panel is permitted by connecting the black signal output SBLK to the

external RGB input pin of the CXA1785R/AR.)

Refer to the attached sheets for detailed timing.

Vertical high-speed scanning

28 LINES

Black display area

(28 LINES)

218 LINES

(225 LINES)

163 LINES

(169 LINES)

Display area

27 LINES

(28 LINES)

Black display area

16 : 9 display

4 : 3 display

Vertical pulse eliminator scanning

(at normal-speed scanning)

Numbers in parentheses are for the LCX009AK/AKB.

All other numbers are for the LCX005BK/BKB.

At high-speed scanning

At normal-speed scanning

VCK1

Quadruple-speed scanning

Normal-speed scanning

HST

2H cycle

4H cycle

FRP

SBLK

– 15 –

CXD2411AR

– 16 –

CXD2411AR

– 17 –

CXD2411AR

– 18 –

CXD2411AR

– 19 –

CXD2411AR

– 20 –

CXD2411AR

– 21 –

CXD2411AR

– 22 –

CXD2411AR

– 23 –

CXD2411AR

– 24 –

CXD2411AR

– 25 –

CXD2411AR

– 26 –

CXD2411AR

– 27 –

CXD2411AR

– 28 –

CXD2411AR

– 29 –

CXD2411AR

– 30 –

CXD2411AR

– 31 –

CXD2411AR

– 32 –

CXD2411AR

– 33 –

CXD2411AR

– 34 –

CXD2411AR

– 35 –

CXD2411AR

– 36 –

CXD2411AR

– 37 –

CXD2411AR

– 38 –

CXD2411AR

– 39 –

CXD2411AR

AC Driving for No Signal

HST1, HST2, HCK1, HCK2, FRP, VCK1, VCK2, XCLP, HD, VD, and VST are made to run free so that the

LCD panel is AC driven even when there are no horizontal and vertical sync signals from the XHD and XVD

pins.

During this time, the PLL counter is made to run free because the horizontal sync separation circuit stops. In

addition, the auxiliary V counter is used to create the reference pulse for generating VD and VST because the

vertical sync separation circuit is also stopped.

The cycle of this V counter is designed to be 269H for NTSC and 321H for PAL. However, when there is no

vertical sync signal for 301H (NTSC) or 360H (PAL), the no signal state is assumed and the free running VD

and VST pulses are generated from the next field.

The RPD is kept at high impedance when there is no signal in order to prevent the AFC circuit from causing

phase errors due to phase comparison.

AFC Circuit (702/1050fh Generation)

4.7µs

XHD

RPD

5V

2.5V

The center of SYNC

0V

A fully synchronized AFC circuit is built in. PLL error detection signal is generated at the following timing.

The phase comparison output of the entire bottom of XHD and the internal H counter becomes RPD. RPD

output is converted to DC error with the lag-lead filter, and then it changes the varicap capacitance and the

oscillating frequency is stabilized at 702, 1050fh in the LCX005BK/BKB, LCX009AK/AKB.

– 40 –

CXD2411AR

Application Circuit

35

32

31 30 29 28 27 26 25

36

34 33

37 N.C.

24

HCK1

HP4

RPD

VSS

38

39

40

41

42

43

44

45

46

47

48

HCK2 23

3.3µ

10k

1k

HST1

VCK1

VCK2

VDD

22

21

20

19

18

17

16

15

14

13

LCD panel

3300p

0.01µ

CKO

CKI

33k

VST

VDD

N.C.

XVD

FP1

FP2

FP3

10k

EN

CLR

L

100k

N.C.

20p

HST2

SLFR

RGB decoder

LCD panel

1

2

3

4

5

6

7

8

9

10 11 12

+5V

16:9

N

R

LCX005BK/BKB

LCX009AK/AKB

PAL

NT

4:3

Reference examples of L value: when using LCX009AK/AKB 4.7µH

when using LCX005BK/BKB 10µH

Recommended varicap: 1T369 (SONY)

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for

any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 41 –

CXD2411AR

Package Outline

Unit: mm

48PIN LQFP (PLASTIC)

9.0 ± 0.2

7.0 ± 0.1

S

36

25

24

13

37

48

B

A

(0.22)

0.13

12

1

+ 0.05

0.127 – 0.02

0.5

+ 0.2

1.5 – 0.1

+ 0.08

0.18 – 0.03

M

0.1

S

0.1 ± 0.1

+ 0.08

0.18 – 0.03

(0.18)

0.18 ± 0.03

0° to 10°

DETAIL B:SOLDER

DETAIL B:PALLADIUM

DETAIL A

NOTE: Dimension “ ” does not include mold protrusion.

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

EPOXY RESIN

SOLDER/PALLADIUM

LQFP-48P-L01

LQFP048-P-0707

SONY CODE

EIAJ CODE

PLATING

42/COPPER ALLOY

0.2g

JEDEC CODE

PACKAGE MASS

– 42 –


型号：	CXD2411AR
厂家：	SONY CORPORATION
描述：	Timing Generator for Color LCD Panels 时序发生器彩色LCD面板消费电路商用集成电路 CD
文件：	总42页 (文件大小：1147K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CXD2411AR [SONY]

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