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ESDALC6V1M3_08 [STMICROELECTRONICS]

Dual low capacitance Transil array for ESD protection; 双低电容阵列的Transil ESD保护
ESDALC6V1M3_08
型号： ESDALC6V1M3_08
厂家： ST    ST
描述：

Dual low capacitance Transil array for ESD protection
双低电容阵列的Transil ESD保护
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ESDALC6V1W5  
Quad TRANSIL™ array for data protection  
Main applications  
Where transient overvoltage protection in ESD  
sensitive equipment is required, such as :  
SOT323-5L  
■ Computers  
■ Printers  
Order codes  
■ Communication systems  
■ Cellular phones and accessories  
■ Wireline and wireless telephone sets  
■ Set top boxes  
Part Number  
ESDALC6V1W5  
Marking  
C61  
ESDALC6V1W5 Functional diagram  
Features  
■ 4 Unidirectional Transil functions  
■ Breakdown voltage:  
V
BR = 6.1 V minimum  
I/01  
GND  
I/02  
I/04  
I/03  
■ Low leakage current: < 1 µA  
■ Low capacitance: 7.5 pF at 3 V  
■ Very small PCB area < 4.2 mm2 typically  
Description  
The ESDALCxxxWx are monolithic suppressors  
designed to protect components connected to  
data and transmission lines against ESD.  
Complies with the following standards  
IEC61000-4-2  
These devices clamp the voltage just above the  
logic level supply for positive transients, and to a  
diode drop below ground for negative transients.  
Level 4  
15 kV (air discharge)  
8 kV(contact discharge)  
MIL STD 883E - Method 3015-7 Class 3  
Benefits  
25 kV HBM (Human Body Model)  
■ High ESD protection level: up to 25 kV  
■ High integration  
TM: TRANSIL is a trademark of STMicroelectronics  
January 2006  
Rev 5  
1/7  
www.st.com  
7
1 Characteristics  
ESDALC6V1W5  
1
Characteristics  
Table 1.  
Symbol  
PPP  
Absolute Ratings (Tamb = 25°C)  
Parameter  
Value  
25  
Unit  
W
Peak pulse power (8/20 µs)  
Tj  
Junction temperature  
150  
°C  
Tstg  
Storage temperature range  
-55 to +150 °C  
260 °C  
-40 to +150 °C  
TL  
Maximum lead temperature for soldering during 10s  
Operating temperature range(1)  
Top  
1. The values of the operating parameters versus temperature are given through curves and αT parameter.  
1.1 Electrical Characteristics (Tamb = 25°C)  
Symbol  
VRM  
VBR  
VCL  
IRM  
Parameter  
Stand-off voltage  
I
IF  
Breakdown voltage  
Clamping voltage  
Leakage current  
VF  
IPP  
Peak pulse current  
Reverse leakage current  
Forward current  
V
CLVBR VRM  
V
IRM  
IR  
IF  
αT  
Voltage temperature coefficient  
Forward voltage drop  
Capacitance  
Slope: 1/Rd  
VF  
IPP  
C
Rd  
Dynamic resistance  
VBR@ IR  
IRM @ VRM  
Rd  
αT  
C
typ.  
typ.(1)  
max.(2)  
min.  
max.  
max.  
Part Numbers  
3V bias  
10-4/°C  
V
V
mA  
µA  
V
Ω
pF  
ESDALC6V1W5  
6.1  
7.2  
1
1
3
1.1  
6
7.5  
1. Square pulse l = 15 A, t = 2.5 µs  
pp  
p
2.  
V
= aT* (T  
- 25 °C) * V (25 °C)  
amb BR  
BR  
2/7  
ESDALC6V1W5  
1 Characteristics  
Figure 1. Peak power dissipation versus  
initial junction temperature  
Figure 2. Peak pulse power versus  
exponential pulse duration  
(Tj initial = 25°C)  
P
(W)  
P
[T initial] / P  
j
[T initial = 25°C]  
pp j  
pp  
pp  
1.1  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0.0  
100  
T
initial = 25°C  
j
t
(µs)  
p
T (°C)  
j
10  
0
25  
50  
75  
100  
125  
150  
175  
1
10  
100  
Figure 3. Clamping voltage versus peak pulse Figure 4. Capacitance versus reverse applied  
current (Tj initial = 25°C, rectangular  
voltage (typical values)  
waveform, tp = 2.5 µs)  
I
(A)  
pp  
C(pF)  
100.0  
10.0  
1.0  
14  
13  
12  
11  
10  
9
F=1MHz  
Vosc=30mVRMS  
Tj=25°C  
8
7
6
5
4
3
2
t
=2.5µs  
p
1
V
(V)  
V
(V)  
cl  
R
T
initial =25°C  
j
0
0.1  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
4.5  
5.0  
0
10  
20  
30  
40  
50  
60  
Figure 5. Relative variation of leakage current Figure 6. Peak forward voltage drop versus  
versus junction temperature  
(typical values)  
peak forward current (typical  
values)  
I
(A)  
FM  
I
[T ] / I [T =25°C]  
R
j
R
j
1.E+00  
1.E-01  
1.E-02  
1.E-03  
100  
10  
1
V
(V)  
FM  
T (°C)  
j
25  
50  
75  
100  
125  
150  
0.4  
0.6  
0.8  
1.0  
1.2  
1.4  
1.6  
1.8  
2.0  
3/7  
2 Ordering information scheme  
ESDALC6V1W5  
Figure 7. ESD response to IEC61000-4-2 (air  
discharge 15 kV, positive surge)  
2
Ordering information scheme  
ESDA LC 6V1 W5  
ESD Array  
Low capacitance  
Breakdown Voltage  
6V1 = 6.1 Volts min  
Package  
W5 = SOT323-5L  
4/7  
ESDALC6V1W5  
3 Package mechanical data  
3
Package mechanical data  
3.1  
SOT323-5L package  
DIMENSIONS  
A
REF.  
Millimeters  
Inches  
E
Min.  
Max.  
Min.  
Max.  
A
A1  
A2  
b
0.8  
0
1.1  
0.1  
1
0.031  
0
0.043  
0.004  
0.039  
0.012  
0.007  
0.086  
0.053  
e
b
D
e
0.8  
0.15  
0.1  
1.8  
1.15  
0.031  
0.006  
0.004  
0.071  
0.045  
0.3  
0.18  
2.2  
1.35  
A1  
c
A2  
D
Q1  
E
c
e
0.65 Typ.  
0.025 Typ.  
HE  
HE  
Q1  
1.8  
0.1  
2.4  
0.4  
0.071  
0.004  
0.094  
0.016  
Figure 8. Footprint dimensions  
0.3  
1.0  
1.0  
2.9  
0.35  
Dimensions in mm  
In order to meet environmental requirements, ST offers these devices in ECOPACK®  
packages. These packages have a Lead-free second level interconnect . The category of  
second level interconnect is marked on the package and on the inner box label, in compliance  
with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also  
marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are  
available at: www.st.com.  
5/7  
4 Ordering information  
ESDALC6V1W5  
4
Ordering information  
Part Number  
Marking  
Package  
Weight  
Base qty  
Delivery mode  
ESDALC6V1W5  
C61  
SOT323-5L  
5.4 mg  
3000  
Tape & reel  
5
Revision history  
Date  
Revision  
Changes  
Jun-2002  
4A  
Previous issue  
Reformatted to current template.  
Figure 5: Range of Tj extended to 150 °C.  
10-Jan-2006  
5
Figure 6: Peak forward voltage drop versus peak forward current (typical  
values) added.  
6/7  
ESDALC6V1W5  
5 Revision history  
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences  
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted  
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject  
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not  
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.  
The ST logo is a registered trademark of STMicroelectronics.  
All other names are the property of their respective owners  
© 2006 STMicroelectronics - All rights reserved  
STMicroelectronics group of companies  
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -  
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America  
www.st.com  
7/7  

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