SUM110N08-07L [VISHAY]
N-Channel 75-V (D-S), 175∑C MOSFET; N通道75 -V （D -S ） ， 175℃ MOSFET
| 型号： | SUM110N08-07L |
| 厂家： | 
VISHAY |
| 描述： | N-Channel 75-V (D-S), 175∑C MOSFET |
| 文件： | 总3页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPICE Device Model SUM110N08-07L
Vishay Siliconix
N-Channel 75-V (D-S), 175°C MOSFET
CHARACTERISTICS
• N-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0 to 10V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to
model the gate charge characteristics while avoiding convergence
difficulties of the switched Cgd model. All model parameter values
are optimized to provide a best fit to the measured electrical data
and are not intended as an exact physical interpretation of the
device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 70308
09-Jun-04
www.vishay.com
1
SPICE Device Model SUM110N08-07L
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Simulated
Data
Measured
Data
Parameter
Symbol
Test Conditions
Unit
Static
Gate Threshold Voltage
On-State Drain Currenta
VGS(th)
ID(on)
2.1
V
A
V
DS = VGS, ID = 250 µA
865
VDS ≥ 5 V, VGS = 10 V
VGS = 10 V, ID = 30 A
0.0056
0.0089
0.011
0.0076
0.93
0.0055
VGS = 10 V, ID = 30 A, TJ = 125°C
VGS = 10 V, ID = 30 A, TJ = 175°C
VGS = 4.5 V, ID = 20 A
Drain-Source On-State Resistancea
rDS(on)
Ω
0.0075
1
Forward Voltagea
VSD
IF = 110 A, VGS = 0 V
V
Dynamicb
Input Capacitance
Ciss
Coss
Crss
Qg
4700
678
330
82
4420
700
310
81
V
GS = 0 V, VDS = 25 V, f = 1 MHz
pF
nC
Output Capacitance
Reverse Transfer Capacitance
Total Gate Chargec
Gate-Source Chargec
Gate-Drain Chargec
Turn-On Delay Timec
Rise Timec
VDS = 30 V, VGS = 10 V, ID = 110 A
Qgs
Qgd
td(on)
tr
20
20
20
20
19
15
12
20
VDD = 30 V, RL = 0.47 Ω
Turn-Off Delay Timec
Fall Timec
td(off)
tf
18
40
I
D ≅ 110 A, VGEN = 10 V, RG = 2.5 Ω
ns
16
15
Source-Drain Reverse Recovery Time
trr
31
55
IF = 110 A, di/dt = 100 A/µs
Notes
a.
b.
c.
Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
Guaranteed by design, not subject to production testing.
Independent of operating temperature.
www.vishay.com
2
Document Number: 70308
09-Jun-04
SPICE Device Model SUM110N08-07L
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 70308
09-Jun-04
www.vishay.com
3
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