AOD409_11 [AOS]

P-Channel Enhancement Mode Field Effect Transistor; P沟道增强型场效应晶体管
AOD409_11
型号: AOD409_11
厂家: ALPHA & OMEGA SEMICONDUCTORS    ALPHA & OMEGA SEMICONDUCTORS
描述:

P-Channel Enhancement Mode Field Effect Transistor
P沟道增强型场效应晶体管

晶体 晶体管 场效应晶体管
文件: 总6页 (文件大小:243K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
AOD409/AOI409  
P-Channel Enhancement Mode Field Effect Transistor  
General Description  
Features  
The AOD/I409 uses advanced trench technology to  
provide excellent RDS(ON), low gate charge and low  
gate resistance. With the excellent thermal resistance  
of the DPAK package, this device is well suited for  
high current load applications.  
VDS (V) = -60V  
ID = -26A (VGS = -10V)  
RDS(ON) < 40m(VGS = -10V) @ -20A  
RDS(ON) < 55m(VGS = -4.5V)  
UIS TESTED!  
Rg,Ciss,Coss,Crss Tested  
TO-251A  
IPAK  
TO252  
DPAK  
Bottom View  
Top View  
Top View  
Bottom View  
D
S
D
D
D
D
G
S
G
G
S
S
D
D
G
G
S
Absolute Maximum Ratings TA=25°C unless otherwise noted  
Parameter  
Symbol  
Maximum  
Units  
VDS  
Drain-Source Voltage  
-60  
V
VGS  
Gate-Source Voltage  
Continuous Drain  
Current G  
±20  
-26  
V
A
TC=25°C  
TC=100°C  
ID  
-18  
Pulsed Drain Current C  
Avalanche Current C  
Repetitive avalanche energy L=0.1mH C  
IDM  
IAR  
EAR  
-60  
-26  
A
33.8  
60  
mJ  
TC=25°C  
PD  
W
Power Dissipation B  
TC=100°C  
30  
TA=25°C  
2.5  
PDSM  
W
Power Dissipation A  
TA=70°C  
1.6  
TJ, TSTG  
Junction and Storage Temperature Range  
-55 to 175  
°C  
Thermal Characteristics  
Parameter  
Symbol  
Typ  
16.7  
40  
Max  
25  
Units  
°C/W  
°C/W  
°C/W  
Maximum Junction-to-Ambient A  
t 10s  
RθJA  
Maximum Junction-to-Ambient A  
Maximum Junction-to-Case C  
50  
Steady-State  
Steady-State  
RθJC  
1.9  
2.5  
Alpha & Omega Semiconductor, Ltd.  
AOD409/AOI409  
Electrical Characteristics (TJ=25°C unless otherwise noted)  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
STATIC PARAMETERS  
BVDSS  
Drain-Source Breakdown Voltage  
ID=-250µA, VGS=0V  
-60  
V
VDS=-48V, VGS=0V  
-0.003  
-1  
-5  
IDSS  
Zero Gate Voltage Drain Current  
µA  
TJ=55°C  
IGSS  
Gate-Body leakage current  
Gate Threshold Voltage  
On state drain current  
VDS=0V, VGS=±20V  
VDS=VGS ID=-250µA  
VGS=-10V, VDS=-5V  
±100  
-2.4  
nA  
V
VGS(th)  
ID(ON)  
-1.2  
-60  
-1.9  
A
VGS=-10V, ID=-20A  
32  
53  
40  
55  
mΩ  
mΩ  
RDS(ON)  
TJ=125°C  
Static Drain-Source On-Resistance  
VGS=-4.5V, ID=-20A  
43  
gFS  
VSD  
IS  
Forward Transconductance  
Diode Forward Voltage  
V
DS=-5V, ID=-20A  
32  
S
V
A
IS=-1A,VGS=0V  
-0.73  
-1  
Maximum Body-Diode Continuous Current  
-30  
DYNAMIC PARAMETERS  
Ciss  
Coss  
Crss  
Rg  
Input Capacitance  
2977  
241  
153  
2
3600  
2.4  
pF  
pF  
pF  
VGS=0V, VDS=-30V, f=1MHz  
Output Capacitance  
Reverse Transfer Capacitance  
Gate resistance  
VGS=0V, VDS=0V, f=1MHz  
SWITCHING PARAMETERS  
Qg(10V)  
Total Gate Charge  
Total Gate Charge  
Gate Source Charge  
Gate Drain Charge  
Turn-On DelayTime  
Turn-On Rise Time  
Turn-Off DelayTime  
Turn-Off Fall Time  
44  
22.2  
9
54  
28  
nC  
nC  
nC  
nC  
ns  
Qg(4.5V)  
V
GS=-10V, VDS=-30V, ID=-20A  
Qgs  
Qgd  
tD(on)  
tr  
10  
12  
VGS=-10V, VDS=-30V, RL=1.5,  
14.5  
38  
ns  
RGEN=3Ω  
tD(off)  
tf  
ns  
15  
ns  
trr  
IF=-20A, dI/dt=100A/µs  
IF=-20A, dI/dt=100A/µs  
40  
Body Diode Reverse Recovery Time  
Body Diode Reverse Recovery Charge  
50  
ns  
Qrr  
59  
nC  
A: The value of R qJA is measured with the device mounted on 1in 2 FR-4 board with 2oz. Copper, in a still air environment with T A =25°C. The  
Power dissipation PDSM is based on R θJA and the maximum allowed junction temperature of 150°C. The value in any a given application depends  
on the user's specific board design, and the maximum temperature fo 175°C may be used if the PCB allows it.  
B. The power dissipation PD is based on T J(MAX)=175°C, using junction-to-case thermal resistance, and is more useful in setting the upper  
dissipation limit for cases where additional heatsinking is used.  
C: Repetitive rating, pulse width limited by junction temperature T J(MAX)=175°C.  
D. The R θJA is the sum of the thermal impedence from junction to case R qJC and case to ambient.  
E. The static characteristics in Figures 1 to 6 are obtained using <300 ms pulses, duty cycle 0.5% max.  
F. These curves are based on the junction-to-case thermal impedence which is measured with the device mounted to a large heatsink, assuming a  
maximum junction temperature of T J(MAX)=175°C.  
G. The maximum current rating is limited by bond-wires.  
H. These tests are performed with the device mounted on 1 in 2 FR-4 board with 2oz. Copper, in a still air environment with T A=25°C. The SOA  
curve provides a single pulse rating.  
*This device is guaranteed green after data code 8X11 (Sep 1 ST 2008).  
Rev 5: Jan 2011  
THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL  
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING  
OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN,  
FUNCTIONS AND RELIABILITY WITHOUT NOTICE  
Alpha & Omega Semiconductor, Ltd.  
AOD409/AOI409  
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS  
30  
25  
20  
15  
10  
5
30  
25  
20  
15  
10  
5
-4.5V  
-10V  
-4V  
VDS=-5V  
-6V  
-5V  
125°C  
-3.5V  
25°C  
VGS=-3V  
4
0
0
0
1
2
3
4
5
0
1
2
3
5
-VGS(Volts)  
-VDS (Volts)  
Figure 2: Transfer Characteristics  
Fig 1: On-Region Characteristics  
50  
2
VGS=-10V  
ID=-20A  
1.8  
1.6  
1.4  
1.2  
1
40  
30  
20  
10  
0
VGS=-4.5V  
VGS=-4.5V  
ID=-20A  
VGS=-10V  
0.8  
0
5
10  
15  
20  
25  
-ID (A)  
0
25  
50  
75  
Temperature (°C)  
Figure 4: On-Resistance vs. Junction Temperature  
100  
125  
150  
175  
Figure 3: On-Resistance vs. Drain Current and Gate  
Voltage  
80  
60  
40  
20  
1.0E+01  
1.0E+00  
1.0E-01  
1.0E-02  
1.0E-03  
1.0E-04  
1.0E-05  
1.0E-06  
ID=-20A  
125°C  
125°C  
25°C  
25°C  
0.0  
0.2  
0.4  
0.6  
-VSD (Volts)  
Figure 6: Body-Diode Characteristics  
0.8  
1.0  
1.2  
2
4
6
8
10  
-VGS (Volts)  
Figure 5: On-Resistance vs. Gate-Source Voltage  
Alpha & Omega Semiconductor, Ltd.  
AOD409/AOI409  
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS  
10  
4000  
VDS=-30V  
ID=-20A  
3600  
3200  
2800  
2400  
2000  
1600  
1200  
800  
Ciss  
8
6
4
Coss  
Crss  
2
400  
0
0
0
5
10  
15  
-VDS (Volts)  
20  
25  
30  
0
5
10 15 20 25 30 35 40 45 50  
-Qg (nC)  
Figure 7: Gate-Charge Characteristics  
Figure 8: Capacitance Characteristics  
100.0  
10.0  
1.0  
1000  
800  
600  
400  
200  
0
10µs  
100µs  
1ms  
TJ(Max)=175°C  
TC=25°C  
RDS(ON)  
limited  
10ms  
DC  
TJ(Max)=175°C, TC=25°C  
0.1  
0.0001  
0.001  
0.01  
0.1  
1
10  
0.1  
1
10  
100  
-VDS (Volts)  
Pulse Width (s)  
Figure 10: Single Pulse Power Rating Junction-to-  
Case (Note F)  
Figure 9: Maximum Forward Biased Safe  
Operating Area (Note F)  
10  
In descending order  
D=Ton/T  
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse  
TJ,PK=TC+PDM.ZθJC.RθJC  
RθJC=2.5°C/W  
1
0.1  
PD  
Ton  
Single Pulse  
T
0.01  
0.00001  
0.0001  
0.001  
0.01  
Pulse Width (s)  
Figure 11: Normalized Maximum Transient Thermal Impedance (Note F)  
0.1  
1
10  
100  
Alpha & Omega Semiconductor, Ltd.  
AOD409/AOI409  
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS  
30  
25  
20  
15  
70  
60  
50  
40  
30  
20  
10  
0
L ID  
tA =  
BV VDD  
TA=25°C  
10  
0
25  
50  
75  
100  
125  
150  
175  
0.00001  
0.0001  
Time in avalanche, tA (s)  
Figure 12: Single Pulse Avalanche capability  
0.001  
TCASE (°C)  
Figure 13: Power De-rating (Note B)  
60  
30  
25  
20  
15  
10  
5
TA=25°C  
50  
40  
30  
20  
10  
0
0
0
25  
50  
75  
TCASE (°C)  
Figure 14: Current De-rating (Note B)  
100  
125  
150  
175  
0.001  
0.01  
0.1  
1
10  
100  
1000  
Pulse Width (s)  
Figure 15: Single Pulse Power Rating Junction-to-  
Ambient (Note H)  
10  
1
D=Ton/T  
In descending order  
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse  
TJ,PK=TA+PDM.ZθJA.RθJA  
RθJA=50°C/W  
0.1  
0.01  
PD  
Single Pulse  
0.001  
Ton  
T
0.001  
0.00001  
0.0001  
0.01  
0.1  
Pulse Width (s)  
Figure 16: Normalized Maximum Transient Thermal Impedance (Note H)  
1
10  
100  
1000  
Alpha & Omega Semiconductor, Ltd.  
AOD409/AOI409  
Gate Charge Test Circuit & Waveform  
Vgs  
Qg  
-
-10V  
-
VDC  
Qgs  
Qgd  
+
Vds  
VDC  
+
DUT  
Vgs  
Ig  
Resistive Switching Test Circuit & Waveforms  
RL  
Vds  
toff  
ton  
t
f
td(off)  
td(on)  
t
r
Vgs  
-
90%  
10%  
DUT  
Vdd  
Vgs  
VDC  
+
Rg  
Vgs  
Vds  
Unclamped Inductive Switching (UIS) Test Circuit & Waveforms  
EAR= 1/2 LIA2R  
L
Vds  
Id  
Vgs  
Vds  
-
BVDSS  
Vgs  
Vdd  
VDC  
+
Id  
Rg  
I AR  
DUT  
Vgs  
Vgs  
Diode Recovery Test Circuit & Waveforms  
Q rr = - Idt  
Vds +  
DUT  
Vgs  
trr  
Vds -  
L
-Isd  
-IF  
Isd  
Vgs  
dI/dt  
-IRM  
+
Vdd  
VDC  
Vdd  
-
-Vds  
Ig  
Alpha & Omega Semiconductor, Ltd.  

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