ICS9250-10 [ICSI]
Frequency Timing Generator for Pentium II Systems; 频率时序发生器奔腾II系统
| 型号： | ICS9250-10 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Timing Generator for Pentium II Systems |
| 文件： | 总16页 (文件大小：668K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9250-10
Integrated
Circuit
Systems, Inc.
Preliminary Product Preview
Frequency Timing Generator for Pentium II Systems
General Description
The ICS9250-10 is a single chip clock for Intel Pentium II.
Features
Generates the following system clocks:
-3CPU(2.5V)66.6/100MHz(upto133MHzthrough
It provides all necessary clock signals for such a system.
I2C selection)
- 9SDRAM(3.3V)upto133MHz
-8PCI(3.3V)@33.3MHz
-2IOAPIC(2.5V)@16.67or33.3MHz
- 2Hublinkclocks(3.3V)@66.6MHz
- 2 USB (3.3V) @ 48 MHz ( Non spread spectrum)
- 1REF(3.3V)@14.318MHz
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces EMI by 8dB to 10 dB.
This simplifies EMI qualification without resorting to board
design iterations or costly shielding. The ICS9250-10
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Supports spread spectrum modulation ,
down spread 0 to -0.5%
I2C support for power management
Efficient power management scheme through PD#
Uses external 14.138 MHz crystal
Block Diagram
Pin Configuration
56-Pin 300 mil SSOP
*60K ohm pull-up to VDD on indicated inputs.
Power Groups
VDD0, GND0=REF&Crystal
VDD1,GND1=3V66[1:0]
VDD2,GND2=PCICLK[7:0]
VDD3,GND3=PLLcore
VDD4,GND4= 48MHz[1:0]
VDD5,GND5 =SDRAM_F,SDRAM[7:0]
VDDL0,GNDL0=CPUCLK[2:0]
VDDL1,GNDL1=IOAPIC[1:0]
Pentium II is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
9250-10 Rev J 6/15/99
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
ICS9250-10
Preliminary Product Preview
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
Latched input at Power On. this determines the IOAPIC frequency.
When a "0" is latched, IOAPIC Freq=16.67MHz
When "1" is latched, IOAPIC Freq=33.3MHz
This pin has a 60K internal pull-up.
FREQ_APIC
IN
1
REF0
X1
OUT 3.3V, 14.318MHz reference clock output.
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
3
4
IN
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
X2
OUT
5, 6, 14, 17, 23,
24, 35, 41, 47
GND (0:5)
3V66 [1:0]
VDD (0:5)
PWR Ground pins for 3.3V supply
8, 7
OUT 3.3V Fixed 66MHz clock outputs for HUB
PWR 3.3V power supply
2, 9, 10, 21,
22, 27, 33, 38, 44
20,19,18,16,
15,13,12,11
PCICLK[7:0]
48MHz (0:1)
FS (0:1)
OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS
OUT 3.3V Fixed 48MHz clock outputs for USB
25, 26
28, 29
30
Function Select pins. Determines CPU frequency, all output
functionality. Please refer to Functionality table on page 3.
IN
SDATA
IN
IN
Data input for I2C serial input.
31
SCLK
Clock input of I2C input
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down
will not be greater than 3ms.
32
PD#
IN
36, 37, 39, 40, 42,
43, 45, 46
3.3V output running 100MHz. All SDRAM outputs can be turned
off through I2C
SDRAM [7:0]
SDRAM_F
OUT
34
OUT 3.3V free running 100MHz SDRAM not affected by I2C
PWR Ground for 2.5V power supply for CPU & APIC
56,48
GNDL [1:0]
CPUCLK [2:0]
2.5V Host bus clock output. 66MHz or 100MHz depending on FS
(0:1) pins Refer page 3.
49,50,52
OUT
51, 53
54, 55
VDDL (0:1)
PWR 2.5V power suypply for CPU & IOAPIC
IOAPIC [1:0]
OUT 2.5V clock outputs running at 16.67MHz or 33.3MHz.
2
ICS9250-10
Preliminary Product Preview
Functionality Table
FS1
0
FS0
0
CPU
Hi-Z
SDRAM
Hi-Z
3V66
Hi-Z
PCICLK
Hi-Z
48MHz
Hi-Z
REF0
Hi-Z
IOAPIC
Hi-Z
Notes
Tristate
Test Mode
0
1
TCLK/2
66 MHz
100 MHz
TCLK/4
100 MHz
100 MHz
TCLK/4
66 MHz
66 MHz
TCLK/8
33 MHz
33MHz
TCLK/2
48 MHz
48 MHz
TCLK
TCLK/16
16.67MHz
16.67MHz
1
0
14.318MHz
14.318MHZ
1
1
Clock Enable Configuration
REF,
PD#
CPUCLK
SDRAM
IOAPIC
66MHz
PCICLK
Osc
VCOs
48MHz
LOW
ON
0
1
LOW
ON
LOW
ON
LOW
ON
LOW
ON
LOW
ON
OFF
ON
OFF
ON
Select Functions
FS1
0
FS0
0
Notes
Tristate
0
1
Test Mode
1
0
Active CPU = 66MHz
Active CPU = 100MHz
1
1
3
ICS9250-10
Preliminary Product Preview
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
Maximum Allowed Current
Max 2.5V supply consumption
Max discrete cap loads,
Vddq2 = 2.625V
Max 2.5V supply consumption
Max discrete cap loads,
Vddq2 = 3.465V
810E
Condition
All static inputs = Vddq3 or GND All static inputs = Vddq3 or GND
Powerdown Mode
(PWRDWN# = 0
10mA
70mA
10mA
280mA
280mA
Full Active 66MHz
SEL1, 0 = 10
Full Active 100MHz
SEL1, 0 = 11
100mA
4
ICS9250-10
Preliminary Product Preview
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
How to Read:
Controller (host) will send start bit.
Controler (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-BackwillsupportIntelPIIX4"Block-Read"protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
5
ICS9250-10
Preliminary Product Preview
Byte5:ICSReservedFunctionalityandfrequencyselectregister(Default=0)
Bit
Desctiption
PWD
Bit7
Bit6
Bit5
ICS RESERVED BIT (Needs to be 0 clock to operate normal)
ICS RESERVED BIT (Needs to be 0 clock to operate normal)
ICS RESERVED BIT (Needs to be 0 clock to operate normal)
Bit (4,3,0)
0
0
0
CPUCLK SDRAM 3V66 PCICLK
FS0
(HW)
SEL3
(Bit4)
SEL2
(Bit3)
SEL1
(Bit0)
MHz
MHz
MHz
MHz
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.67
70.67
74.66
82.66
63.5
68.67
72.67
88.66
100
100
106
112
124
95.25
103
109
133
100
106
112
124
95.25
103
109
133
66.67
70.67
74.67
82.66
63.5
33.33
35.33
37.33
41.33
31.75
34.33
36.33
44.33
33.33
35.33
37.33
41.33
31.75
34.33
36.33
44.33
68.67
72.67
88.66
66.67
70.67
74.67
82.66
63.5
Bit
(4,3,0)
XXXX
Note 1
106
112
124
95.25
103
68.67
72.67
88.66
109
133
Bit2
Bit1
Not used (Needs to be 1 for normal clock operation)
Not used (Needs to be 1 for normal clock operation)
1
1
Note1: Default at power-up will be for latched logic inputs to define frequency, as diplayed by Bit 3.
6
ICS9250-10
Preliminary Product Preview
Byte 0: Control Register
(1 = enable, 0 = disable)
Bit
Pin#
Name
Reserved
Reserved
Reserved
Reserved
PWD
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
0
0
0
1
SpreadSpectrum
(1=On/0=Off)
Bit 3
1
(Active/Inactive)
Bit 2
Bit 1
Bit 0
26
25
49
48MHz 1
48MHz 0
CPUCLK2
1
1
1
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Byte 1: Control Register
(1 = enable, 0 = disable)
Bit
Pin#
36
37
39
40
42
43
45
46
Name
SDRAM7
PWD
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Byte 2: Control Register
(1 = enable, 0 = disable)
Bit
Pin#
20
19
18
16
15
13
12
-
Name
PCICLK7
PWD
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
0
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
Reserved
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured
at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
7
ICS9250-10
Preliminary Product Preview
Byte 3: Reserved Register
(1 = enable, 0 = disable)
Bit
Pin#
Name
Reserved
PWD
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 4: Reserved Register
(1 = enable, 0 = disable)
Bit
Pin#
Name
Reserved
PWD
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured
at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
8
ICS9250-10
Preliminary Product Preview
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
-5
0.8
5
A
µ
IIH
VIN = VDD
A
µ
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
2.0
-100
60
A
µ
IIL2
-200
IDD3.3OP CL = 0 pF; Select @ 66M
100
600
mA
Supply Current
Power Down
A
µ
IDD3.3PD CL = 0 pF; With input address to Vdd or GND
400
Supply Current
Input frequency
Pin Inductance
Fi
VDD = 3.3 V;
14.318
MHz
nH
pF
Lpin
CIN
7
5
Input Capacitance1
Logic Inputs
Cout
CINX
Ttrans
Ts
Out put pin capacitance
X1 & X2 pins
6
pF
27
45
3
pF
Transition Time1
Settling Time1
Clk Stabilization1
Delay
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
mS
mS
mS
nS
3
TSTAB
3
tPZH,tPZH output enable delay (all outputs)
tPLZ,tPZH
1Guarenteed by design, not 100% tested in production.
1
1
10
10
output disable delay (all outputs)
nS
9
ICS9250-10
Preliminary Product Preview
Electrical Characteristics - CPU
TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
13.5
13.5
2
TYP MAX UNITS
1
RDSP2B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
45
45
Ω
Ω
1
RDSN2B
VOH2B
VOL2B
IOH2B
IOL2B
V
IOL = 1 mA
0.4
-27
30
V
VOH @MIN= 1.0V , VOH@ MAX= 2.375V
VOL @MIN= 1.2V , VOL@ MAX= 0.3V
VOL = 0.4 V, VOH = 2.0 V
VOH = 0.4 V, VOL = 2.0 V
VT = 1.25 V
-27
27
mA
mA
ns
ns
%
1
tr2B
0.4
0.4
45
1.6
1.6
55
1
Fall Time
tf2B
1
Duty Cycle
dt2B
50
1
Skew
tsk2B
VT = 1.25 V
175
250
ps
ps
1
tjcyc-cyc
VT = 1.25 V
Jitter
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
12
TYP MAX UNITS
1
RDSP1
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
55
55
Ω
Ω
1
RDSN1
12
VOH1
VOL1
IOH1
IOL1
2.4
V
IOL = 1 mA
0.55
-33
38
V
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33
mA
mA
ns
ns
%
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
30
0.5
0.5
45
1
tr1
2
1
Fall Time
tf1
2
1
Duty Cycle
dt1
55
1
Skew
tsk1
VT = 1.5 V
175
500
ps
ps
Jitter
tjcyc-cyc
VT = 1.5 V
1Guarenteed by design, not 100% tested in production.
10
ICS9250-10
Preliminary Product Preview
Electrical Characteristics - IOAPIC
TA = 0 - 70C;VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS
1
RDSP4B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -5.5 mA
IOL = 9.0 mA
9
9
2
30
30
Ω
Ω
1
RDSN4B
VOH4\B
VOL4B
IOH4B
V
0.4
-27
30
V
VOH@ min = 1.0 V, VOH@ MAX = 2.375 V
VOL@ MIN = 1.2 V, VOL@ MAX= 0.3V
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
-27
27
mA
mA
ns
ns
%
IOL4B
1
tr4B
0.4
0.4
45
1.6
1.6
55
1
Fall Time
tf4B
1
Duty Cycle
dt4B
Jitter
tjcyc-cyc
VT = 1.25 V
500
250
ps
ps
1
Tsk4
Skew
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
10
TYP MAX UNITS
1
RDSP3
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
24
24
Ω
Ω
1
RDSN3
10
VOH3
VOL3
IOH3
IOL3
2.4
V
IOL = 1 mA
0.4
-46
53
V
VOH @MIN= 2.0 V, VOH@ MAX=3.135 V
VOL@ MIN= 1.0 V, VOL@ MAX=0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-54
54
mA
mA
ns
ns
%
1
Tr3
0.4
0.4
45
1.6
1.6
55
1
Fall Time
Tf3
1
Duty Cycle
Dt3
1
Skew
Tsk3
VT = 1.5 V
250
250
ps
ps
Jitter
tjcyc-cyc VT = 1.5 V
1Guarenteed by design, not 100% tested in production.
11
ICS9250-10
Preliminary Product Preview
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
12
TYP MAX UNITS
1
RDSP1
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
55
55
Ω
Ω
1
RDSN1
12
VOH1
VOL1
IOH1
IOL1
2.4
V
IOL = 1 mA
0.55
-33
38
V
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33
mA
mA
ns
ns
%
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
30
0.5
0.5
45
1
tr1
2
1
Fall Time
tf1
2
1
Duty Cycle
dt1
55
1
Skew
tsk1
VT = 1.5 V
500
500
ps
ps
Jitter
tjcyc-cyc
VT = 1.5 V
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - REF, 48MHz_0 (Pin 25)
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output LowCurrent
Rise Time
SYMBOL
CONDITIONS
MIN
20
TYP MAX UNITS
1
RDSP5
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = 1 mA
60
60
Ω
Ω
1
RDSN5
20
VOH5
VOL5
IOH5
IOL5
2.4
V
IOL = -1 mA
0.4
-23
27
V
VOH @MIN=1 V, VOH@MAX= 3.135 V
VOL@MIN=1.95 V, VOL@MIN=0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-29
29
mA
mA
ns
ns
%
1
tr5
1.8
1.7
4
1
Fall Time
tf5
4
1
Duty Cycle
dt5
45
55
1
Jitter
tjcyc-cyc
VT = 1.5 V; Fixed Clocks
VT = 1.5 V; Ref Clocks
VT = 1.5 V
500
1000
250
ps
ps
ps
1
tjcyc-cyc
Tsk
Skew
1Guarenteed by design, not 100% tested in production.
12
ICS9250-10
Preliminary Product Preview
Electrical Characteristics - 48MHz_1 (Pin 26)
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
10
TYP MAX UNITS
1
RDSP3
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
24
24
Ω
Ω
1
RDSN3
10
VOH3
VOL3
IOH3
IOL3
2.4
V
IOL = 1 mA
0.4
-46
53
V
VOH @MIN= 2.0 V, VOH@ MAX=3.135 V
VOL@ MIN= 1.0 V, VOL@ MAX=0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-54
54
mA
mA
ns
ns
%
1
Tr3
0.4
0.4
45
1.6
1.6
55
1
Fall Time
Tf3
1
Duty Cycle
Dt3
1
Skew
Tsk3
VT = 1.5 V
250
250
ps
ps
tjcyc-cyc VT = 1.5 V
Jitter
1Guarenteed by design, not 100% tested in production.
13
ICS9250-10
Preliminary Product Preview
Group Offset Waveforms
Group Skews at Common Transition Edges: (CPU = 66MHz)
CPU & IOAPIC load (lumped) = 20pf; PCI, SDRAM, 3V66 LOAD (LUMPED) = 30pf.
GROUP
SYMBOL
SCPU1-3V66
CONDITIONS
MIN
TYP
MAX UNITS
CPU @ 1.25V, 3V66 @ 1.5V
(Note: 180° offset between CPU & 66MHz
CPU @ 1.25V, SDRAM @ 1.5V
CPU to 3V66
0
500
500
ps
ps
CPU to SDRAM
SCPU2-SDRAM
0
(Note: 180° offset between CPU & 66MHz
3V66 to PCI
S3V66-PCI 3V66 @ 1.5V, PCI @ 1.5V
1.5
0
4
ns
ps
IOAPIC to PCI
SIOAPIC-PCI IOAPIC @ 1.25V, PCI @1.5V
500
1Guarenteed by design, not 100% tested in production.
Group Skews at Common Transition Edges: (CPU = 100MHz)
CPU & IOAPIC load (lumped) = 20pf; PCI, SDRAM, 3V66 LOAD (LUMPED) = 30pf.
GROUP
SYMBOL
SCPU1-3V66
CONDITIONS
MIN
TYP
MAX UNITS
CPU @ 1.25V, 3V66 @ 1.5V
(Note: 180° offset between CPU & 100MHz
CPU @ 1.25V, SDRAM @ 1.5V
CPU to 3V66
0
500
500
ps
ps
CPU to SDRAM
SCPU2-SDRAM
0
(Note: 180° offset between CPU & 100MHz
3V66 to PCI
S3V66-PCI 3V66 @ 1.5V, PCI @ 1.5V
1.5
0
4
ns
ps
IOAPIC to PCI
SIOAPIC-PCI IOAPIC @ 1.25V, PCI @1.5V
500
1Guarenteed by design, not 100% tested in production.
14
ICS9250-10
Preliminary Product Preview
GeneralLayoutPrecautions:
1) Use a ground plane on the top layer of the
PCB in all areas not used by traces.
2) Make all power traces and vias as wide as
possible to lower inductance.
Notes:
1) All clock outputs should have series
terminating resistor. Not shown in all
places to improve readibility of diagram.
2) 47 ohm / 56pf RC termination should be
used on all over 50MHz outputs.
3) Optional crystal load capacitors are
recommended.
CapacitorValues:
C1, C2 : Crystal load values determined by user
C3:100pFceramic
All unmarked capacitors are 0.01µF ceramic
ConnectionstoVDD:
15
ICS9250-10
Preliminary Product Preview
SSOP Package
SYMBOL
COMMON DIMENSIONS
VARIATIONS
D
N
MIN.
.095
.008
.088
.008
.005
NOM.
.101
.012
.090
.010
MAX.
.110
.016
.092
.0135
.0085
MIN.
.620
.720
NOM. MAX.
A
A1
A2
B
AC
AD
.625
.725
.630
.730
48
56
C
.006
D
E
See Variations
.296
.292
.299
e
H
h
0.025 BSC
.406
.013
.400
.010
.024
.410
.016
.040
L
.032
N
See Variations
0°
5°
8°
X
.085
.093
.100
Ordering Information
ICS9250yF-10
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
16
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