SUB70N03-09P-E3 [VISHAY]
Power Field-Effect Transistor, N-Channel, Metal-oxide Semiconductor FET;
| 型号： | SUB70N03-09P-E3 |
| 厂家： | 
VISHAY |
| 描述： | Power Field-Effect Transistor, N-Channel, Metal-oxide Semiconductor FET |
| 文件： | 总3页 (文件大小：204K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPICE Device Model SUP/SUB70N03-09P
Vishay Siliconix
N-Channel 30-V (D-S), 175°C MOSFET PWM Optimized
CHARACTERISTICS
• N-Channel Vertical DMOS
• Macro Model (Model Subcircuit Schematic)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model schematic is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-to-5V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to
model the gate charge characteristics while avoiding convergence
difficulties of the switched Cgd model. All model parameter values
are optimized to provide a best fit to the measured electrical data
and are not intended as an exact physical interpretation of the
device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 71566
05-Nov-98
www.vishay.com
1
SPICE Device Model SUP/ SUB70N03-09P
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter
Symbol
Test Conditions
Typical
Unit
Static
Gate Threshold Voltage
On-State Drain Currenta
VGS(th)
ID(on)
1.67
621
V
A
VDS = VGS, ID = 250 µA
VDS = 5 V, VGS = 10 V
VGS = 10 V, ID = 30 A
0.007
0.011
0.0108
0.0127
51
VGS = 4.5 V, ID = 20 A
VGS = 10 V, ID = 30 A, 125°C
VGS = 10 V, ID = 30 A, 175°C
VDS = 15 V, ID = 30 A
Drain-Source On-State Resistancea
rDS(on)
Ω
Forward Transconductancea
Diode Forward Voltagea
gfs
S
V
VSD
IF = 70 A, VGS = 0 V
0.92
Dynamicb
Input Capacitance
Ciss
Coss
Crss
Qg
2681
664
310
46
Output Capacitance
Reverse Transfer Capacitance
Total Gate Chargec
Gate-Source Chargec
Gate-Drain Chargec
Turn-On Delay Timec
Rise Timec
VGS = 0 V, VDS = 25 V, f = 1 MHz
VDS = 15 V, VGS = 10 V, ID = 70 A
pf
Qgs
Qgd
td(on)
tr
8.5
11
nC
13
11
VDD = 15 V, RL = 0.21 Ω
Turn-Off Delay Timec
Fall Timec
td(off)
tf
35
I
D ≅ 70 A, VGEN = 10 V, RG = 2.5 Ω
ns
12
Source-Drain Reverse Recovery Time
trr
35
IF = A, di/dt = 100 A/µs
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
c. Independent of operating temperature
www.vishay.com
2
Document Number: 71566
05-Nov-98
SPICE Device Model SUP/SUB70N03-09P
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 71566
05-Nov-98
www.vishay.com
3
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