FGH30N6S2_01 [FAIRCHILD]
600V, SMPS II Series N-Channel IGBT; 600V ，开关电源II系列N沟道IGBT
| 型号： | FGH30N6S2_01 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 600V, SMPS II Series N-Channel IGBT |
| 文件： | 总11页 (文件大小：260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 2001
FGH30N6S2 / FGP30N6S2 / FGB30N6S2
600V, SMPS II Series N-Channel IGBT
General Description
Features
The FGH30N6S2, FGP30N6S2, and FGB30N6S2 are Low
Gate Charge, Low Plateau Voltage SMPS II IGBTs combin-
ing the fast switching speed of the SMPS IGBTs along with
lower gate charge and plateau voltage and avalanche capa-
bility (UIS). These LGC devices shorten delay times, and
reduce the power requirement of the gate drive. These de-
vices are ideally suited for high voltage switched mode pow-
er supply applications where low conduction loss, fast
switching times and UIS capability are essential. SMPS II
LGC devices have been specially designed for:
• 100kHz Operation at 390V, 14A
• 200kHZ Operation at 390V, 9A
• 600V Switching SOA Capability
• Typical Fall Time. . . . . . . . . . . 90ns at TJ = 125oC
• Low Gate Charge . . . . . . . . . 23nC at VGE = 15V
• Low Plateau Voltage . . . . . . . . . . . . .6.5V Typical
• UIS Rated . . . . . . . . . . . . . . . . . . . . . . . . . 150mJ
• Low Conduction Loss
•
•
•
•
•
•
Power Factor Correction (PFC) circuits
Full bridge topologies
Half bridge topologies
Push-Pull circuits
Uninterruptible power supplies
Zero voltage and zero current switching circuits
Formerly Developmental Type TA49367.
Symbol
Package
JEDEC STYLE TO-247
JEDEC STYLE TO-220AB
JEDEC STYLE TO-263AB
C
E
C
E
C
G
G
C
G
G
E
E
Device Maximum Ratings T = 25°C unless otherwise noted
C
Symbol
BV
Parameter
Collector to Emitter Breakdown Voltage
Collector Current Continuous, T = 25°C
Ratings
Units
600
45
V
A
A
A
V
V
CES
I
C25
C
I
Collector Current Continuous, T = 110°C
20
C110
C
I
Collector Current Pulsed (Note 1)
Gate to Emitter Voltage Continuous
Gate to Emitter Voltage Pulsed
108
CM
V
±20
GES
GEM
V
±30
SSOA
Switching Safe Operating Area at T = 150°C, Figure 2
60A at 600V
150
J
E
Pulsed Avalanche Energy, I = 20A, L = 1.3mH, V = 50V
mJ
W
AS
CE
DD
P
Power Dissipation Total T = 25°C
167
D
C
Power Dissipation Derating T > 25°C
1.33
W/°C
°C
C
T
Operating Junction Temperature Range
Storage Junction Temperature Range
-55 to 150
-55 to 150
J
T
°C
STG
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. Pulse width limited by maximum junction temperature.
©2001 Fairchild Semiconductor Corporation
FGH30N6S2 / FGP30N6S2 / FGB30N6S2 Rev. A
Package Marking and Ordering Information
Device Marking
30N6S2
Device
Package
TO-247
Tape Width
Quantity
FGH30N6S2
FGP30N6S2
FGB30N6S2
-
-
-
-
30N6S2
TO-220AB
TO-263AB
30N6S2
24mm
800
Electrical Characteristics T = 25°C unless otherwise noted
J
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off State Characteristics
BV
BV
Collector to Emitter Breakdown Voltage
Emitter to Collector Breakdown Voltage
Collector to Emitter Leakage Current
I
I
= 250µA, V = 0
600
10
-
25
-
-
-
V
V
CES
ECS
C
C
GE
= 10mA, V = 0
GE
I
V
= 600V
= ± 20V
T = 25°C
-
-
-
100
2
µA
mA
nA
CES
CE
J
T = 125°C
-
J
I
Gate to Emitter Leakage Current
V
-
±250
GES
GE
On State Characteristics
V
Collector to Emitter Saturation Voltage
I
V
= 12A,
T = 25°C
-
-
2.0
1.7
2.5
2.0
V
V
CE(SAT)
C
J
= 15V
GE
T = 125°C
J
Dynamic Characteristics
Q
Gate Charge
I
V
= 12A,
V
V
= 15V
= 20V
-
-
23
26
29
33
nC
nC
V
G(ON)
C
GE
= 300V
CE
GE
V
Gate to Emitter Threshold Voltage
Gate to Emitter Plateau Voltage
I
I
= 250µA, V = 600V
3.5
-
4.3
6.5
5.0
8.0
GE(TH)
C
C
CE
V
= 12A, V = 300V
V
GEP
CE
Switching Characteristics
SSOA
Switching SOA
T = 150°C, R = 10Ω, V =
GE
60
-
-
A
J
G
15V, L = 100µH, V = 600V
CE
t
Current Turn-On Delay Time
Current Rise Time
IGBT and Diode at T = 25°C,
-
-
-
-
-
-
-
-
-
-
-
-
-
-
6
-
ns
ns
ns
ns
µJ
µJ
µJ
ns
ns
ns
ns
µJ
µJ
µJ
d(ON)I
J
I
= 12A,
t
CE
10
-
rI
d(OFF)I
V
V
= 390V,
= 15V,
CE
GE
t
Current Turn-Off Delay Time
Current Fall Time
40
-
t
53
-
-
fI
R
= 10Ω
G
E
E
E
Turn-On Energy (Note 2)
Turn-On Energy (Note 2)
Turn-Off Energy (Note 3)
Current Turn-On Delay Time
Current Rise Time
55
ON1
ON2
OFF
L = 200µH
Test Circuit - Figure 20
110
100
11
-
150
-
t
IGBT and Diode at T = 125°C
J
d(ON)I
I
= 12A,
t
CE
17
-
rI
d(OFF)I
V
V
= 390V,
= 15V,
CE
t
Current Turn-Off Delay Time
Current Fall Time
73
100
100
-
GE
t
90
fI
R
= 10Ω
G
E
E
E
Turn-On Energy (Note 2)
Turn-On Energy (Note 2)
Turn-Off Energy (Note 3)
55
ON1
ON2
OFF
L = 200µH
Test Circuit - Figure 20
160
250
200
350
Thermal Characteristics
R
Thermal Resistance Junction-Case
-
-
0.75
°C/W
θJC
NOTE:
2. Values for two Turn-On loss conditions are shown for the convenience of the circuit designer. E
is the turn-on loss
ON1
of the IGBT only. E
is the turn-on loss when a typical diode is used in the test circuit and the diode is at the same T
J
ON2
as the IGBT. The diode type is specified in figure 20.
3. Turn-Off Energy Loss (E
) is defined as the integral of the instantaneous power loss starting at the trailing edge of
OFF
the input pulse and ending at the point where the collector current equals zero (I = 0A). All devices were tested per
CE
JEDEC Standard No. 24-1 Method for Measurement of Power Device Turn-Off Switching Loss. This test method produc-
es the true total Turn-Off Energy Loss.
©2001 Fairchild Semiconductor Corporation
FGH30N6S2 / FGP30N6S2 / FGS30N6S2 Rev. A
Typical Performance Curves
70
60
50
40
30
20
10
0
50
TJ = 150oC, RG = 10
Ω, VGE = 15V, L = 100mH
40
30
20
10
0
25
50
75
100
125
150
0
100
200
300
400
500
600
700
TC, CASE TEMPERATURE (oC)
VCE, COLLECTOR TO EMITTER VOLTAGE (V)
Figure 1. DC Collector Current vs Case
Temperature
Figure 2. Minimum Switching Safe Operating Area
1000
12
10
8
350
300
250
200
150
100
o
TC
V
= 390V, R = 10Ω, T = 125 C
G J
CE
75oC
VGE = 10V
VGE = 15V
I
SC
t
fMAX1 = 0.05 / (td(OFF)I + td(ON)I
)
SC
100
fMAX2 = (PD - PC) / (EON2 + EOFF
)
6
PC = CONDUCTION DISSIPATION
(DUTY FACTOR = 50%)
RØJC = 0.49oC/W, SEE NOTES
4
TJ = 125oC, RG = 3
Ω, L = 200mH, VCE = 390V
2
9
10
11
12
13
14
15
16
10
20
30
1
10
ICE, COLLECTOR TO EMITTER CURRENT (A)
V
, GATE TO EMITTER VOLTAGE (V)
GE
Figure 3. Operating Frequency vs Collector to
Emitter Current
Figure 4. Short Circuit Withstand Time
18
18
DUTY CYCLE < 0.5%, VGE = 10V
PULSE DURATION = 250ms
DUTY CYCLE < 0.5%, VGE =15V
PULSE DURATION = 250ms
16
16
14
12
10
8
14
12
10
8
6
6
TJ = 150oC
TJ = 125oC
TJ = 125oC
TJ = 150oC
4
2
0
4
TJ = 25oC
1.75
TJ = 25oC
1.75
2
0
.5
.75
1
1.25
1.50
2.0
2.25
0.50
0.75
1.00
1.25
1.50
2.00
2.25
VCE, COLLECTOR TO EMITTER VOLTAGE (V)
VCE, COLLECTOR TO EMITTER VOLTAGE (V)
Figure 5. Collector to Emitter On-State Voltage
Figure 6. Collector to Emitter On-State Voltage
©2001 Fairchild Semiconductor Corporation
FGH30N6S2 / FGP30N6S2 / FGS30N6S2 Rev. A
Typical Performance Curves (Continued)
600
500
400
300
200
100
0
400
RG = 10Ω, L = 500mH, VCE = 390V
RG = 10Ω, L = 500mH, VCE = 390V
350
300
250
200
150
100
50
TJ = 125oC, VGE = 10V, VGE = 15V
TJ = 125oC, VGE = 10V, VGE = 15V
TJ = 25oC, VGE = 10V, VGE = 15V
TJ = 25oC, VGE = 10V, VGE = 15V
0
0
5
10
15
20
25
0
5
10
15
20
25
ICE, COLLECTOR TO EMITTER CURRENT (A)
ICE, COLLECTOR TO EMITTER CURRENT (A)
Figure 7. Turn-On Energy Loss vs Collector to
Emitter Current
Figure 8. Turn-Off Energy Loss vs Collector to
Emitter Current
16
40
RG = 10
Ω
, L = 500
µH, VCE = 390V
RG = 10Ω, L = 500mH, VCE = 390V
14
12
10
8
35
30
25
20
15
10
5
TJ = 25oC, TJ = 125oC, VGE = 10V
TJ = 125oC, VGE = 15V, VGE = 10V
6
4
TJ = 25oC, VGE = 10V, VGE =15V
TJ = 25oC, TJ = 125oC, VGE = 15V
2
0
0
0
5
10
15
20
25
0
5
10
15
20
25
ICE, COLLECTOR TO EMITTER CURRENT (A)
ICE, COLLECTOR TO EMITTER CURRENT (A)
Figure 9. Turn-On Delay Time vs Collector to
Emitter Current
Figure 10. Turn-On Rise Time vs Collector to
Emitter Current
90
120
RG = 10Ω, L = 500µH, VCE = 390V
RG = 10Ω, L = 500µH, VCE = 390V
80
70
60
50
40
30
20
100
80
TJ = 125oC, VGE = 10V OR 15V
60
TJ = 25oC, VGE = 10V OR 15V
40
0
5
10
15
20
25
0
5
10
15
20
25
ICE, COLLECTOR TO EMITTER CURRENT (A)
ICE, COLLECTOR TO EMITTER CURRENT (A)
Figure 11. Turn-Off Delay Time vs Collector to
Emitter Current
Figure 12. Fall Time vs Collector to Emitter
Current
©2001 Fairchild Semiconductor Corporation
FGH30N6S2 / FGP30N6S2 / FGS30N6S2 Rev. A
Typical Performance Curves (Continued)
16
14
12
10
8
175
o
DUTY CYCLE < 0.5%, VCE = 10V
I
= 1mA, R = 25Ω, T = 25 C
L J
G(REF)
PULSE DURATION = 250µs
150
125
100
75
VCE = 600V
TJ = 25oC
6
VCE = 400V
50
4
VCE = 200V
TJ = 125o
C
7
25
2
TJ = -55oC
0
0
0
2
4
6
8
10 12 14 16 18 20 22 24
5
6
8
9
10
11
12
13
14
15
16
QG, GATE CHARGE (nC)
VGE , GATE TO EMITTER VOLTAGE (V)
Figure 13. Transfer Characteristic
Figure 14. Gate Charge
10
1.2
1.0
0.8
0.6
0.4
0.2
0
R
= 10
Ω
, L = 500mH, V = 390V, V = 15V
CE GE
TJ = 125oC, L = 500
ETOTAL = EON2 + EOFF
µ
H, VCE = 390V, VGE = 15V
G
E
= E
+ E
TOTAL
ON2 OFF
I
= 24A
CE
ICE = 24A
1
I
= 12A
= 6A
CE
I
= 12A
CE
I
CE
I
= 6A
CE
0.1
1.0
10
100
, GATE RESISTANCE (Ω)
1000
150
25
50
75
100
125
o
R
G
T
, CASE TEMPERATURE ( C)
C
Figure 15. Total Switching Loss vs Case
Temperature
Figure 16. Total Switching Loss vs Gate
Resistance
3.5
1.4
DUTY CYCLE < 0.5%
PULSE DURATION = 250µ
s, TJ = 25oC
FREQUENCY = 1MHz
1.2
1.0
0.8
0.6
0.4
0.2
0.0
3.0
2.5
2.0
1.5
CIES
ICE = 24A
ICE = 12A
ICE = 6A
COES
CRES
10
0
20
30
40
50
60
70
80
90
100
6
7
8
9
10
11
12
13
14
15
16
VCE, COLLECTOR TO EMITTER VOLTAGE (V)
VGE, GATE TO EMITTER VOLTAGE (V)
Figure 17. Capacitance vs Collector to Emitter
Voltage
Figure 18. Collector to Emitter On-State Voltage vs
Gate to Emitter Voltage
©2001 Fairchild Semiconductor Corporation
FGH30N6S2 / FGP30N6S2 / FGS30N6S2 Rev. A
Typical Performance Curves (Continued)
0
10
0.50
0.20
0.10
t
1
P
D
-1
10
t
2
0.05
DUTY FACTOR, D = t / t
1
2
0.02
0.01
PEAK T = (P X Z
X R ) + T
J
D
θ
JC
θJC C
SINGLE PULSE
-2
10
-5
-4
-3
-2
-1
0
1
10
10
10
10
10
10
10
t , RECTANGULAR PULSE DURATION (s)
1
Figure 19. IGBT Normalized Transient Thermal Impedance, Junction to Case
Test Circuit and Waveforms
FGP30N6S2D
DIODE TA4949390
90%
OFF
10%
V
GE
E
ON2
E
L = 200mH
V
CE
RG = 10
Ω
90%
10%
+
-
I
CE
t
t
FGP30N6S2
d(OFF)I
VDD = 390V
rI
t
fI
t
d(ON)I
Figure 20. Inductive Switching Test Circuit
Figure 21. Switching Test Waveforms
©2001 Fairchild Semiconductor Corporation
FGH30N6S2 / FGP30N6S2 / FGS30N6S2 Rev. A
Handling Precautions for IGBTs
Operating Frequency Information
Operating frequency information for a typical device
(Figure 3) is presented as a guide for estimating
device performance for a specific application. Other
Insulated Gate Bipolar Transistors are susceptible to
gate-insulation damage by the electrostatic
discharge of energy through the devices. When
handling these devices, care should be exercised to
assure that the static charge built in the handler’s
body capacitance is not discharged through the
device. With proper handling and application
procedures, however, IGBTs are currently being
extensively used in production by numerous
equipment manufacturers in military, industrial and
consumer applications, with virtually no damage
problems due to electrostatic discharge. IGBTs can
be handled safely if the following basic precautions
are taken:
typical frequency vs collector current (I ) plots are
CE
possible using the information shown for a typical
unit in Figures 5, 6, 7, 8, 9 and 11. The operating
frequency plot (Figure 3) of a typical device shows
f
or f
; whichever is smaller at each point.
MAX1
MAX2
The information is based on measurements of a
typical device and is bounded by the maximum rated
junction temperature.
f
is defined by f
= 0.05/(t
+ t
).
MAX1
MAX1
d(OFF)I d(ON)I
Deadtime (the denominator) has been arbitrarily held
to 10% of the on-state time for a 50% duty factor.
Other definitions are possible. t
and t
are
d(OFF)I
d(ON)I
1. Prior to assembly into a circuit, all leads should be
kept shorted together either by the use of metal
shorting springs or by the insertion into conduc-
tive material such as “ECCOSORBD™ LD26” or
equivalent.
defined in Figure 21. Device turn-off delay can
establish an additional frequency limiting condition
for an application other than T . t is important
JM d(OFF)I
when controlling output ripple under a lightly loaded
condition.
2. When devices are removed by hand from their
carriers, the hand being used should be
grounded by any suitable means - for example,
with a metallic wristband.
f
is defined by f
= (P - P )/(E
+ E
).
MAX2
MAX2
D
C
OFF
ON2
The allowable dissipation (P ) is defined by
D
P
= (T - T )/R . The sum of device switching
D
JM C θJC
and conduction losses must not exceed P . A 50%
duty factor was used (Figure 3) and the conduction
D
3. Tips of soldering irons should be grounded.
4. Devices should never be inserted into or removed
from circuits with power on.
losses (P ) are approximated by P = (V x I )/2.
C
C
CE
CE
E
and E
are defined in the switching
OFF
ON2
5. Gate Voltage Rating - Never exceed the gate-
waveforms shown in Figure 21. E
of the instantaneous power loss (I x V ) during
is the integral
ON2
voltage rating of V
. Exceeding the rated V
GEM
GE
CE
CE
can result in permanent damage to the oxide
layer in the gate region.
turn-on and E
is the integral of the instantaneous
OFF
power loss (I x V ) during turn-off. All tail losses
CE
CE
6. Gate Termination - The gates of these devices
are essentially capacitors. Circuits that leave the
gate open-circuited or floating should be avoided.
These conditions can result in turn-on of the
device due to voltage buildup on the input
are included in the calculation for E
; i.e., the
OFF
collector current equals zero (I = 0)
CE
capacitor due to leakage currents or pickup.
7. Gate Protection - These devices do not have an
internal monolithic Zener diode from gate to
emitter. If gate protection is required an external
Zener is recommended.
ECCOSORBD is a Trademark of Emerson and Cumming, Inc.
©2001 Fairchild Semiconductor Corporation
FGH30N6S2 / FGP30N6S2 / FGS30N6S2 Rev. A
TO-247
3 LEAD JEDEC STYLE TO-247 PLASTIC PACKAGE
A
TERM. 4
INCHES
MILLIMETERS
E
ØP
ØS
SYMBOL
MIN
MAX
MIN
MAX
4.82
NOTES
A
b
0.180
0.046
0.060
0.095
0.020
0.800
0.605
0.190
0.051
0.070
0.105
0.026
0.820
0.625
4.58
1.17
-
Q
1.29
2, 3
ØR
b1
b2
c
1.53
1.77
1, 2
D
2.42
2.66
1, 2
0.51
0.66
1, 2, 3
D
20.32
15.37
20.82
15.87
-
-
L
E
1
b1
b2
e
0.219 TYP
0.438 BSC
0.090
5.56 TYP
11.12 BSC
2.29
4
4
5
-
L
c
e1
J1
L
b
0.105
0.640
0.155
0.144
0.220
0.205
0.270
2.66
16.25
3.93
3.65
5.58
5.20
6.85
1
2
3
3
2
1
0.620
0.145
0.138
0.210
0.195
0.260
15.75
3.69
3.51
5.34
4.96
6.61
J
e
1
BACK VIEW
L1
ØP
Q
1
-
e1
-
ØR
ØS
-
-
NOTES:
1. Lead dimension and finish uncontrolled in L1.
2. Lead dimension (without solder).
3. Add typically 0.002 inches (0.05mm) for solder coating.
4. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimen-
sion D.
5. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimen-
sion D.
6. Controlling dimension: Inch.
7. Revision 1 dated 1-93.
©2001 Fairchild Semiconductor Corporation
FGH30N6S2 / FGP30N6S2 / FGS30N6S2 Rev. A
TO-263AB
SURFACE MOUNT JEDEC TO-263AB PLASTIC PACKAGE
INCHES
MIN
MILLIMETERS
NOTE
S
-
4, 5
4, 5
4, 5
2
4, 5
-
-
7
7
-
SYMBOL
MAX
0.180
0.052
0.034
0.055
-
MIN
4.32
1.22
0.77
1.15
7.88
0.46
MAX
4.57
1.32
0.86
1.39
-
0.55
10.79
10.28
E
A
A
0.170
0.048
0.030
0.045
0.310
0.018
0.405
0.395
A
1
A
1
H
1
b
TERM. 4
b
b
1
D
L
2
c
0.022
0.425 10.29
0.405 10.04
D
E
e
L
2
L
1
0.100 TYP
0.200 BSC
2.54 TYP
5.08 BSC
1
3
e
1
H
0.045
0.095
0.175
0.090
0.050
0.315
0.055
1.15
1.39
2.66
4.95
2.79
1.77
-
1
b
b1
c
e
J
0.105
0.195
0.110
0.070
-
2.42
4.45
2.29
1.27
8.01
-
-
1
J
1
e1
L
0.450
(11.43)
L
L
L
4, 6
3
2
TERM. 4
1
2
3
L
3
NOTES:
0.350
(8.89)
1. These dimensions are within allowable dimensions of
Rev. C of JEDEC TO-263AB outline dated 2-92.
b
2
0.700
(17.78)
2. L and b dimensions established a minimum mounting
3
2
surface for terminal 4.
3. Solder finish uncontrolled in this area.
4. Dimension (without solder).
0.150
(3.81)
3
1
5. Add typically 0.002 inches (0.05mm) for solder plating.
0.080 TYP (2.03)
0.062 TYP (1.58)
6. L is the terminal length for soldering.
1
7. Position of lead to be measured 0.120 inches (3.05mm)
from bottom of dimension D.
8. Controlling dimension: Inch.
MINIMUM PAD SIZE RECOMMENDED FOR
SURFACE-MOUNTED APPLICATIONS
9. Revision 10 dated 5-99.
4.0mm
TO-263AB
24mm TAPE REEL
1.5mm
DIA. HOLE
1.75mm
USER DIRECTION OF FEED
2.0mm
C
L
24mm
16mm
COVER TAPE
40mm MIN.
ACCESS HOLE
30.4mm
13mm
330mm
100mm
GENERAL INFORMATION
1. 800 PIECES PER REEL.
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
24.4mm
3. MEETS EIA-481 REVISION "A" SPECIFICATIONS.
©2001 Fairchild Semiconductor Corporation
FGH30N6S2 / FGP30N6S2 / FGS30N6S2 Rev. A
TO-220AB
3 LEAD JEDEC TO-220AB PLASTIC PACKAGE
A
INCHES
MILLIMETERS
MIN
E
ØP
SYMBOL
MIN
MAX
MAX
4.57
1.32
0.86
1.39
0.48
15.49
4.06
10.41
0.76
NOTES
A
1
A
A1
b
0.170
0.048
0.030
0.045
0.014
0.590
-
0.180
0.052
0.034
0.055
0.019
0.610
0.160
0.410
0.030
4.32
1.22
0.77
1.15
0.36
14.99
-
-
Q
H
1
-
3, 4
TERM. 4
D
b1
c
2, 3
o
E
45
2, 3, 4
1
D
1
D
-
-
L
1
D1
E
b1
b
0.395
-
10.04
-
-
L
E1
e
-
c
0.100 TYP
0.200 BSC
0.235
2.54 TYP
5.08 BSC
6.47
5
5
-
o
60
e1
H1
J1
L
1
2
e
3
J
1
0.255
0.110
0.550
0.150
0.153
0.112
5.97
2.54
13.47
3.31
3.79
2.60
e1
0.100
0.530
0.130
0.149
0.102
2.79
13.97
3.81
6
-
L1
ØP
Q
2
-
3.88
2.84
-
NOTES:
1. These dimensions are within allowable dimensions of Rev. J of JEDEC TO-
220AB outline dated 3-24-87.
2. Lead dimension and finish uncontrolled in L1.
3. Lead dimension (without solder).
4. Add typically 0.002 inches (0.05mm) for solder coating.
5. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimen-
sion D.
6. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimen-
sion D.
7. Controlling dimension: Inch.
8. Revision 2 dated 7-97.
©2001 Fairchild Semiconductor Corporation
FGH30N6S2 / FGP30N6S2 / FGS30N6S2 Rev. A
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OPTOPLANAR™
PACMAN™
POP™
STAR*POWER™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
TruTranslation™
UHC™
Power247™
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QFET™
HiSeC™
EcoSPARK™
ISOPLANAR™
LittleFET™
MicroFET™
MICROWIRE™
OPTOLOGIC™
QS™
E2CMOS™
QT Optpelectronics™
Quiet Series™
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PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
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As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H3
©2001 Fairchild Semiconductor Corporation
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