SUM110N08-05 [VISHAY]
N-Channel 75-V (D-S) 200∑C MOSFET; N通道75 -V ( D- S) 200℃ MOSFET型号: | SUM110N08-05 |
厂家: | VISHAY |
描述: | N-Channel 75-V (D-S) 200∑C MOSFET |
文件: | 总4页 (文件大小:179K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SPICE Device Model SUM110N08-05
Vishay Siliconix
N-Channel 75-V (D-S) 200°C MOSFET
CHARACTERISTICS
• N-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0 to 10V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to
model the gate charge characteristics while avoiding convergence
difficulties of the switched Cgd model. All model parameter values
are optimized to provide a best fit to the measured electrical data
and are not intended as an exact physical interpretation of the
device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 70511
09-Jun-04
www.vishay.com
1
SPICE Device Model SUM110N08-05
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Simulated
Data
Measured
Data
Parameter
Symbol
Test Conditions
Unit
Static
Gate Threshold Voltage
On-State Drain Currenta
VGS(th)
ID(on)
3.1
V
A
VDS = VGS, ID = 250 µA
1197
0.0038
0.0063
0.0084
109
VDS > 5 V, VGS = 10 V
VGS = 10 V, ID = 30 A
0.0038
Drain-Source On-State Resistancea
rDS(on)
Ω
VGS = 10 V, ID = 30 A, TJ = 125°C
V
GS = 10 V, ID = 30 A, TJ = 200°C
Forward Transconductancea
Forward Voltage a
gfs
VDS = 15 V, ID = 30 A
S
V
VSD
IS = 110 A, VGS = 0 V
0.92
1
Dynamic b
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Chargec
Gate-Source Chargec
Gate-Drain Chargec
Turn-On Delay Time c
Rise Time c
Ciss
Coss
Crss
Qg
7663
936
406
139
36
7900
950
550
145
30
V
GS = 0 V, VDS = 25 V, f = 1 MHz
Pf
VDS = 35 V, VGS = 10 V, ID = 110 A
NC
Qgs
Qgd
td(on)
tr
45
45
88
25
110
130
149
55
200
65
VDD = 35 V, RL = 0.40 Ω
Turn-Off Delay Time c
Fall Time c
td(off)
tf
I
D ≅ 110 A, VGEN = 10 V, RG = 2.5 Ω
Ns
165
80
Reverse Recovery Time
trr
IF = 85 A, di/dt = 100 A/µs
Notes:
a.
b.
c.
Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
Guaranteed by design, not subject to production testing.
Independent of operating temperature.
www.vishay.com
2
Document Number: 70511
09-Jun-04
SPICE Device Model SUM110N08-05
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 70511
09-Jun-04
www.vishay.com
3
SPICE Device Model SUM110N08-05
Vishay Siliconix
www.vishay.com
4
Document Number: 70511
09-Jun-04
相关型号:
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